AD ADA4062-2ARZ-R7 Tiny, low power jfet-input op amp Datasheet

Tiny, Low Power JFET-Input Op Amp
ADA4062-2
PIN CONFIGURATIONS
Low input bias current: 50 pA maximum
Offset voltage
1.5 mV maximum for ADA4062-2 B grade
2.5 mV maximum for ADA4062-2 A grade
Offset voltage drift: 4 μV/°C typical
Slew rate: 3.3 V/μs typical
CMRR: 90 dB typical
Low supply current: 165 μA typical
High input impedance
Unity-gain stable
Packaging: SOIC, MSOP
OUT A 1
–IN A 2
ADA4062-2
+IN A 3
TOP VIEW
(Not to Scale)
V– 4
8
V+
7
OUT B
6
–IN B
5
+IN B
07670-001
FEATURES
OUT A 1
–IN A 2
+IN A 3
8
ADA4062-2
V+
7
TOP VIEW
(Not to Scale)
OUT B
6
–IN B
5
+IN B
V– 4
07670-002
Figure 1. 8-Lead Narrow-Body SOIC
Figure 2. 8-Lead MSOP
APPLICATIONS
Power control and monitoring
Active filters
Industrial/process control
Body probe electronics
Data acquisition
Integrators
Input buffering
GENERAL DESCRIPTION
Table 1. Low Power Op Amps
The ADA4062-2 is a dual JFET-input amplifier with industryleading performance. It offers lower power, offset voltage, drift
and ultralow bias current. The ADA4062-2 B grade features typical
low offset voltage of 0.5 mV, offset drift of 4 μV/°C, and bias current
of 2 pA. The ADA4062-2 is ideal for various applications, including
process control, industrial and instrumentation equipment, active
filtering, data conversion, buffering, and power control and
monitoring. With a low supply current of 165 μA per amplifier,
it is also very well suited for lower power applications. The
ADA4062-2 is specified for the extended industrial temperature
range of −40°C to +125°C and is available in lead-free SOIC and
MSOP packages.
Supply
Single
40 V
OP97
36 V
AD820
Dual
OP297
Quad
OP497
OP282
AD8682
AD822
OP482
AD8684
AD824
12 V to 16 V
AD8641
AD8663
AD8642
AD8667
5V
AD8541
AD8643
AD8669
AD8544
AD8542
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
ADA4062-2
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................4
Applications ....................................................................................... 1
Typical Performance Characteristics ..............................................5
Pin Configurations ........................................................................... 1
Applications Information .............................................................. 14
General Description ......................................................................... 1
Notch Filter ................................................................................. 14
Revision History ............................................................................... 2
High-Side Signal Conditioning ................................................ 14
Specifications..................................................................................... 3
Micropower Instrumentation Amplifier ................................. 14
Electrical Characteristics ............................................................. 3
Phase Reversal ............................................................................ 14
Absolute Maximum Ratings............................................................ 4
Schematic ......................................................................................... 16
Thermal Resistance ...................................................................... 4
Outline Dimensions ....................................................................... 17
Power Sequencing ........................................................................ 4
Ordering Guide .......................................................................... 18
REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADA4062-2
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VSY = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
B Grade
Symbol
Conditions
Min
Typ
Max
Unit
0.5
1.5
3
2.5
5
50
5
25
2.5
+15
mV
mV
mV
mV
pA
nA
pA
nA
V
VOS
−40°C ≤ TA ≤ +125°C
A Grade
0.75
−40°C ≤ TA ≤ +125°C
Input Bias Current
IB
2
−40°C ≤ TA ≤ +125°C
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
B Grade
IOS
Offset Voltage Drift
Input Resistance
Input Capacitance, Differential Mode
Input Capacitance, Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
B Grade
AVO
∆VOS/∆T
RIN
CINDM
CINCM
VOH
VOL
ISC
ZOUT
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
Gain Bandwidth Product
Phase Margin
Channel Separation
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
VCM = −11.5 V to +11.5 V
−40°C ≤ TA ≤ +125°C
VCM = −11.5 V to +11.5 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = −10 V to +10 V
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
80
80
74
70
76
72
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
13
12.5
90
dB
dB
dB
dB
dB
dB
μV/°C
TΩ
pF
pF
90
83
4
10
1.5
4.8
13.5
−13.8
−13
−12.5
20
4
f = 100 kHz, AV = 1
V
V
V
V
mA
Ω
PSRR
A Grade
Supply Current per Amplifier
−11.5
CMRR
A Grade
Large-Signal Voltage Gain
0.5
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
ISY
VSY = ±4 V to ±18 V
−40°C ≤ TA ≤ +125°C
VSY = ±4 V to ±18 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
−40°C ≤ TA ≤ +125°C
80
80
74
70
90
90
165
200
220
dB
dB
dB
dB
μA
μA
SR
tS
GBP
ΦM
CS
RL = 10 kΩ, CL = 100 pF, AV = 1
To 0.01%, VIN = 2 V step, CL = 100 pF, RL = 5 kΩ, AV = 1
RL = 10 kΩ, AV = 1
RL = 10 kΩ, AV = 1
f = 10 kHz
3.3
3.5
1.4
80
130
V/μs
μs
MHz
Degrees
dB
en p-p
en
in
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
1.5
36
5
μV p-p
nV/√Hz
fA/√Hz
Rev. 0 | Page 3 of 20
ADA4062-2
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Parameter
Supply Voltage
Input Voltage
Differential Input Voltage
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. It was
measured using a standard 2-layer board.
Rating
±18 V
±VSY
±VSY
Indefinite
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
Table 4. Thermal Resistance
Package Type
8-Lead SOIC
8-Lead MSOP
θJA
158
210
θJC
43
45
Unit
°C/W
°C/W
POWER SEQUENCING
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
The op amp supply voltages must be established simultaneously
with, or before, any input signals are applied. If this is not
possible, the input current must be limited to 10 mA.
ESD CAUTION
Rev. 0 | Page 4 of 20
ADA4062-2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
280
70
VSY = ±15V
VCM = 0V
60
NUMBER OF AMPLIFERS
200
160
120
80
30
20
10
–2
–1
0
1
2
3
VOS (mV)
0
–4
NUMBER OF AMPLIFERS
20
10
0
2
4
6
8
10
TCVOS (µV/°C)
10
–2
5
3
2
2
1
1
VOS (mV)
3
0
–1
–2
–3
–4
–4
–3
0
3
6
9
2
4
6
8
10
12
VCM (V)
15
VSY = ±5V
0
–3
–6
0
–1
–2
–9
4
20
4
–12
3
Figure 7. Input Offset Voltage Drift Distribution
VSY = ±15V
–5
–15
2
TCVOS (µV/°C)
–5
–4
07670-006
VOS (mV)
4
1
VSY = ±5V
–40°C ≤ TA ≤ +125°C
Figure 4. Input Offset Voltage Drift Distribution
5
0
30
0
07670-005
NUMBER OF AMPLIFERS
40
VSY = ±15V
–40°C ≤ TA ≤ +125°C
–2
–1
Figure 6. Input Offset Voltage Distribution
30
0
–2
VOS (mV)
Figure 3. Input Offset Voltage Distribution
40
–3
07670-055
–3
07670-003
0
40
07670-054
40
50
–3
–2
–1
0
1
2
3
4
VCM (V)
Figure 5. Input Offset Voltage vs. Common-Mode Voltage
Figure 8. Input Offset Voltage vs. Common-Mode Voltage
Rev. 0 | Page 5 of 20
5
07670-056
NUMBER OF AMPLIFERS
240
VSY = ±5V
VCM = 0V
ADA4062-2
10000
10000
VSY = ±15V
1000
100
100
10
10
1
1
–25
0
25
50
75
100
125
TEMPERATURE (°C)
0.1
–50
07670-009
0.1
–50
25
50
75
100
125
Figure 12. Input Bias Current vs. Temperature
3
VSY = ±15V
2
3
1
VSY = ±5V
2
0
1
–1
–4
–2
0
2
4
6
8
10
12
14
16
VCM (V)
–2
–3
10
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
VCC – VOH
VOL – VEE
0.1
1
10
LOAD CURRENT (mA)
100
1
2
3
4
5
VSY = ±5V
VCC – VOH
1
0.1
0.01
07670-011
0.1
0.01
0
Figure 13. Input Bias Current vs. Input Common-Mode Voltage
VSY = ±15V
1
–1
VCM (V)
Figure 10. Input Bias Current vs. Input Common-Mode Voltage
10
–2
VOL – VEE
0.1
1
10
LOAD CURRENT (mA)
Figure 11. Output Voltage to Supply Rail vs. Load Current
Figure 14. Output Voltage to Supply Rail vs. Load Current
Rev. 0 | Page 6 of 20
100
07670-014
–6
07670-010
–8
07670-013
IB (pA)
IB (pA)
4
0
–12 –10
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
0
TEMPERATURE (°C)
Figure 9. Input Bias Current vs. Temperature
5
–25
07670-012
IB (pA)
IB (pA)
1000
VSY = ±5V
ADA4062-2
2.0
VOL – VEE
1.0
0.5
–25
0
25
50
75
100
125
TEMPERATURE (°C)
VCC – VOH
0.5
0
–50
0
25
50
75
100
125
Figure 18. Output Voltage to Supply Rail vs. Temperature
120
120
100
100
80
80
80
80
60
60
60
60
100
PHASE
40
40
GAIN
20
20
0
0
GAIN (dB)
VSY = ±15V
PHASE (Degrees)
120
120
VSY = ±5V
PHASE
40
100
40
GAIN
20
20
0
0
–20
–20
–20
–20
–40
–40
–40
–40
10k
100k
1M
–60
100M
10M
–60
1k
07670-016
–60
1k
FREQUENCY (Hz)
10k
1M
FREQUENCY (Hz)
VSY = ±15V
AV = +100
–60
100M
10M
50
50
VSY = ±5V
AV = +100
40
40
30
30
AV = +10
GAIN (dB)
AV = +10
20
10
AV = +1
10
0
AV = +1
–10
–10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
100M
–20
10
07670-017
–20
10
20
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 20. Closed-Loop Gain vs. Frequency
Figure 17. Closed-Loop Gain vs. Frequency
Rev. 0 | Page 7 of 20
100M
07670-020
0
100k
Figure 19. Open-Loop Gain and Phase vs. Frequency
Figure 16. Open-Loop Gain and Phase vs. Frequency
GAIN (dB)
–25
TEMPERATURE (°C)
Figure 15. Output Voltage to Supply Rail vs. Temperature
GAIN (dB)
VOL – VEE
1.0
PHASE (Degrees)
0
–50
1.5
07670-018
1.5
VSY = ±5V
RL = 10kΩ
07670-019
VCC – VOH
OUTPUT VOTLAGE TO SUPPLY RAIL (V)
VSY = ±15V
RL = 10kΩ
07670-015
OUTPUT VOTLAGE TO SUPPLY RAIL (V)
2.0
ADA4062-2
1000
1000
VSY = ±15V
VSY = ±5V
100
100
AV = +10
AV = +1
0.1
100
AV = +100
AV = +10
AV = +1
1
1k
10k
100k
1M
10M
FREQUENCY (Hz)
0.1
100
80
70
70
60
60
CMRR (dB)
80
50
40
30
20
10
10
1M
10M
FREQUENCY (Hz)
VSY = ±5V
40
20
100k
0
100
1k
1M
120
VSY = ±15V
10M
VSY = ±5V
100
100
80
60
PSRR (dB)
80
PSRR+
40
60
PSRR+
40
PSRR–
20
PSRR–
20
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
–20
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 26. PSRR vs. Frequency
Figure 23. PSRR vs. Frequency
Rev. 0 | Page 8 of 20
1M
10M
07670-026
0
0
07670-023
PSRR (dB)
100k
Figure 25. CMRR vs. Frequency
120
–20
10k
FREQUENCY (Hz)
Figure 22. CMRR vs. Frequency
140
10M
50
30
07670-022
CMRR (dB)
90
10k
1M
100
VSY = ±15V
1k
100k
Figure 24. Output Impedance vs. Frequency
90
0
100
10k
FREQUENCY (Hz)
Figure 21. Output Impedance vs. Frequency
100
1k
07670-025
1
10
07670-024
ZOUT (Ω)
10
07670-021
ZOUT (Ω)
AV = +100
ADA4062-2
60
50
OVERSHOOT (%)
30
20
40
30
20
10000
CL (pF)
0
10
10000
Figure 30. Small-Signal Overshoot vs. Load Capacitance
07670-028
VOLTAGE (1V/DIV)
VSY = ±15V
VIN = 20V p-p
AV = +1
RL = 10kΩ
CL = 100pF
VSY = ±5V
VIN = 4V p-p
AV = +1
RL = 10kΩ
CL = 100pF
TIME (4µs/DIV)
Figure 31. Large-Signal Transient Response
VOLTAGE (20mV/DIV)
Figure 28. Large-Signal Transient Response
07670-029
VSY = ±15V
VIN = 100mV p-p
AV = +1
RL = 10kΩ
CL = 100pF
TIME (10µs/DIV)
1000
CL (pF)
Figure 27. Small-Signal Overshoot vs. Load Capacitance
TIME (10µs/DIV)
100
07670-031
1000
VSY = ±5V
VIN = 100mV p-p
AV = +1
RL = 10kΩ
CL = 100pF
TIME (10µs/DIV)
Figure 32. Small-Signal Transient Response
Figure 29. Small-Signal Transient Response
Rev. 0 | Page 9 of 20
07670-032
100
07670-027
0
10
07670-030
10
10
VOLTAGE (5V/DIV)
VSY = ±5V
AV = +1
RL = 10kΩ
50
40
VOLTAGE (20mV/DIV)
OVERSHOOT (%)
60
VSY = ±15V
AV = +1
RL = 10kΩ
ADA4062-2
4
4
VSY = ±15V
VSY = ±5V
2
INPUT
INPUT
OUTPUT
0
–2
–10
–4
–15
07670-033
–20
TIME (2µs/DIV)
Figure 36. Negative Overload Recovery
2
10
5
OUTPUT
–5
–2
Figure 37. Positive Overload Recovery
INPUT
IDEAL STEP
FUNCTION
OF 10V
VOLTAGE (1V/DIV)
+10mV
OUTPUT
0V
VSY = ±5V
+2mV
OUTPUT
0V
ERROR BAND
–10mV
TIME (1µs/DIV)
–2mV
TIME (2µs/DIV)
Figure 38. Positive Settling Time to 0.01%
Figure 35. Positive Settling Time to 0.01%
Rev. 0 | Page 10 of 20
07670-035
VSY = ±15V
0
TIME (2µs/DIV)
07670-042
VOLTAGE (5V/DIV)
2
OUTPUT
Figure 34. Positive Overload Recovery
ERROR
BAND
4
0
TIME (2µs/DIV)
INPUT
–2
OUTPUT VOLTAGE (V)
15
INPUT VOLTAGE (V)
–2
OUTPUT VOLTAGE (V)
0
VSY = ±5V
INPUT
07670-037
VSY = ±15V
INPUT
07670-034
INPUT VOLTAGE (V)
0
–6
TIME (2µs/DIV)
Figure 33. Negative Overload Recovery
2
OUTPUT VOLTAGE (V)
–5
07670-036
0
INPUT VOLTAGE (V)
OUTPUT
OUTPUT VOLTAGE (V)
0
INPUT VOLTAGE (V)
0
2
ADA4062-2
VSY = ±5V
VSY = ±15V
+10mV
0V
+2mV
OUTPUT
ERROR BAND
0V
–2mV
TIME (1µs/DIV)
TIME (2µs/DIV)
Figure 39. Negative Settling Time to 0.01%
Figure 42. Negative Settling Time to 0.01%
1000
VOLTAGE NOISE DENSITY (nV/√Hz)
VSY = ±15V
1
10
100
1k
10k
100k
FREQUENCY (Hz)
VSY = ±5V
100
10
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 40. Voltage Noise Density
Figure 43. Voltage Noise Density
VSY = ±15V
VSY = ±5V
INPUT NOISE VOLTAGE (0.5µV/DIV)
07670-041
TIME (1s/DIV)
TIME (1s/DIV)
Figure 41. 0.1 Hz to 10 Hz Noise
Figure 44. 0.1 Hz to 10 Hz Noise
Rev. 0 | Page 11 of 20
07670-044
10
07670-040
100
INPUT NOISE VOLTAGE (0.5µV/DIV)
VOLTAGE NOISE DENSITY (nV/√Hz)
1000
07670-039
07670-038
–10mV
07670-043
OUTPUT
ERROR
BAND
INPUT
VOLTAGE (1V/DIV)
VOLTAGE (5V/DIV)
INPUT
ADA4062-2
410
410
390
SUPPLY CURRENT (µA)
125°C
370
85°C
350
25°C
330
–40°C
3
4
5
6
7
8
VSY = ±15V
350
VSY = ±5V
330
310
290
9 10 11 12 13 14 15 16 17 18 19 20
SUPPLY VOLTAGE (±V)
270
–50
50
75
100
125
VSY = ±5V
VIN = 5V p-p
RL = 10kΩ
–20
CHANNEL SEPARATION (dB)
–40
–60
–80
–100
–120
–40
–60
–80
–100
–120
–140
1k
10k
100k
FREQUENCY (Hz)
–160
07670-046
–160
100
100
10k
100k
FREQUENCY (Hz)
Figure 46. Channel Separation vs. Frequency
Figure 49. Channel Separation vs. Frequency
100
VSY = ±15V
f = 1kHz
RL = 10kΩ
10
1
1
THD + N (%)
10
0.1
VSY = ±5V
f = 1kHz
RL = 10kΩ
0.1
0.01
0.01
0.1
1
AMPLITUDE (V rms)
10
07670-047
0.01
0.001
0.001
1k
07670-049
CHANNEL SEPARATION (dB)
0
VSY = ±15V
VIN = 10V p-p
RL = 10kΩ
–140
THD + N (%)
25
Figure 48. Supply Current vs. Temperature
0
100
0
TEMPERATURE (°C)
Figure 45. Supply Current vs. Supply Voltage
–20
–25
Figure 47. THD + N vs. Amplitude
0.001
0.001
0.01
0.1
1
AMPLITUDE (V rms)
Figure 50. THD + N vs. Amplitude
Rev. 0 | Page 12 of 20
10
07670-050
290
370
07670-048
310
07670-045
SUPPLY CURRENT (µA)
390
ADA4062-2
10
VSY = ±15V
VIN = 0.5 V rms
RL = 10kΩ
1
1
0.1
0.1
THD + N (%)
0.01
0.001
0.01
0.001
10
100
1k
10k
FREQUENCY (Hz)
100k
07670-051
0.0001
VSY = ±5V
VIN = 0.5 V rms
RL = 10kΩ
0.0001
Figure 51. THD + N vs. Frequency
10
100
1k
10k
FREQUENCY (Hz)
Figure 52. THD + N vs. Frequency
Rev. 0 | Page 13 of 20
100k
07670-052
THD + N (%)
10
ADA4062-2
APPLICATIONS INFORMATION
NOTCH FILTER
HIGH-SIDE SIGNAL CONDITIONING
A notch filter rejects a specific interfering frequency and can
be implemented using a single op amp. Figure 53 shows a 60 Hz
notch filter that uses the twin T network with the ADA4062-2
configured as a voltage follower. The ADA4062-2 works as a buffer
that provides high input resistance and low output impedance.
The low bias current (2 pA typical) and high input resistance
(10 TΩ typical) of the ADA4062-2 enable large resistors and
small capacitors to be used.
There are many applications that require the sensing of signals
near the positive rail. The ADA4062-2 can be used in high-side
current sensing applications. Figure 55 shows a high-side signal
conditioning circuit using the ADA4062-2. The ADA4062-2 has
an input common-mode range that includes the positive supply
(−11.5 V ≤ VCM ≤ +15 V). In the circuit, the voltage drop across
a low value resistor, such as the 0.1 Ω shown in Figure 55, is
amplified by a factor of 5 using the ADA4062-2.
+VSY
IN
R1
804kΩ
R2
804kΩ
C1
3.3nF
1/2
VO
ADA4062-2
C3
6.6nF
R3
402kΩ
–VSY
C2
3.3nF
1
fO = 2π R C
1 1
C1 = C2 =
07670-060
R1 = R2 = 2R3
C3
2
500kΩ
100kΩ
100kΩ
VO
1/2
ADA4062-2
500kΩ
–15V
Figure 55. High-Side Signal Conditioning
MICROPOWER INSTRUMENTATION AMPLIFIER
The ADA4062-2 is a dual amplifier and is perfectly suited for
applications that require lower supply currents. For supply voltages
of ±15 V, the supply current per amplifier is 165 μA typical. The
ADA4062-2 also offers a typical low offset voltage drift of 4 μV/°C
and a very low bias current of 2 pA, which makes it well suited for
instrumentation amplifiers.
Figure 56 shows the classic 2-op-amp instrumentation amplifier
with four resistors using the ADA4062-2. The key to high CMRR
for this instrumentation amplifier are resistors that are well
matched to both the resistive ratio and relative drift. For true
difference amplification, matching of the resistor ratio is very
important, where R3/R4 = R1/R2. Assuming perfectly matched
resistors, the gain of the circuit is 1 + R2/R1, which is approximately 100. Tighter matching of two op amps in one package,
as is the case with the ADA4062-2, offers a significant boost in
performance over the 3-op-amp configuration. Overall, the circuit
only requires about 330 μA of supply current.
R3
10.1kΩ
Figure 53. Notch Filter Circuit
R4
1MΩ
20
R2
1MΩ
+15V
R1
10.1kΩ
1/2
10
+15V
1/2
ADA4062-2
0
V1
–10
–20
VO
ADA4062-2
–15V
V2
–15V
VO = 100(V2 – V1)
TYPICAL: 0.5mV < │V2 – V1│< 135mV
TYPICAL: –13.8V < VO < +13.5V
USE MATCHED RESISTORS
–30
–40
Figure 56. Micropower Instrumentation Amplifier
–50
–60
PHASE REVERSAL
–70
Phase reversal occurs in some amplifiers when the input commonmode voltage range is exceeded. When the voltage driving the
input to these amplifiers exceeds the maximum input commonmode voltage range, the output of the amplifiers changes polarity.
–80
10
100
FREQUENCY (Hz)
Figure 54. Notch Filter: Gain vs. Frequency
1k
07670-057
GAIN (dB)
RL
+15V
07670-059
Therefore, to achieve the desired performance, 1% or better component tolerances are usually required. In addition, a notch filter
requires an op amp with a bandwidth of at least 100 to 200 times
the center frequency. Hence, using the ADA4062-2 with a
bandwidth of 1.4 MHz is excellent for a 60 Hz notch filter.
Figure 54 shows the gain of the notch filter with respect to
frequency. At 60 Hz, the notch filter has about 50 dB attenuation of signal.
0.1Ω
+15V
07670-058
Alternatively, different combinations of resistors and capacitors
values can be used to achieve the desired notch frequency.
However, the major drawback to this circuit topology is the
need to ensure that all the resistors and capacitors be closely
matched. If they are not closely matched, the notch frequency
offset and drift cause the circuit to attenuate at a frequency
other than the ideal notch frequency.
Rev. 0 | Page 14 of 20
ADA4062-2
Most JFET input amplifiers have phase reversal if either input
exceeds the input common-mode range.
+VSY
R
D1
10kΩ IN5711
1/2
VO
ADA4062-2
–VSY
07670-053
IN
Figure 57. Phase Reversal Solution Circuit
Rev. 0 | Page 15 of 20
VSY = ±15V
VOUT
TIME (40µs/DIV)
Figure 58. No Phase Reversal
07670-038
VOLTAGE (5V/DIV)
For the ADA4062-2, the output does not phase reverse if one or
both of the inputs exceeds the input voltage range but stays below
the positive supply rail and 0.5 V above the negative supply rail.
With a supply voltage of ±15 V, phase reversal occurs when the
input voltage is a negative signal greater than −14.5 V. This is due
to saturation of the input stage leading to forward biasing of the
gate-drain diode. Phase reversal in ADA4062-2 can be prevented
by using a Schottky diode to clamp the input terminals to each
other. In the simple buffer circuit in Figure 57, D1 protects the
op amp against phase reversal and R limits the input current
that flows into the op amp.
VIN
ADA4062-2
SCHEMATIC
VCC
OUT A/
OUT B
VEE
Figure 59. Simplified Schematic
Rev. 0 | Page 16 of 20
07670-062
+IN A/
+IN B
–IN A/
–IN B
ADA4062-2
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
3.20
3.00
2.80
5.15
4.90
4.65
5
1
4
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.15
0.00
0.38
0.22
COPLANARITY
0.10
0.80
0.60
0.40
8°
0°
0.23
0.08
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 60. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-A A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 61. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. 0 | Page 17 of 20
012407-A
4.00 (0.1574)
3.80 (0.1497)
ADA4062-2
ORDERING GUIDE
Model
ADA4062-2ARMZ 1
ADA4062-2ARMZ-RL1
ADA4062-2ARZ1
ADA4062-2ARZ-R71
ADA4062-2ARZ-RL1
ADA4062-2BRZ1
ADA4062-2BRZ-R71
ADA4062-2BRZ-RL1
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
Z = RoHS Compliant Part.
Rev. 0 | Page 18 of 20
Package Option
RM-8
RM-8
R-8
R-8
R-8
R-8
R-8
R-8
Branding
A25
A25
ADA4062-2
NOTES
Rev. 0 | Page 19 of 20
ADA4062-2
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07670-0-10/08(0)
Rev. 0 | Page 20 of 20