a FEATURES Specified for VDD of 3 V to 5.5 V Read-Only Operation AD7854–200 kSPS; AD7854L–100 kSPS System and Self-Calibration Low Power Normal Operation AD7854: 15 mW (VDD = 3 V) AD7854L: 5.5 mW (V DD = 3 V) Automatic Power-Down After Conversion (25 W) AD7854: 1.3 mW 10 kSPS AD7854L: 650 W 10 kSPS Flexible Parallel Interface 12-Bit Parallel/8-Bit Parallel (AD7854) 28-Lead DIP, SOIC and SSOP Packages (AD7854) APPLICATIONS Battery-Powered Systems (Personal Digital Assistants, Medical Instruments, Mobile Communications) Pen Computers Instrumentation and Control Systems High Speed Modems 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs AD7854/AD7854L FUNCTIONAL BLOCK DIAGRAM AGND AVDD AD7854/AD7854L AIN(+) T/H AIN(–) DVDD 2.5V REFERENCE REFIN/ REFOUT COMP BUF DGND CREF1 CHARGE REDISTRIBUTION DAC CLKIN SAR + ADC CONTROL CREF2 CALIBRATION MEMORY AND CONTROLLER BUSY PARALLEL INTERFACE/CONTROL REGISTER DB11–DB0 CS RD WR HBEN GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7854/AD7854L is a high speed, low power, 12-bit ADC that operates from a single 3 V or 5 V power supply, the AD7854 being optimized for speed and the AD7854L for low power. The ADC powers up with a set of default conditions at which time it can be operated as a read-only ADC. The ADC contains self-calibration and system calibration options to ensure accurate operation over time and temperature and has a number of power-down options for low power applications. 1. Operation with either 3 V or 5 V power supplies. The AD7854 is capable of 200 kHz throughput rate while the AD7854L is capable of 100 kHz throughput rate. The input track-and-hold acquires a signal in 500 ns and features a pseudodifferential sampling scheme. The AD7854 and AD7854L input voltage range is 0 to VREF (unipolar) and –VREF/2 to +VREF/2, centered at VREF/2 (bipolar). The coding is straight binary in unipolar mode and twos complement in bipolar mode. Input signal range is to the supply and the part is capable of converting full-power signals to 100 kHz. CONVST 2. Flexible power management options including automatic power-down after conversion. By using the power management options a superior power performance at slower throughput rates can be achieved: AD7854: 1 mW typ @ 10 kSPS AD7854L: 1 mW typ @ 20 kSPS 3. Operates with reference voltages from 1.2 V to AVDD. 4. Analog input ranges from 0 V to AVDD. 5. Self-calibration and system calibration. 6. Versatile parallel I/O port. 7. Lower power version AD7854L. CMOS construction ensures low power dissipation of typically 5.4 mW for normal operation and 3.6 µW in power-down mode. The part is available in 28-lead, 0.6 inch wide dual-in-line package (DIP), 28-lead small outline (SOIC) and 28-lead small shrink outline (SSOP) packages. See Page 27 for data sheet index. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 1, 2 (AV = DV = +3.0 V to +5.5 V, REF /REF = 2.5 V AD7854/AD7854L–SPECIFICATIONS External Reference, f = 4 MHz (for L Version: 1.8 MHz (0ⴗC to +70ⴗC) and 1 MHz (–40ⴗC to +85ⴗC)); f = 200 kHz (AD7854), 100 kHz DD DD CLKIN IN OUT SAMPLE (AD7854L); TA = TMIN to TMAX, unless otherwise noted.) Specifications in () apply to the AD7854L. Parameter A Version1 B Version1 S Version1 Units Test Conditions/Comments DYNAMIC PERFORMANCE Signal to Noise + Distortion Ratio3 (SNR) 70 71 70 dB min Total Harmonic Distortion (THD) –78 –78 –78 dB max Peak Harmonic or Spurious Noise –78 –78 –78 dB max Typically SNR is 72 dB VIN = 10 kHz Sine Wave, fSAMPLE = 200 kHz (L Version: fSAMPLE = 100 kHz @ fCLKIN = 2 MHz) VIN = 10 kHz Sine Wave, fSAMPLE = 200 kHz (L Version: fSAMPLE = 100 kHz @ fCLKIN = 2 MHz) VIN = 10 kHz Sine Wave, fSAMPLE = 200 kHz (L Version: fSAMPLE = 100 kHz @ fCLKIN = 2 MHz) Intermodulation Distortion (IMD) Second Order Terms –78 –78 –78 dB typ –78 –78 –78 dB typ 12 ±1 ±1 ±3 ±2 ±4 ±2 ±4 ±2 ±4 ±2 ±4 12 ± 0.5 ±1 ±3 ±2 ±4 ±2 ±4 ±2 ±4 ±2 ±4 12 ±1 ±1 ±4 ±2 ±4 ±2 ±5 ±2 ±5 ±2 ±5 Bits LSB max LSB max LSB max LSB typ LSB max LSB typ LSB max LSB typ LSB max LSB typ LSB max 0 to VREF 0 to VREF 0 to VREF Volts ± VREF/2 ± VREF/2 ± VREF/2 Volts ±1 20 ±1 20 ±1 20 µA max pF typ 2.3/VDD 150 2.3/2.75 20 2.3/VDD 150 2.3/2.7 20 2.3/VDD 150 2.3/2.7 20 V min/max kΩ typ V min/max ppm/°C typ Functional from 1.2 V 3 2.1 0.4 0.6 ± 10 10 3 2.1 0.4 0.6 ± 10 10 3 2.1 0.4 0.6 ± 10 10 V min V min V max V max µA max pF max AVDD = DVDD = 4.5 V to 5.5 V AVDD = DVDD = 3.0 V to 3.6 V AVDD = DVDD = 4.5 V to 5.5 V AVDD = DVDD = 3.0 V to 3.6 V Typically 10 nA, VIN = 0 V or VDD 4 2.4 4 2.4 4 2.4 V min V min Third Order Terms DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Unipolar Offset Error Unipolar Gain Error Bipolar Positive Full-Scale Error Negative Full-Scale Error Bipolar Zero Error ANALOG INPUT Input Voltage Ranges Leakage Current Input Capacitance REFERENCE INPUT/OUTPUT REFIN Input Voltage Range Input Impedance REFOUT Output Voltage REFOUT Tempco LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance4 Output Coding CONVERSION RATE Conversion Time Track/Hold Acquisition Time 0.4 ± 10 10 4.6 (10) 0.5 (1) 0.4 0.4 ± 10 ± 10 10 10 Straight (Natural) Binary Twos Complement 4.6 (9) 0.5 (1) 4.6 (9) 0.5 (1) –2– V max µA max pF max fa = 9.983 kHz, fb = 10.05 kHz, fSAMPLE = 200 kHz (L Version: fSAMPLE = 100 kHz @ fCLKIN = 2 MHz) fa = 9.983 kHz, fb = 10.05 kHz, fSAMPLE = 200 kHz (L Version: fSAMPLE = 100 kHz @ fCLKIN = 2 MHz) 5 V Reference VDD = 5 V Guaranteed No Missed Codes to 12 Bits i.e., AIN(+) – AIN(–) = 0 to VREF, AIN(–) can be biased up but AIN(+) cannot go below AIN(–). i.e., AIN(+) – AIN(–) = –VREF/2 to +VREF/2, AIN(–) should be biased to +VREF/2 and AIN(+) can go below AIN(–) but cannot go below 0 V. ISOURCE = 200 µA AVDD = DVDD = 4.5 V to 5.5 V AVDD = DVDD = 3.0 V to 3.6 V ISINK = 0.8 mA Unipolar Input Range Bipolar Input Range µs max µs min tCLKIN × 18 (L Versions Only, 0°C to +70°C, 1.8 MHz CLKIN) (L Versions Only, –40°C to +85°C, 1 MHz CLKIN) REV. B AD7854/AD7854L Parameter POWER REQUIREMENTS AVDD, DVDD IDD Normal Mode5 Sleep Mode6 With External Clock On With External Clock Off Normal Mode Power Dissipation Sleep Mode Power Dissipation With External Clock On With External Clock Off A Version1 B Version1 S Version1 Units +3.0/+5.5 +3.0/+5.5 +3.0/+5.5 V min/max 5.5 (1.8) 5.5 (1.8) 6 (1.8) mA max 5.5 (1.8) 5.5 (1.8) 6 (1.8) mA max 10 10 10 µA typ 400 400 400 µA typ 5 5 5 µA max 200 200 200 µA typ 30 (10) 20 (6.5) 30 (10) 20 (6.5) 30 (10) 20 (6.5) mW max mW max Full power-down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 0. Partial power-down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 1. Typically 1 µA. Full power-down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 0. Partial power-down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 1. VDD = 5.5 V: Typically 25 mW (8) VDD = 3.6 V: Typically 15 mW (5.4) 55 36 27.5 18 55 36 27.5 18 55 36 27.5 18 µW typ µW typ µW max µW max VDD = 5.5 V VDD = 3.6 V VDD = 5.5 V: Typically 5.5 µW VDD = 3.6 V: Typically 3.6 µW V max/min V max/min Allowable Offset Voltage Span for Calibration Allowable Full-Scale Voltage Span for Calibration SYSTEM CALIBRATION Offset Calibration Span7 Gain Calibration Span7 +0.05 × VREF/–0.05 × VREF +0.025 × VREF/–0.025 × VREF Test Conditions/Comments AVDD = DVDD = 4.5 V to 5.5 V. Typically 4.5 mA (1.5 mA); AVDD = DVDD = 3.0 V to 3.6 V. Typically 4.0 mA (1.5 mA). NOTES 1 Temperature ranges as follows: A, B Versions, –40°C to +85°C; S Version, –55°C to +125°C. 2 Specifications apply after calibration. 3 Not production tested. Guaranteed by characterization at initial product release. 4 Sample tested @ +25°C to ensure compliance. 5 All digital inputs @ DGND except for CONVST @ DVDD. No load on the digital outputs. Analog inputs @ AGND. 6 CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST @ DVDD. No load on the digital outputs. Analog inputs @ AGND. 7 The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7854/AD7854L can calibrate. Note also that these are voltage spans and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ± 0.05 × VREF, and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be VREF ± 0.025 × VREF (unipolar mode) and V REF/2 ± 0.025 × VREF (bipolar mode)). This is explained in more detail in the calibration section of the data sheet. Specifications subject to change without notice. REV. B –3– AD7854/AD7854L 1 (AVDD = DVDD = +3.0 V to +5.5 V; fCLKIN = 4 MHz for AD7854 and 1.8 MHz for AD7854L; TIMING SPECIFICATIONS TA = TMIN to TMAX, unless otherwise noted) Limit at TMIN, TMAX (A, B, S Versions) 5V 3V Units Description 500 4 1.8 100 90 4.5 10 15 5 0 0 70 50 5 40 70 0 5 0 0 70 10 5 1/2 tCLKIN 70 70 60 60 2.5 tCLKIN 31.25 kHz min MHz max MHz max ns min ns max µs max µs max ns min ns min ns min ns min ns min ns max ns min ns max ns min ns min ns max ns min ns max ns min ns min ns min ns min ns min ns min ns min ns min ns max ms typ Master Clock Frequency t10 t11 t12 t13 t14 t15 t16 t17 t184 t19 t20 t21 t22 t23 tCAL6 500 4 1.8 100 50 4.5 10 15 5 0 0 55 50 5 40 60 0 5 0 0 55 10 5 1/2 tCLKIN 50 50 40 40 2.5 tCLKIN 31.25 tCAL16 27.78 27.78 ms typ tCAL26 3.47 3.47 ms typ Parameter fCLKIN2 t1 3 t2 tCONVERT t3 t4 t5 t6 t7 t8 4 t9 5 L Version CONVST Pulsewidth CONVST to BUSY ↑ Propagation Delay Conversion Time = 18 tCLKIN L Version 1.8 MHz CLKIN. Conversion Time = 18 tCLKIN HBEN to RD Setup Time HBEN to RD Hold Time CS to RD to Setup Time CS to RD Hold Time RD Pulsewidth Data Access Time After RD Bus Relinquish Time After RD Minimum Time Between Reads HBEN to WR Setup Time HBEN to WR Hold Time CS to WR Setup Time CS to WR Hold Time WR Pulsewidth Data Setup Time Before WR Data Hold Time After WR New Data Valid Before Falling Edge of BUSY HBEN High Pulse Duration HBEN Low Pulse Duration Propagation Delay from HBEN Rising Edge to Data Valid Propagation Delay from HBEN Falling Edge to Data Valid CS↑ to BUSY ↑ in Calibration Sequence Full Self-Calibration Time, Master Clock Dependent (125013 tCLKIN) Internal DAC Plus System Full-Scale Cal Time, Master Clock Dependent (111124 tCLKIN) System Offset Calibration Time, Master Clock Dependent (13889 tCLKIN) NOTES 1 Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. 2 Mark/Space ratio for the master clock input is 40/60 to 60/40. 3 The CONVST pulsewidth here only applies for normal operation. When the part is in power-down mode, a different CONVST pulsewidth applies (see Power-Down section). 4 Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V. 5 t9 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 9, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 6 The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to the 1.8 MHz master clock. Specifications subject to change without notice. –4– REV. B AD7854/AD7854L 1.6mA TO OUTPUT PIN ABSOLUTE MAXIMUM RATINGS 1 IOL (TA = +25°C unless otherwise noted) AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V REFIN/REFOUT to AGND . . . . . . . . . –0.3 V to AVDD + 0.3 V Input Current to Any Pin Except Supplies2 . . . . . . . . . ± 10 mA Operating Temperature Range Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C Commercial (S Version) . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature Range . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Cerdip Package, Power Dissipation . . . . . . . . . . . . . . 450 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W Lead Temperature, (Soldering, 10 secs) . . . . . . . . . +300°C SOIC, SSOP Package, Power Dissipation . . . . . . . . . 450 mW θJA Thermal Impedance . . . 75°C/W (SOIC) 115°C/W (SSOP) θJC Thermal Impedance . . . 25°C/W (SOIC) 35°C/W (SSOP) Lead Temperature, Soldering Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C +2.1V CL 50pF 200µA IOH Figure 1. Load Circuit for Digital Output Timing Specifications PIN CONFIGURATION FOR DIP, SOIC AND SSOP CONVST 1 28 BUSY WR 2 27 CLKIN RD 3 26 DB11 CS 4 25 DB10 REFIN/REFOUT 5 AD7854 24 DB9 AVDD 6 TOP VIEW 23 DGND (Not to Scale) 22 DVDD AGND 7 CREF1 8 21 DB8 CREF2 9 20 DB7 AIN(+) 10 19 DB6 AIN(–) 11 18 DB5 HBEN 12 17 DB4 DB0 13 16 DB3 DB1 14 15 DB2 NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latchup. ORDERING GUIDE Model AD7854AQ AD7854SQ AD7854AR AD7854BR AD7854ARS AD7854LAQ3 AD7854LAR3 AD7854LARS3 EVAL-AD7854CB4 EVAL-CONTROL BOARD5 Temperature Range1 Linearity Error (LSB) Power Dissipation (mW) Package Option2 –40°C to +85°C –55°C to +125°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 1 1 1 1/2 1 1 1 1 15 15 15 15 15 5.5 5.5 5.5 Q-28 Q-28 R-28 R-28 RS-28 Q-28 R-28 RS-28 NOTES 1 Linearity error refers to the integral linearity error. 2 Q = Cerdip; R = SOIC; RS = SSOP. 3 L signifies the low power version. 4 This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes. 5 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. For more information on Analog Devices products and evaluation boards visit our World Wide Web home page at http://www.analog.com. REV. B –5– AD7854/AD7854L PIN FUNCTION DESCRIPTIONS Pin Mnemonic Description 1 CONVST Convert Start. Logic input. A low to high transition on this input puts the track/hold into its hold mode and starts conversion. When this input is not used, it should be tied to DVDD. 2 WR Write Input. Active low logic input. Used in conjunction with CS and HBEN to write to internal registers. 3 RD Read Input. Active low logic input. Used in conjunction with CS and HBEN to read from internal registers. 4 CS Chip Select Input. Active low logic input. The device is selected when this input is active. 5 REFIN/ REFOUT Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V and this appears at the pin. This pin can be overdriven by an external reference and can be taken as high as AVDD. When this pin is tied to AVDD, then the CREF1 pin should also be tied to AVDD. 6 AVDD Analog Positive Supply Voltage, +3.0 V to +5.5 V. 7 AGND Analog Ground. Ground reference for track/hold, reference and DAC. 8 CREF1 Reference Capacitor (0.1 µF multilayer ceramic). This external capacitor is used as a charge source for the internal DAC. The capacitor should be tied between the pin and AGND. 9 CREF2 Reference Capacitor (0.01 µF ceramic disc). This external capacitor is used in conjunction with the on-chip reference. The capacitor should be tied between the pin and AGND. 10 AIN(+) Analog Input. Positive input of the pseudo-differential analog input. Cannot go below AGND or above AVDD at any time, and cannot go below AIN(–) when the unipolar input range is selected. 11 AIN(–) Analog Input. Negative input of the pseudo-differential analog input. Cannot go below AGND or above AVDD at any time. 12 HBEN High Byte Enable Input. The AD7854 operates in byte mode only but outputs 12 bits of data during a read cycle with HBEN low. When HBEN is high, then the high byte of data that is written to or read from the part is on DB0 to DB7. When HBEN is low, then the lowest byte of data being written to the part is on DB0 to DB7. If reading from the part with HBEN low, then the lowest 12 bits of data appear on pins DB0 to DB11. This allows a single read from the ADC or from the control register in a 16-bit bus system. However, two reads are needed to access the calibration registers. Also, two writes are necessary to write to any of the registers. 13–21 DB0–DB8 Data Bits 0 to 8. Three state data I/O pins that are controlled by CS, RD, WR and HBEN. Data output is straight binary (unipolar mode) or twos complement (bipolar mode). 22 DVDD Digital Supply Voltage, +3.0 V to +5.5 V. 23 DGND Digital Ground. Ground reference point for digital circuitry. 24–26 DB9–DB11 Data Bits 9 to 11. Three state data output pins that are controlled by CS, RD and HBEN. Data output is straight binary (unipolar mode) or twos complement (bipolar mode). These output pins should be tied to DVDD via 100 kΩ resistors when the AD7854/AD7854L is being interfaced to an 8-bit data bus. 27 CLKIN Master Clock Signal for the device (4 MHz for AD7854, 1.8 MHz for AD7854L). Sets the conversion and calibration times. 28 BUSY Busy Output. The busy output is triggered high by the falling edge of CONVST and remains high until conversion is completed. BUSY is also used to indicate when the AD7854/AD7854L has completed its onchip calibration sequence. –6– REV. B AD7854/AD7854L Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7854/AD7854L, it is defined as: TERMINOLOGY Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition, and full scale, a point 1/2 LSB above the last code transition. 2 THD (dB) = 20 log Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. 2 2 2 V1 where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonics. Unipolar Offset Error This is the deviation of the first code transition (00 . . . 000 to 00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB) when operating in the unipolar mode. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak. Unipolar Gain Error This is the deviation of the last code transition (111 . . . 110 to 111 . . . 111) from the ideal, i.e., AIN(–) +VREF/2 – 1.5 LSB, after the unipolar offset error has been adjusted out. Bipolar Positive Full-Scale Error This applies to the bipolar modes only and is the deviation of the last code transition from the ideal AIN(+) voltage. For bipolar mode, the ideal AIN(+) voltage is (AIN(–) +VREF/2 – 1.5 LSB). Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). Negative Full-Scale Error This applies to the bipolar mode only and is the deviation of the first code transition (10 . . . 000 to 10 . . . 001) from the ideal AIN(+) voltage (AIN(–) – VREF/2 + 0.5 LSB). Bipolar Zero Error This is the deviation of the midscale transition (all 0s to all 1s) from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB). Testing is performed using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs. Track/Hold Acquisition Time The track/hold amplifier returns into track mode and the end of conversion. Track/Hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within ± 1/2 LSB, after the end of conversion. Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus for a 12-bit converter, this is 74 dB. REV. B 2 (V 2 +V 3 +V 4 +V 5 +V 6 ) –7– AD7854/AD7854L AD7854/AD7854L ON-CHIP REGISTERS The AD7854/AD7854L powers up with a set of default conditions, and the user need not ever write to the device. In this case the AD7854/AD7854L will operate as a read-only ADC. The WR pin should be tied to DVDD for operating the AD7854/AD7854L as a read-only ADC. Extra features and flexibility such as performing different power-down options, different types of calibrations including system calibration, and software conversion start can be selected by writing to the part. The AD7854/AD7854L contains a control register, ADC output data register, status register, test register and 10 calibration registers. The control register is write-only, the ADC output data register and the status register are read-only, and the test and calibration registers are both read/write registers. The test register is used for testing the part and should not be written to. Addressing the On-Chip Registers Writing To write to the AD7854/AD7854L, a 16-bit word of data must be transferred. This transfer consists of two 8-bit writes. The first 8 bits of data that are written must consist of the 8 LSBs of the 16-bit word and the second 8 bits that are written must consist of the 8 MSBs of the 16-bit word. For each of these 8-bit writes, the data is placed on Pins DB0 to DB7, Pin DB0 being the LSB of each transfer and Pin DB7 being the MSB of each transfer. The two MSBs of the 16-bit word, ADDR1 and ADDR0, are decoded to determine which register is addressed, and the 14 LSBs are written to the addressed register. Table I shows the decoding of the address bits, while Figure 2 shows the overall write register hierarchy. Table I. Write Register Addressing ADDR1 ADDR0 Comment 0 0 1 0 1 0 1 1 This combination does not address any register. This combination addresses the TEST REGISTER. The 14 LSBs of data are written to the test register. This combination addresses the CALIBRATION REGISTER. The 14 least significant data bits are written to the selected calibration register. This combination addresses the CONTROL REGISTER. The 14 least significant data bits are written to the control register. Reading To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address bits while Figure 3 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be from the ADC output data register. Note: when reading from the calibration registers, the low byte must always be read first. Once the read selection bits are set in the control register all subsequent read operations that follow are from the selected register until the read selection bits are changed in the control register. Table II. Read Register Addressing RDSLT1 RDSLT0 Comment 0 0 0 1 1 1 0 1 All successive read operations are from the ADC OUTPUT DATA REGISTER. This is the default powerup setting. There is always four leading zeros when reading from the ADC output data register. All successive read operations are from the TEST REGISTER. All successive read operations are from the CALIBRATION REGISTERS. All successive read operations are from the STATUS REGISTER. RDSLT1, RDSLT0 DECODE ADDR1, ADDR0 DECODE 01 10 TEST REGISTER GAIN(1) OFFSET(1) DAC(8) CALSLT1, CALSLT0 DECODE 00 11 CALIBRATION REGISTERS GAIN(1) OFFSET(1) 01 OFFSET(1) 10 00 CONTROL REGISTER ADC OUTPUT DATA REGISTER 01 GAIN(1) OFFSET(1) DAC(8) GAIN(1) 11 CALSLT1, CALSLT0 DECODE 10 00 11 CALIBRATION REGISTERS TEST REGISTER GAIN(1) OFFSET(1) 01 OFFSET(1) 10 CONTROL REGISTER GAIN(1) 11 Figure 3. Read Register Hierarchy/Address Decoding Figure 2. Write Register Hierarchy/Address Decoding –8– REV. B AD7854/AD7854L CONTROL REGISTER The arrangement of the control register is shown below. The control register is a write only register and contains 14 bits of data. The control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register is described below. The power-up status of all bits is 0. MSB ZERO ZERO RDSLT0 AMODE ZERO ZERO PMGT1 PMGT0 RDSLT1 CONVST CALMD CALSLT1 CALSLT0 STCAL LSB Control Register Bit Function Description Bit Mnemonic Comment 13 12 11 10 ZERO ZERO ZERO ZERO These four bits must be set to 0 when writing to the control register. 9 8 PMGT1 PMGT0 Power Management Bits. These two bits are used for putting the part into various power-down modes (See Power-Down section for more details). 7 6 RDSLT1 RDSLT0 Theses two bits determine which register is addressed for the read operations. See Table II. 5 AMODE Analog Mode Bit. This pin allows two different analog input ranges to be selected. A logic 0 in this bit position selects range 0 to VREF (i.e., AIN(+) – AIN(–) = 0 to VREF). In this range AIN(+) cannot go below AIN(–) and AIN(–) cannot go below AGND and data coding is straight binary. A logic 1 in this bit position selects range –VREF/2 to +VREF/2 (i.e., AIN(+) – AIN(–) = –VREF /2 to +VREF/2). AIN(+) cannot go below AGND, so for this range, AIN(–) needs to be biased to at least +VREF/2 to allow AIN(+) to go as low as AIN(–) –VREF/2 V. Data coding is twos complement for this range. 4 CONVST Conversion Start Bit. A logic one in this bit position starts a single conversion, and this bit is automatically reset to 0 at the end of conversion. This bit may also used in conjunction with system calibration (see Calibration section). 3 CALMD Calibration Mode Bit. A 0 here selects self-calibration and a 1 selects a system calibration (see Table III). 2 1 0 CALSLT1 CALSLT0 STCAL Calibration Selection Bits and Start Calibration Bit. These bits have two functions. With the STCAL bit set to 1, the CALSLT1 and CALSLT0 bits determine the type of calibration performed by the part (see Table III). The STCAL bit is automatically reset to 0 at the end of calibration. With the STCAL bit set to 0, the CALSLT1 and CALSLT0 bits are decoded to address the calibration register for read/write of calibration coefficients (see section on the calibration registers for more details). Table III. Calibration Selection CALMD CALSLT1 CALSLT0 Calibration Type 0 0 0 A full internal calibration is initiated. First the internal DAC is calibrated, then the internal gain error and finally the internal offset error are removed. This is the default setting. 0 0 1 First the internal gain error is removed, then the internal offset error is removed. 0 1 0 The internal offset error only is calibrated out. 0 1 1 The internal gain error only is calibrated out. 1 0 0 A full system calibration is initiated. First the internal DAC is calibrated, followed by the system gain error calibration, and finally the system offset error calibration. 1 0 1 First the system gain error is calibrated out followed by the system offset error. 1 1 0 The system offset error only is removed. 1 1 1 The system gain error only is removed. REV. B –9– AD7854/AD7854L STATUS REGISTER The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The status register is selected by writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the bits in the status register are described below. The power-up status of all bits is 0. START WRITE TO CONTROL REGISTER SETTING RDSLT0 = RDSLT1 = 1 READ STATUS REGISTER Figure 4. Flowchart for Reading the Status Register MSB ZERO ZERO ZERO ZERO ZERO ZERO PMGT1 PMGT0 ONE ONE AMODE BUSY CALMD CALSLT1 CALSLT0 STCAL LSB Status Register Bit Function Description Bit Mnemonic Comment 15 14 13 12 11 10 ZERO ZERO ZERO ZERO ZERO ZERO These six bits are always 0. 9 8 PMGT1 PMGT0 Power Management Bits. These bits will indicate if the part is in a power-down mode or not. See Table VI in Power-Down Section for description. 7 6 ONE ONE Both these bits are always 1. 5 AMODE Analog Mode Bit. When this bit is a 0, the device is set up for the unipolar analog input range. When this bit is a 1, the device is set up for the bipolar analog input range. 4 BUSY Conversion/Calibration Busy Bit. When this bit is 1, this indicates that there is a conversion or calibration in progress. When this bit is 0, there is no conversion or calibration in progress. 3 CALMD Calibration Mode Bit. A 0 in this bit indicates a self-calibration is selected, and a 1 in this bit indicates a system calibration is selected (see Table III). 2 1 0 CALSLT1 CALSLT0 STCAL Calibration Selection Bits and Start Calibration Bit. The STCAL bit is read as a 1 if a calibration is in progress and as a 0 if there is no calibration in progress. The CALSLT1 and CALSLT0 bits indicate which of the calibration registers are addressed for reading and writing (see section on the Calibration Registers for more details). –10– REV. B AD7854/AD7854L CALIBRATION REGISTERS The AD7854/AD7854L has 10 calibration registers in all, 8 for the DAC, 1 for offset and 1 for gain. Data can be written to or read from all 10 calibration registers. In self- and system calibration, the part automatically modifies the calibration registers; only if the user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers. Addressing the Calibration Registers The calibration selection bits in the control register CALSLT1 and CALSLT0 determine which of the calibration registers are addressed (See Table IV). The addressing applies to both the read and write operations for the calibration registers. The user should not attempt to read from and write to the calibration registers at the same time. Table IV. Calibration Register Addressing CALSLT1 CALSLT0 Comment 0 0 1 1 0 1 0 1 This combination addresses the Gain (1), Offset (1) and DAC Registers (8). Ten registers in total. This combination addresses the Gain (1) and Offset (1) Registers. Two registers in total. This combination addresses the Offset Register. One register in total. This combination addresses the Gain Register. One register in total. Writing to/Reading from the Calibration Registers When writing to the calibration registers a write to the control register is required to set the CALSLT0 and CALSLT1 bits. When reading from the calibration registers a write to the control register is required to set the CALSLT0 and CALSLT1 bits and also to set the RDSLT1 and RDSLT0 bits to 10 (this addresses the calibration registers for reading). The calibration register pointer is reset on writing to the control register setting the CALSLT1 and CALSLT0 bits, or upon completion of all the calibration register write/read operations. When reset it points to the first calibration register in the selected write/read sequence. The calibration register pointer points to the gain calibration register upon reset in all but one case, this case being where the offset calibration register is selected on its own (CALSLT1 = 1, CALSLT0 = 0). Where more than one calibration register is being accessed, the calibration register pointer is automatically incremented after each full calibration register write/read operation. The calibration register address pointer is incremented after the high byte read or write operation in byte mode. Therefore when reading from or writing to the calibration registers, the low byte transfer must be carried out first, i.e., HBEN is at logic zero. The order in which the 10 calibration registers are arranged is shown in Figure 5. Read/Write operations may be aborted at any time before all the calibration registers have been accessed, and the next control register write operation resets the calibration register pointer. The flowchart in Figure 6 shows the sequence for writing to the calibration registers. Figure 7 shows the sequence for reading from the calibration registers. When reading from the calibration registers there are always two leading zeros for each of the registers. CALIBRATION REGISTERS CAL REGISTER ADDRESS POINTER GAIN REGISTER (1) OFFSET REGISTER (2) DAC 1ST MSB REGISTER (3) DAC 8TH MSB REGISTER (10) CALIBRATION REGISTER ADDRESS POINTER POSITION IS DETERMINED BY THE NUMBER OF CALIBRATION REGISTERS ADDRESSED AND THE NUMBER OF READ/WRITE OPERATIONS. Figure 5. Calibration Register Arrangement REV. B –11– START WRITE TO CONTROL REGISTER SETTING STCAL = 0 AND CALSLT1, CALSLT0 = 00, 01, 10, 11 CAL REGISTER POINTER IS AUTOMATICALLY RESET WRITE TO CAL REGISTER (ADDR1 = 1, ADDR0 = 0) CAL REGISTER POINTER IS AUTOMATICALLY INCREMENTED LAST REGISTER WRITE OPERATION OR ABORT ? NO YES FINISHED Figure 6. Flowchart for Writing to the Calibration Registers AD7854/AD7854L has a weighting of 1.25%, and so on down to the LSB which has a weighting of 0.0006%. This gives a resolution of ± 0.0006% of VREF approximately. The resolution can also be expressed as ± (0.05 × VREF)/213 volts. This equals ± 0.015 mV, with a 2.5 V reference. The maximum offset that can be compensated for is ± 5% of the reference voltage, which equates to ± 125 mV with a 2.5 V reference and ± 250 mV with a 5 V reference. START WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1, RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11 CAL REGISTER POINTER IS AUTOMATICALLY RESET Q. If a +20 mV offset is present in the analog input signal and the reference voltage is 2.5 V, what code needs to be written to the offset register to compensate for the offset ? READ CAL REGISTER CAL REGISTER POINTER IS AUTOMATICALLY INCREMENTED LAST REGISTER READ OPERATION OR ABORT ? A. 2.5 V reference implies that the resolution in the offset register is 5% × 2.5 V/213 = 0.015 mV. +20 mV/0.015 mV = 1310.72; rounding to the nearest number gives 1311. In binary terms this is 00 0101 0001 1111, therefore increase the offset register by 00 0101 0001 1111. NO This method of compensating for offset in the analog input signal allows for fine tuning the offset compensation. If the offset on the analog input signal is known, there is no need to apply the offset voltage to the analog input pins and do a system calibration. The offset compensation can take place in software. YES FINISHED Figure 7. Flowchart for Reading from the Calibration Registers Adjusting the Gain Calibration Register Adjusting the Offset Calibration Register The offset calibration register contains 16 bits. The two MSBs are zero and the 14 LSBs contain offset data. By changing the contents of the offset register, different amounts of offset on the analog input signal can be compensated for. Decreasing the number in the offset calibration register compensates for negative offset on the analog input signal, and increasing the number in the offset calibration register compensates for positive offset on the analog input signal. The default value of the offset calibration register is 0010 0000 0000 0000 approximately. This is not the exact value, but the value in the offset register should be close to this value. Each of the 14 data bits in the offset register is binary weighted; the MSB has a weighting of 5% of the reference voltage, the MSB-1 has a weighting of 2.5%, the MSB-2 The gain calibration register contains 16 bits. The two MSBs are zero and the 14 LSBs contain gain data. As in the offset calibration register the data bits in the gain calibration register are binary weighted, with the MSB having a weighting of 2.5% of the reference voltage. The gain register value is effectively multiplied by the analog input to scale the conversion result over the full range. Increasing the gain register compensates for a smaller analog input range and decreasing the gain register compensates for a larger input range. The maximum analog input range that the gain register can compensate for is 1.025 times the reference voltage, and the minimum input range is 0.975 times the reference voltage. –12– REV. B AD7854/AD7854L CIRCUIT INFORMATION The AD7854/AD7854L is a fast, 12-bit single supply A/D converter. The part requires an external 4 MHz/1.8 MHz master clock (CLKIN), two CREF capacitors, a CONVST signal to start conversion and power supply decoupling capacitors. The part provides the user with track/hold, on-chip reference, calibration features, A/D converter and parallel interface logic functions on a single chip. The A/D converter section of the AD7854/ AD7854L consists of a conventional successive-approximation converter based around a capacitor DAC. The AD7854/ AD7854L accepts an analog input range of 0 to +VREF. VREF can be tied to VDD. The reference input to the part connected via a 150 kΩ resistor to the internal 2.5 V reference and to the on-chip buffer. A major advantage of the AD7854/AD7854L is that a conversion can be initiated in software as well as applying a signal to the CONVST pin. The part is available in a 28-Lead SSOP package, and this offers the user considerable space saving advantages over alternative solutions. The AD7854L version typically consumes only 5.5 mW making it ideal for battery-powered applications. When using the software conversion start for maximum throughput, the user must ensure the control register write operation extends beyond the falling edge of BUSY. The falling edge of BUSY resets the CONVST bit to 0 and allows it to be reprogrammed to 1 to start the next conversion. TYPICAL CONNECTION DIAGRAM Figure 8 shows a typical connection diagram for the AD7854/ AD7854L. The AGND and the DGND pins are connected together at the device for good noise suppression. The first CONVST applied after power-up starts a self-calibration sequence. This is explained in the calibration section of the data sheet. Applying the RD and CS signals causes the conversion result to be output on the 12 data pins. Note that after power is applied to AVDD and DVDD, and the CONVST signal is applied, the part requires (70 ms + 1/sample rate) for the internal reference to settle and for the self-calibration to be completed. 4MHz/1.8MHz OSCILLATOR ANALOG SUPPLY +3V TO +5V 10F 0.1F 0.1F CONVERTER DETAILS CONVERSION START SIGNAL The master clock for the part is applied to the CLKIN pin. Conversion is initiated on the AD7854/AD7854L by pulsing the CONVST input or by writing to the control register and setting the CONVST bit to 1. On the rising edge of CONVST (or at the end of the control register write operation), the on-chip track/ hold goes from track to hold mode. The falling edge of the CLKIN signal which follows the rising edge of CONVST initates the conversion, provided the rising edge of CONVST (or WR when converting via the control register) occurs typically at least 10 ns before this CLKIN edge. The conversion takes 16.5 CLKIN periods from this CLKIN falling edge. If the 10 ns setup time is not met, the conversion takes 17.5 CLKIN periods. AVDD DVDD 0V TO 2.5V INPUT AIN(–) 0.1F 0.01F HBEN AD7854/ AD7854L CS RD CREF2 WR C/P AGND DB0 DGND DB11 REFIN /REFOUT OPTIONAL EXTERNAL REFERENCE AD780/ REF192 0.1nF EXTERNAL REFERENCE 0.1F ON-CHIP REFERENCE Figure 8. Typical Circuit For applications where power consumption is a major concern, the power-down options can be programmed by writing to the part. See Power-Down section for more detail on low power applications. With the AD7854L, 100 kSPS throughput can be obtained as follows: the CLKIN and CONVST signals are arranged to give a conversion time of 16.5 CLKIN periods as described above and 1.5 CLKIN periods are allowed for the acquisition time. With a 1.8 MHz clock, this gives a full cycle time of 10 µs, which equates to a throughput rate of 100 kSPS. REV. B CREF1 CONVST BUSY The time required by the AD7854/AD7854L to acquire a signal depends upon the source resistance connected to the AIN(+) input. Please refer to the Acquisition Time section for more details. When a conversion is completed, the BUSY output goes low, and the result of the conversion can be read by accessing the data through the data bus. To obtain optimum performance from the part, read or write operations should not occur during the conversion or less than 200 ns prior to the next CONVST rising edge. Reading/writing during conversion typically degrades the Signal to (Noise + Distortion) by less than 0.5 dBs. The AD7854 can operate at throughput rates of over 200 kSPS (up to 100 kSPS for the AD7854L). CLKIN AIN(+) –13– AD7854/AD7854L ANALOG INPUT –72 125⍀ TRACK AIN(+) 125⍀ CAPACITOR DAC SW1 AIN(–) 20pF NODE A SW2 HOLD –76 –80 RIN = 1k⍀ –84 –88 –92 RIN = 50⍀, 10nF AS IN FIGURE 13 0 20 40 60 INPUT FREQUENCY – kHz 80 100 Figure 10. THD vs. Analog Input Frequency The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases. Figure 10 shows a graph of the total harmonic distortion vs. analog input signal frequency for different source impedances. With the setup as in Figure 11, the THD is at the –90 dB level. With a source impedance of 1 kΩ and no capacitor on the AIN(+) pin, the THD increases with frequency. In a single supply application (both 3 V and 5 V), the V+ and V– of the op amp can be taken directly from the supplies to the AD7854/AD7854L which eliminates the need for extra external power supplies. When operating with rail-to-rail inputs and outputs at frequencies greater than 10 kHz, care must be taken in selecting the particular op amp for the application. In particular, for single supply applications the input amplifiers should be connected in a gain of –1 arrangement to get the optimum performance. Figure 11 shows the arrangement for a single supply application with a 50 Ω and 10 nF low-pass filter (cutoff frequency 320 kHz) on the AIN(+) pin. Note that the 10 nF is a capacitor with good linearity to ensure good ac performance. Recommended single supply op amps are the AD820 and the AD820-3V. HOLD TRACK THD VS. FREQUENCY FOR DIFFERENT SOURCE IMPEDANCES THD – dB The equivalent analog input circuit is shown in Figure 9. During the acquisition interval the switches are both in the track position and the AIN(+) charges the 20 pF capacitor through the 125 Ω resistance. On the rising edge of CONVST switches SW1 and SW2 go into the hold position retaining charge on the 20 pF capacitor as a sample of the signal on AIN(+). The AIN(–) is connected to the 20 pF capacitor, and this unbalances the voltage at Node A at the input of the comparator. The capacitor DAC adjusts during the remainder of the conversion cycle to restore the voltage at Node A to the correct value. This action transfers a charge, representing the analog input signal, to the capacitor DAC which in turn forms a digital representation of the analog input signal. The voltage on the AIN(–) pin directly influences the charge transferred to the capacitor DAC at the hold instant. If this voltage changes during the conversion period, the DAC representation of the analog input voltage is altered. Therefore it is most important that the voltage on the AIN(–) pin remains constant during the conversion period. Furthermore, it is recommended that the AIN(–) pin is always connected to AGND or to a fixed dc voltage. COMPARATOR AGND Figure 9. Analog Input Equivalent Circuit Acquisition Time The track-and-hold amplifier enters its tracking mode on the falling edge of the BUSY signal. The time required for the track-and-hold amplifier to acquire an input signal depends on how quickly the 20 pF input capacitance is charged. There is a minimum acquisition time of 400 ns. For large source impedances, >2 kΩ, the acquisition time is calculated using the formula: tACQ = 9 × (RIN + 125 Ω) × 20 pF +3V TO +5V 10F where RIN is the source impedance of the input signal, and 125 Ω, 20 pF is the input R, C. 0.1F 10k⍀ VIN (–VREF /2 TO +VREF /2) DC/AC Applications For dc applications, high source impedances are acceptable, provided there is enough acquisition time between conversions to charge the 20 pF capacitor. For example with RIN = 5 kΩ, the required acquisition time is 922 ns. 10k⍀ 10k⍀ VREF /2 10k⍀ For ac applications, removing high frequency components from the analog input signal is recommended by use of an RC lowpass filter on the AIN(+) pin, as shown in Figure 11. In applications where harmonic distortion and signal to noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. They may require the use of an input buffer amplifier. The choice of the amplifier is a function of the particular application. –14– V+ 50⍀ IC1 V– AD820 AD820-3V 10nF (NPO) TO AIN(+) OF AD7854/AD7854L Figure 11. Analog Input Buffering REV. B AD7854/AD7854L Input Ranges Transfer Functions The analog input range for the AD7854/AD7854L is 0 V to VREF in both the unipolar and bipolar ranges. For the unipolar range the designed code transitions occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . . FS – 3/2 LSBs). The output coding is straight binary for the unipolar range with 1 LSB = FS/4096 = 3.3 V/4096 = 0.8 mV when VREF = 3.3 V. The ideal input/ output transfer characteristic for the unipolar range is shown in Figure 14. The only difference between the unipolar range and the bipolar range is that in the bipolar range the AIN(–) should be biased up to at least +VREF/2 and the output coding is twos complement (see Table V and Figures 14 and 15). Table V. Analog Input Connections OUTPUT CODE Analog Input Range Input Connections AIN(+) AIN(–) Connection Diagram 0 V to VREF1 ± VREF/22 VIN VIN Figure 12 Figure 13 AGND VREF/2 111...111 111...110 111...101 111...100 NOTES 1 Output code format is straight binary. 2 Range is ±VREF/2 biased about VREF/2. Output code format is twos complement. Note that the AIN(–) pin on the AD7854/AD7854L can be biased up above AGND in the unipolar mode, or above VREF/2 in bipolar mode if required. The advantage of biasing the lower end of the analog input range away from AGND is that the analog input does not have to swing all the way down to AGND. Thus, in single supply applications the input amplifier does not have to swing all the way down to AGND. The upper end of the analog input range is shifted up by the same amount. Care must be taken so that the bias applied does not shift the upper end of the analog input above the AVDD supply. In the case where the reference is the supply, AVDD, the AIN(–) should be tied to AGND in unipolar mode or to AVDD/2 in bipolar mode. AIN(+) VIN = 0 TO VREF AIN(–) TRACK AND HOLD AMPLIFIER DB0 . . . DB11 1LSB = 000...011 FS 4096 000...010 000...001 000...000 0V 1LSB +FS –1LSB VIN = (AIN(+) – AIN(–)), INPUT VOLTAGE Figure 14. AD7854/AD7854L Unipolar Transfer Characteristic Figure 13 shows the AD7854/AD7854L’s ± VREF/2 bipolar analog input configuration. AIN(+) cannot go below 0 V, so for the full bipolar range, AIN(–) should be biased to at least +VREF /2. Once again the designed code transitions occur midway between successive integer LSB values. The output coding is twos complement with 1 LSB = 4096 = 3.3 V/4096 = 0.8 mV. The ideal input/output transfer characteristic is shown in Figure 15. STRAIGHT BINARY FORMAT OUTPUT CODE 011...111 AD7854/AD7854L 011...110 (VREF/2) – 1LSB Figure 12. 0 to VREF Unipolar Input Configuration 000...001 000...000 0V + FS – 1LSB 111...111 (VREF/2) + 1 LSB AIN(+) TRACK AND HOLD AMPLIFIER AIN(–) . . . VIN = 0 TO VREF DB0 DB11 VREF/2 2’S COMPLEMENT FORMAT FS = VREFV 000...001 FS 1LSB = 4096 000...000 AD7854/AD7854L VREF/2 VIN = (AIN(+) – AIN(–)), INPUT VOLTAGE Figure 15. AD7854/AD7854L Bipolar Transfer Characteristic Figure 13. ±VREF/2 about VREF/2 Bipolar Input Configuration REV. B 000...010 –15– AD7854/AD7854L REFERENCE SECTION AD7854/AD7854L PERFORMANCE CURVES For specified performance, it is recommended that when using an external reference, this reference should be between 2.3 V and the analog supply AVDD. The connections for the reference pins are shown below. If the internal reference is being used, the REFIN/REFOUT pin should be decoupled with a 100 nF capacitor to AGND very close to the REFIN/REFOUT pin. These connections are shown in Figure 16. Figure 18 shows a typical FFT plot for the AD7854 at 200 kHz sample rate and 10 kHz input frequency. 0 –40 SNR – dB If the internal reference is required for use external to the ADC, it should be buffered at the REFIN/REFOUT pin and a 100 nF capacitor should be connected from this pin to AGND. The typical noise performance for the internal reference, with 5 V supplies is 150 nV/√Hz @ 1 kHz and dc noise is 100 µV p-p. ANALOG SUPPLY +3V TO +5V AVDD = DVDD = 3.3V FSAMPLE = 200kHz FIN = 10kHz SNR = 72.04dB THD = –88.43dB –20 –60 –80 –100 10F 0.1F 0.1F –120 CREF1 0.1F CREF2 0.01F AVDD 20 DVDD 40 60 FREQUENCY – kHz 80 100 Figure 18. FFT Plot Figure 19 shows the SNR versus frequency for different supplies and different external references. AD7854/ AD7854L 74 REFIN/REFOUT 0.1F 0 AVDD = DVDD WITH 2.5V REFERENCE UNLESS STATED OTHERWISE 73 S(N+D) RATIO – dB Figure 16. Relevant Connections Using Internal Reference The REFIN/REFOUT pin may be overdriven by connecting it to an external reference. This is possible due to the series resistance from the REFIN/REFOUT pin to the internal reference. This external reference can be in the range 2.3 V to AVDD. When using AVDD as the reference source, the 10 nF capacitor from the REFIN/REFOUT pin to AGND should be as close as possible to the REFIN/REFOUT pin, and also the CREF1 pin should be connected to AVDD to keep this pin at the same voltage as the reference. The connections for this arrangement are shown in Figure 17. When using AVDD it may be necessary to add a resistor in series with the AVDD supply. This has the effect of filtering the noise associated with the AVDD supply. Note that when using an external reference, the voltage present at the REFIN/REFOUT pin is determined by the external reference source resistance and the series resistance of 150 kΩ from the REFIN/REFOUT pin to the internal 2.5 V reference. Thus, a low source impedance external reference is recommended. ANALOG SUPPLY +3V TO +5V 10F 0.1F 0.1F 0.01F 0.01F 0.1F CREF1 CREF2 AVDD 5.0V SUPPLIES, WITH 5V REFERENCE 72 5.0V SUPPLIES 5.0V SUPPLIES, L VERSION 71 70 3.3V SUPPLIES 69 0 20 40 60 INPUT FREQUENCY – kHz 80 100 Figure 19. SNR vs. Frequency Figure 20 shows the power supply rejection ratio versus frequency for the part. The power supply rejection ratio is defined as the ratio of the power in ADC output at frequency f to the power of a full-scale sine wave: PSRR (dB) = 10 log (Pf/Pfs) Pf = Power at frequency f in ADC output, Pfs = power of a fullscale sine wave. Here a 100 mV peak-to-peak sine wave is coupled onto the AVDD supply while the digital supply is left unaltered. Both the 3.3 V and 5.0 V supply performances are shown. DVDD AD7854/ AD7854L REFIN/REFOUT Figure 17. Relevant Connections, AVDD as the Reference –16– REV. B AD7854/AD7854L POWER-UP TIMES Using an External Reference –78 AVDD = DVDD = 3.3V/5.0V, 100mV pk-pk SINE WAVE ON AVDD When the AD7854/AD7854L are powered up, the parts are powered up from one of two conditions. First, when the power supplies are initially powered up and, secondly, when the parts are powered up from a software power-down (see last section). –80 PSRR – dB –82 3.3V –84 5.0V –86 –88 –90 0 20 40 60 INPUT FREQUENCY – kHz 80 100 Figure 20. PSRR vs. Frequency POWER-DOWN OPTIONS The AD7854/AD7854L provides flexible power management to allow the user to achieve the best power performance for a given throughput rate. The power management options are selected by programming the power management bits, PMGT1 and PMGT0, in the control register. Table VI summarizes the powerdown options that are available and how they can be selected by programming the power management bits in the control register. The AD7854/AD7854L can be fully or partially powered down. When fully powered down, all the on-chip circuitry is powered down and IDD is 10 µA typ. If a partial power-down is selected, then all the on-chip circuitry except the reference is powered down and IDD is 400 µA typ with the external clock running. Additional power savings may be made if the external clock is off. The choice of full or partial power-down does not give any significant improvement in the throughput rate which can be achieved with a power-down between conversions. This is discussed in the next section—Power-Up Times. But a partial power-down does allow the on-chip reference to be used externally even though the rest of the AD7854/AD7854L circuitry is powered down. It also allows the AD7854/AD7854L to be powered up faster after a long power-down period when using the on-chip reference (See Power-Up Times section—Using the Internal (On-Chip) Reference). As can be seen from Table VI, the AD7854/AD7854L can be programmed for normal operation, a full power-down at the end of a conversion, a partial power-down at the end of a conversion and finally a full power-down whether converting or not. The full and partial power-down at the end of a conversion can be used to achieve a superior power performance at slower throughput rates, in the order of 50 kSPS (see Power vs. Throughput Rate section of this data sheet). Table VI. Power Management Options PMGT1 PMGT0 Bit Bit Comment 0 0 1 1 Normal Operation Full Power-Down After a Conversion Full Power-Down Partial Power-Down After a Conversion REV. B 0 1 0 1 When AVDD and DVDD are powered up, the AD7854/AD7854L enters a mode whereby the CONVST signal initiates a timeout followed by a self-calibration. The total time taken for this timeout and calibration is approximately 70 ms—see Calibration on Power-Up in the calibration section of this data sheet. The powerup calibration mode can be disabled if the user writes to the control register before a CONVST signal is applied. If the timeout and self-calibration are disabled, then the user must take into account the time required by the AD7854/AD7854L to power up before a self-calibration is carried out. This power-up time is the time taken for the AD7854/AD7854L to power up when power is first applied (300 µs typ) or the time it takes the external reference to settle to the 12-bit level—whichever is the longer. The AD7854/AD7854L powers up from a full software powerdown in 5 µs typ. This limits the throughput which the part is capable of to 100 kSPS for the AD7854 and 60 kSPS for the AD7854L when powering down between conversions. Figure 21 shows how a full power-down between conversions is implemented using the CONVST pin. The user first selects the power-down between conversions option by setting the power management bits, PMGT1 and PMGT0, to 0 and 1 respectively in the control register (see last section). In this mode the AD7854/AD7854L automatically enters a full power-down at the end of a conversion, i.e., when BUSY goes low. The falling edge of the next CONVST pulse causes the part to power up. Assuming the external reference is left powered up, the AD7854/AD7854L should be ready for normal operation 5 µs after this falling edge. The rising edge of CONVST initiates a conversion so the CONVST pulse should be at least 5 µs wide. The part automatically powers down on completion of the conversion. Where the software convert start is used, the part may be powered up in software before a conversion is initiated. START CONVERSION ON RISING EDGE POWER-UP ON FALLING EDGE 5s 4.6s CONVST tCONVERT BUSY POWER-UP TIME NORMAL OPERATION FULL POWER-DOWN POWER-UP TIME Figure 21. Using the CONVST Pin to Power Up the AD7854 for a Conversion –17– AD7854/AD7854L Using The Internal (On-Chip) Reference POWER VS. THROUGHPUT RATE As in the case of an external reference the AD7854/AD7854L can power up from one of two conditions, power-up after the supplies are connected or power-up from a software power-down. The main advantage of a full power-down after a conversion is that it significantly reduces the power consumption of the part at lower throughput rates. When using this mode of operation, the AD7854/AD7854L is only powered up for the duration of the conversion. If the power-up time of the AD7854/AD7854L is taken to be 5 µs and it is assumed that the current during power-up is 4.5 mA/1.5 mA typ, then power consumption as a function of throughput can easily be calculated. The AD7854 has a conversion time of 4.6 µs with a 4 MHz external clock, and the AD7854L has a conversion time of 9 µs with a 1.8 MHz clock. This means the AD7854/AD7854L consumes 4.5 mA/ 1.5 mA typ for 9.6 µs/14 µs in every conversion cycle if the parts are powered down at the end of a conversion. The four graphs, Figures 24, 25, 26 and 27, show the power consumption of the AD7854 and AD7854L for VDD = 3 V as a function of throughput. Table VII lists the power consumption for various throughput rates. When using the on-chip reference and powering up when AVDD and DVDD are first connected, it is recommended that the powerup calibration mode be disabled as explained above. When using the on-chip reference, the power-up time is effectively the time it takes to charge up the external capacitor on the REFIN/ REFOUT pin. This time is given by the equation: tUP = 9 × R × C where R ≈ 150K and C = external capacitor. The recommended value of the external capacitor is 100 nF; this gives a power-up time of approximately 135 ms before a calibration is initiated and normal operation should commence. When CREF is fully charged, the power-up time from a software power-down reduces to 5 µs. This is because an internal switch opens to provide a high impedance discharge path for the reference capacitor during power-down—see Figure 22. An added advantage of the low charge leakage from the reference capacitor during power-down is that even though the reference is being powered down between conversions, the reference capacitor holds the reference voltage to within 0.5 LSBs with throughput rates of 100 samples/second and over with a full power-down between conversions. A high input impedance op amp like the AD707 should be used to buffer this reference capacitor if it is being used externally. Note, if the AD7854/AD7854L is left in its powered-down state for more than 100 ms, the charge on CREF will start to leak away and the power-up time will increase. If this longer power-up time is a problem, the user can use a partial power-down for the last conversion so the reference remains powered up. Throughput Rate Power AD7854 Power AD7854L 1 kSPS 10 kSPS 20 kSPS 50 kSPS 130 µW 1.3 mW 2.6 mW 6.48 mW 65 µW 650 µW 1.25 mW 3.2 mW 4MHz/1.8MHz OSCILLATOR ANALOG SUPPLY +3V TO +5V 10F 0.1F 0.1F CONVERSION START SIGNAL AVDD DVDD 0V TO 2.5V INPUT AD7854/ AD7854L SWITCH OPENS DURING POWER-DOWN REFIN/OUT Table VII. Power Consumption vs. Throughput AIN(–) ON-CHIP REFERENCE EXTERNAL CAPACITOR 0.1F TO OTHER CIRCUITRY BUF CLKIN AIN(+) 0.01F CREF1 CONVST HBEN AD7854/ AD7854L CREF2 CS RD WR C/P BUSY AGND Figure 22. On-Chip Reference During Power-Down DB0 DGND REFIN/REFOUT OPTIONAL EXTERNAL REFERENCE DB11 0.1nF EXTERNAL REFERENCE 0.1F ON-CHIP REFERENCE AD780/ REF192 FULL POWER-DOWN AFTER A CONVERSION PMGT1 = 0 PMGT0 = 1 Figure 23. Typical Low Power Circuit –18– REV. B AD7854/AD7854L 1 10 AD7854 FULL POWER-DOWN VDD = 3V CLKIN = 4MHz ON-CHIP REFERENCE AD7854 FULL POWER-DOWN VDD = 3V CLKIN = 4MHz ON-CHIP REFERENCE POWER – mW POWER – mW 1 0.1 0.01 0 2 4 6 8 THROUGHPUT RATE – kSPS 0.1 0.01 0 10 10 20 30 40 THROUGHPUT RATE – kSPS 50 Figure 26. Power vs. Throughput AD7854 Figure 24. Power vs. Throughput AD7854 10 AD7854L FULL POWER-DOWN VDD = 3V CLKIN = 1.8MHz 1 ON-CHIP REFERENCE AD7854L FULL POWER-DOWN VDD = 3V CLKIN = 1.8MHz ON-CHIP REFERENCE POWER – mW POWER – mW 1 0.1 0.01 0 4 8 12 16 THROUGHPUT RATE – kSPS 0.01 20 0 10 20 30 40 THROUGHPUT RATE – kSPS 50 Figure 27. Power vs. Throughput AD7854L Figure 25. Power vs. Throughput AD7854L REV. B 0.1 –19– AD7854/AD7854L CALIBRATION SECTION Calibration Overview AVDD = DVDD The automatic calibration that is performed on power-up ensures that the calibration options covered in this section are not required in a significant number of applications. A calibration does not have to be initiated unless the operating conditions change (CLKIN frequency, analog input mode, reference voltage, temperature, and supply voltages). The AD7854/AD7854L has a number of calibration features that may be required in some applications, and there are a number of advantages in performing these different types of calibration. First, the internal errors in the ADC can be reduced significantly to give superior dc performance; and second, system offset and gain errors can be removed. This allows the user to remove reference errors (whether it be internal or external reference) and to make use of the full dynamic range of the AD7854/AD7854L by adjusting the analog input range of the part for a specific system. There are two main calibration modes on the AD7854/AD7854L, self-calibration and system calibration. There are various options in both self-calibration and system calibration as outlined previously in Table III. All the calibration functions are initiated by writing to the control register and setting the STCAL bit to 1. The duration of each of the different types of calibration is given in Table IX for the AD7854 with a 4 MHz master clock. These calibration times are master clock dependent. Therefore the calibration times for the AD7854L (CLKIN = 1.8 MHz) are larger than those quoted in Table VIII. Table VIII. Calibration Times (AD7854 with 4 MHz CLKIN) Type of Self-Calibration or System Calibration Full Gain + Offset Offset Gain Time 31.25 ms 6.94 ms 3.47 ms 3.47 ms Automatic Calibration on Power-On The automatic calibration on power-on is initiated by the first CONVST pulse after the AVDD and DVDD power on. From the CONVST pulse the part internally sets a 32/72 ms (4 MHz/ 1.8 MHz CLKIN) timeout. This time is large enough to ensure that the internal reference has settled before the calibration is performed. However, if an external reference is being used, this reference must have stabilized before the automatic calibration is initiated. This first CONVST pulse also triggers the BUSY signal high, and once the 32/72 ms has elapsed, the BUSY signal goes low. At this point the next CONVST pulse that is applied initiates the automatic full self-calibration. This CONVST pulse again triggers the BUSY signal high, and after 32/72 ms (4 MHz/ 1.8 MHz CLKIN), the calibration is completed and the BUSY signal goes low. This timing arrangement is shown in Figure 28. The times in Figure 28 assume a 4 MHz/1.8 MHz CLKIN signal. POWER ON CONVERSION IS INITIATED ON THIS EDGE CONVST BUSY 32/72 ms 32/72 ms TIMEOUT PERIOD AUTOMATIC CALIBRATION DURATION Figure 28. Timing Arrangement for Autocalibration on Power-On The CONVST signal is gated with the BUSY internally so that as soon as the timeout is initiated by the first CONVST pulse all subsequent CONVST pulses are ignored until the BUSY signal goes low, 32/72 ms later. The CONVST pulse that follows after the BUSY signal goes low initiates an automatic full selfcalibration. This takes a further 32/72 ms. After calibration, the part is accurate to the 12-bit level and the specifications quoted on the data sheet apply, and all subsequent CONVST pulses initiate conversions. There is no need to perform another calibration unless the operating conditions change or unless a system calibration is required. This autocalibration at power-on is disabled if the user writes to the control register before the autocalibration is initiated. If the control register write operation occurs during the first 32/72 ms timeout period, then the BUSY signal stays high for the 32/72 ms and the CONVST pulse that follows the BUSY going low does not initiate an automatic full self-calibration. It initiates a conversion and all subsequent CONVST pulses initiate conversions as well. If the control register write operation occurs when the automatic full self-calibration is in progress, then the calibration is not be aborted; the BUSY signal remains high until the automatic full self-calibration is complete. Self-Calibration Description There are four different calibration options within the selfcalibration mode. There is a full self-calibration where the DAC, internal offset, and internal gain errors are removed. There is the (Gain + Offset) self-calibration which removes the internal gain error and then the internal offset errors. The internal DAC is not calibrated here. Finally, there are the self-offset and self-gain calibrations which remove the internal offset errors and the internal gain errors respectively. The internal capacitor DAC is calibrated by trimming each of the capacitors in the DAC. It is the ratio of these capacitors to each other that is critical, and so the calibration algorithm ensures that this ratio is at a specific value by the end of the calibration routine. For the offset and gain there are two separate capacitors, one of which is trimmed during offset calibration and one of which is trimmed during gain calibration. In bipolar mode the midscale error is adjusted by an offset calibration and the positive full-scale error is adjusted by the gain calibration. In unipolar mode the zero-scale error is adjusted by the offset calibration and the positive full-scale error is adjusted by the gain calibration. –20– REV. B AD7854/AD7854L Self-Calibration Timing MAX SYSTEM FULL SCALE IS ±2.5% FROM VREF Figure 29 shows the timing for a software full self-calibration. Here the BUSY line stays high for the full length of the selfcalibration. A self-calibration is initiated by writing to the control register and setting the STCAL bit to 1. The BUSY line goes high at the end of the write to the control register, and BUSY goes low when the full self-calibration is complete after a time tCAL as show in Figure 29. VREF + SYS OFFSET VREF – 1LSB ANALOG INPUT RANGE Hi-Z DATA VALID MAX SYSTEM OFFSET IS ±5% OF VREF Figure 30. System Offset Calibration Figure 31 shows a system gain calibration (assuming a system full scale greater than the reference voltage) where the analog input range has been increased after the system gain calibration is completed. A system full-scale voltage less than the reference voltage may also be accounted for a by a system gain calibration. WR DATA SYS OFFSET AGND MAX SYSTEM OFFSET IS ±5% OF VREF DATA LATCHED INTO CONTROL REGISTER ANALOG INPUT RANGE CALIBRATION SYS OFFSET AGND t23 CS VREF – 1LSB SYSTEM OFFSET Hi-Z BUSY tCAL MAX SYSTEM FULL SCALE IS ±2.5% FROM VREF Figure 29. Timing Diagram for Full Self-Calibration SYS FULL S. For the self-(gain + offset), self-offset and self-gain calibrations, the BUSY line is triggered high at the end of the write to the control register and stays high for the full duration of the selfcalibration. The length of time for which BUSY is high depends on the type of self-calibration that is initiated. Typical values are given in Table VIII. The timing diagram for the other selfcalibration options is similar to that outlined in Figure 29. System Calibration Description System calibration allows the user to remove system errors external to the AD7854/AD7854L, as well as remove the errors of the AD7854/AD7854L itself. The maximum calibration range for the system offset errors is ± 5% of VREF, and for the system gain errors it is ± 2.5% of VREF. If the system offset or system gain errors are outside these ranges, the system calibration algorithm reduces the errors as much as the trim range allows. Figures 30 through 32 illustrate why a specific type of system calibration might be used. Figure 30 shows a system offset calibration (assuming a positive offset) where the analog input range has been shifted upwards by the system offset after the system offset calibration is completed. A negative offset may also be removed by a system offset calibration. MAX SYSTEM FULL SCALE IS ±2.5% FROM VREF SYS FULL S. VREF – 1LSB VREF – 1LSB ANALOG INPUT RANGE SYSTEM OFFSET ANALOG INPUT RANGE CALIBRATION AGND AGND Figure 31. System Gain Calibration Finally in Figure 32 both the system offset error and gain error are removed by the system offset followed by a system gain calibration. First the analog input range is shifted upwards by the positive system offset and then the analog input range is adjusted at the top end to account for the system full scale. MAX SYSTEM FULL SCALE IS ±2.5% FROM VREF SYS F.S. VREF – 1LSB SYS OFFSET MAX SYSTEM FULL SCALE IS ±2.5% FROM VREF VREF + SYS OFFSET SYS F.S. VREF – 1LSB SYSTEM OFFSET CALIBRATION ANALOG FOLLOWED BY INPUT RANGE SYSTEM GAIN CALIBRATION SYS OFFSET AGND MAX SYSTEM OFFSET IS ±5% OF VREF ANALOG INPUT RANGE AGND MAX SYSTEM OFFSET IS ±5% OF VREF Figure 32. System (Gain + Offset) Calibration REV. B –21– AD7854/AD7854L System Gain and Offset Interaction The architecture of the AD7854/AD7854L leads to an interaction between the system offset and gain errors when a system calibration is performed. Therefore it is recommended to perform the cycle of a system offset calibration followed by a system gain calibration twice. When a system offset calibration is performed, the system offset error is reduced to zero. If this is followed by a system gain calibration, then the system gain error is now zero, but the system offset error is no longer zero. A second sequence of system offset error calibration followed by a system gain calibration is necessary to reduce system offset error to below the 12-bit level. The advantage of doing separate system offset and system gain calibrations is that the user has more control over when the analog inputs need to be at the required levels, and the CONVST signal does not have to be used. The timing for a system (gain + offset) calibration is very similar to that of Figure 33, the only difference being that the time tCAL1 is replaced by a shorter time of the order of tCAL2 as the internal DAC is not calibrated. The BUSY signal signifies when the gain calibration is finished and when the part is ready for the offset calibration. DATA LATCHED INTO CONTROL REGISTER t23 CS WR DATA Alternatively, a system (gain + offset) calibration can be performed. At the end of one system (gain + offset) calibration, the system offset error is zero, while the system gain error is reduced from its initial value. Three system (gain + offset) calibrations are required to reduce the system gain error to below the 12-bit error level. There is never any need to perform more than three system (gain + offset) calibrations. In bipolar mode the midscale error is adjusted for an offset calibration and the positive full-scale error is adjusted for the gain calibration; in unipolar mode the zero-scale error is adjusted for an offset calibration and the positive full-scale error is adjusted for a gain calibration. System Calibration Timing The timing diagram in Figure 33 is for a software full system calibration. It may be easier in some applications to perform separate gain and offset calibrations so that the CONVST bit in the control register does not have to be programmed in the middle of the system calibration sequence. Once the write to the control register setting the bits for a full system calibration is completed, calibration of the internal DAC is initiated and the BUSY line goes high. The full-scale system voltage should be applied to the analog input pins, AIN(+) and AIN(–) at the start of calibration. The BUSY line goes low once the DAC and system gain calibration are complete. Next the system offset voltage should be applied across the AIN(+) and AIN(–) pins for a minimum setup time (tSETUP) of 100 ns before the rising edge of CS. This second write to the control register sets the CONVST bit to 1 and at the end of this write operation the BUSY signal is triggered high (note that a CONVST pulse can be applied instead of this second write to the control register). The BUSY signal is low after a time tCAL2 when the system offset calibration section is complete. The full system calibration is now complete. Hi-Z DATA VALID Hi-Z Hi-Z CONVST BIT SET TO 1 IN CONTROL REGISTER DATA VALID BUSY tCAL1 t23 tCAL2 tSETUP AIN VOFFSET VSYSTEM FULL SCALE Figure 33. Timing Diagram for Full System Calibration The timing diagram for a system offset or system gain calibration is shown in Figure 34. Here again a write to the control register initiates the calibration sequence. At the end of the control register write operation the BUSY line goes high and it stays high until the calibration sequence is finished. The analog input should be set at the correct level for a minimum setup time (tSETUP) of 100 ns before the CS rising edge and stay at the correct level until the BUSY signal goes low. –22– t23 CS DATA LATCHED INTO CONTROL REGISTER WR DATA Hi-Z DATA VALID Hi-Z BUSY tCAL2 tSETUP AIN VSYSTEM FULL SCALE OR VOFFSET Figure 34. Timing Diagram for System Gain or System Offset Calibration REV. B AD7854/AD7854L to DB11. Bringing HBEN high causes the 8 MSBs of the 16-bit word to be output on pins DB0 to DB7. Note that with this arrangement the data lines are always active. PARALLEL INTERFACE Reading The timing diagram for a read cycle is shown in Figure 35. The CONVST and BUSY signals are not shown here as the read cycle may occur while a conversion is in progress or after the conversion is complete. t1 The HBEN signal is low for the first read and high for the second read. This ensures that it is the lower 12 bits of the 16-bit word are output in the first read and the 8 MSBs of the 16-bit word are output in the second read. If required, the HBEN signal may be high for the first read and low for the second read to ensure that the high byte is output in the first read and the lower byte in the second read. The CS and RD signals are gated together internally and level triggered active low. Both CS and RD may be tied together as the timing specification for t5 and t6 are both 0 ns min. The data is output a time t8 after both CS and RD go low. The RD rising edge should be used to latch the data by the user and after a time t9 the data lines will go into their high impedance state. In Figure 35, the first read outputs the 12 LSBs of the 16-bit word on pins DB0 to DB11 (DB0 being the LSB of the 12-bit read). The second read outputs the 8 MSBs of the 16-bit word on pins DB0 to DB7 (DB0 being the LSB of the 8-bit read). If the system has a 12-bit or a 16-bit data bus, only one read operation is necessary to obtain the 12-bit conversion result (12 bits are output in the first read). A second read operation is not required. If the system has an 8-bit data bus then two reads are needed. Pins DB0 to DB7 should be connected the 8-bit data bus. Pins DB8 to DB11 should be tied to DGND or DVDD via 10 kΩ resistors. With this arrangement, HBEN is pulled low for the first read and the 8 LSBs of the 16-bit word are output on pins DB0 to DB7 (data on pins DB8 to DB11 will be ignored). HBEN is pulled high for the second read and now the 8 MSBs of the 16-bit word are output on pins DB0 to DB7. t3 = 15ns MIN, t4 = 5ns MIN, t5 = t6 = 0ns MIN, t8 = 50ns MAX, t9 = 5/40ns MIN/MAX, t10 = 70ns MIN t1 = 100ns MIN, t20 = 70ns MIN, t19 = t20 = 70ns MIN, t21 = t22 = 60ns MAX CONVST CONVERSION IS INITIATED ON THIS EDGE t2 tCONVERT BUSY t20 t19 HBEN t21 t18 DATA OLD DATA VALID NEW DATA VALID (DB0–DB11) t22 NEW DATA VALID (DB8–DB11) NEW DATA VALID (DB0–DB11) NEW DATA VALID (DB8–DB11) ON PINS DB0 TO DB11 ON PINS DB0 TO DB7 Figure 36. Read Cycle Timing Diagram with CS and RD Tied Low Writing The timing diagram for a write cycle is shown in Figure 37. The CONVST and BUSY signals are not shown here as the write cycle may occur while a conversion is in progress or after the conversion is complete. To write a 16-bit word to the AD7854/AD7854L, two 8-bit writes are required. The HBEN signal must be low for the first write and high for the second write. This ensures that it is the lower 8 bits of the 16-bit word are latched in the first write and the 8 MSBs of the 16-bit word are latched in the second write. For both write operations the 8 bits of data should be present on pins DB0 to DB7 (DB0 being the LSB of the 8-bit write). Any data on pins DB8 to DB11 is ignored when writing to the device. The CS and WR signals are gated together internally. Both CS and WR may be tied together as the timing specification for t13 and t14 are both 0 ns min. The data is latched on the rising edge of WR. The data needs to be set up a time t16 before the WR rising edge and held for a time t17 after the WR rising edge. HBEN t11 = 0ns MIN, t12 = 5ns MIN, t13 = t14 = 0ns MIN, t15 = 70ns MIN, t16 = 10ns MIN, t17 = 5ns MIN t4 t3 t4 t3 CS t5 t6 t11 t7 RD DATA VALID DATA VALID WR In the case where the AD7854/AD7854L is operated as a readonly ADC, the WR pin can be tied permanently high. The read operation need only consist of one read if the system has a 12bit or a 16-bit data bus. When both the CS and RD signals are tied permanently low a different timing arrangement results, as shown in Figure 36. Here the data is output a time t20 before the falling edge of the BUSY signal. This allows the falling edge of BUSY to be used for latching the data. Again if HBEN is low during the conversion the 12 LSBs of the 16-bit word will be output on pins DB0 t11 t12 t10 t13 t14 t15 t17 Figure 35. Read Cycle Timing Diagram Using CS and RD REV. B t12 CS t9 t8 DATA HBEN t10 t16 DATA DATA VALID DATA VALID Figure 37. Write Cycle Timing Diagram Resetting the Parallel Interface If random data has been inadvertently written to the test register, it is necessary to write the 16-bit word 0100 0000 0000 0010 (in two 8-bit bytes) to restore the test register to its default value. –23– AD7854/AD7854L MICROPROCESSOR INTERFACING AD7854/AD7854L to TMS32020, TMS320C25 and TMS320C5x The parallel port on the AD7854/AD7854L allows the device to be interfaced to microprocessors or DSP processors as a memory mapped or I/O mapped device. The CS and RD inputs are common to all memory peripheral interfacing. Typical interfaces to different processors are shown in Figures 38 to 41. A parallel interface between the AD7854/AD7854L and the TMS32020, TMS320C25 and TMS320C5x family of DSPs are shown in Figure 39. The memory mapped addresses chosen for the AD7854/AD7854L should be chosen to fall in the I/O memory space of the DSPs. In all the interfaces shown, an external timer controls the CONVST input of the AD7854/AD7854L and the BUSY output interrupts the host DSP. Also, the HBEN pin is connected to address line A0 (XA0 in the case of the TMS320C30). This maps the AD7854/AD7854L to two locations in the processor memory space, ADCaddr and ADCaddr+1. Thus when writing to the ADC, first the 8 LSBs of the 16-bit are written to address location ADCaddr and then the 8 MSBs to location ADCaddr+1. All the interfaces use a 12-bit data bus, so only one read is needed from location ADCaddr to access the ADC output data register or the status register. To read from the other registers, the 8 MSBs must be read from location ADCaddr+1. Interfacing to 8-bit bus systems is similar, except that two reads are required to obtain data from all the registers. The parallel interface on the AD7854/AD7854L is fast enough to interface to the TMS32020 with no extra wait states. In the TMS320C25 interface, data accesses may be slowed sufficiently when reading from and writing to the part to require the insertion of one wait state. In such a case, this wait state can be generated using the single OR gate to combine the CS and MSC signals to drive the READY line of the TMS320C25, as shown in Figure 39. Extra wait states are necessary when using the TMS320C5x at their fastest clock speeds. Wait states can be programmed via the IOWSR and CWSR registers (please see TMS320C5x User Guide for details). AD7854/AD7854L to ADSP-21xx where D is the memory location where the data is to be stored and ADCaddr is the I/O address of the AD7854/AD7854L. Figure 38 shows the AD7854/AD7854L interfaced to the ADSP-21xx series of DSPs as a memory mapped device. A single wait state may be necessary to interface the AD7854/ AD7854L to the ADSP-21xx depending on the clock speed of the DSP. This wait state can be programmed via the data memory waitstate control register of the ADSP-21xx (please see ADSP-2100 Family Users Manual for details). The following instruction reads data from the AD7854/AD7854L: AX 0 = DM(ADCaddr) Data is read from the ADC using the following instruction: IN D,ADCaddr Data is written to the ADC using the following two instructions: OUT D8LSB, ADCaddr OUT D8MSB, ADCaddr+1 where D8LSB is the memory location where the 8 LSBs of data are stored, D8MSB is the location where the 8 MSBs of data are stored and ADCaddr and ADCaddr+1 are the I/O memory spaces that the AD7854/AD7854L is mapped into. Data can be written to the AD7854/AD7854L using the instructions: A15–A1 DM (ADCaddr) = AY 0 TMS32020/ TMS320C25/ TMS320C50* IS DM (ADCaddr+1) = AY 1 where ADCaddr is the address of the AD7854/AD7854L in ADSP-21xx data memory, AX0 contains the data read from the ADC, and AY 0 contains the 8 LSBs and AY 1 the 8 MSBs of data written to the AD7854/AD7854L. ADDRESS BUS EN ADDR DECODE READY MSC A0 STRB R/W TMS320C25 ONLY CS AD7854/ AD7854L* HBEN WR RD A13–A1 ADDRESS BUS INTx ADSP-21xx* DMS D23–D0 EN ADDR DECODE AD7854/ AD7854L* WR WR RD RD IRQ2 D23–D8 DATA BUS DB11–DB0 CS *ADDITIONAL PINS OMITTED FOR CLARITY Figure 39. AD7854/AD7854L to TMS32020/C25/C5x Parallel Interface HBEN A0 BUSY BUSY DATA BUS DB11–DB0 *ADDITIONAL PINS OMITTED FOR CLARITY Figure 38. AD7854/AD7854L to ADSP-21xx Parallel Interface –24– REV. B AD7854/AD7854L AD7854/AD7854L to TMS320C30 AD7854/AD7854L to DSP5600x Figure 40 shows a parallel interface between the AD7854/ AD7854L and the TMS320C3x family of DSPs. The AD7854/AD7854L is interfaced to the Expansion Bus of the TMS320C3x. Two wait states are required in this interface. These can be programmed using the WTCNT bits of the Expansion Bus Control register (see TMS320C3x Users Guide for details). Data from the AD7854/AD7854L can be read using the following instruction: Figure 41 shows a parallel interface between the AD7854/ AD7854L and the DSP5600x series of DSPs. The AD7854/ AD7854L should be mapped into the top 64 locations of Y data memory. If extra wait states are needed in this interface, they can be programmed using the Port A bus control register (please see DSP5600x User’s Manual for details). Data can be read from the DSP5600x using the following instruction: LDI *ARn,Rx Data can be loaded into the AD7854/AD7854L using the instructions: MOVE Y:ADCaddr, X 0 Data can be written to the AD7854/AD7854L using the following two instructions: MOVE X0, Y:ADCaddr STI Ry,*ARn++ MOVE X1, Y:ADCaddr+1 STI Rz,*ARn-where ARn is an auxiliary register containing the lower 16 bits of the address of the AD7854/AD7854L in the TMS320C3x memory space, Rx is the register into which the ADC data is loaded during a load operation, Ry contains the 8 LSBs of data and Rz contains the 8 MSBs of data to be written to the AD7854/AD7854L. Where ADCaddr is the address in the DSP5600x address space to which the AD7854/AD7854L has been mapped. A15–A1 DSP56000/ DSP56002* X/Y DS XA12–XA1 TMS320C30* XA0 CS AD7854/ AD7854L* AD7854/ AD7854L* HBEN WR RD RD D23–D0 WR CS WR IRQ HBEN IOSTRB XR/W ADDR DECODE A0 EXPANSION ADDRESS BUS ADDR DECODE ADDRESS BUS BUSY DATA BUS DB11–DB0 *ADDITIONAL PINS OMITTED FOR CLARITY RD INTx XD23–XD0 BUSY EXPANSION DATA BUS Figure 41. AD7854/AD7854L to DSP5600x Parallel Interface DB11–DB0 *ADDITIONAL PINS OMITTED FOR CLARITY Figure 40. AD7854/AD7854L to TMS320C30 Parallel Interface REV. B –25– AD7854/AD7854L APPLICATION HINTS Grounding and Layout The analog and digital supplies of the AD7854/AD7854L are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The part has very good immunity to noise on the power supplies as can be seen by the PSRR versus frequency graph. However, care should still be taken with regard to grounding and layout. The printed circuit board on which the AD7854/AD7854L is mounted should be designed such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should only be joined in one place. If the AD7854/AD7854L is the only device requiring an AGND to DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD7854/ AD7854L. If the AD7854/AD7854L is in a system where multiple devices require AGND to DGND connections, the connection should still be made at one point only, a star ground point which should be established as close as possible to the AD7854/AD7854L. Avoid running digital lines under the device as these couple noise onto the die. The analog ground plane should be allowed to run under the AD7854/AD7854L to avoid noise coupling. The power supply lines to the AD7854/AD7854L should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks and the data inputs should be shielded with digital ground to avoid radiating noise to other sections of the board and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled with a 10 µF tantalum capacitor in parallel with 0.1 µF disc ceramic capacitor to AGND. All digital supplies should have a 0.1 µF disc ceramic capacitor to DGND. To achieve the best performance from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. In systems where a common supply voltage is used to drive both the AVDD and DVDD of the AD7854/AD7854L, it is recommended that the system’s AVDD supply is used. In this case an optional 10 Ω resistor between the AVDD pin and DVDD pin can help to filter noise from digital circuitry. This supply should have the recommended analog supply decoupling capacitors between the AVDD pin of the AD7854/AD7854L and AGND and the recommended digital supply decoupling capacitor between the DVDD pin of the AD7854/AD7854L and DGND. Evaluating the AD7854/AD7854L Performance The recommended layout for the AD7854/AD7854L is outlined in the evaluation board for the AD7854/AD7854L. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the PC via the EVAL-CONTROL BOARD. The EVAL-CONTROL BOARD can be used in conjunction with the AD7854/AD7854L Evaluation board, as well as many other Analog Devices evaluation boards ending in the CB designator, to demonstrate/evaluate the ac and dc performance of the AD7854/AD7854L. The software allows the user to perform ac (fast Fourier transform) and dc (histogram of codes) tests on the AD7854/ AD7854L. It also gives full access to all the AD7854/AD7854L on-chip registers allowing for various calibration and powerdown options to be programmed. AD785x Family All parts are 12 bits, 200 kSPS, 3.0 V to 5.5 V. AD7853 – Single Channel Serial AD7854 – Single Channel Parallel AD7858 – Eight Channel Serial AD7859 – Eight Channel Parallel –26– REV. B AD7854/AD7854L PAGE INDEX Topic Page Topic Page FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 CALIBRATION SECTION . . . . . . . . . . . . . . . . . . . . . . . . 20 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 Calibration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . 1 Automatic Calibration on Power-On . . . . . . . . . . . . . . . . 20 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Self-Calibration Description . . . . . . . . . . . . . . . . . . . . . . . 20 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 4 Self-Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 5 System Calibration Description . . . . . . . . . . . . . . . . . . . . 21 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 System Gain and Offset Interaction . . . . . . . . . . . . . . . . . 22 PINOUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 System Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . 22 TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PARALLEL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . 23 PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . 7 Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AD7854/AD7854L ON-CHIP REGISTERS . . . . . . . . . . . . 8 Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Addressing the On-Chip Registers . . . . . . . . . . . . . . . . . . . 8 Resetting the Parallel Interface . . . . . . . . . . . . . . . . . . . . . 23 Writing/Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 MICROPROCESSOR INTERFACING . . . . . . . . . . . . . . . 24 CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 AD7854/AD7854L to ADSP-21xx . . . . . . . . . . . . . . . . . . 24 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 CALIBRATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 11 AD7854/AD7854L to TMS32020, TMS320C25 and TMS320C5x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Addressing the Calibration Registers . . . . . . . . . . . . . . . . 11 AD7854/AD7854L to TMS320C30 . . . . . . . . . . . . . . . . 25 Writing to/Reading from the Calibration Registers . . . . . . 11 AD7854/AD7854L to DSP5600x . . . . . . . . . . . . . . . . . . 25 Adjusting the Offset Calibration Register . . . . . . . . . . . . . 12 APPLICATIONS HINTS . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Adjusting the Gain Calibration Register . . . . . . . . . . . . . . 12 Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . 13 Evaluating the AD7854/AD7854L Performance . . . . . . . 26 CONVERTER DETAILS . . . . . . . . . . . . . . . . . . . . . . . . . . 13 INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 TYPICAL CONNECTION DIAGRAM . . . . . . . . . . . . . . 13 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 28 ANALOG INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TABLE INDEX Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 # DC/AC Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 I Write Register Addressing . . . . . . . . . . . . . . . . . . . . . . . 8 Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 II Read Register Addressing . . . . . . . . . . . . . . . . . . . . . . . 8 Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 III Calibration Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 REFERENCE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . 16 IV Calibrating Register Addressing . . . . . . . . . . . . . . . . . 11 AD7854/AD7854L PERFORMANCE CURVES . . . . . . . . 16 V Analog Input Connections . . . . . . . . . . . . . . . . . . . . . 15 POWER-DOWN OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 17 VI Power Management Options . . . . . . . . . . . . . . . . . . . . 17 POWER-UP TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VII Power Consumption vs. Throughput . . . . . . . . . . . . . 18 Using an External Reference . . . . . . . . . . . . . . . . . . . . . . 17 VIII Calibration Times (AD7854 with 4 MHz CLKIN) . . . 20 Using the Internal (On-Chip) Reference . . . . . . . . . . . . . 18 POWER VS. THROUGHPUT RATE . . . . . . . . . . . . . . . . 18 REV. B –27– Title Page AD7854/AD7854L OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.005 (0.13) MIN C2117–0–3/00 (rev. B) 28-Lead Cerdip (Q-28) 0.100 (2.54) MAX 28 15 0.610 (15.49) 0.500 (12.70) 1 14 PIN 1 0.620 (15.75) 0.590 (14.99) 0.015 (0.38) MIN 0.150 (3.81) MIN 1.490 (37.85) MAX 0.225 (5.72) MAX 0.200 (5.08) 0.026 (0.66) 0.110 (2.79) 0.070 (1.78) SEATING 0.125 (3.18) 0.014 (0.36) 0.090 (2.29) 0.030 (0.76) PLANE 0.018 (0.46) 0.008 (0.20) 15° 0° 28-Lead Small Outline Package (R-28) 28 15 1 14 0.1043 (2.65) 0.0926 (2.35) PIN 1 0.0118 (0.30) 0.0040 (0.10) 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) 0.7125 (18.10) 0.6969 (17.70) 0.0500 (1.27) BSC 0.0291 (0.74) ⴛ 45° 0.0098 (0.25) 8° 0.0500 (1.27) 0.0192 (0.49) SEATING 0.0125 (0.32) 0° 0.0157 (0.40) 0.0138 (0.35) PLANE 0.0091 (0.23) 28-Lead Shrink Small Outline Package (RS-28) 0.407 (10.34) 0.397 (10.08) 15 1 14 0.078 (1.98) PIN 1 0.068 (1.73) 0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC PRINTED IN U.S.A. 0.212 (5.38) 0.205 (5.21) 0.311 (7.9) 0.301 (7.64) 28 0.07 (1.79) 0.066 (1.67) 8° 0.015 (0.38) 0° SEATING 0.009 (0.229) 0.010 (0.25) PLANE 0.005 (0.127) –28– 0.03 (0.762) 0.022 (0.558) REV. B