Infineon ADM6993X-AD-T-1 Adm6993/x hdlc to fast ethernet converter Datasheet

Data Sheet, Rev 1.11, Nov. 2005
ADM6993/X
ADM6993/X HDLC to Fast Ethernet Converter
Communications
N e v e r
s t o p
t h i n k i n g .
Edition 2005-11-28
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2005.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
ADM6993/X ADM6993/X HDLC to Fast Ethernet Converter
Revision History: 2005-11-28, Rev 1.11
Previous Version:
Page/Date
Subjects (major changes since last revision)
2003-07-02 Rev. 1.0: First release of ADM6993
2003-10-13 Rev. 1.1: Added sections 4.3&4.4
2005-08-15 Changed to the new Infineo format
2005-09-09 Rev. 1.11: when changed to the new Infineon format
2005-11-28 Minor change. Included Green package information
Trademarks
ABM®, ACE®, AOP®, ARCOFI®, ASM®, ASP®, DigiTape®, DuSLIC®, EPIC®, ELIC®, FALC®, GEMINAX®, IDEC®,
INCA®, IOM®, IPAT®-2, ISAC®, ITAC®, IWE®, IWORX®, MUSAC®, MuSLIC®, OCTAT®, OptiPort®, POTSWIRE®,
QUAT®, QuadFALC®, SCOUT®, SICAT®, SICOFI®, SIDEC®, SLICOFI®, SMINT®, SOCRATES®, VINETIC®,
10BaseV®, 10BaseVX® are registered trademarks of Infineon Technologies AG. 10BaseS™, ConverGate™,
EasyPort™, VDSLite™ are trademarks of Infineon Technologies AG. Microsoft® and Visio® are registered
trademarks of Microsoft Corporation, Linux® of Linus Torvalds, and FrameMaker® of Adobe Systems Incorporated.
Template: template_A4_3.0.fm / 3 / 2005-03-10
ADM6993/X
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1
1.1
1.2
1.3
1.4
Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Lengths Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.1
2.2
2.3
2.4
Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Type and Buffer Type Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 2 MII/RMII/GPSI/HDLC Interfaces Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
11
12
21
3
3.1
3.2
3.2.1
3.2.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.8
3.3.9
3.3.10
3.3.11
3.3.12
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.5
3.5.1
3.5.2
3.5.3
3.6
3.6.1
3.6.2
3.7
3.7.1
Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10/100M PHY Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto Negotiation and Speed Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speed Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Recognition and Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffers and Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Back off Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inter-Packet Gap (IPG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Illegal Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Half Duplex Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Full Duplex Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Broadcast Storm Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto TP MDIX Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Converter Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Redundant Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop-Back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Snooping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fiber_SD LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Management Interface (SMI) Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preamble Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read EEPROM Register via SMI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write EEPROM Register via SMI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HDLC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HDLC Frame Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HDLC Frame Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write EEPROM Register via EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
22
23
23
23
24
24
25
25
25
25
25
26
26
26
26
26
27
27
27
27
28
28
28
28
29
29
30
30
30
30
31
31
Data Sheet
4
8
8
8
9
9
Rev 1.11, 2005-11-28
ADM6993/X
Table of Contents
4
4.1
4.2
4.2.1
4.3
4.4
4.4.1
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Default Value of SMI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMI Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMI Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
5.1
5.2
Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
DC Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
AC Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Data Sheet
5
32
32
34
36
55
56
57
Rev 1.11, 2005-11-28
ADM6993/X
List of Figures
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Data Sheet
ADM6993/X Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ADM6993/X Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SMI Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SMI Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Power on Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
EEPROM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10Base-Tx MII Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10Base-TX MII Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
100Base-TX MII Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
100Base-TX MII Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Reduce MII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
GPSI (7-wire) Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
GPSI (7-wire) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
HDLC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SMI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
128 PQFP packaging for ADM6993/X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6
Rev 1.11, 2005-11-28
ADM6993/X
List of Tables
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 43
Table 44
Data Sheet
Data Lengths Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ADM6993/XAbbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Port 0/1 Twisted Pair Interface (8 Pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Port 2 (MII/RMII/GPSI) Interface (17 Pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Port 1 Alternative MII Port Interface (17 Pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LED Interface (13 Pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
EEPROM Interface (4 Pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Configuration Interface (28 Pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Ground/Power Interface (27 Pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Miscellaneous (14 Pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Port 2 MII/RMII/GPSI/HDLC Interfaces Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Speed Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Port Rising/Falling Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Drop Scheme for each queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SMI Read/Write Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
EEPROM Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Registers Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Register Access Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Registers Clock DomainsRegisters Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Other Filter Regsiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Other Tag Port Rule 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Other Tag Port Rule 1 Regsiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Default Value of SMI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Registers Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Register Access Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Registers Clock DomainsRegisters Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Other Per Port Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Electrical Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
DC Electrical Characteristics for 3.3 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Power on Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
EEPROM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10Base-Tx MII Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10Base-TX MII Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
100Base-TX MII Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
100Base-TX MII Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
100Base-TX MII Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
GPSI (7-wire) Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
GPSI (7-wire) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
HDLC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SMI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7
Rev 1.11, 2005-11-28
ADM6993/X
Product Overview
1
Product Overview
Features and the block diagram.
1.1
Overview
The ADM6993/X is a single chip integrating two 10/100 Mbps MDIX TX/FX transceivers, a three-port 10/100M
Ethernet L2 switch controller, and features converter mode to meet demanding applications, including Fiber-toEthernet media converters, 2/3 port Ethernet switches, VoIP gateways, and NAT routers. The ADM6993X is the
environmentally friendly “green” package version.
The ADM6993/X supports priority features on Port-Base priority, VLAN TAG priority and IP TOS precedence
checking at individual ports. This is done through a small low-cost micro controller to initialize or on-the-fly to
configure. The priority of packets can be tagged based on TCP port number for the multi-media application.
The 2nd MAC interface could be selected as TP/FX or MII/RMII/GPSI to connect with bridge devices for different
media. The 3rd MAC interface could be selected as MII/RMII/GPSI/HDLC to connect with routing devices, and
bridge devices for different media. The dedicated HDLC channel supports rate from 64Kbps to 50Mbps.
On the media side of port0/1, the ADM6993/X supports auto MDIX 10Base-T/100Base-TX and 100Base-FX as
specified by the IEEE 802.3 committee through uses of digital circuitry and high speed A/D.
ADM6993/X supports serial management interface (SMI) for a small low-cost micro controller to initialize or
configure. It also provides port status for remote agent monitor and smart counter for port statistics.
1.2
Features
Main features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3-port10/100M switch integrated with a 2-port PHY (10/100TX and 100FX) and 3rd MAC port as
GPSI/MII/RMII/HDLC.
Provides TX<-->FX Converter modes with faulted propagation and redundant capability by using of two
ADM6993/X.
Short latency on the converter mode.
Built-in data buffer 6Kx64bit SRAM.
Up to 2k MAC Unicast addresses with a 4-way associative hashing table.
MAC address learning table with aging function.
Two queues per port for QoS purposes.
Port-base, 802.1p and TCP/IP ToS priority.
Store & forward architecture.
802.3x flow control for full duplex and back-pressure for half duplex in case the buffer is full.
Supports Auto-Negotiation.
Packet lengths up to 1536 bytes.
Broadcast storming filter.
Port-base VLAN/tag-base VLAN.
16 entries of packet classification and marking or filtering for TCP/UDP Port Numbering, IP Protocol ID and
Ethernet Type.
Serial Management Interface for low-end CPUs.
Provides port status for remote agent monitoring .
Provides smart counters for port statistics reporting.
128 PQFP packaging with 2.5 V/3.3 V power supply.
Data Sheet
8
Rev 1.11, 2005-11-28
ADM6993/X
Product Overview
1.3
Block Diagram
DMA
PORT0
TX/FX PHY
Packet Buffer
PORT0
MAC
Learn
Switch
Fabric
Buffer
Management
Link List
Link List Buffer
PORT1
TX/FX PHY
DMA
MII
MUX
PORT1
MAC
Address Filtering
MAC Address
Buffer
Learn
RMII
SMI
Interface
GPSI
CLKGEN
RSTGEN
CENCTRL
EEPROM
Interface
HDLC
DMA
MII
MUX
PORT2
MAC
RCV
RMII
Learn
LED
Display
GPSI
Figure 1
ADM6993/X Block Diagram
1.4
Data Lengths Conventions
Table 1
Data Lengths Conventions
qword
64 bits
dword
32 bits
word
16 bits
byte
8 bits
nibble
4 bits
Data Sheet
9
Rev 1.11, 2005-11-28
ADM6993/X
Interface Description
2
Interface Description
This chapter describes Pin Diagram, Pin Type and Buffer Type Abbreviations, and Pin Descriptions.
2.1
Pin Diagram
˄˃ˆ
˄˃ˇ
˄˃ˈ
˄˃ˉ
˄˃ˊ
˄˃ˋ
˄˃ˌ
˄˄˃
˄˄˄
˄˄˅
˄˄ˆ
˄˄ˇ
˄˄ˈ
˄˄ˉ
˄˄ˊ
˄˄ˋ
˄˄ˌ
˄˅˃
˄˅˄
˄˅˅
˄˅ˆ
˄˅ˇ
˄˅ˈ
˄˅ˉ
˄˅ˊ
˄˅ˋ
Figure 2
Data Sheet
ADM6993
P1TXD1
P1TXD0
VCC2IK
P1TXCLK
P1TXEN
P1RXDV
P1RXCLK
TEST
P2_FCDIS
GNDIK
P0_FCDIS
FTPR_MODE0
FTPR_MODE1
P1_ANDIS
P1_RECHALF
P1_REC10
P1_FCDIS
RC
XI
XO
BYPASS_PAUSE
LEDMODE2
NC
VCCPLL
GNDPLL
CONTROL
VREF
GNDBIAS
RTX
VCCBIAS
ˆˌ
ˇ˃
ˇ˄
ˇ˅
ˇˆ
ˇˇ
ˇˈ
ˇˉ
ˇˊ
˅˃
˅˄
˅˅
˅ˆ
˅ˇ
˅ˈ
˅ˉ
˅ˊ
˅ˋ
˅ˌ
ˆ˃
ˆ˄
ˆ˅
ˆˆ
ˆˇ
ˆˈ
ˆˉ
ˆˊ
ˆˋ
LPT_DIS
CHIP_DIS
CAS_DIS
LPBK_P0
LPBK_P1
LPBK_P2
P2LINKF
P2SPDTEN
P2DPHALF
P2COL
P2CRS
VCC2IK
P2TXCLK
GNDIK
P2TXEN
P2TXD0
P2TXD1
P2TXD2
P2TXD3
P1RXD3
P1RXD2
P1RXD1
P1RXD0
VCC3O
CK25MO
GNDO
NC
NC
NC
NC
NC
NC
NC
NC
P0_MDI
XOVEN
SCAN_EN
SCAN_MD
˄˃˅
˄˃˄
˄˃˃
ˌˌ
ˌˋ
ˌˊ
ˌˉ
ˌˈ
ˌˇ
ˌˆ
ˌ˅
ˌ˄
ˌ˃
ˋˌ
ˋˋ
ˋˊ
ˋˉ
ˋˈ
ˋˇ
ˋˆ
ˋ˅
ˋ˄
ˋ˃
ˊˌ
ˊˋ
ˊˊ
ˊˉ
ˊˈ
ˊˇ
ˊˆ
ˊ˅
ˊ˄
ˊ˃
ˉˌ
ˉˋ
ˉˊ
ˉˉ
ˉˈ
ˇˋ
ˇˌ
ˈ˃
ˈ˄
ˈ˅
ˈˆ
ˈˇ
ˈˈ
ˈˉ
ˈˊ
ˈˋ
ˈˌ
ˉ˃
ˉ˄
ˉ˅
ˉˆ
ˉˇ
˄ˆ
˄ˇ
˄ˈ
˄ˉ
˄ˊ
˄ˋ
˄ˌ
VCCA2(2.5)
TXP0
TXN0
GNDA
RXP0
RXN0
VCCAD(3.3)
RXN1
RXP1
GNDA
TXN1
TXP1
VCCA2(2.5)
GNDIK
P1TXD3
P1TXD2
ˌ
˄˃
˄˄
˄˅
LED_LINK1
LED_FULL0
LED_FULL1
LED_LPBK
NC
INT_N
EEDO
EEDI
VCC2IK
VCC2IK
EESK
EECS
GNDIK
SDC
SDIO
P0_ANDIS
P0_RECHALF
P0_REC10
P2RXCLK
P2RXDV
P2RXD0
P2RXD1
P2RXD2
P2RXD3
GNDIK
GNDIK
P1COL
P1CRS
LNKACT0/LED_DATA0
LNKACT1/LED_DATA1
VCC2IK
VCC2IK
P1LINKF
GNDO
GNDO
P1SPDTEN
P1DPHALF
LDSPD0
LDSPD1/LED_FIBER_SD
DUPCOL0/LED_COL0
DUPCOL1/LED_COL1
VCC3O
VCC3O
LED_LINK0
˄
˅
ˆ
ˇ
ˈ
ˉ
ˊ
ˋ
ADM6993/X Pin Assignment
10
Rev 1.11, 2005-11-28
ADM6993/X
Interface Description
2.2
Pin Type and Buffer Type Abbreviations
Standardized abbreviations:
Table 2
ADM6993/XAbbreviations for Pin Type
Abbreviations
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
AO
Output. Analog levels.
AI/O
Input or Output. Analog levels.
PWR
Power
GND
Ground
MCL
Must be connected to Low (JEDEC Standard)
MCH
Must be connected to High (JEDEC Standard)
NU
Not Usable (JEDEC Standard)
NC
Not Connected (JEDEC Standard)
Table 3
Abbreviations for Buffer Type
Abbreviations
Description
Z
High impedance
PU1
Pull up, 10 k Ω
PD1
Pull down, 10 k Ω
PD2
Pull down, 20 k Ω
TS
Tristate capability: The corresponding pin has 3 operational states: Low, high and highimpedance.
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR. An external pull-up is required to sustain the
inactive state until another agent drives it, and must be provided by the central resource.
OC
Open Collector
PP
Push-Pull. The corresponding pin has 2 operational states: Active-low and active-high
(identical to output with no type attribute).
OD/PP
Open-Drain or Push-Pull. The corresponding pin can be configured either as an output with
the OD attribute or as an output with the PP attribute.
ST
Schmitt-Trigger characteristics
TTL
TTL characteristics
Data Sheet
11
Rev 1.11, 2005-11-28
ADM6993/X
Interface Description
2.3
Pin Descriptions
ADM6993/X pins are categorized into one of the following groups:
•
•
•
•
•
•
•
•
Port 0/1 Twisted Pair Interface, 8 pins
Port 2 (MII/RMII/GPSI) Interface, 17 pins
Port 1 alternative MII Port Interface, 17 pins
LED Interface, 13 pins
EEPROM Interface, 4 pins
Configuration Interface, 28 pins
Ground/Power Interface, 27 pins
Miscellaneous, 14 pins
Note: If not specified, all signals default to digital signals.
Table 4
Port 0/1 Twisted Pair Interface (8 Pins)
Pin or Ball No. Name
Pin
Type
40
TXP_0
AO
50
TXP_1
AO
41
TXN_0
AO
49
TXN_1
AO
43
RXP_0
AI
47
RXP_1
AI
44
RXN_0
AI
46
RXN_1
AI
Table 5
Buffer
Type
Function
Twisted Pair Transmit
Output Positive.
Twisted Pair Transmit
Output Negative.
Twisted Pair Receive
Input Positive.
Twisted Pair Receive
Input Negative.
Port 2 (MII/RMII/GPSI) Interface (17 Pins)
Pin or Ball No. Name
Pin
Type
Buffer
Type
87
I/O
TTL, PD, Port 2 MII Transmit Data bit 0
Synchronous to the rising edge of TXCLK.
8mA
P2TXD0
FXMODE0
86
P2TXD1
FXMODE1
Data Sheet
Function
FXMODE0
During power on reset, value will be latched by
ADM6993/X at the rising edge of RESETL as bit 0 of
FXMODE.
I/O
TTL, PD, Port 2 MII Transmit Data bit 1
8mA
Synchronous to the rising edge of TXCLK.
FXMODE1
During power on reset, value will be latched by
ADM6993/X at the rising edge of RESETL as bit 1 of
FXMODE.
FXMODE [1:0] Interface
00B , Both Port0 & Port1 are TP port
01B , Port0 is TP port and Port1 is FX port
10B , Port0 is TP port and Port1 is FX port (converter
mode)
11B , Both Port0 & Port1 are FX port
12
Rev 1.11, 2005-11-28
ADM6993/X
Interface Description
Table 5
Port 2 (MII/RMII/GPSI) Interface (17 Pins) (cont’d)
Pin or Ball No. Name
Pin
Type
Buffer
Type
85
I/O
TTL, PD, Port 2 MII Transmit Data bit 2
8mA
Synchronous to the rising edge of TXCLK.
P2TXD2
P2BUSMD0
84
P2TXD3
P2BUSMD0
During power on reset, value will be latched by
ADM6993/X at the rising edge of RESETL as
P2BUSMD0.
I/O
P2BUSMD1
88
P2TXEN
P2RXD_3
107
P2RXD_2
106
P2RXD_1
105
P2RXD_0
104
PD, 8mA Port 2 MII Transmit Data bit 3
P2BUSMD1
During power on reset, value will be latched by
ADM6993/X at the rising edge of RESETL as
P2BUSMD1.
BUSMD[1:0] Interface
00B , MII(Default)
01B , RMII
10B , GPSI
11B , HDLC
I/O
DISBP
108
Function
PD, 8mA Port 2 MII Transmit Enable
Synchronous to the rising edge of TXCLK
DISBP. Disable Back Pressure
0B
, Enable back-pressure(Default)
1B
, Disable back-pressure
I
TTL, PD Port 2 MII Receive Data bit 3 ~ 0
P2RXDV
I
TTL, PD Port 2 MII Receive Data Valid
93
P2COL
I
TTL, PD Port 2 MII Collision input
92
P2CRS
I
TTL, PD Port 2 MII Carrier Sense
103
P2RXCLK
I
TTL, PD Port 2 MII Receive Clock Input
90
P2TXCLK
I
TTL, PD Port 2 MII Transmit Clock Input
96
P2LINKF
I
TTL, PU P2LINKF
This pin will be used to input the Link Status of Port2
1B
, Link Fail
95
P2SPDTEN
I
TTL, PD P2SPDTEN
This pin will be used as Port 2 Speed Status input
1B
, 10M
94
P2DPHALF
I
TTL, PD P2DPHALF
This pin will be used as Port 2 Duplex Status input
1B
, Half Duplex
Data Sheet
13
Rev 1.11, 2005-11-28
ADM6993/X
Interface Description
Table 6
Port 1 Alternative MII Port Interface (17 Pins)
Pin or Ball No. Name
Pin
Type
Buffer
Type
Function
56
P1TXD0/CHIPID I/O
_0
TTL, PD, Port 1 MII Transmit Data bit 0/Chip ID Bit 0
8mA
During power on reset, value will be latched by
ADM6993/X at the rising edge of RESETL as
CHIPID_0.This pin will become P1RXD0 if
P1BUSMD[1:0] is 11. Synchronous to the rising edge of
TXCLK.
55
P1TXD1/CHIPID I/O
_1
TTL, PD, Port 1 MII Transmit Data bit 1/Chip ID Bit 1
8mA
During power on reset, value will be latched by
ADM6993/X at the rising edge of RESETL as
CHIPID_1.This pin will become P1RXD1 if
P1BUSMD[1:0] is 11. Synchronous to the rising edge of
TXCLK.
54
P1TXD2/P1BUS I/O
MD0
TTL, PU, Port 1 MII Transmit Data bit 2/ Port 1 Bus Mode bit 0
8mA
During power on reset, value will be latched by
ADM6993/X at the rising edge of RESETL as
P1BUSMD0.This pin will become P1RXD2 if
P1BUSMD[1:0] is 11. Synchronous to the rising edge of
TXCLK.
P1BUSMD[1:0] Interface
00B , MII (Power Down TX Phy)
01B , RMII (Power Down TX Phy)
10B , GPSI (Power Down TX Phy)
11B , TP/FX (default)
53
P1TXD3/P1BUS I/O
MD1
TTL, PU, Port 1 MII Transmit Data bit 3/ Port 1 Bus Mode bit 1
8mA
During power on reset, value will be latched by
ADM6993/X at the rising edge of RESETL as
P1BUSMD1.This pin will become P1RXD3 if
P1BUSMD[1:0] is 11. Synchronous to the rising edge of
TXCLK.
P1BUSMD[1:0] Interface
00B , MII (Power Down TX Phy)
01B , RMII (Power Down TX Phy)
10B , GPSI (Power Down TX Phy)
11B , TP/FX (default)
59
P1TXEN
TTL, PD, Port 1 MII Transmit Enable
8mA
This pin will become P1RXDV if P1BUSMD[1:0] is 11.
Synchronous to the rising edge of TXCLK
IDLE_MODE
Data Sheet
O
IDEL_MODE
During power on reset, value will be latched by
ADM6993/X at the rising edge of RESETL as HDLC
IDLE frame control mode.
IDLE_MODE IDLE Pattern
0B
,
FFH(Default)
1B
,
7EH
14
Rev 1.11, 2005-11-28
ADM6993/X
Interface Description
Table 6
Port 1 Alternative MII Port Interface (17 Pins) (cont’d)
Pin or Ball No. Name
Pin
Type
Buffer
Type
83
P1RXD_3
I
82
P1RXD_2
81
P1RXD_1
TTL, PD Port 1 MII Receive Data bit 3 ~ 0
These pins will become P1TXD[3:0] if P1BUSMD[1:0] is
11
80
P1RXD_0
60
P1RXDV
I
TTL, PD Port 1 MII Receive Data Valid
This pin will become P1TXEN if P1BUSMD[1:0] is 11
111
P1COL
I/O
TTL, PD Port 1 MII Collision input
This pin will become P1COL if P1BUSMD[1:0] is 11 and
becomes an output pin
112
P1CRS
I/O
TTL, PD Port 1 MII Carrier Sense
This pin will become P1CRS if P1BUSMD[1:0] is 11 and
becomes an output pin
61
P1RXCLK
I/O
TTL, PD Port 1 MII Receive Clock Input
This pin will become P1CRS if P1BUSMD[1:0] is 11 and
becomes an output pin
58
P1TXCLK
I/O
TTL, PD Port 1 MII Transmit clock Input
This pin will become P1CRS if P1BUSMD[1:0] is 11 and
becomes an output pin.
117
P1LINKF
I
TTL, PU Port 1 Link Fail Status
This pin will be used to input the Link Status of Port1 if
Port1 is not connected to internal PHY
1B
, Link Fail
120
P1SPDTEN
I
TTL, PD Port 1 Speed Status
This pin will be used as Port 1 Speed Status input if
Port1 is not connected to internal PHY
1B
, 10M
121
P1DPHALF
I
TTL, PD Port 1 Duplex Status
This pin will be used as Port 2 Duplex Status input if
Port1 is not connected to internal PHY
1B
, Half Duplex
Data Sheet
Function
15
Rev 1.11, 2005-11-28
ADM6993/X
Interface Description
Table 7
LED Interface (13 Pins)
Pin or
Ball
No.
Name
Pin
Type
Buffer Function
Type
113
LNKACT_0
I/O
TTL
PD
8mA
114
PORT0 Link & Active LED/Link LED.
If LEDMODE_0 is 1, this pin indicates both link status and RX/TX
activity. When link status is LINK_UP, LNKACT_0 will be turned
on. While PORT0 is receiving/transmitting data, LNKACT_0 will
be off for 100ms and then on for 100ms.
If LEDMODE_0 is 0, this pin only indicates RX/TX activity.
LED_DATA_0
Port0 LED DATA
LEDMODE_0
LED mode for LINK/ACT LED of PORT0.
During power on reset, value will be latched by ADM6993/X at the
rising edge of RESETL as LEDMODE_0.
LNKACT_1
I/O
TTL
PD
8mA
PORT1 Link & Active LED/Link LED.
If LEDMODE_2 is 1, this pin indicates both link status and RX/TX
activity. When link status is LINK_UP, LNKACT_1 will be turned
on. While PORT1 is receiving/transmitting data, LNKACT_1 will
be off for 100ms and then on for 100ms.
If LEDMODE_2 is 0, this pin only indicates RX/TX activity.
LED_DATA_1
Port1 LED DATA
LEDMODE_1
LED mode DUPLEX/COL LED of PORT0 & PORT1.
During power on reset, value will be latched by ADM6993/X at the
rising edge of RESETL as LEDMODE_1.
If LEDMODE_1 is 1, DUPCOL[1:0] will display both duplex
condition and collision status.
If LEDMODE_1 is 0, only collision status will be displayed.
30
LEDMODE_2
I
TTL
PD
LED mode for LINK/ACT LED of PORT1
0B
, ACT
1B
, LINK/ACT
124
DUPCOL_0
I/O
TTL
PD
8mA
PORT0 Duplex LED
If LEDMODE_1 is 1, this pin indicates both duplex condition and
collision status. When FULL_DUPLEX, this pin will be turned on
for PORT0. When HALF_DUPLEX and no collision occurs, this
pin will be turned off. When HALF_DUPLEX and a collision
occurs, this pin will be off for 100ms and then on for 100ms.
If LEDMODE_1 is 0, this pin indicates collision status. When in
HALF_DUPLEX and a collision occurs, this pin will be off for
100ms and turn on for 100ms.
LED_COL_0
Port0 Collision LED
DIS_LEARN
Disable Address Learning.
During power on reset, value will be latched by ADM6993/X at the
rising edge of RESETL as DIS_LEARN. If DIS_LEARN is 1, MAC
address learning will be disabled.
Data Sheet
16
Rev 1.11, 2005-11-28
ADM6993/X
Interface Description
Table 7
LED Interface (13 Pins) (cont’d)
Pin or
Ball
No.
Name
Pin
Type
Buffer Function
Type
125
DUPCOL_1
/LED_COL_1
I/O
TTL
PU
8mA
PORT1 Duplex
If LEDMODE_1 is 1, this pin indicates both duplex condition and
collision status. When FULL_DUPLEX, this pin will be turned on
for PORT1. When HALF_DUPLEX and no collision occurs, this
pin will be turned off. When HALF_DUPLEX and a collision
occurs, this pin will be off for 100ms and then on for 100ms. If
LEDMODE_1 is 0, this pin indicates collision status. When
HALF_DUPLEX and a collision occurs, this pin will be off for
100ms and turn on for 100ms.
122
LDSPD_0
I/O
TTL
PU
8mA
PORT0 Speed LED
Used to indicate speed status of PORT0. When operating in
100Mbps this pin is turned on, and when operating in 10Mbps this
pin is off.
RDNT_EN
123
LDSPD_1
Enable Redundant Capability
During power on reset, value will be latched by ADM6993/X at the
rising edge of RESETL as RDNT_EN. If RDNT_EN is 0,
“REDUNDANT” capability will be disabled. For TS1000
application this pin should have a value of 0.
I/O
TTL
PU
8mA
PORT1 Speed LED
Used to indicate speed status of PORT1. When operating in
100Mbps this pin is turned on, and when operating in 10Mbps this
pin is off.
LED_FIBER_SD
LED_FIBER_SD
Used to indicate signal status of PORT1 when ADM6993/X is
operating in converter mode.
SNP_EN
Enable Snooping Mode
During power on reset, value will be latched by ADM6993/X at the
rising edge of RESETL as SNP_EN. If SNP_EN is 0,
“SNOOPING” capability will be disabled.
1
LED_LINK_1
128
LED_LINK_0
3
LED_FULL_1
2
LED_FULL_0
4
LED_LPBK
Data Sheet
O
TTL
8mA
PORT[1:0] Link LED
These pins indicate link status. When link status is LINK_UP,
these pins will be turned on for relevant port.
O
TTL
8mA
PORT[1:0] Full Duplex LED
These pins indicate current duplex condition of PORT0. When
FULL_DUPLEX, these pins will be turned on for relevant port.
When HALF_DUPLEX these pins will be turned off for relevant
port.
O
TTL
8mA
Loop Back Test LED
While performing loop back test this pin is turned on.
17
Rev 1.11, 2005-11-28
ADM6993/X
Interface Description
Table 8
EEPROM Interface (4 Pins)
Pin or
Ball
No.
Name
Pin
Type
Buffer Function
Type
7
EEDO
I
TTL
PU
EEPROM Data Output
Serial data input from EEPROM. This pin is internal pull-up.
12
EECS
I/O
PD
4mA
EEPROM Chip Select
This pin is active high chip enabled for EEPROM. When RESETL
is low, it will be tristate.
11
EECK
I/O
TTL
PU
4mA
Serial Clock
This pin is the EEPROM clock source. When RESETL is low, it will
be tristate. This pin is internal pull-up.
8
EEDI
I/O
TTL
PU
4mA
EEPROM Serial Data Input
This pin is the output for serial data transfer. When RESETL is
low, it will be tristate.
Table 9
Configuration Interface (28 Pins)
Pin or
Ball
No.
Name
Pin
Type
Buffer
Type
Function
16
P0_ANDIS
I
TTL
PD
Auto-Negotiation Disable for PORT0
0B
E, Enable
1B
D, Disable
17
P0_RECHALF
I
TTL
PD
Recommend Half Duplex Communication for PORT0
0B
F, Full
1B
H, Half
18
P0_REC10
I
TTL
PD
Recommend 10M for PORT0
0B
100, 100M
1B
10, 10M
19
P0_FCDIS
I
TTL
PD
Flow Control Disable for PORT0
0B
E, Enable
1B
D, Disable
22
P1_ANDIS
I
TTL
PD
Auto-Negotiation Disable for PORT1
0B
E, Enable
1B
D, Disable
23
P1_RECHALF
I
TTL
PD
Recommend Half Duplex Communication for PORT1
0B
F, Full
1B
H, Half
24
P1_REC10
I
TTL
PD
Recommend 10M for PORT1
0B
100, 100M
1B
10, 10M
25
P1_FCDIS
I
TTL
PD
Flow Control Disable for PORT1
0B
E, Enable
1B
D, Disable
63
P2_FCDIS
I
TTL
PD
Flow Control Disable for PORT2
0B
E, Enable
1B
D, Disable
Data Sheet
18
Rev 1.11, 2005-11-28
ADM6993/X
Interface Description
Table 9
Configuration Interface (28 Pins) (cont’d)
Pin or
Ball
No.
Name
Pin
Type
Buffer
Type
Function
67
XOVEN
I
TTL
PD
Auto-MDIX Enable.
0B
D, Disable
1B
E, Enable
68
P0_MDI
I
TTL
PU
MDI/MDIX Control for PORT0
This setting will be ignore if enable Auto-MDIX.
0B
MDIX, MDIX
1B
MDI, MDI
21, 20
FTPR_MODE[1: I
0
TTL
PD
Fault Propagation Mode
00B R, Reserved
01B Fx, FX fail -> UTP fail, UTP fail -> FX transmit FEFI
10B R, Reserved
11B D, Disable
99
LPBK_P0
I
TTL
PD
Enable Loop Back Test for PORT0
0B
D, Disable
1B
E, Enable
98
LPBK_P1
I
TTL
PD
Enable Loop Back Test for PORT1
0B
D, Disable
1B
E, Enable
97
LPBK_P2
I
TTL
PD
Enable Loop Back Test for PORT2
0B
D, Disable
1B
E, Enable
101
CHIP_DIS
I
TTL
PD
Chip Disable
0B
D, Disable
1B
E, Enable
100
CAS_DIS
O
TTL
4mA
Disable Cascaded Chip
0B
D, Disable
1B
E, Enable
102
LPT_DIS
I
TTL
PD
Link Pass Through Disable
0B
E, Enable
1B
D, Disable
29
BYPASS_PAUS I
E
TTL
PD
Bypass Frame
The destination address is reserved IEEE MAC address
0B
D, Disable
1B
E, Enable
Table 10
Ground/Power Interface (27 Pins)
Pin or
Ball
No.
Name
Pin
Type
42, 48
GNDTR
GND, A
Ground
Used by AD receiver/transmitter block.
39, 51
VCCA2
PWR, A
2.5 V used for Analogue block
45
VCCAD
PWR, A
3.3 V used for TX line driver
Data Sheet
Buffer
Type
Function
19
Rev 1.11, 2005-11-28
ADM6993/X
Interface Description
Table 10
Ground/Power Interface (27 Pins) (cont’d)
Pin or
Ball
No.
Name
Pin
Type
36
GNDBIAS
GND, A
Ground used by digital substrate
38
VCCBIAS
PWR, A
3.3 V used for bios block
33
GNDPLL
GND, A
Ground used by PLL
32
VCCPLL
PWR, A
2.5 V used for PLL
13, 52, GNDIK
64, 89,
109,
110
GND, D
Ground used by digital core and pre-driver
9, 10,
VCCIK
57, 91,
115,
116
PWR, D
2.5 V used for digital core and pre-driver
77,
118,
119
GNDO
GND, D
Ground used by digital pad
79,
126,
127
VCC3O
PWR, D
3.3 V used for digital pad.
Table 11
Buffer
Type
Function
Miscellaneous (14 Pins)
Pin or
Ball
No.
Name
Pin
Type
Buffer
Type
Function
6
INT
O
TTL
OD
4mA
Interrupt
This pin will be used to interrupt external management device.
This is a low active and open drain pin.
15
SDIO
I/O
TTL
PU
8mA
Serial Management Data
This pin is in/out to PHY. When RESETL is low, this pin will be
tristate.
14
SDC
I
TTL
8mA
Serial Management Data Clock
78
CKO25M
O
TTL
PU
8mA
50M output for RMII and 25M Clock output for others
34
CONTROL
AO
FET Control Signal
The pin is used to control FET for 3.3 V to 2.5 V regulator.
37
RTX
A
TX Resistor
35
VREF
A
Analog Power Failure Detected
26
RC
I
27
XI
AI
Data Sheet
TTL
ST
RC Input for Power On Reset
ADM6993/X sample pin RC as RESETL with the clock input
from pin XI.
25M Crystal Input
25M Crystal Input. Variation is limited to +/- 50ppm.
20
Rev 1.11, 2005-11-28
ADM6993/X
Interface Description
Table 11
Miscellaneous (14 Pins) (cont’d)
Pin or
Ball
No.
Name
Pin
Type
28
XO
AO
5, 31,
62, 65,
66, 69,
70, 71,
72, 73,
74, 75,
76
NC
Buffer
Type
Function
25M Crystal Output
When connected to oscillator, this pin should left unconnected.
No Connection
2.4
Port 2 MII/RMII/GPSI/HDLC Interfaces Comparison
Table 12
Port 2 MII/RMII/GPSI/HDLC Interfaces Comparison
Pin No.
MII
RMII
GPSI
HDLC
87
P2TXD0(O)
P2TXD0(O)
P2TXD0(O)
P2TXD0(O)
86
P2TXD1(O)
P2TXD1(O)
85
P2TXD2(O)
84
P2TXD3(O)
88
P2TXEN(O)
No Support
P2TXER(O)
90
P2TXCLK(I)
105
P2RXD0(I)
P2RXD0(I)
106
P2RXD1(I)
P2RXD1(I)
107
P2RXD2(I)
108
P2RXD3(I)
104
P2RXDV(I)
P2CRS_DV(I)
No Support
P2RXER(I)
P2RXER(I)
93
P2COL(I)
92
P2CRS(I)
103
P2RXCLK(I)
P2REFCLK(I)
P2RXCLK(I)
P2RXCLK(I)
96
P2LINKF(I)
P2LINKF(I)
P2LINKF(I)
P2LINKF(I)=’0’
95
P2SPDTEN(I)
P2SPDTEN(I)
P2SPDTEN(I)
94
P2DPHALF(I)
P2DPHALF(I)
P2DPHALF(I)
P2TXEN(O)
P2TXE(O)
P2RXCLK(I)
P2RXCLK(I)
P2RXD0(I)
P2RXD0(I)
P2RXE/CRS(I)
P2COL(I)
Port Status
ADM6993/X doesn't provide MDC/MDIO to access external PHY, but provides PxLINKF, PxSPDTEN, and
PxDPHALF to update MAC status from external PHY LINK/SPEED/DUPLEX LED pin.PxLINKF, Input = 1B means
unlink, 0B means link.PxSPDTEN, Input = 1B means 10Mbps, 0B means 100Mbps.PxDPHALF, Input = 1B means
Half Duplex, 0B means Full Duplex.
Data Sheet
21
Rev 1.11, 2005-11-28
ADM6993/X
Function Description
3
Function Description
The ADM6993/X integrates a two 100Base-X physical layer device (PHY), two complete 10Base-T modules, a 3port 10/100 switch controller and memory into a single chip for both 10 Mbps and 100 Mbps Ethernet switch
operations. It also supports 100Base-FX operation through external fiber-optic transceivers. The device is capable
of operating in either Full-Duplex or Half-Duplex mode in both 10 Mbps and 100 Mbps operations. Operation
modes can be selected by hardware configuration pins, software settings of management registers, or determined
by the on-chip auto negotiation logic.
The ADM6993/X consists of four major blocks:
•
•
•
10/100M PHY Block
Switch Controller Block
Built-in 6Kx64 SSRAM
3.1
10/100M PHY Block
The 100Base-X section of the device implements the following functional blocks:
•
•
•
100Base-X physical coding sub-layer (PCS)
100Base-X physical medium attachment (PMA)
100Base-X physical medium dependent (PMD)
The 10Base-T section of the device implements the following functional blocks:
•
•
10Base-T physical layer signaling (PLS)
10Base-T physical medium attachment (PMA)
The 100Base-X and 10Base-T sections share the following functional blocks:
•
•
•
Clock synthesizer module
MII Registers
IEEE 802.3u auto negotiation
The interfaces used for the communication between the PHY block and the switch core is a MII interface.
An Auto MDIX function is supported. This function can be Enabled/Disabled by using the hardware pin. A digital
approach for the integrated PHY of the ADM6993/X has been adopted.
Data Sheet
22
Rev 1.11, 2005-11-28
ADM6993/X
Function Description
3.2
Auto Negotiation and Speed Configuration
3.2.1
Auto Negotiation
The Auto Negotiation function provides a mechanism for exchanging configuration information between two ends
of a link segment and automatically selecting the highest performance mode of operations supported by both
devices. Fast Link Pulse (FLP) Bursts provide the signaling used to communicate auto negotiation abilities
between two devices at each end of a link segment. For further detail regarding auto negotiation, refer to Clause
28 of the IEEE 802.3u specification. The ADM6993/X supports four different Ethernet protocols, so the inclusion
of auto negotiation ensures that the highest performance protocol will be selected based on the ability of the link
partner.
The auto negotiation function within the ADM6993/X can be controlled either by internal register access or by the
use of configuration pins. If disabled, auto negotiation will not occur until software enables bit 12 in MII Register
0. If auto negotiation is enabled, the negotiation process will commence immediately.
When auto negotiation is enabled, the ADM6993/X transmits the abilities programmed into the auto negotiation
advertisement register at address 04H via FLP bursts. Any combination of 10 Mbps, 100 Mbps, half duplex, and
full duplex modes may be selected. Auto negotiation controls the exchange of configuration information. Upon
successfully auto negotiating, the abilities reported by the link partner are stored in the auto negotiation link partner
ability register at address 05H.
The contents of the “auto negotiation link partner ability register” are used to automatically configure the highest
performance protocol between the local and far-end nodes. Software can determine which mode has been
configured by auto negotiation, by comparing the contents of register 04H and 05H and then selecting the
technology whose bit is set in both registers of highest priority relative to the following list:
1.
2.
3.
4.
100Base-TX full duplex (highest priority)
100Base-TX half duplex
10Base-T full duplex
10Base-T half duplex (lowest priority)
The basic mode control register at address 0H controls the enabling, disabling and restarting of the auto
negotiation function. When auto negotiation is disabled, the speed selection bit (bit 13) controls switching between
10 Mbps or 100 Mbps operation, while the duplex mode bit (bit 8) controls switching between full duplex operation
and half duplex operation. The speed selection and duplex mode bits have no effect on the mode of operations
when the auto negotiation enable bit (bit 12) is set.
The basic mode status register at address 1H indicates the set of available abilities for technology types (bit 15 to
bit 11), auto negotiation ability (bit 3), and extended register capability (bit 0). These bits are hardwired to indicate
the full functionality of the ADM6993/X. The BMSR also provides status on:
•
•
•
Whether auto negotiation is complete (bit 5)
Whether the Link Partner is advertising that a remote fault has occurred (bit 4)
Whether a valid link has been established (bit 2)
The auto negotiation advertisement register at address 4H indicates the auto negotiation abilities to be advertised
by the ADM6993/X. All available abilities are transmitted by default, but writing to this register or configuring
external pins can suppress any ability.
The auto negotiation link partner ability register at address 05H indicates the abilities of the Link Partner as
indicated by auto negotiation communication. The contents of this register are considered valid when the auto
negotiation complete bit (bit 5, register address 1H) is set.
3.2.2
Speed Configuration
The twelve sets of four pins listed in Table 13 configure the speed capability of each channel of the ADM6993/X.
The logic states of these pins are latched into the advertisement register (register address 4H) for auto negotiation
Data Sheet
23
Rev 1.11, 2005-11-28
ADM6993/X
Function Description
purpose. These pins are also used for evaluating the default value in the base mode control register (register 0H)
according to Table 13.
In order to make these pins with the same Read/Write priority as software, they should be programmed to
11111111B in case a user wishes to update the advertisement register through software.
Table 13
Speed Configuration
Advertis
e all
capabilit
y
Advertis
e single
capabili
ty
Paralle
l detect
follow
IEEE
std.
Auto
Negotiation
(Pin &
EEPROM)
Speed
(Pin &
EEPROM
)
Duplex
Auto
Negot
(Pin &
EEPROM iation
)
Advertise
Capability
1
0
0
1
X
X
1
1
1
1
1
1
0
1
0
1
0
1
1
X
X
1
1
1
1
1
0
1
0
1
1
1
0
1
X
X
1
1
0
0
0
1
0
0
0
1
1
1
1
X
X
1
1
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
1
0
0
0
1
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
X
1
1
0
1
0
1
0
1
0
1
0
1
0
1
X
1
1
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
1
1
0
0
1
1
0
0
1
0
0
0
1
1
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
0
1
1
1
0
1
1
0
0
1
0
0
0
0
1
0
X
X
1
0
0
1
0
0
0
1
0
0
0
1
X
X
X
0
1
1
0
1
—
—
—
—
—
—
—
X
X
X
0
1
0
0
—
1
—
—
—
—
—
—
X
X
X
0
0
1
0
—
—
1
—
—
—
—
—
X
X
X
0
0
0
0
—
—
—
1
—
—
—
—
3.3
Parallel Detect
Capability
10 10 10 10 10 10 10 10
0F 0H F H 0F 0H F H
Switch Functional Description
The ADM6993/X uses a “store & forward” switching approach for the following reason:
Store & forward switches allow switching between different speed media (e.g. 10BaseX and 100BaseX). Such
switches require the large elastic buffer especially bridging between a server on a 100Mbps network and clients
on a 10Mbps segment.
Store & forward switches improve overall network performance by acting as a “network cache”
Store & forward switches prevent the forwarding of corrupted packets by the frame check sequence (FCS) before
forwarding to the destination port.
3.3.1
Basic Operation
The ADM6993/X receives incoming packets from one of its ports, searches in the Address Table for the
Destination MAC Address and then forwards the packet to the other port within the same VLAN group, if
appropriate. If the destination address is not found in the address table, the ADM6993/X treats the packet as a
broadcast packet and forwards the packet to the other ports which in the same VLAN group.
Data Sheet
24
Rev 1.11, 2005-11-28
ADM6993/X
Function Description
The ADM6993/X automatically learns the port number of attached network devices by examining the Source MAC
Address of all incoming packets at wire speed. If the Source Address is not found in the Address Table, the device
adds it to the table.
3.3.2
Address Learning
The ADM6993/X uses a hash algorithm to learn the MAC address and can learn up to 2K MAC addresses.
Address is stored in the Address Table. The ADM6993/X searches for the Source Address (SA) of an incoming
packet in the Address Table and acts as below:
If the SA was not found in the Address Table (a new address), the ADM6993/X waits until the end of the packet
(non-error packet) and updates the Address Table. If the SA was found in the Address Table, then aging value of
each corresponding entry will be reset to 0.
When the DA is PAUSE command, then the learning process will be disabled automatically by ADM6993/X.
3.3.3
Address Recognition and Packet Forwarding
The ADM6993/X forwards the incoming packets between bridged ports according to the Destination Address (DA)
as below. All the packet forwarding will check VLAN first. A forwarding port must be within the same VLAN as the
source port.
1. If the DA is an UNICAST address and the address was found in the Address Table, the ADM6993/X will check
the port number and acts as follows:
a) If the port number is equal to the port on which the packet was received, the packet is discarded.
b) If the port number is different, the packet is forwarded across the bridge.
2. If the DA is an UNICAST address and the address was not found, the ADM6993/X treats it as a multicast
packet and forwards across the bridge.
3. If the DA is a Multicast address, the packet is forwarded across the bridge.
4. If the DA is PAUSE Command (01-80-C2-00-00-01), then this packet will be dropped by ADM6993/X.
ADM6993/X can issue and learn PAUSE command.
5. ADM6993/X will forward by defaulted or filtering out the packet with DA of (01-80-C2-00-00-00), discarding the
packet with DA of (01-80-C2-00-00-01), filtering out the packet with DA of (01-80-C2-00-00-02 ~ 01-80-C2-0000-0F), and forwarding the packet with DA of (01-80-C2-00-00-10 ~ 01-80-C2-00-00-FF) decided by EEPROM
Reg.7H.
3.3.4
Address Aging
Address aging is supported for topology changes such as an address moving from one port to the other. When
this happens, the ADM6993/X internally has a 300 seconds timer will aged out (remove) the address from the
address table. Aging function can be enabled/disabled by user. Normally, disabling aging function is for security
purpose.
3.3.5
Buffers and Queues
The ADM6993/X incorporates transmitted queues and the receiving buffer area for the three ETHERNET ports.
The receiving buffers as well as the transmitted queues are located within the ADM6993/X along with the switch
fabric. The buffers are divided into 192 blocks of 256 bytes each. The queues of each port are managed according
to each port's read/write pointer.
3.3.6
Back off Algorithm
The ADM6993/X implements the truncated exponential back off algorithm compliant to the IEEE802.3 CSMA/CD
standard. ADM6993/X will restart the back off algorithm by choosing 0-9 collision counts. The ADM6993/X resets
the collision counter after 16 consecutive retransmit trials.
Data Sheet
25
Rev 1.11, 2005-11-28
ADM6993/X
Function Description
3.3.7
Inter-Packet Gap (IPG)
IPG is the idle time between any two successive packets from the same port. The typical number is 96-bits time.
The value is 9.6µs for 10Mbps ETHERNET, and 960ns for 100Mbps fast ETHERNET. ADM6993/X provides the
option of a 92-bit gap in EEPROM to prevent packet lost when Flow Control is turned off and clock P.P.M. value
differs.
3.3.8
Illegal Frames
The ADM6993/X will discard all illegal frames such as runt packet (less than 64 bytes), oversize packet (greater
than 1518 or 1522 bytes) and bad CRC. Dribbling packing with good CRC value will accept by ADM6993/X. In
case of bypass mode enabled, ADM6993/X will support tagged up to 1522bytes, and untagged packets up to 1518
bytes. In case of non-bypass mode, ADM6993/X will support tagged packets up to 1522 bytes, and untagged
packets up to 1518 bytes.
3.3.9
Half Duplex Flow Control
Back Pressure function is supported for half-duplex operation. When the ADM6993/X cannot allocate a receiving
buffer for an incoming packet (buffer full), the device will transmit a jam pattern on the port, thus forcing a collision.
Back Pressure is enabled by the BPEN set during RESET asserting. An Infineon-ADMtek Co Ltd proprietary
algorithm is implemented inside the ADM6993/X to prevent back pressure function causing HUB partitioned under
heavy traffic environment and reduce the packet lost rate to increase the whole system performance.
3.3.10
Full Duplex Flow Control
When full duplex port runs out of its receiving buffer, a PAUSE packet command will be issued by ADM6993/X to
notice the packet sender to pause the transmission. This frame based flow control is totally compliant to IEEE
802.3x. ADM6993/X can issue or receive pause packet.
3.3.11
Broadcast Storm Filter
If Broadcast Storming filter is enable, the broadcast packets over the rising threshold within 50 ms will be discarded
by the threshold setting. See EEPROM Reg.5H.
Broadcast storm mode after initial:
Time interval: 50 ms
The max. packet number = 7490 in 100Base, 749 in 10Base
Table 14
Port Rising/Falling Threshold
Per Port Rising Threshold
00
01
10
11
All 100TX
Disable
10%
20%
40%
Not All 100TX
Disable
1%
2%
4%
00
01
10
11
All 100TX
Disable
5%
10%
20%
Not All 100TX
Disable
0.5%
1%
2%
Per Port Falling Threshold
Data Sheet
26
Rev 1.11, 2005-11-28
ADM6993/X
Function Description
Table 15
Drop Scheme for each queue
Drop Scheme for each queue
Discard Mode 00
Utilization
01
10
11
00
0%
0%
0%
0%
01
0%
0%
25%
50%
11
0%
25%
50%
75%
3.3.12
Auto TP MDIX Function
At normal application which Switch connect to NIC card is by one by one TP cable. If Switch connects other device
such as another Switch must by two way. First one is Cross Over TP cable. Second way is to use extra RJ45 which
crossover internal TX+- and RX+- signal. By second way customers can use one by one cable to connect two
Switch devices. All these efforts need extra cost and are not good solutions. ADM6993/X provides Auto MDIX
function which can adjust TX+- and RX+- at correct pin. Users can use one by one cable between ADM6993/X
and other device either switches or NICs.
3.4
Converter Functional Description
3.4.1
Fault Propagation
The ADM6993/X Media Converter incorporates a Fault Propagation feature, which allows indirect sensing of a
Fiber Link Loss via the 10/100Base-TX UTP connection. Whenever the ADM6993/X Media Converter detects a
Link Loss condition on the Receive fiber (Fiber LNK OFF), it disables its UTP link pulse so that a Link Loss
condition will be sensed on the UTP port to which the ADM6993/X Media Converter is connected. This link loss
can then be sensed and reported by a Network Management agent in the remote UTP port's host equipment. This
feature will affect the ADM6993/X UTP LNK LED.
The ADM6993/X Media Converter also incorporates a Far End Fault feature, which allows the stations on both
ends of a pairs of fibers to be informed when there is a problem with one of the fibers. Without Far End Fault, it is
impossible for a fiber interface to detect a problem that affects only its Transmitting fiber.
When Far End Fault is supported and enabled, a loss of received signal (link) will cause the transmitter to generate
a Far End Fault pattern in order to inform the device at the far end of the fiber pair that a fault has occurred. Unless
Fiber Link Loss occurred, if the UTP port link failed, the ADM6993/X Media Converter will also generate a Far End
Fault pattern in order to inform the device at the far end of the fiber pair that a fault has occurred.
3.4.2
Redundant Link
The ADM6993/X Media Converter incorporates a Redundant Link feature, which allows designing a cost-effective
Redundant TX FX Media Converter to provide a more reliable fiber link.
At converter mode (FXMODE[1:0]=10 and RDNT_EN=1), pin CAS_DIS of primary ADM6993/X connects to pin
CHIP_DIS of secondary ADM6993/X.
•
•
•
While FX port works well, pin CAS_DIS will output “1” to disable 2nd ADM6993/X
While FX fiber link loss or the remote fault detection happens, pin CAS_DIS will output “0” to enable 2nd
ADM6993/X.
While ADM6993/X disable, TX port will become Hi-Z state.
Data Sheet
27
Rev 1.11, 2005-11-28
ADM6993/X
Function Description
3.4.3
Loop-Back mode
The ADM6993/X Media Converter incorporates a Loop-Back mode, which allows users or ISP to diagnose the
local or the remote network equipment. The loop-back is used to check the operation of the switch and ensure the
device's connection on the media side.
•
•
•
While LPBK_P0=1, the received data from Port 1/Port 2 will be routed through the receiving path back to the
transmitting path on Port 0 MII interface (between switch core and embedded port 0 PHY).
While LPBK_P1=1, the received data from Port 0/Port 2 will be routed through the receiving path back to the
transmitting path on Port 1 MII interface (between switch core and embedded port 1 PHY).
While LPBK_P2=1, the received data from Port 0/Port 1 will be routed through the receiving path back to the
transmitting path on Port 2 MII interface.
Note: The address learning, packet filter, CRC check, length check and loop-back function are not performed in
snooping mode.
3.4.4
Snooping mode
The ADM6993/X Media Converter incorporates a Snooping mode, which allows packets perform cut-through
between TX<-->FX while both TX and FX ports operate on 100M Full mode. On snooping mode, the packets will
not enter the switch core to perform store and forward mechanisms.
•
•
While SNP_EN=1, the ADM6993/X TX FX Media Converter will act TX<-->FX bridge while both TX and FX
ports operate on 100M mode.
While SNP_EN=0, the ADM6993/X TX FX Media Converter will force all packets to enter the switch core to
perform store and forward mechanisms.
3.4.5
Fiber_SD LED
The ADM6993/X Media Converter provides a Fiber_SD LED on original LDSPD_1 pin. Fiber_SD is used to
indicate the signal status of the fiber port.
3.5
Serial Management Interface (SMI) Register Access
The SMI consists of two pins, management data clock (SDC) and management data input/output (SDIO). The
ADM6993/X is designed to support an SDC frequency up to 25 MHz. The SDIO line is bi-directional and may be
shared with other devices.
The SDIO pin requires a 1.5 KΩ pull-up which, during idle and turn around periods, will pull SDIO to a logic “1“
state. ADM6993/X requires a single initialization sequence of 35 bits of preamble following power-up/hardware
reset. The first 35 bits are preamble consisting of 35 contiguous logic “1“bits on SDIO and 35 corresponding cycles
on SDC. Following preamble, the start-of-frame field is indicated by a <01> pattern. The next field signals the
operation code (OP): <10> indicates read from management register operation, and <01> indicates write to
management register operation. The next field is management register address. It is 10 bits wide and the most
significant bit is transferred first.
Table 16
SMI Read/Write Command Format
Operation
Preamble
SFD
OP CHIPID[1:0]
Unused
Register
Address
TA Data
Read
35”1”s
01
10
2 bits
000
5 bits Address
Z0
32 bits Data
Read
Write
35”1”s
01
01
2 bits
000
5 bits Address
10
32 bits Data
Write
Data Sheet
28
Rev 1.11, 2005-11-28
ADM6993/X
Function Description
During Read operation, a 2-bit turn around (TA) time spacing between the register address field and data field is
provided for the SDIO to avoid contention. Following the turnaround time, a 32-bit data stream is read from or
written into the management registers of the ADM6993/X.
SDC
SDIO
(STA)
SDIO
(AD2109)
z
0
Preamble
1
1
0
0
Opcode
(Read)
Start
0
0
Unused
0
0
0
0
0
0
0
Register Address (5'h0 in this
example)
ID[1:0]
z
0
0
0
1
0
0
TA
1
1
0
0
~
~
0
0
0
0
z
Register Data (32'h13000000 in this Example)
SMI Read Operation
Figure 3
SMI Read Operation
SDC
SDIO (STA)
z
0
Preamble
1
Start
0
1
Opcode
(Write)
0
0
0
Unused
0
0
0
ID[1:0]
0
0
0
0
Register Address (5'h0 in this
example)
1
0
0
0
0
TA
1
0
0
1
1
0
0
0
~
~
0
0
0
z
Register Data (32'h13000000 in this Example)
SMI Write Operation
Figure 4
SMI Write Operation
3.5.1
Preamble Suppression
The SMI of ADM6993/X supports a preamble suppression mode. If the station management entity (i.e. MAC or
other management controller) determines that all devices which are connected to the same SDC/SDIO in the
system support preamble suppression, then the station management entity needs not generate preamble for each
management transaction. The ADM6993/X requires a single initialization sequence of 35 bits of preamble
following power-up/hardware reset. This requirement is generally met by pulling-up the resistor of SDIO. While the
ADM6993/X will respond to management accesses without preamble, a minimum of one idle bit between
management transactions is required.
When ADM6993/X detects that there is address match, then it will enable Read/Write capability for external
access. When an address is mismatched, then ADM6993/X will tri-state the SDIO pin.
3.5.2
Read EEPROM Register via SMI Register
The following 2 steps are for reading the data of EEPROM Register via SMI Interface.
Write the address of the desired EEPROM Register and READ command to SMI Register 04H
EX. <35”1”s><01><01><00000><00100><10><000 0000000 000001 0000000000000000>
CMD ADDRESS DATA
Read ADM6993/X Internal EEPROM mapping Reg.1H. Read SMI Register 04. The data of desired EEPROM
Register will be in bit [15:0].
EX. <35”1”s><01><10><00000><00100><z0><000 0000000 000000 1000001000001111>
CMD ADDRESS DATA
Get ADM6993/X Internal EEPROM mapping Reg.1H. value 820f.
Data Sheet
29
Rev 1.11, 2005-11-28
ADM6993/X
Function Description
3.5.3
Write EEPROM Register via SMI Register
To write data into desired EEPROM Register, write the address of the EEPROM Register.
EX. <35”1”s><01><01><00000><00100><10><001 0000000 000001 1000001000001111>
CMD ADDRESS DATA
Write ADM6993/X Internal EEPROM mapping Reg.1H. with value 820f.
3.6
HDLC Controller
The ADM6993/X has an interface to HDLC. The main function is to forward Ethernet Packet from local LAN to
WAN.
3.6.1
HDLC Frame Receiver
A received packet consists of an opening flag, data bytes, a 16-bit CRC, and a closing flag. The received cycle
starts with the detection of data after the opening flag in the packet. After a flag is detected, the HDLC checks the
data bit stream for minimum (less then 62 bytes including CRC-16) and maximum (more than 1534 bytes including
CRC-16) packet lengths, zero deletion, abort characters, and idle characters. HDLC Controller will remove CRC16 2 byte in the received packet before writing to BUFFER.
Clocking The HDLC Controller Receiver gets data from HDLC_RXD at the positive edge of HDLC_RXCLK.
Flag Detection The HDLC supports the following received flag (01111110) sequence:
Multiple flags between packets
(.......0111111001111110......)
A flag shared as the closing and opening flags between two packets
(......Data CRC 01111110 Data......)
A shared zero between flags
(......011111101111110......)
All incoming flags are ignored and discarded by the HDLC. The first bit received, which is not a part of the flag
character, signifies the start of the packet. If a flag is received during a packet, it indicates the end of the packet.
The CRC is checked (the last two bytes of the packet), and a decision is generated to forward or not.
Zero Deletion Each bit received between the opening and closing flag is checked for zero bit insertion. A zero that
follows five contiguous ones is discarded from the incoming bit stream. HDLC is defined this feature to avoid the
occurrence of flags in user data field.
Cyclic Redundancy Check (CRC) The frame check sequence (FCS) consists of 16 bits immediately preceding
the closing flag. The 16-bit FCS detects data errors through the use of a cycle redundancy check (CRC) code. The
CRC is generated from the incoming data and compared against the received CRC (remainder), carried in the FCS
field of the packet. If the comparison does not match because of a bit error or burst error, the HDLC discards the
packet by flushing the memory buffer regions, and waits for the next packet to be received. The CRC check
polynomials are as follows:
CRC-16: X16+X12+X5+1
3.6.2
HDLC Frame Transmitter
A transmitted packet consists of an opening flag, data bytes, 16-bit CRC, and a closing flag. The transmitter timing
is asynchronous in relationship with the receive timing.
Clocking The HDLC Controller Transmitter send data to HDLC_TXD at the positive edge of external
HDLC_TXCLK.
Flag Generation The HDLC Controller generates either (01111110) or multiple flags (0111111001111110...),
depending on the packet data present in the BUFFER stored by LAN interface.
Data Sheet
30
Rev 1.11, 2005-11-28
ADM6993/X
Function Description
Zero Insertion The data in the packet read from the BUFFER is checked for the number of contiguous ones prior
to the transmission. A zero is inserted into the transmitted bit stream after five contiguous ones are detected,
excluding Flags or Abort characters. By this, HDLC can avoid the confusion between flag and data, which has the
same value with flag.
Cyclic Redundancy Check (CRC) Generation The Frame Check Sequence (FCS) consists of 16 bits
immediately preceding the closing flag. The 16-bit FCS detects data errors through the use of a cycle redundancy
check (CRC) code. When all user data is transmitted, the calculated value is transmitted after the last data byte,
and encloses the frame with a closing flag. The CRC check polynomials are as follows:
CRC-16: X16+X12+X5+1
3.7
Reset Operation
The ADM6993/X can be reset either by hardware or software. A hardware reset is accomplished by applying a
negative pulse, with the duration of at least 100 ms to the RC pin of the ADM6993/X during normal operation to
guarantee internal SSRAM is reset well.
Hardware reset operation samples the pins and initializes all registers to their default values. This process includes
re-evaluation of all hardware configurable registers. A hardware reset affects all embedded PHYs in the device.
Software reset can reset all embedded PHY and it does not latch the external pins nor reset the registers to their
respective default value. This can be achieved by writing FF to EEPROM Reg.3FH.
Logic levels on several I/O pins are detected during a hardware reset to determine the initial functionality of
ADM6993/X. Some of these pins are used as output ports after reset operation.
Care must be taken to ensure that the configuration setup will not interfere with normal operations. Dedicated
configuration pins can be tied to VCC or Ground directly. Configuration pins multiplexed with logic level output
functions should be either weakly pulled up or weakly pulled down through external resistors.
3.7.1
Write EEPROM Register via EEPROM Interface
To write data into desired EEPROM Register via EEPROM interface:
If external EEPROM 93C46 or 93C66 exists, any WRITE programming instructions after EWEN instruction be
executed can be updated effectively on EEPROM content and ADM6993/X internal mapping register on the same
time.
If no external EEPROM exists, EECS/EECK/EEDI must be kept tri-state at least 100ms after hardware reset. Any
WRITE programming instructions after EWEN instruction be executed can be updated effectively on ADM6993/X
internal mapping register. Please notice that ADM6993/X can only identify 93C66-programming instructions if no
external EEPROM.
Data Sheet
31
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
4
Registers Description
This chapter describes descriptions of EEPROM Registers and SMI Registers.
4.1
EEPROM Registers
Table 17
EEPROM Register Map
Register
Bit 15-8
00H
Signature
4154H
01H
Port 0 Configuration
820FH
02H
Port 1 Configuration
820FH
03H
Port 2 Configuration
820FH
04H
TOS priority Map Low
05H
Miscellaneous Configuration 0
C0
06H
Miscellaneous Configuration 1
82E8H
07H
Miscellaneous Configuration 2
1480
08H
Bit 7-0
Port 2 To Port
Map
Default Value
VLAN priority Map Low
Port 1 To Port
Map
Port 0 To Port
Map
F0F0H
777H
09H
Filter Control Register 1
Filter Control Register 0
0H
0AH
Filter Control Register 3
Filter Control Register 2
0H
0BH
Filter Control Register 5
Filter Control Register 4
0H
0CH
Filter Control Register 7
Filter Control Register 6
0H
0DH
Filter Control Register 9
Filter Control Register 8
0H
0EH
Filter Control Register 11
Filter Control Register 10
0H
0FH
Filter Control Register 13
Filter Control Register 12
0H
10H
Filter Control Register 15
Filter Control Register 14
0H
11H
Filter Type Register 0
0H
12H
Filter Type Register 1
0H
13H
Filter Register 0
0H
14H
Filter Register 1
0H
15H
Filter Register 2
0H
16H
Filter Register 3
0H
17H
Filter Register 4
0H
18H
Filter Register 5
0H
19H
Filter Register 6
0H
1AH
Filter Register 7
0H
1BH
Filter Register 8
0H
1CH
Filter Register 9
0H
1DH
Filter Register 10
0H
1EH
Filter Register 11
0H
1FH
Filter Register 12
0H
20H
Filter Register 13
0H
21H
Filter Register 14
0H
Data Sheet
32
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
Table 17
EEPROM Register Map (cont’d)
Register
Bit 15-8
22H
Filter Register 15
0H
23H
PVID and PCID MASK of Port 0
1H
24H
PVID and PCID MASK of Port 0
0H
25H
PVID and PCID MASK of Port 1
1H
26H
PVID and PCID MASK of Port 1
0H
27H
PVID and PCID MASK of Port 2
1H
28H
PVID and PCID MASK of Port 2
0H
29H
Tag Rule 0
F000H
2AH
Tag Rule 0
00FFH
2BH
Tag Rule 1
F000H
2CH
Tag Rule 1
00FFH
2DH
Tag Rule 2
F000H
2EH
Tag Rule 2
00FFH
2FH
Tag Rule 3
F000H
30H
Tag Rule 3
00FFH
31H
Tag Rule 4
F000H
32H
Tag Rule 4
00FFH
33H
Tag Rule 5
F000H
34H
Tag Rule 5
00FFH
35H
Tag Rule 6
F000H
36H
Tag Rule 6
00FFH
37H
Tag Rule 7
F000H
38H
Tag Rule 7
00FFH
39H
Miscellaneous Configuration 2
0000H
3AH
Vendor Code[15:0]
0000H
3BH
Model Number [7:0]
3CH
Vendor Code[23:8]
Data Sheet
Bit 7-0
Vendor Code [23:16]
Default Value
0000H
0000H
33
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
4.2
EEPROM Register Descriptions
Table 18
Registers Address Space
Module
Base Address
End Address
EEPROM
00H
3CH
Table 19
Note
Registers Overview
Register Short Name
Register Long Name
Offset Address
Page Number
SR
Signature Register
00H
36
PCR_0
Port Configuration Register 0
01H
36
PCR_1
Port Configuration Register 1
02H
37
PCR_2
Port Configuration Register 2
03H
38
VLAN_TOS_PMR
VLAN(TOS) Priority Map Register
04H
39
MC_0
Miscellaneous Configuration 0
05H
40
MCR_1
Miscellaneous Configuration Register 1
06H
41
MCR_2
Miscellaneous Configuration Register 2
07H
42
PBVLAN_MR
Port Base VLAN port Map Register
08H
42
PCFC_1_0
Packet Filter Control Register 1 and 0
09H
44
TFTR_0
Filter Type Register 0
11H
45
TFTR_1
Filter Type Register 1
12H
45
FR_0
Filter Register 0
13H
46
FR_1
Filter Register 1
14H
46
FR_2
Filter Register 2
15H
46
FR_3
Filter Register 3
16H
46
FR_4
Filter Register 4
17H
46
FR_5
Filter Register 5
18H
46
FR_6
Filter Register 6
19H
46
FR_7
Filter Register 7
1AH
46
FR_8
Filter Register 8
1BH
46
FR_9
Filter Register 9
1CH
47
FR_10
Filter Register 10
1DH
47
FR_11
Filter Register 11
1EH
47
FR_12
Filter Register 12
1FH
47
FR_13
Filter Register 13
20H
47
FR_14
Filter Register 14
21H
47
FR_15
Filter Register 15
22H
47
PB_ID_0_0
Port Base VLAN ID and Mask 0 of Port 0
23H
48
PB_ID_1_0
Port Base VLAN ID and Mask 1 of Port 0
24H
48
PB_ID_0_1
Port Base VLAN ID and Mask 0 of Port 1
25H
49
PB_ID_1_1
Port Base VLAN ID and Mask 1 of Port 1
26H
49
PB_ID_0_2
Port Base VLAN ID and Mask 0 of Port 2
27H
50
PB_ID_1_2
Port Base VLAN ID and Mask 1 of Port 2
28H
50
Data Sheet
34
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
Table 19
Registers Overview (cont’d)
Register Short Name
Register Long Name
Offset Address
Page Number
TPR_0_0
Tag Port Rule 0 Register 0
29H
51
TPR_1_0
Tag Port Rule 1 Register 0
2AH
51
TPR_0_1
Tag Port Rule 0 Register 1
2BH
51
TPR_1_1
Tag Port Rule 1 Register 1
2CH
52
TPR_0_2
Tag Port Rule 0 Register 2
2DH
51
TPR_1_2
Tag Port Rule 1 Register 2
2EH
52
TPR_0_3
Tag Port Rule 0 Register 3
2FH
51
TPR_1_3
Tag Port Rule 1 Register 3
30H
52
TPR_0_4
Tag Port Rule 0 Register 4
31H
51
TPR_1_4
Tag Port Rule 1 Register 4
32H
52
TPR_0_5
Tag Port Rule 0 Register 5
33H
51
TPR_1_5
Tag Port Rule 1 Register 5
34H
52
TPR_0_6
Tag Port Rule 0 Register 6
35H
51
TPR_1_6
Tag Port Rule 1 Register 6
36H
52
TPR_0_7
Tag Port Rule 0 Register 7
37H
51
TPR_1_7
Tag Port Rule 1 Register 7
38H
52
MCR_3
Miscellaneous Configuration Register 3
39H
52
MCR_4
Miscellaneous Configuration 4
3AH
54
MCR_5
Miscellaneous Configuration Register 5
3BH
54
MCR_6
Miscellaneous Configuration Register 6
3CH
54
The register is addressed wordwise.
Table 20
Register Access Types
Mode
Symbol Description HW
Description SW
read/write
rw
Register is used as input for the HW
Register is read and writable by SW
read
r
Register is written by HW (register
Value written by software is ignored by
between input and output -> one cycle hardware; that is, software may write any
delay)
value to this field without affecting hardware
behavior (= Target for development.)
Read only
ro
Register is set by HW (register between SW can only read this register
input and output -> one cycle delay)
Read virtual
rv
Physically, there is no new register, the SW can only read this register
input of the signal is connected directly
to the address multiplexer.
Latch high,
self clearing
lhsc
Latch high signal at high level, clear on SW can read the register
read
Latch low,
self clearing
llsc
Latch high signal at low-level, clear on SW can read the register
read
Latch high,
mask clearing
lhmk
Latch high signal at high level, register SW can read the register, with write mask
cleared with written mask
the register can be cleared (1 clears)
Latch low,
mask clearing
llmk
Latch high signal at low-level, register
cleared on read
Data Sheet
35
SW can read the register, with write mask
the register can be cleared (1 clears)
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
Table 20
Register Access Types (cont’d)
Mode
Symbol Description HW
Description SW
Interrupt high,
self clearing
ihsc
Differentiate the input signal (low>high) register cleared on read
SW can read the register
Interrupt low,
self clearing
ilsc
Differentiate the input signal (high>low) register cleared on read
SW can read the register
Interrupt high,
mask clearing
ihmk
Differentiate the input signal (highSW can read the register, with write mask
>low) register cleared with written mask the register can be cleared
Interrupt low,
mask clearing
ilmk
Differentiate the input signal (low>high) register cleared with written
mask
SW can read the register, with write mask
the register can be cleared
Interrupt enable ien
register
Enables the interrupt source for
interrupt generation
SW can read and write this register
latch_on_reset
lor
rw register, value is latched after first
clock cycle after reset
Register is read and writable by SW
Read/write
self clearing
rwsc
Register is used as input for the hw, the Writing to the register generates a strobe
register will be cleared due to a HW
signal for the HW (1 pdi clock cycle)
mechanism.
Register is read and writable by SW.
Table 21
Registers Clock DomainsRegisters Clock Domains
Clock Short Name
4.2.1
Description
EEPROM Register Format
Signature Register
SR
Signature Register
Offset
00H
Reset Value
4154H
6LJQDWXUH
UR
Field
Bits
Type
Description
Signature
15:0
ro
Signature
4154H
SIG, Default (AT)
Port Configuration Register 0
Data Sheet
36
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
PCR_0
Port Configuration Register 0
%0
/70
UZ
UZ
Offset
01H
Reset Value
820FH
$13' $16& 3%3
UZ
UZ
UZ
35
';
63
$1(
)&
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
BM
15
rw
Bypass Mode(TX packets same as RX)
1B
E, Enable
LTM
14:10
rw
Limit Total MAC
00000B, Disable
OthersB, Maximum total MAC
ANPD
9
rw
Port 0 Auto-Negotiation Parallel Detect Follow IEEE802.3
0B
B, Both
1B
H, Half Only (Default)
ANSC
8
rw
Port 0 Auto-Negotiation Advertise Single Capability
0B
E, Expand(Default)
1B
S, Single
PBP
7
rw
Port-base priority
PR
6:4
rw
Priority Rule/000
000B , port base priority
001B , [TCP,TOS,TAG]
010B , [TCP,TAG,TOS]
011B , [TAG,TCP,TOS]
100B , [TOS,TAG]
101B , [TAG,TOS]
DX
3
rw
Duplex
This bit is unused if corresponding port is not connected to internal PHY
0B
HD, Half Duplex
1B
FD, Full Duplex (Default)
SP
2
rw
Speed
This bit is unused if corresponding port is not connected to internal PHY
0B
10M, 10Base-T
1B
100M, 100TX
ANE
1
rw
Auto negotiation Enable
This bit is unused if corresponding port is not connected to internal PHY
0B
D, Disable Auto-negotiation
1B
E, Enable Auto-negotiation. (Default)
FC
0
rw
802.3x Flow Control Command Ability
Port Configuration Register 1
Data Sheet
37
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
PCR_1
Port Configuration Register 1
%0
/70
UZ
UZ
Offset
02H
Reset Value
820FH
$13' $16& 3%3
UZ
UZ
UZ
35
';
63
$1(
)&
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
BM
15
rw
Bypass Mode(TX packets same as RX)
1B
E, Enable
LTM
14:10
rw
Limit Total MAC
00000B, Disable
OthersB, Maximum total MAC
ANPD
9
rw
Port 1 Auto-Negotiation Parallel Detect Follow IEEE802.3
0B
B, Both
1B
H, Half Only (Default)
ANSC
8
rw
Port 1 Auto-Negotiation Advertise Single Capability
0B
E, Expand(Default)
1B
S, Single
PBP
7
rw
Port-base priority
PR
6:4
rw
Priority Rule/000
000B , port base priority
001B , [TCP,TOS,TAG]
010B , [TCP,TAG,TOS]
011B , [TAG,TCP,TOS]
100B , [TOS,TAG]
101B , [TAG,TOS]
DX
3
rw
Duplex
This bit is unused if corresponding port is not connected to internal PHY
0B
HD, Half Duplex
1B
FD, Full Duplex (Default)
SP
2
rw
Speed
This bit is unused if corresponding port is not connected to internal PHY
0B
10M, 10Base-T
1B
100M, 100TX
ANE
1
rw
Auto negotiation Enable
This bit is unused if corresponding port is not connected to internal PHY
0B
D, Disable Auto-negotiation
1B
E, Enable Auto-negotiation. (Default)
FC
0
rw
802.3x Flow Control Command Ability
Port Configuration Register 2
Data Sheet
38
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
PCR_2
Port Configuration Register 2
Offset
03H
%0
/70
+0
UZ
UZ
""
Reset Value
820FH
+&0 3%3
""
UZ
35
';
63
$1(
)&
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
BM
15
rw
Bypass Mode(TX packets same as RX)
1B
E, Enable
LTM
14:10
rw
Limit Total MAC
00000B, Disable
OthersB, Maximum total MAC
HM
9
rw
HDLC Mode
0B
, By-pass pre/SFD
1B
, Remove pre/SFD(Default)
HCM
8
rw
HDLC CRC Mode
0B
, 16 bits CRC(Default)
1B
, 32 bits CRC
PBP
7
rw
Port-base priority
PR
6:4
rw
Priority Rule/000
000B , port base priority
001B , [TCP,TOS,TAG]
010B , [TCP,TAG,TOS]
011B , [TAG,TCP,TOS]
100B , [TOS,TAG]
101B , [TAG,TOS]
DX
3
rw
Duplex
This bit is unused if corresponding port is not connected to internal PHY
0B
HD, Half Duplex
1B
FD, Full Duplex (Default)
SP
2
rw
Speed
This bit is unused if corresponding port is not connected to internal PHY
0B
10M, 10Base-T
1B
100M, 100TX
ANE
1
rw
Auto negotiation Enable
This bit is unused if corresponding port is not connected to internal PHY
0B
D, Disable Auto-negotiation
1B
E, Enable Auto-negotiation. (Default)
FC
0
rw
802.3x Flow Control Command Ability
VLAN(TOS) priority Map Register
Data Sheet
39
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
VLAN_TOS_PMR
VLAN(TOS) Priority Map Register
Offset
04H
,3
,3
,3
,3
,3
,3
,3
,3
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Reset Value
F0F0H
7$* 7$* 7$* 7$* 7$* 7$* 7$* 7$*
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
IP7
15
rw
Priority of the packet which the precedence field of IP header is 7
IP6
14
rw
Priority of the packet which the precedence field of IP header is 6
IP5
13
rw
Priority of the packet which the precedence field of IP header is 5
IP4
12
rw
Priority of the packet which the precedence field of IP header is 4
IP3
11
rw
Priority of the packet which the precedence field of IP header is 3
IP2
10
rw
Priority of the packet which the precedence field of IP header is 2
IP1
9
rw
Priority of the packet which the precedence field of IP header is 1
IP0
8
rw
Priority of the packet which the precedence field of IP header is 0
TAG7
7
rw
Priority of the packet which the priority field of TAG is 7
TAG6
6
rw
Priority of the packet which the priority field of TAG is 6
TAG5
5
rw
Priority of the packet which the priority field of TAG is 5
TAG4
4
rw
Priority of the packet which the priority field of TAG is 4
TAG3
3
rw
Priority of the packet which the priority field of TAG is 3
TAG2
2
rw
Priority of the packet which the priority field of TAG is 2
TAG1
1
rw
Priority of the packet which the priority field of TAG is 1
TAG0
0
rw
Priority of the packet which the priority field of TAG is 0
Note: 0B: low priority queue. Q0; 1B: High priority queue. Q1. The weight ratio is 1:N. The default is Q0 for un-tag
and none IP frame.
Miscellaneous Configuration 0
MC_0
Miscellaneous Configuration 0
Data Sheet
Offset
05H
'0
9/$1
3/
UZ
UZ
UZ
Reset Value
C0H
345
0$'
6&
,3*
UZ
""
""
UZ
40
(&& '%2 %6(
""
""
UZ
%67
UZ
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
Field
Bits
Type
Description
DM
15:12
rw
Discard Mode (drop scheme for each queue)
VLAN
11
rw
Enable Replace VLAN ID 0 &1 by PVID
PL
10
rw
Packet Length
0B
, 1536
1B
, 1518
PQR
9:8
rw
Priority Queue ratio
00B , 1:2
01B , 1:4
10B , 1:8
11B , 1:16
MAD
7
rw
Disable MCC_AVERAGE
1B
D, Disable MCC Average
SC
6
rw
SWCLK(Switch RXCLK to TXCLK for 7-wire)
IPG
5
rw
IPG Leveling
0B
, 96BT(Default)
1B
, 92BT
ECC
4
rw
XCRC
0B
XCRCCHK, Enable CRC Check
DBO
3
rw
Disable Back-Off
1B
D, Disable Back-Off
BSE
2
rw
Broadcast Storming Enable
BST
1:0
rw
Broadcast Storming Threshold[1:0]
Miscellaneous Configuration Register 1
MCR_1
Miscellaneous Configuration Register 1
Offset
06H
5HV
(7
&'3
UR
UZ
UZ
Reset Value
82E8H
5HV
'))(
'3
$'
UR
UZ
UZ
UZ
Field
Bits
Type
Description
Res
15:11
ro
Reserved
ET
10
rw
Enable TENLMT
1B
E, Enable
CDP
9
rw
Check The Destination Port is in the same VLAN Group
1B
E, Enable
Res
8:3
ro
Reserved
DFFE
2
rw
DISFEFI(Disable Far End Fault/0)
Data Sheet
41
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
Field
Bits
Type
Description
DP
1
rw
Discard Packet after 16th Collision
0B
D, Don’t discard
AD
0
rw
Aging Disable
0B
E, Enable Aging
Miscellaneous Configuration Register2
MCR_2
Miscellaneous Configuration Register 2
Offset
07H
Reset Value
1480H
3)0
3)0
3)0
3)0
&31
/0
/0
/0
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
PFM1
15:14
rw
Packet Filtering Mode for Received DA= 01 80 c2 00 00 10 ~ 01 80 c2
00 00 ff
PFM2
13:12
rw
Packet Filtering Mode for Received DA= 01 80 c2 00 00 02 ~ 01 80 c2
00 00 0f
PFM3
11:10
rw
Packet Filtering Mode for Received DA= 01 80 c2 00 00 01 and
OPCODE!= PAUSE
PFM4
9:8
rw
Packet Filtering Mode for Received DA= 01 80 c2 00 00 00
CPN
7:6
rw
CPU Port Number
LM2
5:4
rw
Learning Mode of Port 2
LM1
3:2
rw
Learning Mode of Port 1
LM0
1:0
rw
Learning Mode of Port 0
Note:
1. Learning Mode: 00B : group 0(default), 01B : group 1, 1x B: according to bit 0 of received VID(bit 0 is used to
set the learning group of untag packet
2. Packet Filtering Mode: 00B : forward, 01B : discard, 10B : forward the packet to CPU port(defined in Bit [7:6] of
register 07H). if this packet is received from CPU Port, this packet will be forward to the VLAN group. 11B :
forward the packet to CPU port. if this packet is received from CPU Port, this packet will be discard.
Port Base VLAN port Map Register
PBVLAN_MR
Port Base VLAN port Map Register
Data Sheet
Offset
08H
42
Reset Value
777H
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
/('
5HV
/3
5HV
30
5HV
30
5HV
30
UZ
UR
UZ
UR
UZ
UR
UZ
UR
UZ
Field
Bits
Type
Description
LED
15
rw
Put Off LEDs of UTP port
0B
, always put off LEDs of UTP port when UTP link down
1B
, LEDs of UTP port show DIPSW setting when auto-negotiation
disable and link down
Res
14:13
ro
Reserved
LP
12
rw
Link Partner
0B
, if auto-negotiation enable, follow speed and duplex setting to
negotiate with link partner.
1B
, if auto-negotiation enable, always advertise full capability to its link
partner.
Res
11
ro
Reserved
PM2
10:8
rw
Port 2 To port Map
Res
7
ro
Reserved
PM1
6:4
rw
Port 1 To port Map
Res
3
ro
Reserved
PM0
2:0
rw
Port 0 To port Map
Data Sheet
43
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
Packet Filter Control Registers 1 and 0
PCFC_1_0
Packet Filter Control Register 1 and 0
$35 $35 $35
UZ
UZ
Offset
09H
23
UZ
Reset Value
0000H
$35 $35 $35
UZ
UZ
UZ
UZ
23
UZ
Field
Bits
Type
Description
APR2
15
rw
Apply to Port 2 Rx
0B
DNA, Do not apply
1B
APL, Apply
APR1
14
rw
Apply to Port 1 Rx
0B
DNA, Do not apply
1B
APL, Apply
APR0
13
rw
Apply to Port 0 Rx
0B
DNA, Do not apply
1B
APL, Apply
OP14
12:8
rw
OP Code for Filter
Defined in Register 14H (16H, 18H, 1AH, 1CH, 1EH, 20H, 22H)
APR2
7
rw
Apply to Port 2 Rx
0B
DNA, Do not apply
1B
APL, Apply
APR1
6
rw
Apply to Port 1 Rx
0B
DNA, Do not apply
1B
APL, Apply
APR0
5
rw
Apply to Port 0 Rx
0B
DNA, Do not apply
1B
APL, Apply
OP13
4:0
rw
OP Code for Filter
which defined in Register 13H (15H, 17H, 19H, 1BH, 1DH, 1FH, 21H)
Note:
OP Code bit[4:3]
00B : Priority. Priority is defined in OP Code bit[2:0] ;
01B : Discard. OP Code bit[2:0] is RESERVED and SHOULD keep always 0;
1xB : RESERVED.
Data Sheet
44
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
Filter Type Register 0
TFTR_0
Filter Type Register 0
Offset
11H
Reset Value
0000H
7)B
7)B
7)B
7)B
7)B
7)B
7)B
7)B
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
TF_7
15:14
rw
Type of Filter 7
TF_6
13:12
rw
Type of Filter 6
TF_5
11:10
rw
Type of Filter 5
TF_4
9:8
rw
Type of Filter 4
TF_3
7:6
rw
Type of Filter 3
TF_2
5:4
rw
Type of Filter 2
TF_1
3:2
rw
Type of Filter 1
TF_0
1:0
rw
Type of Filter 0
Note:
00B : TCP/UDP Port Number;
01B : IP Protocol ID;
10B : Ethernet Type;
11B : RESERVED
Filter Type Register 1
TFTR_1
Filter Type Register 1
Offset
12H
Reset Value
0000H
7)B
7)B
7)B
7)B
7)B
7)B
7)B
7)B
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
TF_15
15:14
rw
Type of Filter 15
TF_14
13:12
rw
Type of Filter 14
Data Sheet
45
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
Field
Bits
Type
Description
TF_13
11:10
rw
Type of Filter 13
TF_12
9:8
rw
Type of Filter 12
TF_11
7:6
rw
Type of Filter 11
TF_10
5:4
rw
Type of Filter 10
TF_9
3:2
rw
Type of Filter 9
TF_8
1:0
rw
Type of Filter 8
Note:
00B : TCP/UDP Port Number;
01B : IP Protocol ID;
10B : Ethernet Type;
11B : RESERVED
Filter Register 0
FR_0
Filter Register 0
Offset
13H
Reset Value
0000H
)LOWHU
UZ
Field
Bits
Type
Description
Filter
15:0
rw
Filter
Other Filter Registers have the same structure and characteristics as Filter Register 0; the offset addresses are
listed in Table 22.
Table 22
Other Filter Regsiters
Register Short Name
Register Long Name
Offset Address
FR_1
Filter Register 1
14H
FR_2
Filter Register 2
15H
FR_3
Filter Register 3
16H
FR_4
Filter Register 4
17H
FR_5
Filter Register 5
18H
FR_6
Filter Register 6
19H
FR_7
Filter Register 7
1AH
FR_8
Filter Register 8
1BH
Data Sheet
46
Page Number
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
Table 22
Other Filter Regsiters (cont’d)
Register Short Name
Register Long Name
Offset Address
FR_9
Filter Register 9
1CH
FR_10
Filter Register 10
1DH
FR_11
Filter Register 11
1EH
FR_12
Filter Register 12
1FH
FR_13
Filter Register 13
20H
FR_14
Filter Register 14
21H
FR_15
Filter Register 15
22H
Data Sheet
47
Page Number
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
Port Base VLAN ID and Mask 0 of Port 0
PB_ID_0_0
Port Base VLAN ID and Mask 0 of Port 0
Offset
23H
Reset Value
0001H
'35,
39,'
UZ
UZ
Field
Bits
Type
Description
DPRI
15:12
rw
PVID Mask[3:0]
Default Priority
PVID
11:0
rw
PVID
Port base VLAN ID
Port Base VLAN ID and Mask 1 of Port 0
PB_ID_1_0
Port Base VLAN ID and Mask 1 of Port 0
Offset
24H
5HV
Reset Value
0000H
39,'
UZ
Field
Bits
Type
Description
PVID
7:0
rw
PVID Mask[11:4]
Note:
If (Tag Packet) then Tag = {TAGIN[15:12], ((TAGIN[11:0] & ~MASK) | (PVID & MASK))}
If (UnTag Packet) then Tag = {PKT_PRT[2:0], 0B, PVID}
Data Sheet
48
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
Port Base VLAN ID and Mask 0 of Port 1
PB_ID_0_1
Port Base VLAN ID and Mask 0 of Port 1
Offset
25H
Reset Value
0001H
'35,
39,'
UZ
UZ
Field
Bits
Type
Description
DPRI
15:12
rw
PVID Mask[3:0]
Default Priority
PVID
11:0
rw
PVID
Port base VLAN ID
Port Base VLAN ID and Mask 1 of Port 1
PB_ID_1_1
Port Base VLAN ID and Mask 1 of Port 1
Offset
26H
5HV
Reset Value
0000H
39,'
UZ
Field
Bits
Type
Description
PVID
7:0
rw
PVID Mask[11:4]
Note:
If (Tag Packet) then Tag = {TAGIN[15:12], ((TAGIN[11:0] & ~MASK) | (PVID & MASK))}
If (UnTag Packet) then Tag = {PKT_PRT[2:0], 0B, PVID}
Data Sheet
49
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
Port Base VLAN ID and Mask 0 of Port 2
PB_ID_0_2
Port Base VLAN ID and Mask 0 of Port 2
Offset
27H
Reset Value
0001H
'35,
39,'
UZ
UZ
Field
Bits
Type
Description
DPRI
15:12
rw
PVID Mask[3:0]
Default Priority
PVID
11:0
rw
PVID
Port base VLAN ID
Port Base VLAN ID and Mask 1 of Port 2
PB_ID_1_2
Port Base VLAN ID and Mask 1 of Port 2
Offset
28H
5HV
Reset Value
0000H
39,'
UZ
Field
Bits
Type
Description
PVID
7:0
rw
PVID Mask[11:4]
Note:
If (Tag Packet) then Tag = {TAGIN[15:12], ((TAGIN[11:0] & ~MASK) | (PVID & MASK))}
If (UnTag Packet) then Tag = {PKT_PRT[2:0], 0B, PVID}
Data Sheet
50
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
Tag Port Rule 0 Register 0
TPR_0_0
Tag Port Rule 0 Register 0
Offset
29H
Reset Value
F000H
50
5XOH
""
""
Field
Bits
Type
Description
RM
15:12
rw
Rule Mask[3:0]
Rule
11:0
rw
Rule
Other Tag Port Rule 0 Registers have the same structure and characteristics as Tag Port Rule 0 Register 0; the
offset addresses are listed in Table 23.
Table 23
Other Tag Port Rule 0 Registers
Register Short Name
Register Long Name
Offset Address
TPR_0_1
Tag Port Rule 0 Register 1
2BH
TPR_0_2
Tag Port Rule 0 Register 2
2DH
TPR_0_3
Tag Port Rule 0 Register 3
2FH
TPR_0_4
Tag Port Rule 0 Register 4
31H
TPR_0_5
Tag Port Rule 0 Register 5
33H
TPR_0_6
Tag Port Rule 0 Register 6
35H
TPR_0_7
Tag Port Rule 0 Register 7
37H
Page Number
Tag Port Rule 1 Register 0
TPR_1_0
Tag Port Rule 1 Register 0
Offset
2AH
5HV
3$5
(5
50
""
""
""
Field
Bits
Type
Description
PAR
11:9
rw
Port to apply the rule
ER
8
rw
Exclude Rule
Data Sheet
Reset Value
00FFH
51
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
Field
Bits
Type
Description
RM
7:0
rw
Rule Mask[11:4]
Other Tag Port Rule 1 Registers have the same structure and characteristics as Tag Port Rule 1 Register 0; the
offset addresses are listed in Table 24.
Table 24
Other Tag Port Rule 1 Regsiters
Register Short Name
Register Long Name
Offset Address
TPR_1_1
Tag Port Rule 1 Register 1
2CH
TPR_1_2
Tag Port Rule 1 Register 2
2EH
TPR_1_3
Tag Port Rule 1 Register 3
30H
TPR_1_4
Tag Port Rule 1 Register 4
32H
TPR_1_5
Tag Port Rule 1 Register 5
34H
TPR_1_6
Tag Port Rule 1 Register 6
36H
TPR_1_7
Tag Port Rule 1 Register 7
38H
Page Number
Miscellaneous Configuration Register 3
MCR_3
Miscellaneous Configuration Register 3
Offset
39H
Reset Value
0000H
5HV
&/&
5/
)3
6
$3B3
//%
31B9
7$*
UR
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
Res
15:14
ro
Reserved
CLC
13
rw
Check of the Length of CRS
0B
, Enable the checking of the length of CRS (default)
1B
, Disable the checking of the length of CRS
RL
12
rw
Redundant Link
0B
, Enable Redundant Link in converter mode(default)
1B
, Disable Redundant Link
FP
11
rw
Fault Propagation
0B
, Enable Fault Propagation in converter mode(default)
1B
, Disable Fault Propagation
100S
10
rw
100M Snooping
0B
, Enable 100M snooping in converter mode(default)
1B
, Disable snooping
AP_P
9:7
rw
All Packet/PPPOE
0B
, all packet
1B
, PPPOE only
Data Sheet
52
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
Field
Bits
Type
Description
LLB
6:4
rw
Local Loop-back for Port2/Port1/Port0
0B
, Normal Operation(default)
1B
, Local Loop-back for Port2/Port1/Port0
PN_V
3
rw
Port Number/VLAN ID Base Grouping
0B
, Port Number base grouping(default)
1B
, Received VLAN ID base grouping
TAG
2:0
rw
VLAN TAG
0B
, Recognize VLAN TAG automatically(default)
1B
, Disable
Data Sheet
53
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
Miscellaneous Configuration Register 4
MCR_4
Miscellaneous Configuration 4
Offset
3AH
Reset Value
0000H
5HV
UR
Field
Bits
Type
Description
Res
15:0
ro
Reserved
Miscellaneous Configuration Register 5
MCR_5
Miscellaneous Configuration Register 5
Offset
3BH
Reset Value
0000H
5HV
UR
Field
Bits
Type
Description
Res
15:0
ro
Reserved
Miscellaneous Configuration Register 6
MCR_6
Miscellaneous Configuration Register 6
Offset
3CH
Reset Value
0000H
5HV
UR
Field
Bits
Type
Description
Res
15:0
ro
Reserved
Data Sheet
54
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
4.3
Default Value of SMI Register
Table 25
Default Value of SMI Register
Register
Bit 31-0
Mode
Default
00H
Chip Identifier
ro
21143H
01H
Hardware Settings
ro
pin
02H
Interrupt Register
lh/roc
0H
03H
Port Status
ro
Real time status
04H
EEPROM Register File Access Control
rw
0H
05H
Port Control Register
rw
0H
06H
Over Flow Flag
lh/roc
0H
07H
P0 Receive Packets
rw
0H
08H
P0 Reveive Byte Count
rw
0H
09H
P0 Transmit Packets
rw
0H
0AH
P0 Transmit Byte Count
rw
0H
0BH
P0 Error Count
rw
0H
0CH
P0 Collision Count
rw
0H
0DH
P1 Receive Packets
rw
0H
0EH
P1 Reveive Byte Count
rw
0H
0FH
P1 Transmit Packets
rw
0H
10H
P1 Transmit Byte Count
rw
0H
11H
P1 Error Count
rw
0H
12H
P1 Collision Count
rw
0H
13H
P2 Receive Packets
rw
0H
14H
P2 Reveive Byte Count
rw
0H
15H
P2 Transmit Packets
rw
0H
16H
P2 Transmit Byte Count
rw
0H
17H
P2 Error Count
rw
0H
18H
P2 Collision Count
rw
0H
19H
Per Port Counter Reset
wr
Note: Any write activity to counter register will reset the counter and the overflow flag of this counter.
Data Sheet
55
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
4.4
SMI Register Descriptions
Table 26
Registers Address Space
Module
Base Address
End Address
SMI
00H
19H
Table 27
Note
Registers Overview
Register Short Name
Register Long Name
Offset Address
Page Number
CI
Chip Identifier
00H
57
HSS
Hardware Setting Status
01H
58
Interrupt
Interrupt Register
02H
58
PSR
Port Status Register
03H
60
EEPROM_FAC
EEPROM Register File Access Control
04H
62
PCR
Port Control Register
05H
62
Overflow_Flag
Overflow Flag
06H
63
PerPortCounter0
Per Port Counter 0
07H
64
PerPortCounter1
Per Port Counter Register 1
08H
65
PerPortCounter2
Per Port Counter Register 2
09H
65
PerPortCounter3
Per Port Counter Register 3
10H
65
PerPortCounter4
Per Port Counter Register 4
11H
65
PerPortCounter5
Per Port Counter Register 5
12H
65
PerPortCounter6
Per Port Counter Register 6
13H
65
PerPortCounter7
Per Port Counter Register 7
14H
65
PerPortCounter8
Per Port Counter Register 8
15H
65
PerPortCounter9
Per Port Counter Register 9
16H
65
PerPortCounterReset
Per Port Counter Reset
19H
65
The register is addressed wordwise.
Table 28
Register Access Types
Mode
Symbol Description HW
Description SW
read/write
rw
Register is used as input for the HW
Register is read and writable by SW
read
r
Register is written by HW (register
Value written by software is ignored by
between input and output -> one cycle hardware; that is, software may write any
delay)
value to this field without affecting hardware
behavior (= Target for development.)
Read only
ro
Register is set by HW (register between SW can only read this register
input and output -> one cycle delay)
Read virtual
rv
Physically, there is no new register, the SW can only read this register
input of the signal is connected directly
to the address multiplexer.
Latch high,
self clearing
lhsc
Latch high signal at high level, clear on SW can read the register
read
Data Sheet
56
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
Table 28
Register Access Types (cont’d)
Mode
Symbol Description HW
Latch low,
self clearing
llsc
Latch high signal at low-level, clear on SW can read the register
read
Latch high,
mask clearing
lhmk
Latch high signal at high level, register SW can read the register, with write mask
cleared with written mask
the register can be cleared (1 clears)
Latch low,
mask clearing
llmk
Latch high signal at low-level, register
cleared on read
SW can read the register, with write mask
the register can be cleared (1 clears)
Interrupt high,
self clearing
ihsc
Differentiate the input signal (low>high) register cleared on read
SW can read the register
Interrupt low,
self clearing
ilsc
Differentiate the input signal (high>low) register cleared on read
SW can read the register
Interrupt high,
mask clearing
ihmk
Differentiate the input signal (highSW can read the register, with write mask
>low) register cleared with written mask the register can be cleared
Interrupt low,
mask clearing
ilmk
Differentiate the input signal (low>high) register cleared with written
mask
SW can read the register, with write mask
the register can be cleared
Interrupt enable ien
register
Enables the interrupt source for
interrupt generation
SW can read and write this register
latch_on_reset
lor
rw register, value is latched after first
clock cycle after reset
Register is read and writable by SW
Read/write
self clearing
rwsc
Register is used as input for the hw, the Writing to the register generates a strobe
register will be cleared due to a HW
signal for the HW (1 pdi clock cycle)
mechanism.
Register is read and writable by SW.
Table 29
Registers Clock DomainsRegisters Clock Domains
Clock Short Name
4.4.1
Description SW
Description
SMI Register Format
Chip Identifier
CI
Chip Identifier
Offset
00H
Reset Value
21143H
3&
5&
UR
UR
Field
Bits
Type
Description
PC
31:4
ro
Project Code
Data Sheet
57
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
Field
Bits
Type
Description
RC
3:0
ro
Revision Code
Hardware Setting Status
HSS
Hardware Setting Status
Offset
01H
Reset Value
pinH
5HV
%0 %0
UR
UR
/( /( '% '0 ,G
(2
/3 ($ 3
)0 ' ' 3 $ 0 (6 3 (5 )30 7 & 00
UR
UR UR UR UR UR UR UR UR
UR
UR UR UR
')&
UR
5$1 56 5'+ &'
UR
Field
Bits
Type
Description
BM2
28:27
ro
Bus Mode of Port 2
BM1
26:25
ro
Bus Mode of Port 1
FM
24:23
ro
Fiber Mode
LED1
22
ro
LEDMODE 1
LED0
21
ro
LEDMODE 0
DBP
20
ro
Disable Back Preasure
DMA
19
ro
Disable MAC address learning
IdM
18
ro
Idle Mode
ES
17
ro
Enable Snooping
EOP
16
ro
Enable OAM Processor
ER
15
ro
Enable Redundant
FPM
14:13
ro
Fault Propagation Mode
LPT
12
ro
Disable Link Pass Through
EAC
11
ro
Enable Auto-Crossover
P0MM
10
ro
P0 MDI/MDIX
DFC
9:7
ro
Disable Flow Control
RAN
6:5
ro
Recommend Auto-Negotiation Ability for TP Port
RS10
4:3
ro
Recommend Speed 10 for TP Port
RDH
2:1
ro
Recommend Duplex Half for TP/FX Port
CD
0
ro
Chip Dis
UR
UR
UR
Interrupt Register
Interrupt
Interrupt Register
Data Sheet
Offset
02H
58
Reset Value
0000 0000H
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
5& 5& 5& %) %) %) )& '& 6& /6 )& '& 6& /6 )& '& 6& /6
&2 ( ( ( $ & $ & $ &
5HV
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFR
Field
Bits
Type
Description
CO
18
lh/roc
Counter Overflow
0B
, Normal
1B
, Any counter defined in register 7H~18H overflow
RCE2
17
lh/roc
Port 2 Receive CRC Error Packet
0B
, Normal
1B
, Reveive CRC error packet
RCE1
16
lh/roc
Port 1 Receive CRC Error Packet
0B
, Normal
1B
, Reveive CRC error packet
RCE0
15
lh/roc
Port 0 Receive CRC Error Packet
0B
, Normal
1B
, Reveive CRC error packet
BF2
14
lh/roc
Port 2 Buffer Full
0B
, Normal
1B
, Buffer Full
BF1
13
lh/roc
Port 1 Buffer Full
0B
, Normal
1B
, Buffer Full
BF0
12
lh/roc
Port 0 Buffer Full
0B
, Normal
1B
, Buffer Full
FCA2
11
lh/roc
Port 2 Flow Control Ability Change
0B
, Normal
1B
, Status Change
DC2
10
lh/roc
Port 2 Duplex Change
0B
, Normal
1B
, Status Change
SC2
9
lh/roc
Port 2 Speed Change
0B
, Normal
1B
, Status Change
LSC2
8
lh/roc
Port 2 Link Status Change
0B
, Normal
1B
, Status Change
FCA1
7
lh/roc
Port 1 Flow Control Ability Change
0B
, Normal
1B
, Status Change
DC1
6
lh/roc
Port 1 Duplex Change
0B
, Normal
1B
, Status Change
Data Sheet
59
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
Field
Bits
Type
Description
SC1
5
lh/roc
Port 1 Speed Change
0B
, Normal
1B
, Status Change
LSC1
4
lh/roc
Port 1 Link Status Change
0B
, Normal
1B
, Status Change
FCA0
3
lh/roc
Port 0 Flow Control Ability Change
0B
, Normal
1B
, Status Change
DC0
2
lh/roc
Port 0 Duplex Change
0B
, Normal
1B
, Status Change
SC0
1
lh/roc
Port 0 Speed Change
0B
, Normal
1B
, Status Change
LSC0
0
lh/roc
Port 0 Link Status Change
0B
, Normal
1B
, Status Change
Port Status Register
PSR
Port Status Register
Offset
03H
Reset Value
Real Time StatusH
&%
&% %) %) %) )& 'X 6S /6 )& 'X 6S /6 )& 'X 6S /6
&%/ &%/ S H S H S H 5HV
UR
UR
UR
UR UR UR UR UR UR UR UR UR UR UR UR UR UR UR UR
Field
Bits
Type
Description
CBL1
20:19
ro
CBBRK_LENGTH of P1
00B , 0~60m
01B , 60~90m
10B , 90~130m
11B , 130~170m
CB1
18
ro
CBBRK of P1
0B
, Normal
1B
, Cable Broken
CBL0
17:16
ro
CBBRK_LENGTH of P0
00B , 0~60m
01B , 60~90m
10B , 90~130m
11B , 130~170m
Data Sheet
60
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
Field
Bits
Type
Description
CB0
15
ro
CBBRK of P0
0B
, Normal
1B
, Cable Broken
BF2
14
ro
Buffer Full Status of Port 2
0B
, Normal
1B
, Buffer Full
BF1
13
ro
Buffer Full Status of Port 1
0B
, Normal
1B
, Buffer Full
BF0
12
ro
Buffer Full Status of Port 0
0B
, Normal
1B
, Buffer Full
FC2
11
ro
Flow Control of Port 2
0B
, Disable
1B
, Enable
Dup2
10
ro
Duplex of Port 2
0B
, Half Duplex
1B
, Full Duplex
Spe2
9
ro
Speed of Port 2
0B
, 10M
1B
, 100M
LS2
8
ro
Link Status of Port 2
0B
, Link Down
1B
, Link Up
FC1
7
ro
Flow Control of Port 1
0B
, Disable
1B
, Enable
Dup1
6
ro
Duplex of Port 1
0B
, Half Duplex
1B
, Full Duplex
Spe1
5
ro
Speed of Port 1
0B
, 10M
1B
, 100M
LS1
4
ro
Link Status of Port 1
0B
, Link Down
1B
, Link Up
FC0
3
ro
Flow Control of Port 0
0B
, Disable
1B
, Enable
Dup0
2
ro
Duplex of Port 0
0B
, Half Duplex
1B
, Full Duplex
Spe0
1
ro
Speed of Port 0
0B
, 10M
1B
, 100M
Data Sheet
61
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
Field
Bits
Type
Description
LS0
0
ro
Link Status of Port 0
0B
, Link Down
1B
, Link Up
EEPROM Register File Access Control
EEPROM_FAC
EEPROM Register File Access Control
Offset
04H
Reset Value
0000 0000H
&00
5HV
$GG
'DWD
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
CMM
31:29
rw
Command
000B , Read
001B , Write
OthersB, Reserved
Res
28:22
rw
Reserved
Should be always 0000000B
Add
21:16
rw
Address
00H~3FH
Data
15:0
rw
Data
Port Control Register
PCR
Port Control Register
Offset
05H
Reset Value
00000H
673
673
673
(B
'35
%&
3'
%&
3'
%&
3'
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
STP2
16:15
rw
STP State of Port 2
0xB , Forwarding
10B , Learning
11B , Blocking & listening
Data Sheet
62
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
Field
Bits
Type
Description
STP1
14:13
rw
STP State of Port 1
0xB , Forwarding
10B , Learning
11B , Blocking & listening
STP0
12:11
rw
STP State of Port 0
0xB , Forwarding
10B , Learning
11B , Blocking & listening
E9_6
10
rw
Enable Bit[9:6]
0B
, Disable
1B
, Enable
DPR
9:6
rw
Destination of the packet received from CPU port
Bit [8:6] : Bit[6] is for P0, Bit[7] is for P1 and Bit[8] is for P2. If the bit is set
to 1, the packet received from CPU port defined in EEPROM
register 7H bit [7:6] will be forward to the corresponding port.Bit
[9]: If the total number of 1 in Bit [8:6] is greater than 1, this bit should
set to 1 too.
BC2
5
rw
P2 Bandwidth Control ON/OFF
0B
, Normal
1B
, Force P2 issue PAUSE packet for full duplex and back pressure
for half duplex
P2D
4
rw
P2 Disable
0B
, Normal
1B
, P2 Disable Receiving/Transmitting
BC1
3
rw
P1 Bandwidth Control ON/OFF
0B
, Normal
1B
, Force P1 issue PAUSE packet for full duplex and back pressure
for half duplex
P1D
2
rw
P1 Disable
0B
, Normal
1B
, P1 Disable Receiving/Transmitting
BC0
1
rw
P0 Bandwidth Control ON/OFF
0B
, Normal
1B
, Force P0 issue PAUSE packet for full duplex and back pressure
for half duplex
P0D
0
rw
P0 Disable
0B
, Normal
1B
, P0 Disable Receiving/Transmitting
Overflow Flag
Overflow_Flag
Overflow Flag
Data Sheet
Offset
06H
63
Reset Value
00000H
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
&& (& 7% 73 5% 53 && (& 7% 73 5% 53 && (& 7% 73 5% 53
& & & & & & 5HV
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFRU
OKFR
Field
Bits
Type
Description
CC2
17
lh/roc
P2 Collision Count
1B
, P2 Collision Count
EC2
16
lh/roc
P2 Error Count
1B
, P2 Error Count
TBC2
15
lh/roc
P2 Transmit Byte Count
1B
, P2 Transmit Byte Count
TP2
14
lh/roc
P2 Transmit Packets
1B
, P2 Transmit Packets
RBC2
13
lh/roc
P2 Receive Byte Count
1B
, P2 Receive Byte Count
RP2
12
lh/roc
P2 Receive Packets
1B
, P2 Receive Packets
CC1
11
lh/roc
P1 Collision Count
1B
, P1 Collision Count
EC1
10
lh/roc
P1 Error Count
1B
, P1 Error Count
TBC1
9
lh/roc
P1 Transmit Byte Count
1B
, P1 Transmit Byte Count
TP1
8
lh/roc
P1 Transmit Packets
1B
, P1 Transmit Packets
RBC1
7
lh/roc
P1 Receive Byte Count
1B
, P1 Receive Byte Count
RP1
6
lh/roc
P1 Receive Packets
1B
, P1 Receive Packets
CC0
5
lh/roc
P0 Collision Count
1B
, P0 Collision Count
EC0
4
lh/roc
P0 Error Count
1B
, P0 Error Count
TBC0
3
lh/roc
P0 Transmit Byte Count
1B
, P0 Transmit Byte Count
TP0
2
lh/roc
P0 Transmit Packets
1B
, P0 Transmit Packets
RBC0
1
lh/roc
P0 Receive Byte Count
1B
, P0 Receive Byte Count
RP0
0
lh/roc
P0 Receive Packets
1B
, P0 Receive Packets
Per Port Counter 0
Data Sheet
64
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
PerPortCounter0
Per Port Counter 0
Offset
07H
Reset Value
0000 0000H
&RXQWHU
UZ
Field
Bits
Type
Description
Counter
31:0
rw
Counter
Other Per Port Counter Registers have the same structure and characteristics as Per Port Counter 0; the offset
addresses are listed in Table 30.
Table 30
Other Per Port Counter Registers
Register Short Name
Register Long Name
Offset Address
PerPortCounter1
Per Port Counter Register 1
08H
PerPortCounter2
Per Port Counter Register 2
09H
PerPortCounter3
Per Port Counter Register 3
10H
PerPortCounter4
Per Port Counter Register 4
11H
PerPortCounter5
Per Port Counter Register 5
12H
PerPortCounter6
Per Port Counter Register 6
13H
PerPortCounter7
Per Port Counter Register 7
14H
PerPortCounter8
Per Port Counter Register 8
15H
PerPortCounter9
Per Port Counter Register 9
16H
Page Number
Per Port Counter Reset
PerPortCounterReset
Per Port Counter Reset
Offset
19H
Reset Value
??H
5HV
Field
Bits
Type
Description
CR2
2
wr
Counter Reset of Port2
1B
, Reset All Counter of Port 2
Data Sheet
65
&5
&5
&5
ZU
ZU
ZU
Rev 1.11, 2005-11-28
ADM6993/X
Registers Description
Field
Bits
Type
Description
CR1
1
wr
Counter Reset of Port1
1B
, Reset All Counter of Port 1
CR0
0
wr
Counter Reset of Port0
1B
, Reset All Counter of Port 0
Data Sheet
66
Rev 1.11, 2005-11-28
ADM6993/X
Electrical Specification
5
Electrical Specification
DC and AC.
5.1
DC Characterization
Table 31
Electrical Absolute Maximum Rating
Parameter
Symbol
Values
Min.
Power Supply
Input Voltage
Output Voltage
Storage Temperature
Power Dissipation
ESD Rating
Table 32
VCC
VIN
Vout
TSTG
PD
ESD
Typ.
Unit
Note / Test Condition
Max.
-0.3
2.7
V
-0.3
VCC + 0.3 V
-0.3
VCC + 0.3 V
-55
155
°C
990
mW
2
KV
Recommended Operating Conditions
Parameter
Symbol
Power Supply1)
Vcc
Vin
Tj
Input Voltage
Junction Operating
Temperature
Values
Unit
Min.
Typ.
Max.
3.135
3.3
3.465
V
0
-
Vcc
V
0
25
115
°C
Note / Test Condition
1) VCC3O. VCCBIAS
Table 33
DC Electrical Characteristics for 3.3 V Operation1)
Parameter
Symbol
Values
Min.
VIL
Input High Voltage
VIH
Output Low Voltage
VOL
Output High Voltage
VOH
Input Pull_up/down Resistance RI
Typ.
Input Low Voltage
2.0
0.4
50
Note / Test Condition
V
TTL
V
TTL
V
TTL
V
TTL
KΩ
VIL = 0 V or VIH = Vcc
Max.
0.8
2.4
Unit
1) Under VCC = 3.0 V~ 3.6 V, Tj = °C ~ 115 °C
5.2
AC Characterization
Power on Reset Timing, EEPROM Interface Timing, 10Base-Tx MII Timing, 100Base-Tx MII Timing, Reduce MII
Timing, GPSI(7-wire) Timing, HDLC Timing, and SMI Timing.
Data Sheet
67
Rev 1.11, 2005-11-28
ADM6993/X
Electrical Specification
Power on Reset Timing
0us
50u s
100us
150us
tRST
RST*
tCONF
All Configuration Pins
Figure 5
Power on Reset Timing
Table 34
Power on Reset Timing
Parameter
Symbol
Values
Unit
Note / Test Condition
100
ms
TTL
100
ns
TTL
Min.
tRST
tCONF
RST Low Period
Start of Idle Pulse Width
Typ.
Max.
EEPROM Interface Timing
0us
10u s
20us
30us
EECS
tESKL
tESKH
tESK
EESK
tEWDD
EEDO
tERDS
tERDH
EEDI
Figure 6
EEPROM Interface Timing
Table 35
EEPROM Interface Timing
Parameter
Symbol
Values
Min.
EESK Period
EESK Low Period
EESK High Period
EEDI to EESK Rising Setup
Time
Data Sheet
tESK
tESKL
tESKH
tERDS
Typ.
Unit
5120
ns
2550
2570
ns
2550
2570
ns
10
Note / Test Condition
Max.
ns
68
Rev 1.11, 2005-11-28
ADM6993/X
Electrical Specification
Table 35
EEPROM Interface Timing (cont’d)
Parameter
Symbol
Values
Min.
EEDI to EESK Rising Hold
Time
tERDH
Typ.
Unit
Note / Test Condition
Max.
10
ns
EESK Falling to EEDO Output tEWDD
Delay Time
20
ns
10Base-Tx MII Input Timing
10Base-Tx Input timing conditions
0ns
1000ns
2000ns
tCK
tCKL
tCK H
MII_RXCLK
tRXOD
MII_RXDV
MII_RXD
tCSVA
MII_CRS
Figure 7
10Base-Tx MII Input Timing
Table 36
10Base-Tx MII Input Timing
Parameter
Symbol
Values
Min.
MII_RXCLK Period
MII_RXCLK Low Period
MII_RXCLK High Period
MII_CRS Rising to MII_RXDV
Rising
MII_RXCLK Rising to
MII_RXD, MII_RXDV,
MII_CRS Output Delay
tCK
tCKL
tCKH
tCSVA
tRXOD
Typ.
Unit
Max.
400
ns
160
240
ns
160
240
ns
0
10
ns
200
Note / Test Condition
ns
10Base-TX MII Output Timing
10Base-TX MII Output timing conditions
Data Sheet
69
Rev 1.11, 2005-11-28
ADM6993/X
Electrical Specification
0ns
500 ns
1000ns
1500ns
2000ns
250 0n
tCK
tCKL
tCKH
MII_TXCLK
tTXS
tTHX
MII_TXEN
MII_TXD
Figure 8
10Base-TX MII Output Timing
Table 37
10Base-TX MII Output Timing
Parameter
Symbol
Values
Min.
MII_TXCLK Period
MII_TXCLK Low Period
MII_TXCLK High Period
MII_TXD, MII_TXEN to
MII_TXCLK Rising Setup Time
MII_TXD, MII_TXEN to
MII_TXCLK Rising Hold Time
tCK
tCKL
tCKH
tTXS
Typ.
Unit
Max.
400
tTXH
Note / Test Condition
ns
160
240
ns
160
240
ns
10
ns
10
ns
100Base-Tx MII Input Timing
100Base Tx MII Input timing conditions
0ns
100ns
200ns
tCK
tCKL
tCKH
MII_RXCLK
tRXOD
MII_RXDV
MII_RXD
tCSVA
MII_CRS
Figure 9
Data Sheet
100Base-TX MII Input Timing
70
Rev 1.11, 2005-11-28
ADM6993/X
Electrical Specification
Table 38
100Base-TX MII Input Timing
Parameter
Symbol
Values
Min.
MII_RXCLK Period
MII_RXCLK Low Period
MII_RXCLK High Period
MII_CRS Rising to MII_RXDV
Rising
MII_RXCLK Rising to
MII_RXD, MII_RXDV,
MII_CRS Output Delay
tCK
tCKL
tCKH
tCSVA
Typ.
Unit
Max.
40
tRXOD
Note / Test Condition
ns
16
24
ns
16
24
ns
0
10
ns
20
30
ns
100Base-TX MII Output Timing
100Base-TX MII Output timing conditions
0ns
50ns
100ns
150ns
200ns
250 ns
tCK
tCKL
tCKH
MII_TXCLK
tTXS
MII_TXEN
tTXH
MII_TXD
Figure 10
100Base-TX MII Output Timing
Table 39
100Base-TX MII Output Timing
Parameter
Symbol
Values
Min.
MII_TXCLK Period
MII_TXCLK Low Period
MII_TXCLK High Period
MII_TXD, MII_TXEN to
MII_TXCLK Rising Setup Time
MII_TXD, MII_TXEN to
MII_TXCLK Rising Hold Time
tCK
tCKL
tCKH
tTXS
tTXH
Typ.
Unit
Note / Test Condition
Max.
40
ns
16
24
ns
16
24
ns
10
ns
10
ns
Reduce MII Timing
Reduce MII timing conditions
Data Sheet
71
Rev 1.11, 2005-11-28
ADM6993/X
Electrical Specification
0ns
50ns
100ns
tCKL
tCK
tCKH
REFCLK
RMII_TXEN
tTXH
tTXS
TXD[1:0]
0ns
50ns
100 ns
tCK
tCKL
tCKH
REFCLK
RMII_CRSDV
tRXH
tRXS
RXD[1:0]
Figure 11
Reduce MII Timing
Table 40
100Base-TX MII Output Timing
Parameter
Symbol
Values
Min.
Typ.
Unit
Max.
tCK
tCKL
tCKH
tTXS
4
ns
TXE, TXD to REFCLK rising
hold time
tTXH
2
ns
CSRDV, RXD to REFCLK
rising setup time
tRXS
4
ns
CRSDV, RXD to REFCLK
rising hold time
tRXH
2
ns
RMII_REFCLK Period
RMII_REFCLK Low Period
RMII_REFCLK High Period
TXEN, TXD to REFCLK rising
setup time
Note / Test Condition
20
ns
10
ns
10
ns
GPSI (7-wire) Input Timing
GPSI (7-wire) Input timing conditions
Data Sheet
72
Rev 1.11, 2005-11-28
ADM6993/X
Electrical Specification
0ns
250 ns
500ns
tCK
tCKL
tCKH
GPSI_RXCLK
GPSI_RXD
tOD
GPSI_CRS/COL
Figure 12
GPSI (7-wire) Input Timing
Table 41
GPSI (7-wire) Input Timing
Parameter
Symbol
Values
Min.
GPSI_RXCLK Period
GPSI_RXCLK Low Period
GPSI_RXCLK High Period
GPSI_RXCLK Rising to
GPSI_CRS/GPSI_COL Output
Delay
TCK
TCKL
TCKH
TOD
Typ.
Unit
Note / Test Condition
Max.
100
ns
40
60
ns
40
60
ns
50
70
ns
GPSI (7-wire) Output Timing
GPSI (7-wire) Output timing conditions
0ns
250 ns
500ns
tCK
tCKL
tCKH
GPSI_TXCLK
tTXH
tTXS
GPSI_TXD
GPSI_TXEN
Figure 13
Data Sheet
GPSI (7-wire) Output Timing
73
Rev 1.11, 2005-11-28
ADM6993/X
Electrical Specification
Table 42
GPSI (7-wire) Output Timing
Parameter
Symbol
Values
Min.
TCK
TCKL
TCKH
TTXS
GPSI_TXCLK Period
GPSI_TXCLK Low Period
GPSI_ T XCLK High Period
GPSI_TXD, GPSI_TXEN to
GPSI_TXCLK Rising Setup
Time
Note / Test Condition
Max.
100
TTXH
GPSI_TXD, GPSI_TXEN to
GPSI_TXCLK Rising Hold
Time
Typ.
Unit
ns
40
60
ns
40
60
ns
10
ns
10
ns
HDLC Timing
0ns
100ns
200ns
tCK
tCKL
tCKH
HDLC_TXCLK
HDLC_TXD
0
tTXH
tTXS
1
1
1
0ns
1
1
1
0
bit0
100ns
bit1
bit2
bit3
bit4
bit3
bit4
200ns
tCK
tCKL
tCKH
HDLC_RXCLK
HDLC_RXD
Figure 14
HDLC Timing
Table 43
HDLC Timing
Parameter
0
tRXH
tRXS
1
1
1
1
1
Symbol
HDLC_REFCLK Low Period
Data Sheet
TCK
TCKL
0
bit0
Values
Min.
HDLC_REFCLK Period
1
Typ.
bit1
Unit
Note / Test Condition
Max.
20
ns
10
ns
74
bit2
Rev 1.11, 2005-11-28
ADM6993/X
Electrical Specification
Table 43
HDLC Timing (cont’d)
Parameter
Symbol
Values
Min.
HDLC_REFCLK High Period
TCKH
TTXS
Typ.
Unit
Max.
10
ns
0
ns
TXD to TXCLK rising hold time TTXH
5
ns
TRXS
0
ns
RXD to RXCLK rising hold time TRXH
5
ns
TXD to TXCLK rising setup
time
RXD to RXCLK rising setup
time
Note / Test Condition
SMI Timing
0ns
25ns
50n s
75n s
100 ns
tSDC
tSDCH
tSDCL
SDC
tSDH
tSDS
SDIO
Figure 15
SMI Timing
Table 44
SMI Timing
Parameter
Symbol
Values
Min.
TCK
SDC Low Period
TCKL
SDC High Period
TCKH
SDIO to SDC rising setup time TSDS
SDC Period
Typ.
Unit
Note / Test Condition
Max.
20
ns
10
ns
10
ns
4
ns
2
ns
on read/write cycle
SDIO to SDC rising hold time
on read/write cycle
Data Sheet
TSDH
75
Rev 1.11, 2005-11-28
ADM6993/X
Packaging
6
Packaging
128 PQFP packaging for ADM6993/X
17.2 +/- 0.2 mm
14.0 +/- 0.1 mm
18.5 mm
23.2 +/- 0.2 mm
20.0 +/- 0.1 mm
12.5 mm
3.4 mm
MAX
0.5 mm
Figure 16
Data Sheet
128 PQFP packaging for ADM6993/X
76
Rev 1.11, 2005-11-28
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