BSI Very Low Power/Voltage CMOS SRAM 256K X 16 bit BS616LV4015 DESCRIPTION FEATURES The BS616LV4015 is a high performance, very low power CMOS Static Random Access Memory organized as 262,144 words by 16 bits and operates from a wide range of 4.5V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 1.5uA and maximum access time of 55ns in 5V operation. Easy memory expansion is provided by an active LOW chip enable(CE) and active LOW output enable(OE) and three-state output drivers. The BS616LV4015 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV4015 is available in DICE form, JEDEC standard 44-pin TSOP Type II package and 48-pin BGA package. • Operation voltage : 4.5 ~ 5.5V • Low power consumption : Vcc = 5.0V C-grade: 45mA (Max.) operating current I-grade: 50mA (Max.) operating current 1.5uA (Typ.) CMOS standby current • High speed access time : -70 70ns (Max.) at Vcc = 5.0V -55 55ns (Max.) at Vcc = 5.0V • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 2V • Easy expansion with CE and OE options • I/O Configuration x8/x16 selectable by LB and UB pin PRODUCT FAMILY PRODUCT FAMILY BS616LV4015DC BS616LV4015EC BS616LV4015BC BS616LV4015AC BS616LV4015DI BS616LV4015EI BS616LV4015BI BS616LV4015AI OPERATING TEMPERATURE Vcc RANGE +0 O C to +70 O C -40 O C to +85 O C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 BS616LV4015EC BS616LV4015EI 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 ( ICCSB1, Max ) PKG TYPE ( ICC, Max ) Vcc= 5.0V Vcc= 5.0V Vcc= 5.0V 4.5V ~ 5.5V 70/55 15uA 45mA 4.5V ~ 5.5V 70/55 50uA 50mA DICE TSOP2-44 BGA-48-0810 BGA-48-0608 DICE TSOP2-44 BGA-48-0810 BGA-48-0608 BLOCK DIAGRAM PIN CONFIGURATIONS A4 A3 A2 A1 A0 CE DQ0 DQ1 DQ2 DQ3 VCC GND DQ4 DQ5 DQ6 DQ7 WE A17 A16 A15 A14 A13 POWER DISSIPATION STANDBY Operating SPEED ( ns ) A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 GND VCC DQ11 DQ10 DQ9 DQ8 NC A8 A9 A10 A11 A12 A4 A3 A2 A1 Address A0 A17 Input A16 A15 A14 A13 A12 Buffer 22 2048 Row Memory Array Decoder 2048 x 2048 2048 16 DQ0 . . . . . . . . Data Input Buffer 16 Column I/O Write Driver Sense Amp 16 Data Output Buffer DQ15 16 128 Column Decoder 14 CE WE OE UB LB Control Address Input Buffer A11 A10 A9 A8 A7 A6 A5 Vcc Gnd Brilliance Semiconductor Inc. reserves the right to modify document contents without notice. R0201-BS616LV4015 1 Revision 2.4 April 2002 BSI BS616LV4015 PIN DESCRIPTIONS Name Function A0-A17 Address Input These 18 address inputs select one of the 262,144 x 16-bit words in the RAM. CE Chip Enable Input CE is active LOW. Chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. LB and UB Data Byte Control Input Lower byte and upper byte data input/output control pins. DQ0 - DQ15 Data Input/Output Ports These 16 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Supply Gnd Ground TRUTH TABLE MODE Not selected (Power Down) Output Disabled Read Write R0201-BS616LV4015 CE WE OE LB UB DQ0~DQ7 DQ8~DQ15 Vcc CURRENT H X X X X High Z High Z ICCSB, ICCSB1 L H H X X High Z High Z ICC L L Dout Dout ICC H L High Z Dout ICC L H Dout High Z ICC L L Din Din ICC L L H L L X H L X Din ICC L H Din X ICC 2 Revision 2.4 April 2002 BSI BS616LV4015 ABSOLUTE MAXIMUM RATINGS(1) SYMBOL PARAMETER V TERM Terminal Voltage with Respect to GND T BIAS Temperature Under Bias OPERATING RANGE RATING UNITS -0.5 to Vcc+0.5 V -40 to +125 O O C T STG Storage Temperature PT Power Dissipation 1.0 W I OUT DC Output Current 20 mA -60 to +150 RANGE AMBIENT TEMPERATURE Vcc Commercial 0 O C to +70 O C 4.5V ~ 5.5V O Industrial C O -40 C to +85 C 4.5V ~ 5.5V CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CIN CDQ PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT VIN=0V 6 pF VI/O=0V 8 pF 1. This parameter is guaranteed and not tested. DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC ) PARAMETER NAME PARAMETER TEST CONDITIONS MIN. TYP. (1 ) MAX. UNITS VIH Guaranteed Input Low Voltage(2) Guaranteed Input High Voltage (2) IIL Input Leakage Current Vcc = Max, VIN = 0V to Vcc -- -- 1 uA IOL Output Leakage Current Vcc = Max, CE = VIH, or OE = VIH, VI/O = 0V to Vcc -- -- 1 uA VOL Output Low Voltage Vcc = Max, IOL = 2mA Vcc=5.0V -- -- 0.4 V VOH Output High Voltage Vcc = Min, I OH = -1mA Vcc=5.0V 2.4 -- -- V ICC Operating Power Supply Current CE = VIL, IDQ = 0mA, F = Fmax Vcc=5.0V -- -- 45 mA ICCSB Standby Current-TTL CE = V IH , IDQ= 0mA Vcc=5.0V -- -- 2 mA ICCSB1 Standby Current-CMOS CE Њ Vcc-0.2V, V IN Њ Vcc - 0.2V or V INЉ0.2V Vcc=5.0V -- 1.5 15 uA VIL (3) Vcc=5.0V -0.5 -- 0.8 V Vcc=5.0V 2.2 -- Vcc+0.2 V 1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC . DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC ) SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) VDR Vcc for Data Retention CE Њ Vcc - 0.2V VIN Њ Vcc - 0.2V or VIN Љ 0.2V 1.5 -- ICCDR Data Retention Current CE Њ Vcc -0.2V VIN Њ Vcc - 0.2V or VIN Љ 0.2V -- 0.1 tCDR Chip Deselect to Data Retention Time 0 TRC (2) tR See Retention Waveform Operation Recovery Time MAX. UNITS -- V 1.5 uA -- -- ns -- -- ns 1. Vcc = 1.5V, TA = + 25 C 2. tRC = Read Cycle Time O R0201-BS616LV4015 3 Revision 2.4 April 2002 BSI BS616LV4015 LOW VCC DATA RETENTION WAVEFORM ( CE Controlled ) Data Retention Mode Vcc VDR ≥ 2.0V Vcc Vcc tR t CDR CE ≥ Vcc - 0.2V VIH CE AC TEST CONDITIONS KEY TO SWITCHING WAVEFORMS Vcc/0V 5ns Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level VIH WAVEFORM 0.5Vcc AC TEST LOADS AND WAVEFORMS 1928 Ω 5.0V 1928 Ω 5.0V OUTPUT OUTPUT 5PF INCLUDING JIG AND SCOPE 1020 Ω 1020 Ω FIGURE 1A FIGURE 1B THEVENIN EQUIVALENT 667 Ω OUTPUT OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H , 100PF INCLUDING JIG AND SCOPE INPUTS DON T CARE: ANY CHANGE PERMITTED CHANGE : STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE 1.73V ALL INPUT PULSES Vcc GND 90% 90% 10% → ← → 10% ← 5ns FIGURE 2 AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 5.0V ) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME tAVAX tAVQV tELQV tBA tGLQV tELQX tBE tGLQX tEHQZ tBDO tGHQZ tRC tAA tACS tBA (1) tOE tCLZ tBE tOLZ tCHZ tBDO tOHZ tAXOX tOH DESCRIPTION Read Cycle Time Data Byte Control Access Time Data Byte Control to Output Low Z 55 -- -- -- -- ns -- -- 70 -- -- 55 ns -- 70 -- -- 55 ns (LB,UB) -- -- 35 -- -- 30 ns -- -- 35 -- -- 30 ns (CE) 10 -- -- 10 -- -- ns (LB,UB) 10 -- -- 10 -- -- ns 10 -- -- 10 -- -- ns (CE) 0 -- 35 0 -- 30 ns (LB,UB) Output Enable to Output in Low Z Chip Deselect to Output in High Z 70 UNIT -- Output Enable to Output Valid Chip Select to Output Low Z BS616LV4015-55 MIN. TYP. MAX. (CE) Address Access Time Chip Select Access Time BS616LV4015-70 MIN. TYP. MAX. 0 -- 35 0 -- 30 ns Output Disable to Output in High Z 0 -- 30 0 -- 25 ns Output Disable to Address Change 10 -- -- 10 -- -- ns Data Byte Control to Output High Z NOTE : 1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle. ; tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle. R0201-BS616LV4015 4 Revision 2.4 April 2002 BSI BS616LV4015 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) t RC ADDRESS t t t OH AA OH D OUT READ CYCLE2 (1,3,4) CE t ACS t BA LB,UB t BE D OUT t t BDO (5) t (5) CHZ CLZ READ CYCLE3 (1,4) t RC ADDRESS t AA OE t OH t OE t OLZ CE (5) t CLZ t t OHZ (5) t CHZ(1,5) ACS t BA LB,UB t BE t BDO D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL . 5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. R0201-BS616LV4015 5 Revision 2.4 April 2002 BSI BS616LV4015 AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 5.0V ) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION BS616LV4015-70 MIN. TYP. MAX. BS616LV4015-55 MIN. TYP. MAX. UNIT tAVAX tWC Write Cycle Time 70 -- -- 55 -- -- ns t E1LWH tCW Chip Select to End of Write 70 -- -- 55 -- -- ns tAVWL tAS Address Setup Time 0 -- -- 0 -- -- ns tAVWH tAW Address Valid to End of Write 70 -- -- 55 -- -- ns tWLWH tWP Write Pulse Width tWHAX t WR1 Write recovery Time tBW tBW(1) Date Byte Control to End of Write tWLQZ tWHZ Write to Output in High Z tDVWH tDW tWHDX tDH tGHQZ tWHOX 35 -- -- 30 -- -- ns (CE,WE) 0 -- -- 0 -- -- ns (LB,UB) 30 -- -- 25 -- -- ns 0 -- 30 0 -- 25 ns Data to Write Time Overlap 30 -- -- 25 -- -- ns Data Hold from Write Time 0 -- -- 0 -- -- ns tOHZ Output Disable to Output in High Z 0 -- 30 0 -- 25 ns tOW End of Write to Output Active 5 -- -- 5 -- -- ns NOTE : 1. tBW is 30ns/25ns (@speed=70ns/55ns) with address toggle. ; tBW is 70ns/55ns (@speed=70ns/55ns) without address toggle. SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) t WC ADDRESS (3) t WR OE (11) t CW (5) CE t BW LB,UB t AW WE (3) t WP t AS (2) (4,10) t OHZ D OUT t DH t DW D IN R0201-BS616LV4015 6 Revision 2.4 April 2002 BSI BS616LV4015 WRITE CYCLE2 (1,6) t WC ADDRESS (11) t CW (5) CE t BW LB,UB t AW WE t WR t WP (3) (2) t t AS DH (4,10) t WHZ D OUT (7) (8) t DW t DH (8,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE going low to the end of write. R0201-BS616LV4015 7 Revision 2.4 April 2002 BSI BS616LV4015 ORDERING INFORMATION BS616LV4015 X X -- Y Y SPEED 70: 70ns 55: 55ns GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE E: TSOP 2 B: BGA - 48 PIN(8x10mm) A: BGA - 48 PIN(6x8mm) D: DICE PACKAGE DIMENSIONS TSOP2-44 R0201-BS616LV4015 8 Revision 2.4 April 2002 BSI BS616LV4015 1.4 Max. 0.25 ̈́ 0.05 PACKAGE DIMENSIONS (continued) NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. SIDE VIEW D 0.1 D1 N D E D1 E1 e 48 10.0 8.0 5.25 3.75 0.75 0.35̈́ 0.05 E1 E ̈́ 0.1 e SOLDER BALL VIEW A 48 mini-BGA (8 x 10mm) NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 1.4 Max. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. BALL PITCH e = 0.75 D E N D1 E1 8.0 6.0 48 5.25 3.75 E1 e D1 VIEW A 48 mini-BGA (6 x 8mm) R0201-BS616LV4015 9 Revision 2.4 April 2002 BSI BS616LV4015 REVISION HISTORY Revision Description Date 2.2 2001 Data Sheet release Apr. 15, 2001 2.3 Modify Standby Current (Typ. and Jun. 29, 2001 Max.) 2.4 Modify some AC parameters. Modify 5V ICCSB1_Max(I-grade) from 25uA to 50uA. R0201-BS616LV4015 10 Note April,11,2002 Revision 2.4 April 2002