Cypress CY8C20110 0809 Capsense expressâ ¢-10 configurable gpios with pwm control Datasheet

CY8C20110
CapSense Express™-10 Configurable
GPIOs with PWM Control
Features
Overview
■
10 configurable IOs supporting
❐ CapSenseTM buttons
❐ LED drive
❐ All GPIOs support LED dimming with configurable delay option
❐ Interrupt outputs.
❐ WAKE on interrupt input
❐ Bi-directional sleep control pin
❐ User defined input or output
The CapSense ExpressTM controller allows the control of 10 IOs
configurable as capacitive sensing buttons or as GPIOs for
driving LEDs or interrupt signals based on various button
conditions.
■
2.4V to 3.6V and 4.75V to 5.25V operating voltage
■
Industrial temperature range: –40°C to +85°C
■
I2C slave interface for configuration and communication
❐ I2C data transfer rate up to 400 kbps
■
Reduce BOM cost
❐ Internal oscillator - no external oscillators or crystal
❐ Free development tool - no external tuning components
The user has the ability to configure buttons, outputs, and parameters through specific commands sent to the I2C port. The IOs
have the flexibility of mapping to capacitive buttons and as
standard GPIO functions such as interrupt output or input, LED
drive, and digital mapping of input to output using simple logical
operations. This enables easy PCB trace routing and reduces
the PCB size and stack up. CapSense Express products are
designed for easy integration into complex products.
■
Low operating current
❐ Active current: continuous sensor scan: 1.5 mA
❐ Deep sleep current: 4 uA
■
Available in 16-pin COL and 16-pin SOIC packages
The CY8C20110 is optimized for dimming LEDs in 15 selectable
duty cycles for back light applications. The device can be
configured to have up to 10 GPIOs connected to the PWM
output. The PWM duty cycle is programmable for variable LED
intensities.
Architecture
The logic block diagram illustrates the internal architecture of
CY8C20110.
The user is able to configure registers with parameters needed
to adjust the operation and sensitivity of the CapSense system.
CY8C20110 supports a standard I2C serial communication
interface that allows the host to configure the device and to read
sensor information in real time through easy register access.
The CapSense Express Core
The CapSense Express Core has a powerful configuration and
control block. It encompasses SRAM for data storage, an
interrupt controller, along with sleep and watchdog timers.
System resources provide additional capability, such as a configurable I2C slave communication interface and various system
resets. The Analog system contains the CapSense PSoC block
which supports capacitive sensing of up to 10 inputs.
Cypress Semiconductor Corporation
Document Number: 001-17345 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
• 408-943-2600
Revised September 06, 2008
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CY8C20110
Logic Block Diagram
External
Vcc
2.4 - 5.25V
10 Configurable IOs with
PWM Control
CapSense ExpressTM
Core
SYSTEM BUS
512B
SRAM
2KB Flash
Configuration and
Control Engine
Interrupt
Controller
Sleep and
Watchdog
Clock Sources
(Internal Main Oscillator)
SYSTEM BUS
CapSense
Block
Document Number: 001-17345 Rev. *E
I2C
Slave
Voltage and
Current
Reference
System
Resets
POR/
LVD
Page 2 of 18
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CY8C20110
Pinouts
Figure 1. Pin Diagram - 16 Pin COL
COL
(TOP VIEW)
Table 1. Pin Definitions - 16 Pin COL
Pin Number
Name
1
GP0[0]
Configurable as CapSense or GPIO
2
GP0[1]
Configurable as CapSense or GPIO
3
I2C SCL
I2C clock
4
I2C SDA
I2C data
5
GP1[0]
Configurable as CapSense or GPIO
6
GP1[1]
Configurable as CapSense or GPIO
7
VSS
8
GP1[2]
Configurable as CapSense or GPIO
9
GP1[3]
Configurable as CapSense or GPIO
10
GP1[4]
Configurable as Capsense or GPIO
11
XRES
Active HIGH external reset with internal pull down
12
GP0[2]
Configurable as CapSense or GPIO
13
VDD
14
GP0[3]
15
CSInt
16
GP0[4]
Document Number: 001-17345 Rev. *E
Description
Ground connection
Supply voltage
Configurable as CapSense or GPIO
Integrating Capacitor Input. The external capacitance is required only if 5:1
SNR cannot be achieved. Typical range is 10-100 nF
Configurable as CapSense or GPIO
Page 3 of 18
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CY8C20110
Figure 2. Pin Diagram - 16 Pin SOIC
GP0[3]
1
16
VDD
CSInt
2
15
GP0[2]
GP0[4]
3
14
XRES
GP0[0]
4
13
GP1[4]
GP0[1]
5
12
GP1[3]
I2CSCL
6
11
GP1[2]
I2CSDA
7
10
VSS
GP1[0]
8
9
SOIC
(Top View)
GP1[1]
Table 2. Pin Definitions - 16 Pin SOIC
Pin Number
Name
1
GP0[3]
2
CSInt
3
GP0[4]
Configurable as CapSense or GPIO
4
GP0[0]
Configurable as CapSense or GPIO
5
GP0[1]
Configurable as CapSense or GPIO
6
2C
I
I2C clock
7
I2C SDA
8
GP1[0]
Configurable as CapSense or GPIO
9
GP1[1]
Configurable as CapSense or GPIO
10
VSS
11
GP1[2]
Configurable as CapSense or GPIO
12
GP1[3]
Configurable as CapSense or GPIO
13
GP1[4]
Configurable as CapSense or GPIO
14
XRES
Active HIGH external reset with internal pull down.
15
GP0[2]
Configurable as CapSense or GPIO
16
VDD
Document Number: 001-17345 Rev. *E
SCL
Description
Configurable as CapSense or GPIO
Integrating Capacitor Input.The external capacitance is required only if 5:1
SNR cannot be achieved. Typical range is 10-100 nF.
I2C data
Ground connection
Supply voltage
Page 4 of 18
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CY8C20110
The CapSense Analog System
CapSense Express Software Tool
The CapSense analog system contains the capacitive sensing
hardware which supports CapSense Successive Approximation
(CSA) algorithm. This hardware performs capacitive sensing and
scanning without external components. Capacitive sensing is
configurable on each pin.
An easy to use software tool integrated with PSoC Express is
available for configuring and tuning CapSense Express devices.
Refer to the Application Note “CapSense (TM) Express Software
Tool - AN42137” for details of the software tool.
Additional System Resources
CapSense Express Register Map
System Resources provide additional capability useful to
complete systems. Additional resources are low voltage
detection and Power On Reset (POR).
CapSense Express supports user configurable registers through
which the device functionality and parameters are configured.
For details, refer to “CY8C201xx Register Reference Guide”
document.
■
The I2C slave provides 50, 100, or 400 kHz communication
over two wires.
■
Low Voltage Detection (LVD) interrupts signal the application
of falling voltage levels and the advanced POR circuit eliminates the need for a system supervisor.
An internal 1.8V reference provides a stable internal reference
so that capacitive sensing functionality is not affected by minor
VDD changes.
I2C Interface
The two modes of operation for the I2C interface are:
■
Device register configuration and status read or write for
controller
■
Command execution
LED Dimming
To change the brightness and intensity of the LEDs, the host
master (MCU, MPU, DSP, and so on) must send I2C commands
and program the PWM registers to enable output pins, set duty
cycle, and mode configuration. The single PWM source is
connected to all GPIO pins and have a common user defined
duty cycle. Each PWM enabled pin has two possible outputs:
PWM and 0/1 (depending on the configuration).
Four different modes of LED dimming are possible, as shown in
Figure 3 to Figure 6. The operation mode of the PWM enabled
pins is common. This means that one pin cannot behave as in
Mode1 and another pin as in Mode 2.
The I2C address is programmable during configuration. It is
locked to prevent accidental change by setting a flag in a configuration register.
Document Number: 001-17345 Rev. *E
Page 5 of 18
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CY8C20110
Figure 3. LED Dimming Mode 1: Change Intensity on ON/OFF Button Status
Document Number: 001-17345 Rev. *E
Page 6 of 18
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CY8C20110
Figure 4. LED Dimming Mode 2: Flash Intensity on ON Button Status
Figure 5. LED Dimming Mode 3: Hold Intensity After ON→OFF Button Transition
Document Number: 001-17345 Rev. *E
Page 7 of 18
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CY8C20110
Figure 6. LED Dimming Mode 4: Toggle Intensity on ON→OFF or OFF→ON Button Transitions
Modes of Operation
CapSense Express devices are configured to operate in any of
the following three modes to meet different power consumption
requirements:
■
Active Mode
■
Sleep Mode
■
Deep Sleep Mode
Active Mode
In the active mode, all the device blocks including the CapSense
sub system are powered. Typical active current consumption of
the device across the operating voltage range is 1.5 mA
Sleep Mode
Sleep mode provides an intermediate power operation mode. It
is enabled by configuring the corresponding device register.
When enabled, the device enters sleep mode and wakes up after
a specified sleep interval. It scans the capacitive sensors before
going back to sleep again. The device can also wake up from
sleep mode with a GPIO interrupt. The following sleep intervals
are supported in CapSense Express. The sleep interval is
configured through registers.
■
1.95 ms (512 Hz)
■
15.6 ms (64 Hz)
■
125 ms (8 Hz)
■
1s (1 Hz)
Document Number: 001-17345 Rev. *E
Deep Sleep Mode
Deep sleep mode provides the lowest power consumption
because there is no operation running. In this mode, the device
is woken up only using an external GPIO interrupt. A sleep timer
interrupt cannot wake up a device from deep sleep mode. This
is treated as a continuous sleep mode without periodic wakeups.
Refer to the Application Note “CapSense Express Power and
Sleep Considerations - AN44209” for details on different sleep
modes.
Bi-Directional Sleep Control Pin
The CY8C20110 requires a dedicated sleep control pin to allow
reliable I2C communication in case any sleep mode is enabled.
This is achieved by pulling the sleep control pin LOW to wake up
the device and start I2C communication. The sleep control pin is
configured on any of the GPIO. If sleep control feature is
enabled, the device have one less GPIO available for
CapSense/GPIO functions. The sleep control pin can also be
configured as interrupt output pin from CY8C20110 to the host
to acknowledge finger press on any button.
Page 8 of 18
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CY8C20110
Electrical Specifications
Absolute Maximum Ratings
Parameter
Description
Min
Typ
Max
Unit
Notes
Higher storage temperatures reduce data
retention time. Recommended storage
temperature is +25°C ± 25°C (0°C to
50°C). Extended duration storage
temperatures above 65°C degrades
reliability.
TSTG
Storage temperature
–55
25
+100
°C
TA
Ambient temperature with power
applied
–40
–
+85
°C
VDD
Supply voltage on VDD relative to VSS
–0.5
–
+6.0
V
VIO
DC input voltage
VSS – 0.5
–
VDD + 0.5
V
VIOZ
DC voltage applied to tri-state
VSS – 0.5
–
VDD + 0.5
V
IMIO
Maximum current into any GPIO pin
–25
–
+50
mA
ESD
Electrostatic discharge voltage
2000
–
-
V
LU
Latch up current
-
–
200
mA
Min
Typ
Max
Unit
Human body model ESD
Operating Temperature
Parameter
Description
TA
Ambient temperature
–40
–
+85
ºC
TJ
Junction temperature
–40
–
+100
ºC
Min
Typ
Max
Unit
Notes
DC Electrical Characteristics
DC Chip Level Specifications
Parameter
Description
Notes
VDD
Supply voltage
2.40
–
5.25
V
IDD
Supply current
–
1.5
2.5
mA
Conditions are VDD = 3.0V, TA = 25°C
ISB
Deep Sleep mode current with POR
and LVD active.
–
2.6
4
µA
VDD = 2.55V, 0°C < TA < 40°C
ISB
Deep Sleep mode current with POR
and LVD active.
–
2.8
5
µA
VDD = 3.3V, –40°C < TA < 85°C
ISB
Deep Sleep mode current with POR
and LVD active.
–
5.2
6.4
µA
VDD = 5.25V, –40°C < TA < 85°C
Document Number: 001-17345 Rev. *E
Page 9 of 18
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CY8C20110
5V and 3.3V DC General Purpose IO Specifications
This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
<TA< 85°C, 3.0V to 3.6V and -40°C<TA< 85°C respectively. Typical parameters apply to 5V and 3.3V at 25°C. These are for design
guidance only.
Parameter
Description
Min
Typ
Max
Unit
Notes
RPU
Pull up resistor
4
5.6
8
kΩ
VOH1
High output voltage
Port 0 pins
VDD – 0.2
–
–
V
IOH < 10 µA, VDD > 3.0V, maximum of 20
mA source current in all IOs.
VOH2
High output voltage
Port 0 pins
VDD – 0.9
–
–
V
IOH = 1 mA,VDD > 3.0V, maximum of 20
mA source current in all IOs.
VOH3
High output voltage
Port 1 pins
VDD – 0.2
–
–
V
IOH < 10 µA, VDD > 3.0V, maximum of 10
mA source current in all IOs.
VOH4
High output voltage
Port 1 pins
VDD – 0.9
–
–
V
IOH = 5 mA, VDD > 3.0V, maximum of 20
mA source current in all IOs.
VOH5
High output voltage
Port 1 pins with 3.0V LDO regulator
enabled
2.75
3.0
3.2
V
IOH < 10 µA, VDD > 3.1V, maximum of 4
IOs all sourcing 5mA.
VOH6
High Output Voltage
2.2
–
–
V
IOH = 5 mA, VDD > 3.1V, maximum of
20 mA source current in all IOs.
2.1
2.4
2.5
V
IOH < 10 µA, VDD > 3.0V, maximum of
20 mA source current in all IOs.
Port 1 pins with 3.0V LDO regulator
VOH7
High Output Voltage
Port 1 pins with 2.4V LDO regulator
VOH8
High Output Voltage
Port 1 pins with 2.4V LDO regulator
enabled
2
–
–
V
IOH < 200 µA,VDD > 3.0V, maximum of
20 mA source current in all IOs.
VOL
Low output voltage
–
–
0.75
V
IOL = 20 mA, VDD > 3V, maximum of 60
mA sink current on even port pins and 60
mA sink current on odd port pins
VIL
Input low voltage
–
–
0.75
V
VDD = 3 to 3.6V
VIH
Input high voltage
1.6
–
–
V
VDD = 3 to 3.6V
VIL
Input low voltage
–
–
0.8
V
VDD = 4.75V to 5.25V
VIH
Input high voltage
2.0
–
–
V
VDD = 4.75V to 5.25V
VH
Input hysteresis voltage
–
140
–
mV
IIL
Input leakage
–
1
–
nA
Gross tested to 1 µA.
CIN
Capacitive load on pins as input
0.5
1.7
5
pF
Package and pin dependent.
Temp = 25°C
COUT
Capacitive load on pins as output
0.5
1.7
5
pF
Package and pin dependent.
Temp = 25°C
Document Number: 001-17345 Rev. *E
Page 10 of 18
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CY8C20110
2.7V DC General Purpose IO Specifications
This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4V to 3.0V and -40°C<TA
<85°C, respectively. Typical parameters apply to 2.7V at 25°C. These are for design guidance only.
Parameter
Description
Min
Typ
Max
Unit
Notes
RPU
Pull up resistor
4
5.6
8
kΩ
VOH1
High output voltage
Port 0 Pins
VDD – 0.2
–
–
V
IOH <10 µA, maximum of 10 mA source
current in all IOs.
VOH2
High output voltage
Port 0 Pins
VDD – 0.5
–
–
V
IOH = 0.2 mA, maximum of 10 mA
source current in all IOs.
VOH3
High output voltage
Port 1 Pins
VDD – 0.2
–
–
V
IOH < 10 µA, maximum of 10 mA source
current in all IOs.
VOH4
High output voltage
Port 1 Pins
VDD – 0.5
–
–
V
IOH = 2 mA, maximum of 10 mA source
current in all IOs.
VOL
Low output voltage
–
–
0.75
V
IOL = 10 mA, maximum of 30 mA sink
current on even port pins and 30 mA sink
current on odd port pins
VOLP1
Low Output Voltage Port 1 Pins
–
–
0.4
V
IOL=5mA Maximum of 50mA sink
current on even port pins and 50mA sink
current on odd port pins
2.4<VDD <3.6V
VIL
Input low voltage
–
–
0.75
V
VDD = 2.4 to 3.6V.
VIH1
Input high voltage
1.4
–
–
V
VDD = 2.4 to 2.7V.
VIH2
Input high voltage
1.6
–
–
V
VDD = 2.7 to 3.6V
VH
Input hysteresis voltage
–
60
–
mV
IIL
Input leakage
–
1
–
nA
Gross tested to 1 µA.
CIN
Capacitive load on pins as input
0.5
1.7
5
pF
Package and pin dependent.
Temp = 25°C.
COUT
Capacitive load on pins as output
0.5
1.7
5
pF
Package and pin dependent.
Temp = 25°C.
2.7V DC Spec for I2C Line with 1.8V External Pull Up
This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4V to 3.0V and -40°C<TA
<85°C, respectively. Typical parameters apply to 2.7V at 25°C. The I2C lines drive mode must be set to open drain and pulled up to
1.8V externally.
Parameter
Description
Min
Typ
Max
Unit
Notes
VOLP1
Low Output Voltage Port 1 Pins
–
–
0.4
V
IOL=5mA Maximum of 50mA sink
current on even port pins and 50mA sink
current on odd port pins
2.4<VDD <3.6V
VIL
Input low voltage
–
–
0.75
V
VDD = 2.4 to 3.6V.
VIH
Input high voltage
1.4
–
–
V
VDD = 2.4 to 2.7V.
CIN
Capacitive load on pins as input
0.5
1.7
5
pF
Package and pin dependent.
Temp = 25°C.
COUT
Capacitive load on pins as output
0.5
1.7
5
pF
Package and pin dependent.
Temp = 25°C.
Document Number: 001-17345 Rev. *E
Page 11 of 18
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CY8C20110
DC POR and LVD Specifications
Parameter
Description
VPPOR0
VPPOR1
VDD Value/ PPOR Trip for
VDD= 2.7V
VDD= 3.3V, 5V
VLVD0
VLVD2
VLVD6
VDD Value for LVD trip
VDD= 2.7V
VDD= 3.3V
VDD= 5V
Min
Typ
Max
Unit
Notes
–
–
2.36
2.60
2.40
2.65
V
V
VDD must be greater than or equal to
2.5V during startup, reset from the XRES
pin, or reset from Watchdog.
2.39
2.75
3.98
2.45
2.92
4.05
2.51
2.99
4.12
V
V
V
DC Programming Specifications
This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and
-40°C<TA<85°C, 3.0V to 3.6V and -40°C<TA<85°C, or 2.4V to 3.0V and -40°C<TA<85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C. These are for design guidance only. Flash Endurance and Retention specifications with the use of EEPROM
user module are valid only within the range: 25°C±20°C during the Flash Write operation.
Refer to the EEPROM user module data sheet instructions for EEPROM Flash Write requirements outside the 25°C±20°C temperature
window. Use of this User Module for Flash Writes outside this range must occur at a known die temperature (±20°C) and requires the
designer to configure the temperature as a variable rather than the default 25°C value hard coded into the API. All use of this UM API
outside the range of 25°C±20°C is at the user’s own risk. This risk includes overwriting the Flash cell (when above the allowable
temperature range) thereby reducing the data sheet specified endurance performance or underwriting the Flash cell (when below the
allowable temperature range) thereby reducing the data sheet specified retention.
Symbol
Description
VddIWRITE Supply Voltage for Flash Write Operations[2]
IDDP
Supply Current During Programming or Verify
VILP
Input Low Voltage During Programming or
Verify
VIHP
Input High Voltage During Programming or
Verify
IILP
Input Current when Applying Vilp to P1[0] or
P1[1] During Programming or Verify
IIHP
Input Current when Applying Vihp to P1[0] or
P1[1] During Programming or Verify
VOLV
Output Low Voltage During Programming or
Verify
VOHV
Output High Voltage During Programming or
Verify
FlashENPB Flash Endurance (per block)
FlashENT Flash Endurance (total)
FlashDR
Flash Data Retention
Min
2.7
–
–
Typ
–
5
–
Max
–
25
0.8
Units
V
mA
V
2.2
–
–
V
–
–
0.2
mA
–
–
1.5
mA
–
–
V
Vdd
–1.0
50,000
1,800,0
00
10
–
Vss +
0.75
Vdd
–
–
–
–
–
–
–
–
Years
Notes
Driving internal pull down
resistor.
Driving internal pull down
resistor.
V
Erase/write cycles per block.
Erase/write cycles.
Note
1. Commands involving Flash Writes (0x01, 0x02, 0x03) must be executed only within the same VCC voltage range detected at POR (power on, XRES, or command
0x06) and above 2.7V. For register details, refer to CY8C201xx Register Reference Guide. If the user powers up the device in the 2.4V–3.6V range, Flash writes must
be performed only between 2.7V and 3.6V. If the user powers up the device in the 4.75V–5.25V range, Flash writes must be performed in that range only.
Document Number: 001-17345 Rev. *E
Page 12 of 18
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CY8C20110
Capsense Electrical Characteristics
Max (V)
Typical (V)
Min (V)
Low Voltage Cutoff (V)
Notes
5.25
5.0
4.75
4.73
See notes [5] and [6]
3.6
3.3
3.02
–
See note [2]
3.02
2.7
2.45
2.45
See notes [3] and [4]
AC Electrical Characteristics
5V and 3.3V AC General Purpose IO Specifications
Parameter
Description
Min
Max
Unit
Notes
TRise0
Rise time, strong mode,
Cload = 50pF, Port 0
15
80
ns
VDD = 3.0V to 3.6V and 4.75V to 5.25V,
10% - 90%
TRise1
Rise time, strong mode,
Cload = 50pF, Port 1
10
50
ns
VDD = 3.0V to 3.6V, 10% - 90%
TFall
Fall time, strong mode,
Cload = 50pF, all ports
10
50
ns
VDD = 3.0V to 3.6V and 4.75V to 5.25V,
10% - 90%
Min
Max
Unit
Notes
2.7V AC General Purpose IO Specifications
Parameter
Description
TRise0
Rise time, strong mode,
Cload = 50pF, Port 0
15
100
ns
VDD = 2.4V to 3.0V, 10% - 90%
TRise1
Rise time, strong mode,
Cload = 50pF, Port 1
10
70
ns
VDD = 2.4V to 3.0V, 10% - 90%
TFall
Fall time, strong mode,
Cload = 50pF, all ports
10
70
ns
VDD = 2.4V to 3.0V, 10% - 90%
Notes
2. If the device is in 3.3V mode of operation and the operating voltage drops below 3.02V, the device automatically reconfigures itself to work in 2.7V mode of operation.
3. If the device is in 2.7V mode of operation and the operating voltage drops below 2.45V, the scanning for Capsense parameters shuts down until the voltage returns to
over 2.45V. If the voltage continues to drop and goes below 2.4V, device goes into reset.
4. If the device is in 2.7V mode of operation and the operating voltage rises above 3.02V, the device automatically reconfigures itself to work in 3.3V mode of operation.
5. If the device is in 5.0V mode of operation and the operating voltage drops below 4.73V, the scanning for Capsense parameters shuts down until the voltage returns to
over 4.73V.
6. Powering up in the 3.6V to 4.75V range is not supported by Capsense Express. The device initializes to the 5.0V parameters but does not enable Capsense scanning
until the voltage goes above 4.73V.
Document Number: 001-17345 Rev. *E
Page 13 of 18
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CY8C20110
AC I2C Specifications
Parameter
Standard Mode
Description
THDSTAI2C Hold time (repeated) START
condition. After this period, the
first clock pulse is generated.
Unit
Min
Max
Min
Max
0
100
0
400
KHz
4.0
–
0.6
–
µs
SCL clock frequency
FSCLI2C
Fast Mode
TLOWI2C
LOW period of the SCL clock
4.7
–
1.3
–
µs
THIGHI2C
HIGH period of the SCL clock
4.0
–
0.6
–
µs
TSUSTAI2C
Setup time for a repeated START
condition
4.7
–
0.6
–
µs
THDDATI2C Data hold time
0
–
0
–
µs
TSUDATI2C Data setup time
250
–
100
–
ns
TSUSTOI2C Setup time for STOP condition
4.0
–
0.6
–
µs
TBUFI2C
BUS free time between a STOP
and START condition
4.7
–
1.3
–
µs
TSPI2C
Pulse width of spikes suppressed
by the input filter
–
–
0
50
ns
Notes
Fast mode not supported for
VDD < 3.0V
~
~
~
~
Figure 7. Definition for Timing for Fast/Standard Mode on the I2C Bus
tf
tLOWI2C
tr
tSUDATI2C
~
~
tf
~
~
SDA
tHDSTAI2C
tSPI2C
tBUFI2C
tr
S
tHDDATI2C
Document Number: 001-17345 Rev. *E
tHIGHI2C
tSUSTAI2C
~
~
tHDSTAI2C
~
~
SCL
Sr
tSUSTOI2C
P
S
Page 14 of 18
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CY8C20110
Ordering Information
Operating
Temperature
Ordering Code
Package Diagram
Package Type
CY8C20110-LDX2I
001-09116
16 COL[9]
Industrial
CY8C20110-SX2I
51-85068
16 SOIC
Industrial
Thermal Impedances by Package
Package
Typical θJA[7]
16 COL[9]
46 °C
16 SOIC
79.96 °C
Solder Reflow Peak Temperature
Minimum Peak Temperature[8]
Maximum Peak Temperature
COL[9]
240 °C
260 °C
16 SOIC
240 °C
260 °C
Package
16
Notes
7. TJ = TA + Power x θJA.
8. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5°C with Sn-Pb or 245 ± 5°C with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
9. Earlier termed as QFN package.
Document Number: 001-17345 Rev. *E
Page 15 of 18
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CY8C20110
Package Diagram
Figure 8. 16L Chip On Lead 3 X 3 mm Package Outline (SAWN) - 001-09116 – (Pb-Free)
001-09116 *D
Figure 9. 16-Pin (150-Mil) SOIC (51-85068)
51-85068-*B
Document Number: 001-17345 Rev. *E
Page 16 of 18
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CY8C20110
Document History Page
Document Title: CY8C20110 CapSense Express™-10 Configurable GPIOs with PWM Control
Document Number: 001-17345
REV.
ECN.
Orig. of
Change
Submission
Date
Description of Change
**
1341766
TUP/SFV
*A
1494145
TUP/AESA
Changed to FINAL Datasheet
Removed table - 2.7V DC General Purpose IO Specifications - Open Drain
with a pull up to 1.8V
Updated Logic Block Diagram
*B
1773608
TUP/AESA
Removed table - 3V DC General Purpose IO Specifications
Updated Logic Block Diagram
Updated table - DC POR and LVD Specifications
Updated table - DC Chip Level Specifications
Updated table - 5V and 3.3V DC General Purpose IO Specifications
Updated table - 2.7V DC General Purpose IO Specifications
Updated table - AC GPIO Specifications and split it into two tables for
5V/3.3V and 2.7V
Added section on CapSense ExpressTM Software tool
Updated 16-QFN Package Diagram
*C
2091026
DZU/MOHD
/AESA
Updated table-DC Chip Level Specifications
Updated table-Pin Definitions 16 pin COL
Updated table-Pin Definitions 16 pin SOIC
Updated table-5V and 3.3V DC General Purpose IO Specifications
Updated table - 2.7V DC General Purpose IO Specifications
Changed definition for Timing for Fast/Standard Mode on the I2C Bus
diagram
*D
2404731
DZU/MOHD
/PYRS
Updated Logic Block Diagram
Added DC Programming Specifications Table
Updated Features
Added CapSense Electrical Characteristics Table
*E
2549237
ZSK/AESA
Document Number: 001-17345 Rev. *E
New Data Sheet
09/06/2008
Changed Data Sheet title from “CY8C20110 Capsense Express (TM)-10
Configurable IOS” to CY8C20110 CapSense Express™-10 Configurable
GPIOs with PWM Control
Logic block diagram modified by adding PWM control block
LED Dimming section added
Different sleep modes explained
Bi-Directional Sleep Control Pin defined
DC Chip Level Specifications table updated with Deep Sleep mode parameters
Table added on “2.7V DC Spec for I2C Line with 1.8V External Pull-Up”
Updated package diagram 001-09116
Page 17 of 18
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CY8C20110
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
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image.cypress.com
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psoc.cypress.com/can
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psoc.cypress.com/precision-analog
© Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-17345 Rev. *E
Revised September 06, 2008
Page 18 of 18
CapSense™, CapSense Express™, PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor
Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated
Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
All products and company names mentioned in this document may be the trademarks of their respective holders.
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