[ /Title (CD74 HC194, CD74H CT194) /Subject (HighSpeed CMOS Logic 4-Bit CD54HC194, CD74HC194, CD74HCT194 Data sheet acquired from Harris Semiconductor SCHS164G September 1997 - Revised May 2006 High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register Features Description • Four Operating Modes - Shift Right, Shift Left, Hold and Reset • Synchronous Parallel or Serial Operation • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The ’HC194 and CD74HCT194 are 4-bit shift registers with Asynchronous Master Reset (MR). In the parallel mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock input (CP). During parallel loading serial data flow is inhibited. Shift left and shift right are accomplished synchronously on the positive clock edge with serial data entered at the shift left (DSL) serial input for the shift left mode, and at the shift right (DSR) serial input for the shift right mode. Clearing the register is accomplished by a Low applied to the Master Reset (MR) pin. • Wide Operating Temperature Range . . . -55oC to 125oC Ordering Information • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Asynchronous Master Reset • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs PART NUMBER • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Pinout CD54HC194 (CERDIP) CD74HC194 (PDIP, SOIC, SOP, TSSOP) CD74HCT194 (PDIP) TOP VIEW MR 1 TEMP. RANGE (oC) CD54HC194F3A -55 to 125 16 Ld CERDIP CD74HC194E -55 to 125 16 Ld PDIP CD74HC194M -55 to 125 16 Ld SOIC CD74HC194MT -55 to 125 16 Ld SOIC CD74HC194M96 -55 to 125 16 Ld SOIC CD74HC194NSR -55 to 125 16 Ld SOP CD74HC194PW -55 to 125 16 Ld TSSOP CD74HC194PWR -55 to 125 16 Ld TSSOP CD74HC194PWT -55 to 125 16 Ld TSSOP CD74HCT194E -55 to 125 16 Ld PDIP NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. 16 VCC DSR 2 15 Q0 D0 3 14 Q1 D1 4 13 Q2 D2 5 12 Q3 D3 6 11 CP DSL 7 10 S1 GND 8 9 S0 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2006, Texas Instruments Incorporated PACKAGE 1 CD54HC194, CD74HC194, CD74HCT194 Functional Diagram D0 D1 D2 D3 DSL 3 15 4 14 5 13 6 12 2 7 9 10 1 DSR 11 Q0 Q1 Q2 Q3 GND = 8 VCC = 16 S0 S1 MR CP TRUTH TABLE INPUTS OPERATING MODE OUTPUT CP MR S1 S0 DSR DSL Dn Q0 Q1 Q2 Q3 Reset (Clear) X L X X X X X L L L L Hold (Do Nothing) X H l l X X X q0 q1 q2 q3 Shift Left ↑ H h l X l X q1 q2 q3 L ↑ H h l X h X q1 q2 q3 H ↑ H l h l X X L q0 q1 q2 ↑ H l h h X X H q0 q1 q2 ↑ H h h X X dn d0 d1 d2 d3 Shift Right Parallel Load H = High Voltage Level, h = High Voltage Level One Set-up Time Prior To The Low to High Clock Transition, L = Low Voltage Level, l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition, dn (qn) = Lower Case Letters Indicate the State of the Referenced Input (or output) One Set-up Time Prior to the Low To High Clock Transition, X = Don’t Care, ↑ = Transition from Low to High Level 2 CD54HC194, CD74HC194, CD74HCT194 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA Package Thermal Impedance, θJA (see Note 2): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) VIH - 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads VOL VIH or VIL - - 3 CD54HC194, CD74HC194, CD74HCT194 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) II VCC or GND - ICC VCC or GND High Level Input Voltage VIH Low Level Input Voltage High Level Output Voltage CMOS Loads PARAMETER Input Leakage Current Quiescent Device Current 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 6 - - ±0.1 - ±1 - ±1 µA 0 6 - - 8 - 80 - 160 µA - - 4.5 to 5.5 2 - - 2 - 2 - V VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC to GND 0 5.5 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC (Note 3) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS CP 0.6 MR 0.55 DSL, DSR, Dn 0.25 Sn 1.10 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g. 360µA max at 25oC. 4 CD54HC194, CD74HC194, CD74HCT194 Prerequisite For Switching Function 25oC PARAMETER SYMBOL TEST CONDITIONS VCC (V) -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX MIN MAX UNITS 2 6 - 5 - 4 - MHz 4.5 30 - 24 - 20 - MHz 6 35 - 28 - 23 - MHz 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns 2 70 - 90 - 105 - ns 4.5 14 - 18 - 21 - ns 6 12 - 15 - 19 - ns 2 60 - 75 - 90 - ns 4.5 12 - 15 - 18 - ns 6 10 - 13 - 15 - ns 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns 2 70 - 90 - 105 - ns 4.5 14 - 18 - 21 - ns 6 12 - 15 - 18 - ns 2 0 - 0 - 0 - ns 4.5 0 - 0 - 0 - ns 6 0 - 0 - 0 - ns 2 0 - 0 - 0 - ns 4.5 0 - 0 - 0 - ns 6 0 - 0 - 0 - ns HC TYPES Max. Clock Frequency (Figure 1) MR Pulse Width (Figure 2) Clock Pulse Width (Figure 1) Set-up Time Data to Clock (Figure 3) Removal Time, MR to Clock (Figure 2) Set-Up Time S1, S0 to Clock (Figure 4) Set-up Time DSL, DSR to Clock (Figure 4) Hold Time S1, S0 to Clock (Figure 4) Hold Time Data to Clock (Figure 3) fMAX tW tW tSU tREM tSU tSU tH tH - - - - - - - - - HCT TYPES Max. Clock Frequency (Figure 1) fMAX - 4.5 27 - 22 - 18 - MHz MR Pulse Width (Figure 2) tW - 4.5 16 - 20 - 24 - ns Clock Pulse Width (Figure 1) tW - 4.5 16 - 20 - 24 - ns Set-up Time, Data to Clock (Figure 3) tSU - 4.5 14 - 18 - 21 - ns Removal Time MR to Clock (Figure 2) tREM - 4.5 12 - 15 - 18 - ns 5 Prerequisite For Switching Function (Continued) 25oC PARAMETER SYMBOL TEST CONDITIONS VCC (V) -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX MIN MAX UNITS Set-up Time S1, S0 to Clock (Figure 4) tSU - 4.5 20 - 25 - 30 - ns Set-up Time DSL, DSR to Clock (Figure 4) tSU - 4.5 14 - 18 - 21 - ns Hold Time S1, S0 to Clock (Figure 4) tH - 4.5 0 - 0 - 0 - ns Hold Time Data to Clock (Figure 3) tH - 4.5 0 - 0 - 0 - ns Switching Specifications PARAMETER HC TYPES Propagation Delay, Clock to Output (Figure 1) Input tr, tf = 6ns SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF Propagation Delay, Clock to Q tPLH, tPHL Output Transition Time (Figure 1) tTLH, tTHL Propagation Delay, MR to Output (Figure 2) tPHL Input Capacitance CL = 50pF CL = 50pF 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS 2 - 175 220 265 ns 4.5 - 35 44 53 ns 6 - 30 37 45 ns 5 14 - - - ns 2 - 75 95 110 ns 4.5 - 15 19 22 ns 6 - 13 16 19 ns 2 - 140 175 210 ns 4.5 - 28 35 42 ns 6 - 24 30 36 ns CIN - - - 10 10 10 pF Maximum Clock Frequency fMAX - 5 60 - - - MHz Power Dissipation Capacitance (Notes 4, 5) CPD - 5 55 - - - pF 4.5 - 37 46 56 ns 5 15 - - - ns HCT TYPES Propagation Delay, Clock to Output (Figure 1) tPLH, tPHL CL = 50pF Propagation Delay, Clock to Q tPLH, tPHL Output Transition Times (Figure 1) tTLH, tTHL CL = 50pF 4.5 - 15 19 22 ns Propagation Delay, MR to Output (Figure 2) tPHL CL = 50pF 4.5 - 40 50 60 ns Input Capacitance CIN - - - 10 10 10 pF Maximum Clock Frequency fMAX - 5 50 - - - MHz Power Dissipation Capacitance (Notes 4, 5) CPD - 5 60 - - - pF - NOTES: 3. CPD is used to determine the dynamic power consumption, per gate. 4. PD = VCC2 fi + ∑ (CL VCC2) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. 6 Test Circuits and Waveforms tr INPUT LEVEL CP 10% tf 90% VS VS 10% MR VS INPUT LEVEL VS GND tW tW tPLH tPHL 90% VS 10% tTLH VS tTHL tPHL VALID S OR DS CP VS INPUT LEVEL VS GND tH GND FIGURE 2. MASTER RESET PREREQUISITE TIMES AND PROPAGATION DELAYS INPUT LEVEL tSU INPUT LEVEL VS VALID VS tREM Q FIGURE 1. CLOCK PREREQUISITE TIMES AND PROPAGATION AND OUTPUT TRANSITION TIMES DATA GND VS CP Q VS tSU INPUT LEVEL CP GND FIGURE 3. DATA PREREQUISITE TIMES tH VS GND INPUT LEVEL GND FIGURE 4. PARALLEL LOAD OR SHIFT-LEFT/SHIFT-RIGHT PREREQUISITE TIMES 7 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-8682601EA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HC194F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD74HC194E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC194EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC194M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC194M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC194M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC194M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC194ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC194MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC194MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC194MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC194MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC194NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC194NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC194NSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC194PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC194PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC194PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC194PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC194PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC194PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC194PWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC194PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC194PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT194E ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 Orderable Device Status (1) Package Type Package Drawing CD74HCT194EE4 ACTIVE PDIP N Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) (RoHS) 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74HC194M96 Package Package Pins Type Drawing SOIC SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC194NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD74HC194PWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC194M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC194NSR SO NS 16 2000 346.0 346.0 33.0 CD74HC194PWR TSSOP PW 16 2000 346.0 346.0 29.0 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. 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