AD ADG5233BRUZ-RL7 High voltage latch-up proof Datasheet

High Voltage Latch-Up Proof,
Triple/Quad SPDT Switches
ADG5233/ADG5234
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Latch-up proof
4.5 pF off source capacitance
10 pF off drain capacitance
−0.6 pC charge injection
Low on resistance: 160 Ω typical
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
VDD to VSS analog signal range
Human body model (HBM) ESD rating
4 kV I/O port to supplies
1 kV I/O port to I/O port
4 kV all other pins
ADG5233
S1A
D1
S1B
S3B
D3
S3A
S2B
D2
S2A
LOGIC
09919-001
IN1 IN2 IN3 EN
SWITCHES SHOWN FOR
A 1 INPUT LOGIC.
Figure 1. ADG5233 TSSOP and LFCSP_WQ
ADG5234
S1A
D1
Automatic test equipment
Data acquisition
Instrumentation
Avionics
Audio and video switching
Communication systems
S4A
D4
S1B
S4B
IN1
IN4
IN2
IN3
S2B
S3B
D2
S2A
D3
S3A
SWITCHES SHOWN FOR
A 1 INPUT LOGIC.
09919-002
APPLICATIONS
Figure 2. ADG5234 TSSOP
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG5233 and ADG5234 are monolithic industrial CMOS
analog switches comprising three independently selectable
single-pole, double throw (SPDT) switches and four independently selectable SPDT switches, respectively.
1.
All channels exhibit break-before-make switching action that
prevents momentary shorting when switching channels. An EN
input on the ADG5233 (LFCSP and TSSOP packages) is used to
enable or disable the device. When disabled, all channels are
switched off.
2.
The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-andhold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth make
these devices suitable for video signal switching.
4.
3.
5.
6.
Trench Isolation Guards Against Latch-Up.
A dielectric trench separates the P and N channel transistors
thereby preventing latch-up even under severe overvoltage
conditions.
Ultralow Capacitance and −0.6 pC Charge Injection.
Dual-Supply Operation.
For applications where the analog signal is bipolar, the
ADG5233/ADG5234 can be operated from dual supplies
up to ±22 V.
Single-Supply Operation.
For applications where the analog signal is unipolar, the
ADG5233/ADG5234 can be operated from a single-rail
power supply up to 40 V.
3 V Logic-Compatible Digital Inputs.
VINH = 2.0 V, VINL = 0.8 V.
No VL Logic Power Supply Required.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
ADG5233/ADG5234
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Continuous Current per Channel, Sx or Dx ..............................8
Applications ....................................................................................... 1
Absolute Maximum Ratings ............................................................9
Functional Block Diagrams ............................................................. 1
ESD Caution...................................................................................9
General Description ......................................................................... 1
Pin Configurations and Function Descriptions ......................... 10
Product Highlights ........................................................................... 1
Typical Performance Characteristics ........................................... 12
Revision History ............................................................................... 2
Test Circuits..................................................................................... 16
Specifications..................................................................................... 3
Terminology .................................................................................... 18
±15 V Dual Supply ....................................................................... 3
Trench Isolation .............................................................................. 19
±20 V Dual Supply ....................................................................... 4
Applications Information .............................................................. 20
12 V Single Supply ........................................................................ 5
Outline Dimensions ....................................................................... 21
36 V Single Supply ........................................................................ 6
Ordering Guide .......................................................................... 22
REVISION HISTORY
3/12—Rev. 0 to Rev. A
Added 16-Lead LFCSP....................................................... Universal
Changes to Ordering Guide ...........................................................22
7/11—Revision 0: Initial Version
Rev. A | Page 2 of 24
Data Sheet
ADG5233/ADG5234
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
25°C
160
200
3.5
8
38
50
±0.02
±0.1
±0.02
±0.1
±0.08
±0.2
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
VDD to VSS
V
Ω typ
Ω max
Ω typ
VS = ±10 V, IS = −1 mA; see Figure 26
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, IS = −1 mA
250
280
9
10
65
70
Ω max
Ω typ
Ω max
±0.2
±0.4
±0.2
±0.4
±0.3
±0.9
nA typ
nA max
nA typ
nA max
nA typ
nA max
2.0
V min
0.8
V max
µA typ
µA max
pF typ
VS = ±10 V, IS = −1 mA
VDD = +16.5 V, VSS = −16.5 V
VS = ±10 V, VD =  10 V; see Figure 28
VS = ±10 V, VD =  10 V; see Figure 28
VS = VD = ±10 V; see Figure 25
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
3
Break-Before-Make Time Delay, tD
170
210
175
215
80
100
60
Charge Injection, QINJ
−0.6
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
−75
dB typ
Channel-to-Channel Crosstalk
−80
dB typ
−3 dB Bandwidth
Insertion Loss
205
−6.3
MHz typ
dB typ
CS (Off )
CD (Off )
CD (On), CS (On)
4.5
10
15
pF typ
pF typ
pF typ
tON (EN)
tOFF (EN)
250
280
255
290
115
125
30
Rev. A | Page 3 of 24
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 32
VS = 0 V, RS = 0 Ω, CL = 1 nF; see
Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 29
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Figure 27
RL = 50 Ω, CL = 5 pF; see Figure 30
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
ADG5233/ADG5234
Parameter
POWER REQUIREMENTS
IDD
ISS
Data Sheet
25°C
−40°C to +85°C
45
55
0.001
70
1
±9/±22
VDD/VSS
1
−40°C to +125°C
Unit
µA typ
µA max
µA typ
µA max
V min/V max
Test Conditions/Comments
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
Digital inputs = 0 V or VDD
GND = 0 V
Guaranteed by design; not subject to production test.
±20 V DUAL SUPPLY
VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
140
160
3.5
8
33
45
±0.02
±0.1
±0.02
±0.1
±0.08
±0.2
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
VDD to VSS
V
Ω typ
Ω max
Ω typ
VS = ±15 V, IS = −1 mA; see Figure 26
VDD = +18 V, VSS = −18 V
VS = ±15 V, IS = −1 mA
200
230
9
10
55
60
±0.2
±0.4
±0.2
±0.4
±0.3
±0.9
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
3
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
Break-Before-Make Time Delay, tD
170
200
165
200
80
95
50
Charge Injection, QINJ
0
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
−75
dB typ
Channel-to-Channel Crosstalk
−80
dB typ
−3 dB Bandwidth
Insertion Loss
210
−5.5
MHz typ
dB typ
tON (EN)
tOFF (EN)
235
260
240
265
105
115
30
Rev. A | Page 4 of 24
VS = ±15 V, IS = −1 mA
VDD = +22 V, VSS = −22 V
VS = ±15 V, VD =  15 V; see Figure 28
VS = ±15 V, VD =  15 V; see Figure 28
VS = VD = ±15 V; see Figure 25
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 32
VS = 0 V, RS = 0 Ω, CL = 1 nF; see
Figure 34
RL = 50 Ω, CL = 5 pF, f = 1MHz; see
Figure 29
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 27
RL = 50 Ω, CL = 5 pF; see Figure 30
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
Data Sheet
Parameter
CS (Off )
CD (Off )
CD (On), CS (On)
POWER REQUIREMENTS
IDD
ISS
ADG5233/ADG5234
25°C
4.5
10
15
−40°C to +85°C
−40°C to +125°C
50
70
0.001
110
1
±9/±22
VDD/VSS
1
Unit
pF typ
pF typ
pF typ
µA typ
µA max
µA typ
µA max
V min/V max
Test Conditions/Comments
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +22 V, VSS = −22 V
Digital inputs = 0 V or VDD
Digital inputs = 0 V or VDD
GND = 0 V
Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
25°C
−40°C to +85°C
−40°C to +125°C
Unit
0 V to VDD
V
Ω typ
360
610
700
Ω max
Ω typ
20
170
280
21
22
VS = 0 V to 10 V, IS = −1 mA
335
370
Ω max
Ω typ
Ω max
nA typ
VDD = 13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V; see
Figure 28
±0.02
±0.1
±0.02
±0.2
Drain Off Leakage, ID (Off )
±0.1
±0.08
±0.2
±0.2
±0.4
±0.3
±0.9
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
±0.4
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
3
235
295
240
305
70
90
125
365
410
380
430
105
115
65
Charge Injection, QINJ
VS = 0 V to 10 V, IS = −1 mA; see
Figure 26
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
500
5.5
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Channel On Leakage, ID (On), IS (On)
Test Conditions/Comments
0
Rev. A | Page 5 of 24
nA max
nA typ
VS = 1 V/10 V, VD = 10 V/1 V; see
Figure 28
nA max
nA typ
nA max
VS = VD = 1 V/10 V; see Figure 25
V min
V max
µA typ
µA max
pF typ
VIN = VGND or VDD
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 32
VS = 6 V, RS = 0 Ω, CL = 1 nF; see
Figure 34
ADG5233/ADG5234
Parameter
Off Isolation
Data Sheet
25°C
−75
−40°C to +85°C
Unit
dB typ
Channel-to-Channel Crosstalk
−80
dB typ
−3 dB Bandwidth
172
MHz typ
Insertion Loss
−8.7
dB typ
5
11
16
pF typ
pF typ
pF typ
40
50
µA typ
µA max
V min/V max
CS (Off )
CD (Off )
CD (On), CS (On)
POWER REQUIREMENTS
IDD
65
9/40
VDD
1
−40°C to +125°C
Test Conditions/Comments
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 29
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 27
RL = 50 Ω, CL = 5 pF; see
Figure 30
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 30
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V
Digital inputs = 0 V or VDD
GND = 0 V, VSS = 0 V
Guaranteed by design; not subject to production test.
36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 4.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
25°C
−40°C to +85°C
−40°C to +125°C
Unit
0 V to VDD
V
Ω typ
140
215
245
Ω max
Ω typ
8
35
50
9
10
VS = 0 V to 30 V, IS = −1 mA
60
65
Ω max
Ω typ
Ω max
nA typ
VDD = 39.6 V, VSS = 0 V
VS = 1 V/30 V, VD = 30 V/1 V; see
Figure 28
±0.02
±0.1
±0.02
±0.2
Drain Off Leakage, ID (Off )
±0.1
±0.08
±0.2
±0.2
±0.4
±0.3
±0.9
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
±0.4
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
VS = 0 V to 30 V, IS = −1 mA; see
Figure 26
VDD = 32.4 V, VSS = 0 V
VS = 0 V to 30 V, IS = −1 mA
170
3.5
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Channel On Leakage, ID (On), IS (On)
Test Conditions/Comments
3
205
255
200
240
85
115
275
290
265
290
115
115
Rev. A | Page 6 of 24
nA max
nA typ
VS = 1 V/30 V, VD = 30 V/1 V; see
Figure 28
nA max
nA typ
nA max
VS = VD = 1 V/30 V; see Figure 25
V min
V max
µA typ
µA max
pF typ
VIN = VGND or VDD
ns typ
ns max
ns typ
ns max
ns typ
ns max
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 33
Data Sheet
Parameter
Break-Before-Make Time Delay, tD
ADG5233/ADG5234
25°C
65
−40°C to +85°C
−40°C to +125°C
Charge Injection, QINJ
−0.6
Unit
ns typ
ns min
pC typ
Off Isolation
−75
dB typ
Channel-to-Channel Crosstalk
−80
dB typ
−3 dB Bandwidth
Insertion Loss
190
−5.9
MHz typ
dB typ
CS (Off )
CD (Off )
CD (On), CS (On)
POWER REQUIREMENTS
IDD
4.5
10
15
pF typ
pF typ
pF typ
35
80
100
VDD
1
130
9/40
Guaranteed by design; not subject to production test.
Rev. A | Page 7 of 24
µA typ
µA max
V min/V max
Test Conditions/Comments
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 18 V; see Figure 32
VS = 18 V, RS = 0 Ω, CL = 1 nF;
see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 29
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 27
RL = 50 Ω, CL = 5 pF; see Figure 30
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VDD = 39.6 V
Digital inputs = 0 V or VDD
GND = 0 V, VSS = 0 V
ADG5233/ADG5234
Data Sheet
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx
Table 5. ADG5233
Parameter
CONTINUOUS CURRENT, Sx OR Dx
VDD = +15 V, VSS = −15 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = +20 V, VSS = −20 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 12 V, VSS = 0 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 36 V, VSS = 0 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
25°C
85°C
125°C
Unit
24
42
16
26.5
11
15
mA maximum
mA maximum
26
46
17
28
11
15
mA maximum
mA maximum
17
24
12
17
7.7
11
mA maximum
mA maximum
25
45
17
28
11
15
mA maximum
mA maximum
25°C
85°C
125°C
Unit
21
15
10
mA maximum
22
15
10
mA maximum
15
11
7
mA maximum
22
15
10
mA maximum
Table 6. ADG5234
Parameter
CONTINUOUS CURRENT, Sx OR Dx
VDD = +15 V, VSS = −15 V
TSSOP (θJA = 112.6°C/W)
VDD = +20 V, VSS = −20 V
TSSOP (θJA = 112.6°C/W)
VDD = 12 V, VSS = 0 V
TSSOP (θJA = 112.6°C/W)
VDD = 36 V, VSS = 0 V
TSSOP (θJA = 112.6°C/W)
Rev. A | Page 8 of 24
Data Sheet
ADG5233/ADG5234
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 7.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
Peak Current, Sx or Dx Pins
ADG5233
ADG5234
Continuous Current, Sx or Dx2
Temperature Range
Operating
Storage
Junction Temperature
Thermal Impedance, θJA
16-Lead TSSOP (4-Layer Board)
20-Lead TSSOP (4-Layer Board)
16-Lead LFCSP (4-Layer Board)
Reflow Soldering Peak
Temperature, Pb Free
Rating
48 V
−0.3 V to +48 V
+0.3 V to −48 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs
first
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs
first
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
76 mA (pulsed at 1 ms, 10%
duty cycle maximum)
67 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Data + 15%
−40°C to +125°C
−65°C to +150°C
150°C
112.6°C/W
143°C/W
30.4°C/W
260(+0/−5)°C
Human Body Model (HBM) ESD
I/O Port to Supplies
4 kV
I/O Port to I/O Port
1 kV
All Other Pins
4 kV
Overvoltages at the INx, Sx, and Dx pins are clamped by internal diodes.
Limit current to the maximum ratings given.
2
See Table 5 and Table 6.
1
Rev. A | Page 9 of 24
ADG5233/ADG5234
Data Sheet
D3
S3A
IN2 8
9
IN3
14 GND
S2B 3
TOP VIEW
(Not to Scale)
11 VSS
10 S3B
9 D3
D2 4
S2A 5
10
ADG5233
09919-003
S2A 7
S1B 2
NOTES
1. EXPOSED PAD TIED TO SUBSTRATE, VSS.
Figure 3. ADG5233 TSSOP Pin Configuration
09919-004
13 VSS
TOP VIEW
S2B 5 (Not to Scale) 12 S3B
11
12 EN
D1 1
S1B 4
D2 6
13 IN1
EN
IN3 7
14
S3A 8
IN1
D1 3
IN2 6
16
15
ADG5233
16 S1A
GND
VDD 1
S1A 2
15 VDD
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. ADG5233 LFCSP_WQ Pin Configuration
Table 8. ADG5233 Pin Function Descriptions
Pin No.
TSSOP LFCSP_WQ
1
15
2
16
3
1
4
2
5
3
6
4
7
5
8
6
9
7
10
8
11
9
12
10
13
11
Mnemonic
VDD
S1A
D1
S1B
S2B
D2
S2A
IN2
IN3
S3A
D3
S3B
VSS
14
12
EN
15
16
13
14
EP
IN1
GND
Exposed
Pad
Description
Most Positive Power Supply Potential.
Source Terminal 1A. This pin can be an input or an output.
Drain Terminal 1. This pin can be an input or an output.
Source Terminal 1B. This pin can be an input or an output.
Source Terminal 2B. This pin can be an input or an output.
Drain Terminal 2. This pin can be an input or an output.
Source Terminal 2A. This pin can be an input or an output.
Logic Control Input 2.
Logic Control Input 3.
Source Terminal 3A. This pin can be an input or an output.
Drain Terminal 3. This pin can be an input or an output.
Source Terminal 3B. This pin can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to
ground.
Active Low Digital Input. When high, the device is disabled and all switches are off. When low, INx
logic inputs determine the on switches.
Logic Control Input 1.
Ground (0 V) Reference.
The exposed pad is connected internally. For increased reliability of the solder joints and maximum
thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Table 9. ADG5233 Truth Table
EN
1
0
0
1
INx
X1
0
1
SxA
Off
Off
On
SxB
Off
On
Off
X is don’t care.
Rev. A | Page 10 of 24
Data Sheet
ADG5233/ADG5234
IN1 1
20 IN4
S1A 2
19 S4A
18 D4
D1 3
S1B 4
ADG5234
17 S4B
VSS 5
16 VDD
S2B 7
14 S3B
TOP VIEW
GND 6 (Not to Scale) 15 NC
S2A 9
IN2 10
13 D3
12 S3A
11 IN3
NC = NO CONNECT. DO NOT
CONNECT TO THIS PIN.
09919-005
D2 8
Figure 5. ADG5234 TSSOP Pin Configuration
Table 10. ADG5234 Pin Function Descriptions
Pin No.
1
2
3
4
5
Mnemonic
IN1
S1A
D1
S1B
VSS
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
GND
S2B
D2
S2A
IN2
IN3
S3A
D3
S3B
NC
VDD
S4B
D4
S4A
IN4
Description
Logic Control Input 1.
Source Terminal 1A. This pin can be an input or an output.
Drain Terminal 1. This pin can be an input or an output.
Source Terminal 1B. This pin can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to
ground.
Ground (0 V) Reference.
Source Terminal 2B. This pin can be an input or an output.
Drain Terminal 2. This pin can be an input or an output.
Source Terminal 2A. This pin can be an input or an output.
Logic Control Input 2.
Logic Control Input 3.
Source Terminal 3A. This pin can be an input or an output.
Drain Terminal 3. This pin can be an input or an output.
Source Terminal 3B. This pin can be an input or an output.
No Connect. This pin is open.
Most Positive Power Supply Potential.
Source Terminal 4B. This pin can be an input or an output.
Drain Terminal 4. This pin can be an input or an output.
Source Terminal 4A. This pin can be an input or an output.
Logic Control Input 4.
Table 11. ADG5234 Truth Table
INx
0
1
SxA
Off
On
SxB
On
Off
Rev. A | Page 11 of 24
ADG5233/ADG5234
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
160
TA = 25°C
TA = 25°C
VDD = +18V
VSS = –18V
120
ON RESISTANCE (Ω)
120
100
VDD = +20V
VSS = –20V
80
VDD = +22V
VSS = –22V
60
100
60
40
20
20
0
–25
–20
–15
–10
–5
0
5
10
15
20
25
VS, VD (V)
VDD = 39.6V
VSS = 0V
VDD = 36V
VSS = 0V
80
40
0
09919-006
ON RESISTANCE (Ω)
VDD = 32.4V
VSS = 0V
140
140
0
5
10
15
20
25
30
35
40
VS, VD (V)
09919-009
160
Figure 9. On Resistance as a Function of VS, VD (36 V Single Supply)
Figure 6. On Resistance as a Function of VS, VD (±20 V Dual Supply)
250
250
TA = 25°C
VDD = +15V
VSS = –15V
VDD = +9V
VSS = –9V
200
200
ON RESISTANCE (Ω)
150
VDD = +13.2V
VSS = –13.2V
100
VDD = +16.5V
VSS = –16.5V
VDD = +15V
VSS = –15V
TA = +25°C
100
TA = –40°C
–15
–10
–5
0
5
10
15
20
VS, VD (V)
Figure 7. On Resistance as a Function of VS, VD (±15 V Dual Supply)
500
0
–15
09919-007
0
–20
0
5
10
15
VS, VD (V)
Figure 10. On Resistance as a Function of VS (VD) for Different Temperatures,
±15 V Dual Supply
VDD = 9V
VSS = 0V
450
180
VDD = 10.8V
VSS = 0V
400
160
300
ON RESISTANCE (Ω)
VDD = 12V
VSS = 0V
VDD = 13.2V
VSS = 0V
350
250
200
150
140
TA = +25°C
80
TA = –40°C
60
40
20
6
8
10
12
14
VS, VD (V)
Figure 8. On Resistance as a Function of VS, VD (12 V Single Supply)
VDD = +20V
VSS = –20V
0
–20
–15
–10
09919-008
4
TA = +85°C
100
50
0
TA = +125°C
120
100
2
–5
200
TA = 25°C
0
–10
09919-010
50
50
ON RESISTANCE (Ω)
TA = +85°C
150
–5
0
VS, VD (V)
5
10
15
20
09919-011
ON RESISTANCE (Ω)
TA = +125°C
Figure 11. On Resistance as a Function of VS (VD) for Different Temperatures,
±20 V Dual Supply
Rev. A | Page 12 of 24
Data Sheet
ADG5233/ADG5234
500
100
ID (OFF) + –
TA = +125°C
340
TA = +85°C
50
300
TA = +25°C
250
200
TA = –40°C
150
100
0
IS (OFF) – +
–50
ID, IS (ON) – –
ID, IS (ON) + +
–100
–150
50
VDD = 12V
VSS = 0V
0
2
4
6
8
10
12
VS, VD (V)
VDD = +20V
VSS = –20V
VBIAS = +15V/–15V
–200
09919-012
0
IS (OFF) + –
ID (OFF) – +
0
25
50
75
125
Figure 15. Leakage Currents as a Function of Temperature,
±20 V Dual Supply
Figure 12. On Resistance as a Function of VS (VD) for Different Temperatures,
12 V Single Supply
100
250
100
TEMPERATURE (°C)
09919-015
400
LEAKAGE CURRENT (pA)
ON RESISTANCE (Ω)
450
VDD = 36V
VSS = 0V
IS (OFF) + – IS (OFF) – +
0
TA = +125°C
150
TA = +85°C
TA = +25°C
100
TA = –40°C
–100
ID, IS (ON) + +
–200
ID (OFF) – +
–300
–400
–500
50
0
5
10
15
20
25
30
35
VS, VD (V)
09919-013
0
–600 VDD = 12V
VSS = 0V
VBIAS = 1V/10V
–700
0
25
75
100
125
Figure 16. Leakage Currents as a Function of Temperature,
12 V Single Supply
200
IS (OFF) + –
IS (OFF) – +
ID (OFF) – +
ID, IS (ON) + +
IS (OFF) + –
0
ID, IS (ON) + +
–50
ID (OFF) + –
ID (OFF) – +
–100
–150
ID, IS (ON) – –
–200
25
50
75
TEMPERATURE (°C)
100
125
09919-014
0
ID (OFF) + –
–400
–600
–800
VDD = +15V
VSS = –15V
VBIAS = +10V/–10V
–250
IS (OFF) – +
–200
Figure 14. Leakage Currents as a Function of Temperature, ±15 V Dual Supply
Rev. A | Page 13 of 24
VDD = 36V
VSS = 0V
VBIAS = 1V/30V
–1000
0
25
ID, IS (ON) – –
50
75
100
125
TEMPERATURE (°C)
Figure 17. Leakage Currents as a Function of Temperature,
36 V Single Supply
09919-017
LEAKAGE CURRENT (pA)
0
LEAKAGE CURRENT (pA)
ID (OFF) + –
50
TEMPERATURE (°C)
Figure 13. On Resistance as a Function of VS (VD) for Different Temperatures,
36 V Single Supply
50
ID, IS (ON) – –
09919-016
LEAKAGE CURRENT (pA)
ON RESISTANCE (Ω)
200
ADG5233/ADG5234
0
–20
Data Sheet
14
TA = 25°C
VDD = +15V
VSS = –15V
TA = 25°C
SOURCE TO DRAIN
12
VDD = +20V
VSS = –20V
CHARGE INJECTION (pC)
OFF ISOLATION (dB)
10
–40
–60
–80
VDD = +15V
VSS = –15V
8
VDD = +36V
VSS = 0V
6
4
VDD = +12V
VSS = 0V
2
0
–100
100k
1M
10M
100M
1G
FREQUENCY (Hz)
–4
–20
09919-018
–120
10k
–10
0
10
20
30
40
VS (V)
09919-020
–2
Figure 20. Charge Injection vs. Source Voltage, Source to Drain
Figure 18. Off Isolation vs. Frequency, ±15 V Dual Supply
0
0
TA = 25°C
VDD = +15V
–20 VSS = –15V
–20
TA = 25°C
VDD = +15V
VSS = –15V
–40
ACPSSR (dB)
BETWEEN SxA AND SxB
–60
–80
NO DECOUPLING
CAPACITORS
–60
–80
–100
BETWEEN S1x AND S2x
–100
–120
–140
10k
100k
1M
10M
100M
FREQUENCY (Hz)
1G
Figure 19. Crosstalk vs. Frequency, ±15 V Dual Supply
–120
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 21. ACPSRR vs. Frequency, ±15 V Dual Supply
Rev. A | Page 14 of 24
10M
09919-021
DECOUPLING
CAPACITORS
09919-019
CROSSTALK (dB)
–40
Data Sheet
0
–2
ADG5233/ADG5234
TA = 25°C
VDD = +15V
VSS = –15V
20
TA = 25°C
VDD = +15V
VSS = –15V
CAPACITANCE (pF)
ATTENUATION (dB)
SOURCE/DRAIN ON
–4
–6
–8
15
DRAIN OFF
10
SOURCE OFF
5
1M
10M
100M
1G
FREQUENCY (Hz)
300
250
VDD = +12V, VSS = 0V
VDD = +36V, VSS = 0V
VDD = +15V, VSS = –15V
VDD = +20V, VSS = –20V
100
50
–20
0
20
40
60
80
100
TEMPERATURE (°C)
120
09919-024
TIME (ns)
200
0
–40
–10
–5
0
5
10
15
VS (V)
Figure 24. Capacitance vs. Source Voltage, ±15 V Dual Supply
Figure 22. Bandwidth
150
0
–15
Figure 23. tTRANSITION Times vs. Temperature
Rev. A | Page 15 of 24
09919-025
–12
100k
09919-023
–10
ADG5233/ADG5234
Data Sheet
TEST CIRCUITS
IS (OFF)
Dx
Dx
A
A
VD
NC = NO CONNECT
VS
09919-031
Sx
09919-027
VD
Figure 25. On Leakage
Figure 28. Off Leakage
VDD
VSS
0.1µF
0.1µF
VDD
NETWORK
ANALYZER
VSS
NC
SxA
SxB
IN
50Ω
50Ω
VS
Dx
VIN
V
RL
50Ω
GND
IDS
VS
OFF ISOLATION = 20 log
Figure 26. On Resistance
VDD
VOUT
VSS
VDD
VS
VSS
0.1µF
0.1µF
VSS
VDD
NETWORK
ANALYZER
VSS
NC
Dx
SxB
VS
VDD
0.1µF
SxA
RL
50Ω
VOUT
Figure 29. Off Isolation
0.1µF
NETWORK
ANALYZER
SxA
R
50Ω
SxB
INx
50Ω
50Ω
VS
Dx
INx
VIN
GND
RL
50Ω
VOUT
VS
09919-029
GND
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
09919-030
Dx
09919-028
Sx
VOUT
INSERTION LOSS = 20 log
Figure 27. Channel-to-Channel Crosstalk
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Figure 30. Bandwidth
Rev. A | Page 16 of 24
VOUT
09919-033
NC
ID (OFF)
Sx
A
ID (ON)
Data Sheet
ADG5233/ADG5234
0.1µF
VDD
VSS
VDD
VS
0.1µF
VIN
50%
50%
VIN
50%
50%
VSS
SxB
Dx
SxA
VOUT
RL
300Ω
INx
CL
35pF
90%
VOUT
90%
tON
TRANSITION
tOFF
TRANSITION
tD
tD
09919-100
GND
VIN
Figure 31. Switching Timing
VDD
VSS
0.1µF
VDD
VSS
SxB
VS
VIN
Dx
SxA
VOUT
RL
300Ω
INx
CL
35pF
VOUT 80%
GND
VIN
09919-035
0.1µF
Figure 32. Break-Before-Make Delay, tD
3V
ENABLE
DRIVE (VIN)
50%
50%
VDD
VSS
VDD
VSS
INx
SxA
VS
SxB
0V
tOFF (EN)
tON (EN)
OUTPUT
0.9VOUT
Dx
EN
OUTPUT
VIN
50Ω
300Ω
Figure 33. Enable Delay, tON (EN), tOFF (EN)
VDD
VSS
0.1µF
0.1µF
VIN (NORMALLY
CLOSED SWITCH)
VDD
SxB
Dx
NC
SxA
INx
VIN
ON
VSS
CL
1nF
VOUT
OFF
VIN (NORMALLY
OPEN SWITCH)
VOUT
ΔVOUT
GND
QINJ = CL × ΔVOUT
09919-037
VS
35pF
09919-101
GND
0.1VOUT
Figure 34. Charge Injection
Rev. A | Page 17 of 24
ADG5233/ADG5234
Data Sheet
TERMINOLOGY
IDD
IDD represents the positive supply current.
CIN
CIN represents digital input capacitance.
ISS
ISS represents the negative supply current.
tON (EN)
tON (EN) represents the delay time between the 50% and 90%
points of the digital input and switch on condition.
VD, VS
VD and VS represent the analog voltage on Terminal Dx and
Terminal Sx, respectively.
tOFF (EN)
tOFF (EN) represents the delay time between the 50% and 90%
points of the digital input and switch off condition.
RON
RON is the ohmic resistance between Terminal Dx and
Terminal Sx.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
∆RON
∆RON represents the difference between the RON of any two
channels.
RFLAT (ON)
The difference between the maximum and minimum value of
on resistance as measured over the specified analog signal range
is represented by RFLAT (ON).
IS (Off)
IS (Off) is the source leakage current with the switch off.
tD
tD represents the off time measured between the 80% point of
both switches when switching from one address state to another.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off channel.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
VINL
VINL is the maximum input voltage for Logic 0.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
VINH
VINH is the minimum input voltage for Logic 1.
On Response
On response is the frequency response of the on switch.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
CD (Off)
CD (Off) represents the off switch drain capacitance, which is
measured with reference to ground.
CS (Off)
CS (Off) represents the off switch source capacitance, which is
measured with reference to ground.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR is a measure of the ability of a part to avoid coupling
noise and spurious signals that appear on the supply voltage pin
to the output of the switch. The dc voltage on the device is
modulated by a sine wave of 0.62 V p-p. The ratio of the
amplitude of the signal on the output to the amplitude of the
modulation is the ACPSRR.
CD (On), CS (On)
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
Rev. A | Page 18 of 24
Data Sheet
ADG5233/ADG5234
TRENCH ISOLATION
In the ADG5233/ADG5234, an insulating oxide layer (trench)
is placed between the NMOS and the PMOS transistors of each
CMOS switch. Parasitic junctions, which occur between the
transistors in junction isolated switches, are eliminated, and the
result is a completely latch-up proof switch.
PMOS
P WELL
N WELL
TRENCH
BURIED OXIDE LAYER
HANDLE WAFER
Figure 35. Trench Isolation
Rev. A | Page 19 of 24
09919-038
In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode can become forward-biased. A silicon controlled rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current that, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up proof switch.
NMOS
ADG5233/ADG5234
Data Sheet
APPLICATIONS INFORMATION
The ADG52xx family of switches and multiplexers provide a
robust solution for instrumentation, industrial, automotive, aerospace, and other harsh environments that are prone to latch-up,
which is an undesirable high current state that can lead to device
failure and persists until the power supply is turned off.
The ADG5233/ADG5234 high voltage switches allow singlesupply operation from 9 V to 40 V and dual supply operation
from ±9 V to ±22 V.
Rev. A | Page 20 of 24
Data Sheet
ADG5233/ADG5234
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
COPLANARITY
0.10
0.75
0.60
0.45
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 36. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
4.10
4.00 SQ
3.90
PIN 1
INDICATOR
0.35
0.30
0.25
16
13
0.65
BSC
PIN 1
INDICATOR
12
1
EXPOSED
PAD
2.70
2.60 SQ
2.50
4
9
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
0.20 MIN
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
08-16-2010-C
0.80
0.75
0.70
5
8
0.45
0.40
0.35
TOP VIEW
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 37. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions shown in millimeters
6.60
6.50
6.40
20
11
4.50
4.40
4.30
6.40 BSC
1
10
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 38. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
Rev. A | Page 21 of 24
0.75
0.60
0.45
ADG5233/ADG5234
Data Sheet
ORDERING GUIDE
Model 1
ADG5233BRUZ
ADG5233BRUZ-RL7
ADG5233BCPZ-RL7
ADG5234BRUZ
ADG5234BRUZ-RL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Description
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
Z = RoHS Compliant Part.
Rev. A | Page 22 of 24
EN Pin
Yes
Yes
Yes
No
No
Package Option
RU-16
RU-16
CP-16-17
RU-20
RU-20
Data Sheet
ADG5233/ADG5234
NOTES
Rev. A | Page 23 of 24
ADG5233/ADG5234
Data Sheet
NOTES
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09919-0-3/12(A)
Rev. A | Page 24 of 24