Intersil EL5176IYZ 250mhz differential twisted-pair driver Datasheet

EL5176
®
Data Sheet
September 7, 2010
FN7343.4
250MHz Differential Twisted-Pair Driver
Features
The EL5176 is a high bandwidth amplifier with an output in
differential form. It is primarily targeted for applications such
as driving twisted-pair lines or any application where
common mode injection is likely to occur. The input signal
can be in either single-ended or differential form but the
output is always in differential form.
• Fully differential inputs, outputs, and feedback
On the EL5176, two feedback inputs provide the user with
the ability to set the device gain (stable at minimum gain of
one).
• 250MHz 3dB bandwidth
• 800V/µs slew rate
• Low distortion at 20MHz
• Single 5V or dual ±5V supplies
• 40mA maximum output current
• Low power - 8mA typical supply current
The output common mode level is set by the reference pin
(REF), which has a -3dB bandwidth of over 50MHz.
Generally, this pin is grounded but it can be tied to any
voltage reference.
• Pb-free (RoHS compliant)
Both outputs (OUT+, OUT-) are short-circuit protected to
withstand temporary overload condition.
• Differential line drivers
The EL5176 is available in the 10 Ld MSOP package and is
specified for operation over the full -40°C to +85°C
temperature range.
Applications
• Twisted-pair drivers
• VGA over twisted-pair
• ADSL/HDSL drivers
• Single-ended to differential amplification
See also EL5171 (EL5176 in 8 Ld MSOP).
• Transmission of analog signals in a noisy environment
Ordering Information
Pinout
PART
NUMBER
EL5176IYZ*
(Note)
PART
MARKING
BAAAC
PACKAGE
10 Ld MSOP
M10.118A
(Pb-free) (3.0mm)
*Add “-T7” or “-T13” suffix for tape and reel. Please refer to TB347
for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
1
EL5176
(10 LD MSOP)
TOP VIEW
PKG.
DWG. #
FBP 1
10 OUT+
IN+ 2
REF 3
IN- 4
FBN 5
9 VS+
-
8 VS+
7 EN
6 OUT-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003-2005, 2007, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL5176
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Supply Voltage Rate-of-rise (dV/dT) . . . . . . . . . . . . . . . . . . . . 1V/µs
Input Voltage (IN+, IN- to VS+, VS-). . . . . . VS- - 0.3V to VS+ + 0.3V
Differential Input Voltage (IN+ to IN-) . . . . . . . . . . . . . . . . . . . . ±4.8V
Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA
Thermal Resistance (Typical)
θJA (°C/W)
θJC (°C/W)
10 Ld MSOP (Note 1). . . . . . . . . . . . . .
150
N/A
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RLD = 1kΩ, RF = 0, RG = OPEN, CLD = 2.7pF, Unless Otherwise
Specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
-3dB Bandwidth
AV = 1, CLD = 2.7pF
250
MHz
AV = 2, RF = 500, CLD = 2.7pF
60
MHz
AV = 10, RF = 500, CLD = 2.7pF
10
MHz
BW
±0.1dB Bandwidth
AV = 1, CLD = 2.7pF
50
MHz
SR
Slew Rate - Rise
VOUT = 3VP-P, 20% to 80%
600
800
1000
V/µs
Slew Rate - Fall
VOUT = 3VP-P, 20% to 80%
540
700
1000
V/µs
tSTL
Settling Time to 0.1%
VOUT = 2VP-P
10
ns
tOVR
Output Overdrive Recovery Time
20
ns
GBWP
Gain Bandwidth Product
100
MHz
AV =1, CLD = 2.7pF
50
MHz
VREFBW (-3dB) VREF -3dB Bandwidth
VREFSR+
VREF Slew Rate - Rise
VOUT = 2VP-P, 20% to 80%
90
V/µs
VREFSR-
VREF Slew Rate - Fall
VOUT = 2VP-P, 20% to 80%
50
V/µs
VN
Input Voltage Noise
at 10kHz
26
nV/√Hz
IN
Input Current Noise
at 10kHz
2
pA/√Hz
HD2
Second Harmonic Distortion
VOUT = 2VP-P, 5MHz
-94
dBc
VOUT = 2VP-P, 20MHz
-94
dBc
VOUT = 2VP-P, 5MHz
-77
dBc
VOUT = 2VP-P, 20MHz
-75
dBc
HD3
Third Harmonic Distortion
dG
Differential Gain at 3.58MHz
RL = 300Ω, AV = 2
0.1
%
dθ
Differential Phase at 3.58MHz
RL = 300Ω, AV = 2
0.5
°
INPUT CHARACTERISTICS
VOS
Input Referred Offset Voltage
IIN
Input Bias Current (VIN+, VIN-)
IREF
Input Bias Current (VREF)
RIN
Differential Input Resistance
CIN
Differential Input Capacitance
DMIR
Differential Mode Input Range
±2.1
±2.3
CMIR+
Common Mode Positive Input Range at VIN+, VIN-
3.1
3.4
2
±1.5
±25
mV
-14
-6
-3
µA
0.5
1.3
4
µA
300
kΩ
1
pF
±2.5
V
V
FN7343.4
September 7, 2010
EL5176
Electrical Specifications
VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RLD = 1kΩ, RF = 0, RG = OPEN, CLD = 2.7pF, Unless Otherwise
Specified. (Continued)
PARAMETER
DESCRIPTION
CMIR-
Common Mode Negative Input Range at VIN+, VIN-
CONDITIONS
VREFIN+
Positive Reference Input Voltage Range
VIN+ = VIN- = 0V
VREFIN-
Negative Reference Input Voltage Range
VIN+ = VIN- = 0V
VREFOS
Output Offset Relative to VREF
CMRR
Input Common Mode Rejection Ratio
VIN = ±2.5V
Gain
Gain Accuracy
VIN = 1
MIN
3.5
TYP
MAX
UNIT
-4.5
-4.2
V
3.8
V
-3.3
-3
V
±60
±100
mV
65
82
0.981
0.996
3.6
3.9
dB
1.011
V
OUTPUT CHARACTERISTICS
Positive Output Swing
VOUT
RL = 500Ω to GND
Negative Output Swing
IOUT(Max)
Maximum Source Output Current
Maximum Sink Output Current
-3.8
RL = 10Ω,
VIN+ = 1.1V,
VIN- = -1.1V,
VREF = 0
35
-3.5
V
-30
mA
50
-40
Output Impedance
ROUT
V
mA
130
mΩ
SUPPLY
VSUPPLY
Supply Operating Range
IS(ON)
Power Supply Current - Per Channel
IS(OFF)+
Positive Power Supply Current - Disabled
IS(OFF)-
Negative Power Supply Current - Disabled
PSRR
Power Supply Rejection Ratio
VS+ to VS-
4.75
6.8
EN pin tied to 4.8V
VS from ±4.5V to ±5.5V
11
V
7.5
8.2
mA
80
120
µA
-200
-120
µA
70
84
dB
ns
ENABLE
tEN
Enable Time
215
tDS
Disable Time
0.95
VIH
EN Pin Voltage for Power-Up
VIL
EN Pin Voltage for Shutdown
IIH-EN
EN Pin Input Current High
At VEN = 5V
IIL-EN
EN Pin Input Current Low
At VEN = 0V
µs
VS+ 1.5
VS+ 0.5
V
40
-6
V
60
-2.5
µA
µA
Pin Descriptions
PIN NUMBER
PIN NAME
PIN DESCRIPTION
1
FBP
Non-inverting feedback input; resistor RF1 must be connected from this pin to VOUT
2
IN+
Non-inverting input
3
REF
Output common-mode control; the common-mode voltage of VOUT will follow the voltage on this pin
4
IN-
Inverting input
5
FBN
Inverting feedback input; resistor RF2 must be connected from this pin to VOUT
6
OUT-
Inverting output
7
EN
Enabled when this pin is floating or the applied voltage ≤ VS+ -1.5
8
VS+
Positive supply
9
VS-
Negative supply
10
OUT+
Non-inverting output
3
FN7343.4
September 7, 2010
EL5176
Connection Diagram
RF1
VREF
0Ω
RS3
50Ω
INP
1 FBP
RS1
RG
50Ω
OPEN
INN-
OUT+ 10
2 IN+
VS- 9
-5V
3 REF
VS+ 8
+5V
4 IN-
RS2
50Ω
OUT+
RLD
1kΩ
EN 7
5 FBN
EN
OUT-
OUT- 6
RF2
0Ω
Typical Performance Curves
AV = 1, RLD = 1kΩ, CLD = 2.7pF
RLD = 1kΩ, CLD = 2.7pF
4
4
NORMALIZED MAGNITUDE (dB)
3
MAGNITUDE (dB)
2
1
0
VOP-P = 200mV
-1
-2
-3
VOP-P = 1VP-P
-4
-5
-6
1M
10M
100M
3
2
1
0
-1
AV = 1
-2
AV = 5
-3
-4
AV = 10
-5
-6
1M
1G
FREQUENCY (Hz)
1G
AV = 1, RLD = 1kΩ
5
3
4
2
3
1
RLD = 1kΩ
0
RLD = 500Ω
-1
-2
RLD = 200Ω
MAGNITUDE (dB)
NORMALIZED GAIN (dB)
AV = 1, CLD = 2.7pF
CLD = 56pF
CLD = 34pF
2
CLD = 23pF
1
0
-1
-2
-3
CLD = 9pF
CLD = 2.7pF
-4
-5
-6
1M
100M
FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS GAIN
4
-4
10M
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE
-3
AV = 2
10M
100M
FREQUENCY (Hz)
FIGURE 3. FREQUENCY RESPONSE vs RLD
4
1G
-5
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 4. FREQUENCY RESPONSE vs CLD
FN7343.4
September 7, 2010
EL5176
Typical Performance Curves
(Continued)
AV = 2, RF = 1kΩ, CLD = 2.7pF
10
10
9
9
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
AV = 2, RLD = 1kΩ, CLD = 2.7pF
8
7
RF = 1kΩ
6
RF = 500Ω
5
4
3
RF = 200Ω
2
8
7
6
RLD = 1kΩ
5
4
RLD = 500Ω
3
2
RLD = 200Ω
1
1
0
1M
10M
100M
0
1M
400M
10M
FREQUENCY (Hz)
100M
400M
FREQUENCY (Hz)
FIGURE 5. FREQUENCY RESPONSE
FIGURE 6. FREQUENCY RESPONSE vs RLD
100
5
4
2
IMPEDANCE (Ω)
MAGNITUDE (dB)
3
1
0
-1
-2
10
1
-3
-4
-5
100k
1M
10M
0.1
10k
100M
100k
FREQUENCY (Hz)
FIGURE 7. FREQUENCY RESPONSE - VREF
100
-10
90
100M
80
-20
70
-30
-40
CMRR (dB)
PSRR (dB)
10M
FIGURE 8. OUTPUT IMPEDANCE vs FREQUENCY
0
PSRR-
-50
PSRR+
-60
60
50
40
30
-70
20
-80
10
-90
1k
1M
FREQUENCY (Hz)
10k
1M
100k
10M
FREQUENCY (Hz)
FIGURE 9. PSRR vs FREQUENCY
5
100M
0
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 10. CMRR vs FREQUENCY
FN7343.4
September 7, 2010
EL5176
Typical Performance Curves
(Continued)
VS = ±5V, AV = 1, RLD = 1kΩ
-50
1k
-60
DISTORTION (dB)
VOLTAGE NOISE (nV/√Hz),
CURRENT NOISE (pA/√Hz)
-55
100
EN
10
100
1k
10k
HD3 (f = 20MHz)
-75
HD3 (f = 5MHz)
-80
-85
1M
100k
-100
1.0
10M
1.5
2.0
2.5
VS = ±5V, AV = 1, RLD = 1kΩ
-55
-55
DISTORTION (dB)
DISTORTION (dB)
-60
HD3 (f = 5MHz)
z)
HD3 (f = 20MH
-75
H
HD2 (f = 5M
-85
z)
-95
1
2
3
4
5
HD
-65
-70
-75
3
(f
HD
3
=
HD
-80
-85
-90
HD2 (f = 20MHz)
-90
20
M
(f
=
5M
Hz
)
2(
f=
6
7
8
9
10
Hz
)
= 5M
Hz)
200
300
400
-40
HD3 (f = 20MHz)
DISTORTION (dB)
DISTORTION (dB)
HD3 (f = 5MHz)
= 20M H
z)
HD2 (f = 5MHz)
-100
200
300
400
600
700
800
900 1000
VS = ±5V, RLD = 1kΩ, VOP-P, DM = 1V for AV = 1,
VOP-P, DM = 2V for AV = 2
HD3 (AV = 1)
-50
-70
-90
500
FIGURE 14. HARMONIC DISTORTION vs RLD
-40
-80
Hz
)
RLD (Ω)
VS = ±5V, AV = 2, VOP-P, DM = 2V
HD2 (f
5.0
-95
-100
100
FIGURE 13. HARMONIC DISTORTION vs DIFFERENTIAL
OUTPUT VOLTAGE
-60
4.5
20M
HD2
(f
VOP-P, DM (V)
-50
4.0
VS = ±5V, AV = 1, VOP-P, DM = 1V
-50
-80
3.5
Hz)
FIGURE 12. HARMONIC DISTORTION vs DIFFERENTIAL
OUTPUT VOLTAGE
-50
-70
3.0
= 5M
VOP-P, DM (V)
FIGURE 11. VOLTAGE AND CURRENT NOISE vs FREQUENCY
-65
Hz )
(f
HD2
-95
FREQUENCY (Hz)
-60
= 20M
HD2 (f
-90
IN
1
10
-65
-70
-60
3
HD
-70
(A V
)
=2
HD2 (AV =
HD2 (AV
2)
= 1)
-80
-90
500
600
700
800
900
RLD (Ω)
FIGURE 15. HARMONIC DISTORTION vs RLD
6
1000
-100
0
10
20
30
40
50
60
FREQUENCY (MHz)
FIGURE 16. HARMONIC DISTORTION vs FREQUENCY
FN7343.4
September 7, 2010
EL5176
Typical Performance Curves
(Continued)
0.5V/DIV
50mV/DIV
10ns/DIV
10ns/DIV
FIGURE 17. SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 18. LARGE SIGNAL TRANSIENT RESPONSE
M = 200ns, CH1 = 500mV/DIV, CH2 = 5V/DIV
M = 100ns, CH1 = 500mV/DIV, CH2 = 5V/DIV
CH1
CH1
CH2
CH2
200ns/DIV
100ns/DIV
FIGURE 20. DISABLED RESPONSE
FIGURE 19. ENABLED RESPONSE
0.6
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.0
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
486mW
POWER DISSIPATION (W)
POWER DISSIPATION (W)
0.9
0.5
MSOP8/10
0.4
θJA = +206°C/W
0.3
0.2
0.1
870mW
0.8
MSOP8/10
0.7
θJA = +115°C/W
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0
25
75 85
50
100
125
AMBIENT TEMPERATURE (°C)
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
7
0
25
50
75 85
100
125
AMBIENT TEMPERATURE (°C)
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7343.4
September 7, 2010
EL5176
Simplified Schematic
VS+
R1
IN+
R3
R2
IN-
FBP
R4
R7
R8
FBN
VB1
OUT+
RCD
REF
RCD
VB2
CC
R9
OUT-
R10
CC
R5
R6
VS-
Description of Operation and Application
Information
Product Description
The EL5176 is a wide bandwidth, low power and
single/differential ended to differential output amplifier. It can
be used as single/differential ended to differential converter.
The EL5176 is internally compensated for closed loop gain
of +1 or greater. Connected in gain of 1 and driving a 1kΩ
differential load, the EL5176 has a -3dB bandwidth of
250MHz. Driving a 200Ω differential load at gain of 2, the
bandwidth is about 30MHz. The EL5176 is available with a
power-down feature to reduce the power while the amplifier
is disabled.
Input, Output, and Supply Voltage Range
The EL5176 has been designed to operate with a single
supply voltage of 5V to 10V or a split supplies with its total
voltage from 5V to 10V. The amplifier has an input common
mode voltage range from -4.5V to 3.4V for ±5V supply. The
differential mode input range (DMIR) between the two inputs
is from -2.3V to +2.3V. The input voltage range at the REF
pin is from -3.3V to 3.8V. If the input common mode or
differential mode signal is outside the above-specified
ranges, it will cause the output signal to become distorted.
The output of the EL5176 can swing from -3.8V to +3.9V at
1kΩ differential load at ±5V supply. As the load resistance
becomes lower, the output swing is reduced.
Differential and Common Mode Gain Settings
The voltage applied at REF pin can set the output common
mode voltage and the gain is one. The differential gain is set
by the RF and RG network.
8
The gain setting for EL5176 is expressed in Equation 1:
2R F⎞
⎛
V ODM = ( V IN + – V IN - ) × ⎜ 1 + -----------⎟
RG ⎠
⎝
V OCM = V REF
(EQ. 1)
R F1 + R F2⎞
⎛
V ODM = V IN + × ⎜ 1 + ----------------------------⎟
RG
⎝
⎠
Where:
• RF1 = RF2 = RF
RF1
FBP
VIN+
VINVREF
VO+
IN+
RG
INREF
VO-
FBN
RF2
FIGURE 23.
Choice of Feedback Resistor and Gain Bandwidth
Product
For applications that require a gain of +1, no feedback resistor
is required. Just short the OUT+ pin to the FBP pin and the
OUT- pin to the FBN pin. For gains greater than +1, the
feedback resistor forms a pole with the parasitic capacitance
at the inverting input. As this pole becomes smaller, the
amplifier's phase margin is reduced. This causes ringing in
the time domain and peaking in the frequency domain.
Therefore, RF has some maximum value that should not be
exceeded for optimum performance. If a large value of RF
must be used, a small capacitor in the few Pico farad range in
parallel with RF can help to reduce the ringing and peaking at
the expense of reducing the bandwidth.
FN7343.4
September 7, 2010
EL5176
The bandwidth of the EL5176 depends on the load and the
feedback network. RF and RG appear in parallel with the
load for gains other than +1. As this combination gets
smaller, the bandwidth falls off. Consequently, RF also has a
minimum value that should not be exceeded for optimum
bandwidth performance. For gain of +1, RF = 0 is optimum.
For the gains other than +1, optimum response is obtained
with RF between 500Ω to 1kΩ.
Power Dissipation
The EL5176 has a gain bandwidth product of 100MHz for
RLD = 1kΩ. For gains ≥5, its bandwidth can be predicted by
Equation 2:
The maximum power dissipation allowed in a package is
determined according to Equation 3:
(EQ. 2)
Gain × BW = 100MHz
With the high output drive capability of the EL5176, it is
possible to exceed the +135°C absolute maximum junction
temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for the application to determine if the load
conditions or package types need to be modified for the
amplifier to remain in the safe operating area.
T JMAX – T AMAX
PD MAX = --------------------------------------------Θ JA
Driving Capacitive Loads and Cables
Where:
The EL5176 can drive a 50pF differential capacitor in parallel
with 1kΩ differential load with less than 5dB of peaking at a
gain of +1. If less peaking is desired in applications, a small
series resistor (usually between 5Ω to 50Ω) can be placed in
series with each output to eliminate most peaking. However,
this will reduce the gain slightly. If the gain setting is greater
than 1, the gain resistor RG can then be chosen to make up
for any gain loss, which may be created by the additional
series resistor at the output.
• TJMAX = Maximum junction temperature
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier's output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
• TAMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or
as expressed in Equation 4:
ΔV O
PD = V S × I SMAX + V S × -----------R
Where:
• VS = Total supply voltage
• ISMAX = Maximum quiescent supply current per channel
• ΔVO = Maximum differential output voltage of the
application
• RLD = Differential load resistance
The EL5176 can be disabled and its outputs placed in a high
impedance state. The turn-off time is about 0.95µs and the
turn-on time is about 215ns. When disabled, the amplifier's
supply current is reduced to 1.7µA for IS+ and 120µA for IStypically, thereby effectively eliminating the power
consumption. The amplifier's power-down can be controlled
by standard CMOS signal levels at the ENABLE pin. The
applied logic signal is relative to VS+ pin. Letting the EN pin
float or applying a signal that is less than 1.5V below VS+ will
enable the amplifier. The amplifier will be disabled when the
signal at the EN pin is above VS+ - 0.5V.
• ILOAD = Load current
The EL5176 has internal short circuit protection. Its typical
short circuit current is ±40mA for EL5176. If the output is
shorted indefinitely, the power dissipation could easily
increase such that the part will be destroyed. Maximum
reliability is maintained if the output current never exceeds
±40mA. This limit is set by the design of the internal metal
interconnect.
9
(EQ. 4)
LD
Disable/Power-Down
Output Drive Capability
(EQ. 3)
By setting the two PDMAX equations equal to each other, we
can solve the output current and RLD to avoid the device
overheat.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as short as possible. The power supply
pin must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the VS- pin is
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from VS+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the VS- pin becomes the negative
supply rail.
For good AC performance, parasitic capacitance should be
kept to a minimum. Use of wire-wound resistors should be
FN7343.4
September 7, 2010
EL5176
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
As the signal is transmitted through a cable, the high
frequency signal will be attenuated. One way to compensate
this loss is to boost the high frequency gain at the receiver
side.
Typical Applications
RF
FBP
50
TWISTED-PAIR
IN+
IN+
RT
RG
IN-
EL5176
EL5172
50
REF
ZO = 100Ω
FBN
VO
INREF
RF
RFR
RGR
FIGURE 24. TWISTED-PAIR CABLE RECEIVER
RF
GAIN
(dB)
FBP
RT
75
RGC
VO+
IN+
RG
IN-
CL
REF
VO-
FBN
fL
RF
2R F
DC Gain = 1 + ----------RG
1
f L ≅ ------------------------2πR G C C
2R F
( HF )Gain = 1 + -------------------------R G || R GC
1
f H ≅ ----------------------------2πR GC C C
fH
FREQUENCY
FIGURE 25. TRANSMIT EQUALIZER
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
FN7343.4
September 7, 2010
EL5176
Package Outline Drawing
M10.118A (JEDEC MO-187-BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP)
Rev 0, 9/09
3.0 ± 0.1
A
0.25
10
DETAIL "X"
CAB
0.18 ± 0.05
SIDE VIEW 2
4.9 ± 0.15
3.0 ± 0.1
1.10 Max
B
PIN# 1 ID
1
2
0.95 BSC
0.5 BSC
TOP VIEW
Gauge
Plane
0.86 ± 0.09
H
0.25
C
3°±3°
SEATING PLANE
0.10 ± 0.05
0.23 +0.07/ -0.08
0.08 C A B
0.55 ± 0.15
0.10 C
DETAIL "X"
SIDE VIEW 1
5.80
4.40
3.00
NOTES:
0.50
0.30
1.
Dimensions are in millimeters.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Plastic or metal protrusions of 0.15mm max per side are not
included.
Plastic interlead protrusions of 0.25mm max per side are not
included.
4.
1.40
5.
Dimensions “D” and “E1” are measured at Datum Plane “H”.
TYPICAL RECOMMENDED LAND PATTERN
6.
This replaces existing drawing # MDP0043 MSOP10L.
11
FN7343.4
September 7, 2010