AD AD8139 Low noise, rail-to-rail, differential adc driver Datasheet

Low Noise, Rail-to-Rail,
Differential ADC Driver
AD8139
FEATURES
APPLICATIONS
Fully differential
Low noise
2.25 nV/√Hz
2.1 pA/√Hz
Low harmonic distortion
98 dBc SFDR @ 1 MHz
85 dBc SFDR @ 5 MHz
72 dBc SFDR @ 20 MHz
High speed
410 MHz, 3 dB BW (G = 1)
800 V/μs slew rate
45 ns settling time to 0.01%
69 dB output balance @ 1 MHz
80 dB dc CMRR
Low offset: ±0.5 mV maximum
Low input offset current: 0.5 μA maximum
Differential input and output
Differential-to-differential or single-ended-to-differential
operation
Rail-to-rail output
Adjustable output common-mode voltage
Wide supply voltage range: 5 V to 12 V
Available in a small SOIC package and an 8-lead LFCSP
ADC drivers to 18 bits
Single-ended-to-differential converters
Differential filters
Level shifters
Differential PCB drivers
Differential cable drivers
–IN 1
AD8139
8
+IN
VOCM 2
7
NC
V+ 3
6
V–
+OUT 4
5
–OUT
NC = NO CONNECT
04679-001
FUNCTIONAL BLOCK DIAGRAMS
Figure 1. 8-Lead SOIC
AD8139
TOP VIEW
(Not to Scale)
–IN 1
8 +IN
VOCM 2
7 NC
V+ 3
6 V–
NC = NO CONNECT
04679-102
5 –OUT
+OUT 4
Figure 2. 8-Lead LFCSP
The AD8139 is manufactured on the Analog Devices, Inc.
proprietary, second-generation XFCB process, enabling it to
achieve low levels of distortion with input voltage noise of only
2.25 nV/√Hz.
100
10
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
1G
04679-078
The AD8139 is an ultralow noise, high performance differential
amplifier with rail-to-rail output. With its low noise, high
SFDR, and wide bandwidth, it is an ideal choice for driving
ADCs with resolutions to 18 bits. The AD8139 is easy to apply,
and its internal common-mode feedback architecture allows its
output common-mode voltage to be controlled by the voltage
applied to one pin. The internal feedback loop also provides
outstanding output balance as well as suppression of even-order
harmonic distortion products. Fully differential and singleended-to-differential gain configurations are easily realized by
the AD8139. Simple external feedback networks consisting of
four resistors determine the closed-loop gain of the amplifier.
The AD8139 is available in an 8-lead SOIC package with an
exposed paddle (EP) on the underside of its body and a 3 mm ×
3 mm LFCSP. It is rated to operate over the temperature range
of −40°C to +125°C.
INPUT VOLTAGE NOISE (nV/ Hz)
GENERAL DESCRIPTION
Figure 3. Input Voltage Noise vs. Frequency
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
Powered by TCPDF (www.tcpdf.org)
IMPORTANT LINKS for the AD8139*
Last content update 10/24/2013 10:44 am
SIMILAR PRODUCTS & PARAMETRIC SELECTION TABLES
DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE
Find Similar Products By Operating Parameters
High Speed Amplifiers Selection Table
ADA4932-1: (single) and ADA4932-2: (dual): Low Cost / Low Power
Differential ADC Driver
Analog Filter Wizard 2.0
ADI DiffAmpCalc™
AD8139 SPICE Macro Model, Rev 0,
ADA4937-1: (single) and ADA4937-2: (dual): Ultralow Distortion
Differential ADC Driver
ADA4938-1: (single) and ADA4938-2: (dual): Ultralow Distortion
Differential ADC Driver
ADA4927-1: (single) and ADA4927-2: (dual): Ultralow Distortion
Current Feedback Differential ADC Driver
ADA4930-1: (single) and ADA4930-2: (dual): Ultralow Noise Drivers
for Low Voltage ADCs
DOCUMENTATION
AN-1026: High Speed Differential ADC Driver Design Considerations
AN-0990: Terminating a Differential Amplifier in Single-Ended Input
Applications
AN-0992: Active Filter Evaluation Board for Differential Amplifiers
AN-649: Using the Analog Devices Active Filter Design Tool
AN-584: Using the AD813X Differential Amplifier
MT-218: Multiple Feedback Band-Pass Design Example
MT-076: Differential Driver Analysis
MT-075: Differential Drivers for High Speed ADCs Overview
A Stress-Free Method for Choosing High-Speed Op Amps
UG-474: Evaluation Board for Differential Amplifiers Offered in 8-Lead
SOIC Packages
UG-190: Differential Amplifier Evaluation Board for Single 8-lead
LFCSP Packages
UG-130: Differential Amplifier Evaluation Board for 8-lead SOIC and
MSOP Packages
Ask The Application Engineer 36, Wideband A/D Converter Front-End
Design Considerations II: Amplifier-or Transformer Drive for the ADC?
“Rules of the Road” for High-Speed Differential ADC Drivers
AD8139/AD8137: Differential Amplifiers For ADC Driving
DESIGN COLLABORATION COMMUNITY
Collaborate Online with the ADI support team and other designers
about select ADI products.
Follow us on Twitter: www.twitter.com/ADI_News
Like us on Facebook: www.facebook.com/AnalogDevicesInc
DESIGN SUPPORT
Submit your support request here:
Linear and Data Converters
Embedded Processing and DSP
Telephone our Customer Interaction Centers toll free:
Americas:
Europe:
China:
India:
Russia:
1-800-262-5643
00800-266-822-82
4006-100-006
1800-419-0108
8-800-555-45-90
Quality and Reliability
Lead(Pb)-Free Data
SAMPLE & BUY
AD8139
View Price & Packaging
Request Evaluation Board
Request Samples
Check Inventory & Purchase
Find Local Distributors
EVALUATION KITS & SYMBOLS & FOOTPRINTS
View the Evaluation Boards and Kits page for documentation and
purchasing
Symbols and Footprints
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet.
Note: Dynamic changes to the content on this page (labeled 'Important Links') does not
constitute a change to the revision number of the product data sheet.
This content may be frequently modified.
AD8139
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configurations and Function Descriptions ............................8
Applications....................................................................................... 1
Typical Performance Characteristics ..............................................9
Functional Block Diagrams............................................................. 1
Test Circuits ................................................................................ 17
General Description ......................................................................... 1
Theory of Operation ...................................................................... 18
Revision History ............................................................................... 2
Typical Connection and Definition of Terms ........................ 18
Specifications..................................................................................... 3
Applications..................................................................................... 19
VS = ±5 V, VOCM = 0 V .................................................................. 3
VS = 5 V, VOCM = 2.5 V ................................................................. 5
Estimating Noise, Gain, and Bandwidth with Matched
Feedback Networks .................................................................... 19
Absolute Maximum Ratings............................................................ 7
Outline Dimensions ....................................................................... 24
Thermal Resistance ...................................................................... 7
Ordering Guide .......................................................................... 24
ESD Caution.................................................................................. 7
REVISION HISTORY
10/07—Rev. A to Rev. B.
Changes to General Description .................................................... 1
Inserted Figure 2; Renumbered Sequentially................................ 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 5
Changes to Table 6 and Layout ....................................................... 8
Inserted Figure 6; Renumbered Sequentially................................ 8
Changes to Figure 30...................................................................... 12
Changes to Layout .......................................................................... 17
Changes to Figure 63...................................................................... 22
Changes to Exposed Paddle (EP) Section ................................... 23
Updated Outline Dimensions ....................................................... 24
8/04—Rev. 0 to Rev. A.
Added 8-Lead LFCSP.........................................................Universal
Changes to General Description .....................................................1
Changes to Figure 2...........................................................................1
Changes to VS = ±5 V, VOCM = 0 V Specifications .........................3
Changes to VS = 5 V, VOCM = 2.5 V Specifications.........................5
Changes to Table 4.............................................................................7
Changes to Maximum Power Dissipation Section........................7
Changes to Figure 26 and Figure 29............................................. 12
Inserted Figure 39 and Figure 42.................................................. 14
Changes to Figure 45 to Figure 47................................................ 15
Inserted Figure 48........................................................................... 15
Changes to Figure 52 and Figure 53............................................. 16
Changes to Figure 55 and Figure 56............................................. 17
Changes to Table 6.......................................................................... 19
Changes to Voltage Gain Section ................................................. 19
Changes to Driving a Capacitive Load Section .......................... 22
Changes to Ordering Guide .......................................................... 24
Updated Outline Dimensions....................................................... 24
5/04—Revision 0: Initial Version
Rev. B | Page 2 of 24
AD8139
SPECIFICATIONS
VS = ±5 V, VOCM = 0 V
TA = 25°C, differential gain = 1, RL, dm = 1 kΩ, RF = RG = 200 Ω, unless otherwise noted. TMIN to TMAX = −40°C to +125°C.
Table 1.
Parameter
DIFFERENTIAL INPUT PERFORMANCE
Dynamic Performance
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.01%
Overdrive Recovery Time
Noise/Harmonic Performance
SFDR
Third-Order IMD
Input Voltage Noise
Input Current Noise
DC Performance
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Open-Loop Gain
Input Characteristics
Input Common-Mode Voltage Range
Input Resistance
Input Capacitance
CMRR
Output Characteristics
Output Voltage Swing
Output Current
Output Balance Error
VOCM TO VO, cm PERFORMANCE
VOCM Dynamic Performance
−3 dB Bandwidth
Slew Rate
Gain
VOCM Input Characteristics
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Voltage Noise
Input Bias Current
CMRR
Conditions
Min
Typ
VO, dm = 0.1 V p-p
VO, dm = 2 V p-p
VO, dm = 0.1 V p-p
VO, dm = 2 V step
VO, dm = 2 V step, CF = 2 pF
G = 2, VIN, dm = 12 V p-p triangle wave
340
210
410
240
45
800
45
30
MHz
MHz
MHz
V/μs
ns
ns
98
85
72
−90
2.25
2.1
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
VO, dm = 2 V p-p, fC = 1 MHz
VO, dm = 2 V p-p, fC = 5 MHz
VO, dm = 2 V p-p, fC = 20 MHz
VO, dm = 2 V p-p, fC = 10.05 MHz ± 0.05 MHz
f = 100 kHz
f = 100 kHz
VIP = VIN = VOCM = 0 V
TMIN to TMAX
TMIN to TMAX
−500
±150
1.25
2.25
0.12
114
−4
Differential
Common mode
Common mode
∆VICM = ±1 V dc, RF = RG = 10 kΩ
Each single-ended output, RF = RG = 10 kΩ
Each single-ended output,
RL, dm = open circuit, RF = RG = 10 kΩ
Each single-ended output
f = 1 MHz
80
0.999
−900
∆VOCM/∆VO, dm, ∆VOCM = ±1 V
74
Rev. B | Page 3 of 24
8.0
0.5
Unit
μV
μV/°C
μA
μA
dB
+4
V
kΩ
MΩ
pF
dB
+VS – 0.20
+VS − 0.15
V
V
100
−69
mA
dB
515
250
1.000
MHz
V/μs
V/V
−3.8
VOS, cm = VO, cm − VOCM; VIP = VIN = VOCM = 0 V
f = 100 kHz
+500
600
1.5
1.2
84
−VS + 0.20
−VS + 0.15
VO, cm = 0.1 V p-p
VO, cm = 2 V p-p
Max
1.001
+3.8
3.5
±300
3.5
1.3
88
+900
4.5
V
MΩ
μV
nV/√Hz
μA
dB
AD8139
Parameter
POWER SUPPLY
Operating Range
Quiescent Current
+PSRR
−PSRR
OPERATING TEMPERATURE RANGE
Conditions
Min
Typ
+4.5
Change in +VS = ±1 V
Change in −VS = ±1 V
Rev. B | Page 4 of 24
95
95
−40
24.5
112
109
Max
Unit
±6
25.5
V
mA
dB
dB
°C
+125
AD8139
VS = 5 V, VOCM = 2.5 V
TA = 25°C, differential gain = 1, RL, dm = 1 kΩ, RF = RG = 200 Ω, unless otherwise noted. TMIN to TMAX = −40°C to +125°C.
Table 2.
Parameter
DIFFERENTIAL INPUT PERFORMANCE
Dynamic Performance
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.01%
Overdrive Recovery Time
Noise/Harmonic Performance
SFDR
Third-Order IMD
Input Voltage Noise
Input Current Noise
DC Performance
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Open-Loop Gain
Input Characteristics
Input Common-Mode Voltage Range
Input Resistance
Input Capacitance
CMRR
Output Characteristics
Output Voltage Swing
Output Current
Output Balance Error
VOCM TO VO, cm PERFORMANCE
VOCM Dynamic Performance
−3 dB Bandwidth
Slew Rate
Gain
VOCM Input Characteristics
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Voltage Noise
Input Bias Current
CMRR
Conditions
Min
Typ
VO, dm = 0.1 V p-p
VO, dm = 2 V p-p
VO, dm = 0.1 V p-p
VO, dm = 2 V step
VO, dm = 2 V step
G = 2, VIN, dm = 7 V p-p triangle wave
330
135
385
165
34
540
55
35
MHz
MHz
MHz
V/μs
ns
ns
99
87
75
−87
2.25
2.1
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
VO, dm = 2 V p-p, fC = 1 MHz
VO, dm = 2 V p-p, fC = 5 MHz, RL = 800 Ω
VO, dm = 2 V p-p, fC = 20 MHz, RL = 800 Ω
VO, dm = 2 V p-p, fC = 10.05 MHz ± 0.05 MHz
f = 100 kHz
f = 100 kHz
VIP = VIN = VOCM = 2.5 V
TMIN to TMAX
TMIN to TMAX
−500
±150
1.25
2.2
0.13
112
1
Differential
Common mode
Common mode
ΔVICM = ±1 V dc, RF = RG = 10 kΩ
Each single-ended output, RF = RG = 10 kΩ
Each single-ended output,
RL, dm = open circuit, RF = RG = 10 kΩ
Each single-ended output
f = 1 MHz
75
0.999
−1.0
ΔVOCM/ΔVO, dm, ΔVOCM = ±1 V
67
Rev. B | Page 5 of 24
7.5
0.5
Unit
μV
μV/°C
μA
μA
dB
4
V
kΩ
MΩ
pF
dB
+VS − 0.15
+VS − 0.10
V
V
80
−70
mA
dB
440
150
1.000
MHz
V/μs
V/V
1.0
VOS, cm = VO, cm − VOCM; VIP = VIN = VOCM = 2.5 V
f = 100 kHz
+500
600
1.5
1.2
79
−VS + 0.15
−VS + 0.10
VO, cm = 0.1 V p-p
VO, cm = 2 V p-p
Max
1.001
3.8
3.5
±0.45
3.5
1.3
79
+1.0
4.2
V
MΩ
mV
nV/√Hz
μA
dB
AD8139
Parameter
POWER SUPPLY
Operating Range
Quiescent Current
+PSRR
−PSRR
OPERATING TEMPERATURE RANGE
Conditions
Min
Typ
+4.5
Change in +VS = ±1 V
Change in −VS = ±1 V
Rev. B | Page 6 of 24
86
92
−40
21.5
97
105
Max
Unit
±6
22.5
V
mA
dB
dB
°C
+125
AD8139
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
VOCM
Power Dissipation
Input Common-Mode Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
Rating
12 V
±VS
See Figure 4
±VS
−65°C to +125°C
−40°C to +125°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The load current consists of differential
and common-mode currents flowing to the load, as well as
currents flowing through the external feedback networks and
the internal common-mode feedback loop. The internal resistor
tap used in the common-mode feedback loop places a 1 kΩ
differential load on the output. RMS output voltages should be
considered when dealing with ac signals.
Airflow reduces θJA. In addition, more metal directly in contact
with the package leads from metal traces, through holes,
ground, and power planes reduce the θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle
(EP) 8-lead SOIC (θJA = 70°C/W) and the 8-lead LFCSP
(θJA = 70°C/W) on a JEDEC standard 4-layer board. θJA values
are approximations.
4.0
MAXIMUM POWER DISSIPATION (W)
θJA is specified for the worst-case conditions, that is, θJA is
specified for device soldered in circuit board for surface-mount
packages.
Table 4.
Package Type
8-Lead SOIC with EP/4-Layer
8-Lead LFCSP/4-Layer
θJA
70
70
Unit
°C/W
°C/W
Maximum Power Dissipation
The maximum safe power dissipation in the AD8139 package
is limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic will change its properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the AD8139. Exceeding a junction
temperature of 175°C for an extended period can result in
changes in the silicon devices potentially causing failure.
3.5
3.0
2.5
2.0
1.5
SOIC
AND LFCSP
1.0
0.5
0
–40
–20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
100
120
04679-055
Table 3.
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
Rev. B | Page 7 of 24
AD8139
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD8139
8
+IN
VOCM 2
7
NC
V+ 3
6
V–
+OUT 4
5
NC = NO CONNECT
–OUT
–IN 1
8 +IN
VOCM 2
7 NC
V+ 3
6 V–
5 –OUT
+OUT 4
NC = NO CONNECT
Figure 5. 8-Lead SOIC Pin Configuration
04679-103
AD8139
04679-003
–IN 1
TOP VIEW
(Not to Scale)
Figure 6. 8-Lead LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
Mnemonic
−IN
VOCM
3
4
5
6
7
8
9
V+
+OUT
−OUT
V−
NC
+IN
Exposed Paddle
Description
Inverting Input.
An internal feedback loop drives the output common-mode voltage to be equal to the voltage applied to
the VOCM pin, provided the operation of the amplifier remains linear.
Positive Power Supply Voltage.
Positive Side of the Differential Output.
Negative Side of the Differential Output.
Negative Power Supply Voltage.
No Internal Connection.
Noninverting Input.
Solder exposed paddle on back of package to ground plane or to a power plane.
Rev. B | Page 8 of 24
AD8139
TYPICAL PERFORMANCE CHARACTERISTICS
2
2
1
1
G=2
–1
–2
–3
–4
–5
G=5
–6
–7
G = 10
–8
–9
–10
RG = 200Ω
VO, dm = 0.1V p-p
–13
1
10
100
1000
FREQUENCY (MHz)
–6
–8
–9
–10
–11
RG = 200Ω
VO, dm = 2.0V p-p
–12
1
10
100
1000
3
1
0
1
–1
0
CLOSED-LOOP GAIN (dB)
2
VS = ±5V
–1
–2
–3
–4
–5
–6
–2
–4
–6
–7
–8
–9
–10
–11
VO, dm = 0.1V p-p
100
1000
FREQUENCY (MHz)
Figure 8. Small Signal Frequency Response for Various Power Supplies
3
3
CLOSED-LOOP GAIN (dB)
0
–2
–3
–4
–40°C
–7
–8
–2
–3
–4
–5
–6
–7
–8
–9
–9
–10
–10
–11
+25°C
FREQUENCY (MHz)
1000
–12
10
04679-006
100
+85°C
1
–1
VO, dm = 0.1V p-p
+125°C
2
0
–6
1000
Figure 11. Large Signal Frequency Response for Various Power Supplies
–1
–5
100
FREQUENCY (MHz)
+85°C
1
VO, dm = 2.0V p-p
–12
10
+125°C
2
VS = +5V
–5
–8
–10
10
VS = ±5V
–3
–7
–12
10
G = 10
–7
2
04679-005
CLOSED-LOOP GAIN (dB)
–5
Figure 10. Large Signal Frequency Response for Various Gains
VS = +5V
3
CLOSED-LOOP GAIN (dB)
–4
FREQUENCY (MHz)
5
4
–11
G=2
–3
–13
Figure 7. Small Signal Frequency Response for Various Gains
–9
G=5
–2
04679-008
–12
–1
Figure 9. Small Signal Frequency Response at Various Temperatures
–40°C
+25°C
VO, dm = 2.0V p-p
100
FREQUENCY (MHz)
1000
04679-009
–11
G=1
0
04679-007
NORMALIZED CLOSED-LOOP GAIN (dB)
G=1
0
04679-004
NORMALIZED CLOSED-LOOP GAIN (dB)
Unless otherwise noted, differential gain = +1, RG = RF = 200 Ω, RL, dm = 1 kΩ, VS = ±5 V, TA = 25°C, VOCM = 0 V. Refer to the basic test
circuit in Figure 57 for the definition of terms.
Figure 12. Large Signal Frequency Response at Various Temperatures
Rev. B | Page 9 of 24
AD8139
3
RL = 200Ω
2
RL = 100Ω
1
0
0
–1
–1
–2
RL = 500Ω
–3
–4
–5
–6
–7
–8
–2
–3
–4
–5
–6
–7
–8
–12
1000
04679-040
100
3
Figure 16. Large Signal Frequency Response for Various Loads
2
CF = 0pF
1
0
CF = 2pF
–5
–6
–7
–8
–4
–5
–6
–7
–8
–9
–11
–12
1000
VOCM = +4.3V
5
0.5
VOCM = +4V
NORMALIZED CLOSED-LOOP GAIN (dB)
3
VOCM = –4V
2
1
0
VOCM = 0V
–1
–2
–3
–4
–5
–6
–7
–9
10
VO, dm = 0.1V p-p
100
1000
FREQUENCY (MHz)
04679-012
–8
1000
Figure 17. Large Signal Frequency Response for Various CF
VOCM = –4.3V
4
100
FREQUENCY (MHz)
Figure 14. Small Signal Frequency Response for Various CF
6
VO, dm = 2.0V p-p
–13
10
RL = 100Ω
(VO, dm = 0.1V p-p)
0.4
RL = 100Ω
(VO, dm = 2.0V p-p)
0.3
RL = 1kΩ
(VO, dm = 2.0V p-p)
0.2
0.1
RL = 1kΩ
(VO, dm = 0.1V p-p)
0
–0.1
–0.2
–0.3
04679-0-042
100
FREQUENCY (MHz)
04679-011
VO, dm = 0.1V p-p
04679-014
–10
–12
10
CF = 2pF
–3
–10
–9
–11
–2
CLOSED-LOOP GAIN (dB)
–2
–4
CF = 1pF
–1
–1
–3
CF = 0pF
1
CF = 1pF
0
1000
FREQUENCY (MHz)
Figure 13. Small Signal Frequency Response for Various Loads
2
RL = 200Ω
100
04679-041
VO, dm = 2.0V p-p
–13
10
RL = 1kΩ
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
RL = 1kΩ
–9
–11
VO, dm = 0.1V p-p
–12
10
CLOSED-LOOP GAIN (dB)
RL = 500Ω
–10
–9
–10
–11
RL = 100Ω
1
CLOSED-LOOP GAIN (dB)
CLOSED-LOOP GAIN (dB)
2
–0.4
–0.5
1
10
100
FREQUENCY (Hz)
Figure 18. 0.1 dB Flatness for Various Loads and Output Amplitudes
Figure 15. Small Signal Frequency Response at Various VOCM
Rev. B | Page 10 of 24
AD8139
–30
–50
DISTORTION (dBc)
VS = ±5V
–70
–80
VS = +5V
–90
–100
–120
10
100
Figure 19. Second Harmonic Distortion vs. Frequency and Supply Voltage
–130
0.1
1
10
100
FREQUENCY (MHz)
Figure 22. Third Harmonic Distortion vs. Frequency and Supply Voltage
–30
–30
VO, dm = 2.0V p-p
–40
–50
VO, dm = 2.0V p-p
–50
–60
DISTORTION (dB)
G=1
–70
–80
G=5
–90
–100
G=2
–110
–70
–80
–90
–100
–110
–120
–120
–130
–130
1
10
100
FREQUENCY (MHz)
–140
0.1
04679-016
–140
0.1
G=1
G=2
G=5
1
10
100
FREQUENCY (MHz)
Figure 20. Second Harmonic Distortion vs. Frequency and Gain
Figure 23. Third Harmonic Distortion vs. Frequency and Gain
–30
–30
VO, dm = 2.0V p-p
–40
–40
–50
–50
–60
DISTORTION (dBc)
–70
RL = 100Ω
RL = 200Ω
–80
–90
RL = 500Ω
–100
RL = 1kΩ
VO, dm = 2.0V p-p
–80
–90
–100
–120
–130
0.1
–130
0.1
100
04679-017
–120
10
Figure 21. Second Harmonic Distortion vs. Frequency and Load
RL = 200Ω
–70
–110
FREQUENCY (MHz)
RL = 100Ω
–60
–110
1
RL = 500Ω
RL = 1kΩ
1
10
100
FREQUENCY (MHz)
Figure 24. Third Harmonic Distortion vs. Frequency and Load
Rev. B | Page 11 of 24
04679-019
–60
DISTORTION (dB)
–90
–100
–120
1
VS = ±5V
–80
–110
FREQUENCY (MHz)
DISTORTION (dBc)
–70
–110
–130
0.1
VS = +5V
–60
04679-018
–60
04679-015
DISTORTION (dBc)
–50
–40
VO, dm = 2.0V p-p
–40
04679-020
–40
–30
VO, dm = 2.0V p-p
AD8139
–30
–30
VO, dm = 2.0V p-p
–50
–50
–60
–60
RF = 200Ω
RF = 500Ω
–90
–100
–110
–70
–80
–90
RF = 200Ω
–100
–110
RF = 1kΩ
–130
0.1
–120
1
10
100
FREQUENCY (MHz)
1
10
Figure 28. Third Harmonic Distortion vs. Frequency and RF
–80
–80
FC = 2MHz
VS = ±5V
–90
–90
VS = +5V
VS = +5V
–100
DISTORTION (dBc)
–110
–120
–130
–130
–140
1
2
3
4
5
6
7
8
–150
04679-022
0
VO, dm (V p-p)
–60
1
2
3
–60
5
6
7
8
VO, dm = 2V p-p
FC = 2MHz
–70
–80
DISTORTION (dBc)
–80
–90
SECOND HARMONIC
–100
–110
–120
–90
SECOND HARMONIC
–100
–110
–120
THIRD HARMONIC
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VOCM (V)
5.0
04679-023
THIRD HARMONIC
–130
4
Figure 29. Third Harmonic Distortion vs. Output Amplitude
VO, dm = 2V p-p
FC = 2MHz
–70
0
VO, dm (V p-p)
Figure 26. Second Harmonic Distortion vs. Output Amplitude
DISTORTION (dBc)
–120
04679-025
–140
VS = ±5V
–110
Figure 27. Harmonic Distortion vs. VOCM, VS = +5 V
–130
–5
–4
–3
–2
–1
0
1
2
3
4
VOCM (V)
Figure 30. Harmonic Distortion vs. VOCM, VS = ±5 V
Rev. B | Page 12 of 24
5
04679-026
DISTORTION (dBc)
–100
–150
100
FREQUENCY (MHz)
Figure 25. Second Harmonic Distortion vs. Frequency and RF
FC = 2MHz
RF = 500Ω
–130
0.1
04679-021
–120
RF = 1kΩ
04679-024
–70
–80
VO, dm = 2.0V p-p
–40
DISTORTION (dBc)
DISTORTION (dBc)
–40
AD8139
100
2.5
VO, dm = 100mV p-p
CF = 0pF
75
CF = 2pF
1.5
CF = 0pF
(CF = 0pF,
VS = ±5V)
25
CF = 0pF
1.0
VO, dm
(CF = 2pF, VS = ±5V)
VO, dm (V)
50
VO, dm (V)
4V p-p
2.0
0
CF = 2pF
0.5
2V p-p
0
–0.5
–25
–1.0
–50
–1.5
–75
5ns/DIV
04679-043
–100
TIME (ns)
–2.5
TIME (ns)
Figure 31. Small Signal Transient Response for Various CF
0.100
Figure 34. Large Signal Transient Response for Various CF
1.5
RS = 31.6Ω
CL, dm = 30pF
0.075
04679-044
–2.0
5ns/DIV
RS = 63.4Ω
CL, dm = 15pF
1.0
0.050
0.5
RS = 63.4Ω
CL, dm = 15pF
VO, dm (V)
VO, dm (V)
0.025
0
–0.025
RS = 31.6Ω
CL, dm = 30pF
0
–0.5
–0.050
–1.0
–0.075
TIME (ns)
Figure 35. Large Signal Transient Response for Capacitive Loads
AMPLITUDE (V)
NORMALIZED OUTPUT (dBc)
1.5
CF = 2pF
VO, dm = 2.0V p-p
1.0
400
0.5
200
0
0
ERROR
–0.5
–200
VO, dm
FREQUENCY (MHz)
04679-027
–1.0
9.95 10.05 10.15 10.25 10.35 10.45 10.55
600
–1.5
–400
35ns/DIV
VIN
–600
TIME (ns)
Figure 36. Settling Time (0.01%)
Figure 33. Intermodulation Distortion
Rev. B | Page 13 of 24
04679-034
Figure 32. Small Signal Transient Response for Capacitive Loads
5
0 VO, dm = 2V p-p
–5 FC1 = 10MHz
–10 FC2 = 10.1MHz
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
9.55 9.65 9.75 9.85
04679-065
TIME (ns)
5ns/DIV
–1.5
ERROR (µV) 1DIV = 0.01%
–0.100
04679-064
5ns/DIV
AD8139
6
±5V
5
4
1.0
–0.5
VO, cm = 2V p-p
VIN, dm = 0V
1
0
–2
–5
–7
–9
10
0
VIN, cm = 0.2V p-p
INPUT CMRR = ΔVO, cm/ΔVIN, cm
VO, cm = 0.2V p-p
VOCM CMRR = ΔVO, dm/ΔVO, cm
–10
–20
–20
–30
–30
RF = RG = 10kΩ
–50
–60
RF = RG = 200Ω
–40
–50
–60
–70
10
100
500
FREQUENCY (MHz)
–90
04679-066
1
1
10
500
Figure 41. VOCM CMRR vs. Frequency
Figure 38. CMRR vs. Frequency
100
VOCM VOLTAGE NOISE (nV/ Hz)
100
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
1G
04679-079
10
1
10
100
FREQUENCY (MHz)
04679-045
–80
–80
INPUT VOLTAGE NOISE (nV/ Hz)
1000
Figure 40. VOCM Frequency Response for Various Supplies
VOCM CMRR (dB)
CMRR (dB)
100
FREQUENCY (MHz)
Figure 37. VOCM Large Signal Transient Response
–70
VS = +5V
–8
04679-069
TIME (ns)
–40
VS = ±5V
VO, cm = 2.0V p-p
–4
–6
–1.5
–90
VS = ±5V
–3
10ns/DIV
–10
VO, cm = 0.1V p-p
–1
10
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
Figure 42. VOCM Voltage Noise vs. Frequency
Figure 39. Input Voltage Noise vs. Frequency
Rev. B | Page 14 of 24
1G
04679-080
VOCM (V)
0
–1.0
2
CLOSED-LOOP GAIN (dB)
+5V
0.5
0
VS = +5V
3
04679-038
1.5
AD8139
0
14
2 × VIN, dm
G=2
12
10
–20
8
–30
6
VOLTAGE (V)
PSRR (dB)
RL, dm = 1kΩ
–10 PSRR = ΔVO, dm/ΔVS
–40
–PSRR
–50
+PSRR
–60
–70
VO, dm
4
2
0
–2
–4
–6
–8
–80
–90
–12
1
10
100
500
FREQUENCY (MHz)
50ns/DIV
–14
04679-047
–100
TIME (ns)
Figure 46. Overdrive Recovery
Figure 43. PSRR vs. Frequency
0
100
VS = +5V
VO, dm = 1V p-p
OUTPUT BALANCE = ΔVO, cm/ΔVO, dm
–10
10
OUTPUT BALANCE (dB)
OUTPUT IMPEDANCE (Ω)
04679-046
–10
VS = ±5V
1
0.1
–20
–30
–40
–50
–60
10
100
1000
FREQUENCY (MHz)
–80
1
10
500
Figure 47. Output Balance vs. Frequency
Figure 44. Single-Ended Output Impedance vs. Frequency
300
700
600
500
300
VOP SWING FROM RAIL (mV)
400
VS+ – VOP
200
100
0
VS = ±5V
VS = +5V
–100
–200
VON – VS–
–300
–400
250
–50
VS = ±5V
G = 1 (RF = RG = 200Ω)
RL, dm = 1kΩ
–100
VS+ – VOP
200
–150
150
–200
VON – VS–
100
–250
–500
–700
100
1k
RESISTIVE LOAD (Ω)
10k
50
–40
–20
0
20
40
60
80
100
120
–300
TEMPERATURE (°C)
Figure 48. Output Saturation Voltage vs. Temperature
Figure 45. Output Saturation Voltage vs. Output Load
Rev. B | Page 15 of 24
04679-077
–600
04679-068
SINGLE-ENDED OUTPUT SWING FROM RAIL (mV)
100
FREQUENCY (MHz)
VON SWING FROM RAIL (mV)
1
04679-028
0.01
0.1
04679-067
–70
AD8139
170
3.0
26
VS = ±5V
IBIAS
2.0
120
1.5
95
OFFSET CURRENT (nA)
145
SUPPLY CURRENT (mA)
25
2.5
24
23
VS = +5V
22
–20
0
20
40
60
80
100
120
70
20
–40
04679-062
TEMPERATURE (°C)
–20
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 49. Input Bias and Offset Current vs. Temperature
Figure 52. Supply Current vs. Temperature
300
10
600
8
VOS, cm
6
250
400
200
200
VS = ±5V
4
VS = +5V
2
VOS, dm (µV)
INPUT BIAS CURRENT (µA)
0
0
–2
–4
–6
150
0
VOS, dm
100
–200
50
–400
VOS, cm (µV)
1.0
–40
04679-060
21
–3
–2
–1
0
1
2
3
4
5
VACM (V)
0
–40
–20
40
60
80
100
120
–600
TEMPERATURE (°C)
5
50
4
45
VS = ±2.5V
COUNT = 350
MEAN = –50µV
STD DEV = 100µV
40
35
2
FREQUENCY
VS = ±5V
1
0
–1
30
25
20
–2
15
–3
10
–4
5
–3
–2
–1
0
1
2
3
VOCM (V)
4
5
Figure 51. VOUT, cm vs. VOCM Input Voltage
–500
–450
–400
–350
–300
–250
–200
–150
–100
–50
0
50
100
150
200
250
300
350
400
450
500
0
–4
04679-048
–5
–5
20
Figure 53. Offset Voltage vs. Temperature
Figure 50. Input Bias Current vs.
Input Common-Mode Voltage
3
0
04679-061
–4
VOS, dm (µV)
Figure 54. VOS, dm Distribution
Rev. B | Page 16 of 24
04679-071
–10
–5
04679-073
–8
VOUT, cm (V)
INPUT BIAS CURRENT (µA)
IOS
AD8139
1.7
6
1.6
4
VOCM BIAS CURRENT (µA)
VOCM BIAS CURRENT (µA)
1.5
1.4
1.3
1.2
1.1
1.0
0.9
VS = ±5V
VS = +5V
2
0
–2
–4
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
–6
–5
04679-063
0.7
–40
–4
–3
–2
–1
0
1
Figure 55. VOCM Bias Current vs. Temperature
RF
50Ω
CF
RG = 200Ω
VOCM
RL, dm = 1kΩ
AD8139
RG = 200Ω
50Ω
–
VO, dm
+
CF
04679-072
60.4Ω
60.4Ω
TEST
SIGNAL
SOURCE
RF
Figure 57. Basic Test Circuit
RF = 200Ω
TEST
SIGNAL
SOURCE
60.4Ω
50Ω
RS
RG = 200Ω
60.4Ω
VOCM
CL, dm
AD8139
RG = 200Ω
RS
RF = 200Ω
Figure 58. Capacitive Load Test Circuit, G = +1
Rev. B | Page 17 of 24
–
RL, dm VO, dm
+
04679-075
50Ω
VTEST
3
4
Figure 56. VOCM Bias Current vs. VOCM Input Voltage
TEST CIRCUITS
VTEST
2
VOCM (V)
5
04679-074
0.8
AD8139
THEORY OF OPERATION
The AD8139 is a high speed, low noise differential amplifier
fabricated on the Analog Devices second-generation eXtra Fast
Complementary Bipolar (XFCB) process. It is designed to
provide two closely balanced differential outputs in response to
either differential or single-ended input signals. Differential
gain is set by external resistors, similar to traditional voltagefeedback operational amplifiers. The common-mode level of
the output voltage is set by a voltage at the VOCM pin and is
independent of the input common-mode voltage. The AD8139
has an H-bridge input stage for high slew rate, low noise, and
low distortion operation and rail-to-rail output stages that
provide maximum dynamic output range. This set of features
allows for convenient single-ended-to-differential conversion, a
common need to take advantage of modern high resolution
ADCs with differential inputs.
TYPICAL CONNECTION AND DEFINITION OF
TERMS
Figure 59 shows a typical connection for the AD8139, using
matched external RF/RG networks. The differential input
terminals of the AD8139, VAP and VAN, are used as summing
junctions. An external reference voltage applied to the VOCM
terminal sets the output common-mode voltage. The two
output terminals, VOP and VON, move in opposite directions in a
balanced fashion in response to an input signal.
outputs of identical amplitude and exactly 180° out of phase. The
output balance performance does not require tightly matched
external components, nor does it require that the feedback factors
of each loop be equal to each other. Low frequency output balance
is limited ultimately by the mismatch of an on-chip voltage divider,
which is trimmed for optimum performance.
Output balance is measured by placing a well-matched resistor
divider across the differential voltage outputs and comparing
the signal at the midpoint of the divider with the magnitude of
the differential output. By this definition, output balance is
equal to the magnitude of the change in output common-mode
voltage divided by the magnitude of the change in output
differential-mode voltage:
VAN = VAP
VOCM
VIN
RG
VON
+
AD8139
VAN
–
RL, dm VO, dm
VOP
–
VOP = VOCM +
+
RF
VON = VOCM −
Figure 59. Typical Connection
VIN
The differential output voltage is defined as
VO, dm = VOP − VON
VOP + VON
2
VO, dm
(6)
2
RG
RF
10pF
(1)
+
Common-mode voltage is the average of two voltages. The
output common-mode voltage is defined as
VO, cm =
(5)
2
and
04679-050
CF
VO, dm
GO
VOP
500Ω
VAN
VAP
(2)
Output Balance
MIDSUPPLY
GCM
GDIFF
+
Output balance is a measure of how well VOP and VON are
matched in amplitude and how precisely they are 180° out of
phase with each other. It is the internal common-mode feedback
loop that forces the signal component of the output common-mode
towards zero, resulting in the near perfectly balanced differential
500Ω
VOCM
GO
VON
10pF
VIP
Rev. B | Page 18 of 24
RG
RF
Figure 60. Block Diagram
04679-051
VAP
(4)
The common-mode feedback loop drives the output commonmode voltage, sampled at the midpoint of the two 500 Ω resistors,
to equal the voltage set at the VOCM terminal. This ensures that
RF
RG
(3)
ΔVO, dm
The block diagram of the AD8139 in Figure 60 shows the
external differential feedback loop (RF/RG networks and the
differential input transconductance amplifier, GDIFF) and the
internal common-mode feedback loop (voltage divider across
VOP and VON and the common-mode input transconductance
amplifier, GCM). The differential negative feedback drives the
voltages at the summing junctions VAN and VAP to be essentially
equal to each other.
CF
VIP
ΔVO, cm
Output Balance =
AD8139
APPLICATIONS
Voltage Gain
ESTIMATING NOISE, GAIN, AND BANDWIDTH
WITH MATCHED FEEDBACK NETWORKS
Estimating Output Noise Voltage
The total output noise is calculated as the root-sum-squared
total of several statistically independent sources. Because the
sources are statistically independent, the contributions of each
must be individually included in the root-sum-square calculation.
Table 6 lists recommended resistor values and estimates of
bandwidth and output differential voltage noise for various
closed-loop gains. For most applications, 1% resistors are
sufficient.
Table 6. Recommended Values of Gain-Setting Resistors and
Voltage Noise for Various Closed-Loop Gains
Gain
1
2
5
10
RG (Ω)
200
200
200
200
RF (Ω)
200
400
1k
2k
3 dB
Bandwidth (MHz)
400
160
53
26
Total Output
Noise (nV/√Hz)
5.8
9.3
19.7
37
The differential output voltage noise contains contributions
from the input voltage noise and input current noise of the
AD8139 as well as those from the external feedback networks.
The contribution from the input voltage noise spectral density
is computed as
⎛ R ⎞
Vo_n1 = vn ⎜⎜1 + F ⎟⎟ , or equivalently, vn/β
⎝ RG ⎠
(7)
The contribution from the input current noise of each input is
computed as
(8)
where in is defined as the input noise current of one input.
Each input needs to be treated separately because the two
input currents are statistically independent processes.
⎞
⎟
⎟
⎠
⎡ RG ⎤
VAN = VAP = VOP ⎢
⎥
⎣ RF + RG ⎦
(12)
VOP − VON = VO, dm =
RF
V
RG i
(13)
An inverting configuration with the same gain magnitude can
be implemented by simply applying the input signal to VIN and
setting VIP = 0. For a balanced differential input, the gain from
VIN, dm to VO, dm is also equal to RF/RG, where VIN, dm = VIP − VIN.
Feedback Factor Notation
When working with differential amplifiers, it is convenient to
introduce the feedback factor β, which is defined as
β=
RG
RF + RG
(14)
This notation is consistent with conventional feedback analysis
and is very useful, particularly when the two feedback loops are
not matched.
The linear range of the VAN and VAP terminals extends to within
approximately 1 V of either supply rail. Because VAN and VAP are
essentially equal to each other, they are both equal to the input
common-mode voltage of the amplifier. Their range is indicated
in the Specifications tables as input common-mode range. The
voltage at VAN and VAP for the connection diagram in Figure 59
can be expressed as
VAN = VAP = VACM =
(V + VIN ) ⎞ ⎛ RG
⎞
⎛ RF
× VOCM ⎟
× IP
⎜
⎟+⎜
R
R
2
R
R
+
+
G
G
⎠
⎝ F
⎠ ⎝ F
(9)
This result can be intuitively viewed as the thermal noise of
each RG multiplied by the magnitude of the differential gain.
(15)
where VACM is the common-mode voltage present at the
amplifier input terminals.
Using the β notation, Equation 15 can be written as follows:
VACM = βVOCM + (1 − β)VICM
The contribution from each RF is computed as
Vo_n4 = √4kTRF
(11)
Solving the above two equations and setting VIP to Vi gives the
gain relationship for VO, dm/Vi.
The contribution from each RG is computed as
⎛R
Vo_n3 = 4kTRG ⎜⎜ F
⎝ RG
VIP − VAP VAP − VON
=
RG
RF
Input Common-Mode Voltage
where vn is defined as the input-referred differential voltage
noise. This equation is the same as that of traditional op amps.
Vo_n2 = in (RF)
The behavior of the node voltages of the single-ended-todifferential output topology can be deduced from the previous
definitions. Referring to Figure 59, (CF = 0) and setting VIN = 0,
one can write
(10)
(16)
or equivalently,
VACM = VICM + β(VOCM − VICM)
where VICM is the common-mode voltage of the input signal,
that is, VICM = VIP + VIN/2.
Rev. B | Page 19 of 24
(17)
AD8139
The input impedance of a conventional inverting op amp
configuration is simply RG, but it is higher in Equation 19
because a fraction of the differential output voltage appears at
the summing junctions, VAN and VAP. This voltage partially
bootstraps the voltage across the input resistor RG, leading to
the increased input resistance.
For proper operation, the voltages at VAN and VAP must stay
within their respective linear ranges.
Calculating Input Impedance
The input impedance of the circuit in Figure 59 depends on
whether the amplifier is being driven by a single-ended or a
differential signal source. For balanced differential input
signals, the differential input impedance (RIN, dm) is simply
RIN, dm = 2RG
Input Common-Mode Swing Considerations
In some single-ended-to-differential applications, when using a
single-supply voltage, attention must be paid to the swing of the
input common-mode voltage, VACM.
(18)
For a single-ended signal (for example, when VIN is grounded
and the input signal drives VIP), the input impedance becomes
RG
RF
1−
2(RG + RF )
Consider the case in Figure 61, where VIN is 5 V p-p swinging
about a baseline at ground, and VREF is connected to ground.
(19)
The circuit has a differential gain of 1.6 and β = 0.38. VICM has
an amplitude of 2.5 V p-p and is swinging about ground. Using
the results in Equation 16, the common-mode voltage at the
inputs of the AD8139, VACM, is a 1.5 V p-p signal swinging
about a baseline of 0.95 V. The maximum negative excursion
of VACM in this case is 0.2 V, which exceeds the lower input
common-mode voltage limit.
5V
0.1µF
+2.5V
GND
–2.5V
2.5V
VREF
3
200Ω
8
VOCM
2
1
VIN
VACM
WITH VREF = 0
2.7nF
AVDD
DVDD
IN–
AD8139
–
0.1µF
15Ω
5
+
6
200Ω
20Ω
0.1µF
324Ω
AD7674
4
324Ω
15Ω
2.7nF
IN+
DGND AGND REFGND REF REFBUFIN PDBUF
47µF
+1.7V
+0.95V
+0.2V
0.1µF
Figure 61. AD8139 Driving AD7674, 18-Bit, 800 kSPS ADC
Rev. B | Page 20 of 24
ADR431
2.5V
REFERENCE
04679-052
RIN =
AD8139
One way to avoid the input common-mode swing limitation is
to bias VIN and VREF at midsupply. In this case, VIN is 5 V p-p
swinging about a baseline at 2.5 V, and VREF is connected to a
low-Z 2.5 V source. VICM now has an amplitude of 2.5 V p-p and
is swinging about 2.5 V. Using the results in Equation 17, VACM
is calculated to be equal to VICM because VOCM = VICM. Therefore,
VACM swings from 1.25 V to 3.75 V, which is well within the
input common-mode voltage limits of the AD8139. Another
benefit seen in this example is that because VOCM = VACM = VICM
no wasted common-mode current flows. Figure 62 illustrates
how to provide the low-Z bias voltage. For situations that do not
require a precise reference, a simple voltage divider suffices to
develop the input voltage to the buffer.
VIN
0V TO 5V
324Ω
200Ω
8
VOCM
2
⎛ R + RG
Vo _ e1 = VIO ⎜⎜ F
⎝ RG
⎛ R + RG
Vo _ e2 = I IO ⎜⎜ F
⎝ RG
AD8139
–
4
200Ω
⎞
⎟ = I IO (RF )
⎟
⎠
+
(22)
The third error voltage is calculated as
TO AD7674 REFBUFIN
AD8031
ADR431
2.5V
REFERENCE
04679-053
Figure 62. Low-Z 2.5 V Buffer
The total differential offset error is the sum of these three error
sources.
Other Impact of Mismatches in the Feedback Networks
Another way to avoid the input common-mode swing limitation is
to use dual power supplies on the AD8139. In this case, the
biasing circuitry is not required.
Bandwidth vs. Closed-Loop Gain
The 3 dB bandwidth of the AD8139 decreases proportionally
to increasing closed-loop gain in the same way as a traditional
voltage feedback operational amplifier. For closed-loop gains
greater than 4, the bandwidth obtained for a specific gain can be
estimated as
RG
× (300 MHz)
RG + RF
(23)
where Δenr is the fractional mismatch between the two
feedback resistors.
–
f − 3 dB,VOUT , dm =
⎞⎛ RG RF
⎟⎜
⎟⎜ R + R
G
⎠⎝ F
Vo_e3 = Δenr × (VICM − VOCM)
0.1µF
(21)
where IIO is defined as the offset between the two input bias
currents.
324Ω
5V
0.1µF
⎞
⎟ , or equivalently as VIO/β
⎟
⎠
The second error is calculated as
5
+
6
10µF
The first output error component is calculated as
3
1
+
Primary differential output offset errors in the AD8139 are due
to three major components: the input offset voltage, the offset
between the VAN and VAP input currents interacting with the
feedback network resistances, and the offset produced by the dc
voltage difference between the input and output common-mode
voltages in conjunction with matching errors in the feedback
network.
where VIO is the input offset voltage. The input offset voltage of the
AD8139 is laser trimmed and guaranteed to be less than 500 μV.
5V
0.1µF
Estimating DC Errors
(20)
or equivalently, β(300 MHz).
The internal common-mode feedback network still forces the
output voltages to remain balanced, even when the RF/RG feedback
networks are mismatched. However, the mismatch will cause a
gain error proportional to the feedback network mismatch.
Ratio-matching errors in the external resistors degrade the
ability to reject common-mode signals at the VAN and VIN input
terminals, much the same as with a four-resistor difference
amplifier made from a conventional op amp. Ratio-matching
errors also produce a differential output component that is
equal to the VOCM input voltage times the difference between the
feedback factors (βs). In most applications using 1% resistors,
this component amounts to a differential dc offset at the output
that is small enough to be ignored.
This estimate assumes a minimum 90° phase margin for the
amplifier loop, which is a condition approached for gains greater
than 4. Lower gains show more bandwidth than predicted by
the equation due to the peaking produced by the lower
phase margin.
Rev. B | Page 21 of 24
AD8139
Driving a Capacitive Load
5
RS = 30.1Ω
4
CL = 15pF
3
2
1
0
–1
–2
RS = 60.4Ω
–3
CL = 15pF
–4
–5
–6
–7
RS = 60.4Ω
–8
CL = 5pF
–9
VS = ±5V
–10
V
= 0.1V p-p
–11 GO,= dm
1 (RF = RG = 200Ω)
–12 R
L, dm = 1kΩ
–13
10M
100M
Figure 64 shows the AD8139 in a unity-gain configuration
driving the AD6645, which is a 14-bit, high speed ADC, and
with the following discussion, provides a good example of how
to provide a proper termination in a 50 Ω environment.
RS = 30.1Ω
CL = 5pF
RS = 0Ω
CL, dm = 0pF
FREQUENCY (Hz)
1G
04679-076
CLOSED LOOP GAIN (dB)
A purely capacitive load reacts with the bondwire and pin
inductance of the AD8139, resulting in high frequency ringing
in the transient response and loss of phase margin. One way to
minimize this effect is to place a small resistor in series with
each output to buffer the load capacitance (see Figure 58 and
Figure 63). The resistor and load capacitance form a first-order,
low-pass filter; therefore, the resistor value should be as small as
possible. In some cases, the ADCs require small series resistors
to be added on their inputs.
The input resistance presented by the AD8139 input circuitry is
seen in parallel with the termination resistor, and its loading
effect must be taken into account. The Thevenin equivalent
circuit of the driver, its source resistance, and the termination
resistance must all be included in the calculation as well. An
exact solution to the problem requires the solution of several
simultaneous algebraic equations and is beyond the scope of
this data sheet. An iterative solution is also possible and simpler,
especially considering the fact that standard 1% resistor values
are generally used.
Figure 63. Frequency Response for
Various Capacitive Load and Series Resistance
The Typical Performance Characteristics that illustrate transient
response vs. the capacitive load were generated using series
resistors in each output and a differential capacitive load.
Layout Considerations
Standard high speed PCB layout practices should be adhered to
when designing with the AD8139. A solid ground plane is
recommended, and good wideband power supply decoupling
networks should be placed as close as possible to the supply pins.
To minimize stray capacitance at the summing nodes, the
copper in all layers under all traces and pads that connect to
the summing nodes should be removed. Small amounts of stray
summing-node capacitance cause peaking in the frequency
response, and large amounts can cause instability. If some stray
summing-node capacitance is unavoidable, its effects can be
compensated for by placing small capacitors across the feedback
resistors.
Terminating a Single-Ended Input
Controlled impedance interconnections are used in most
high speed signal applications, and they require at least one
line termination. In analog applications, a matched resistive
termination is generally placed at the load end of the line. This
section deals with how to properly terminate a single-ended
input to the AD8139.
The termination resistor, RT, in parallel with the 268 Ω input
resistance of the AD8139 circuit (calculated using Equation 19),
yields an overall input resistance of 50 Ω that is seen by the
signal source. To have matched feedback loops, each loop must
have the same RG if they have the same RF. In the input (upper)
loop, RG is equal to the 200 Ω resistor in series with the (+)
input plus the parallel combination of RT and the source
resistance of 50 Ω. In the upper loop, RG is therefore equal to
228 Ω. The closest standard 1% value to 228 Ω is 226 Ω and is
used for RG in the lower loop. Greater accuracy could be
achieved by using two resistors in series to obtain a resistance
closer to 228 Ω.
Things get more complicated when it comes to determining
the feedback resistor values. The amplitude of the signal source
generator VS is two times the amplitude of its output signal
when terminated in 50 Ω. Therefore, a 2 V p-p terminated
amplitude is produced by a 4 V p-p amplitude from VS. The
Thevenin equivalent circuit of the signal source and RT must
be used when calculating the closed-loop gain, because in
the upper loop, RG is split between the 200 Ω resistor and
the Thevenin resistance looking back toward the source. The
Thevenin voltage of the signal source is greater than the signal
source output voltage when terminated in 50 Ω because RT
must always be greater than 50 Ω. In this case, RT is 61.9 Ω and
the Thevenin voltage and resistance are 2.2 V p-p and 28 Ω,
respectively. Now the upper input branch can be viewed as a
2.2 V p-p source in series with 228 Ω. Because this is a unitygain application, a 2 V p-p differential output is required, and
RF must therefore be 228 × (2/2.2) = 206 Ω. The closest
standard value to this is 205 Ω.
When generating the Typical Performance Characteristics data,
the measurements were calibrated to take the effects of the
terminations on the closed-loop gain into account.
Rev. B | Page 22 of 24
AD8139
Exposed Paddle (EP)
Because this is a single-ended-to-differential application on a
single supply, the input common-mode voltage swing must be
checked. From Figure 64, β = 0.52, VOCM = 2.4 V, and VICM is
1.1 V p-p swinging about ground. Using Equation 16, VACM is
calculated to be 0.53 V p-p swinging about a baseline of 1.25 V,
and the minimum negative excursion is approximately 1 V.
The 8-lead SOIC and the 8-lead LFCSP have an exposed paddle
on the bottom of the package. To achieve the specified thermal
resistance, the exposed paddle must be soldered to one of the
PCB planes. The exposed paddle mounting pad should contain
several thermal vias within it to ensure a low thermal path to
the plane.
5V
3.3V
0.01µF
0.01µF
0.01µF
205Ω
VS
SIGNAL
SOURCE
2V p-p
RT
61.9Ω
200Ω
8
VOCM
2
1
226Ω
25Ω
AIN
AVCC
5
+
AD8139
–
6
DVCC
AD6645
4
AIN
205Ω
25Ω
GND C1
C2
0.1µF
2.4V
Figure 64. AD8139 Driving AD6645, 14-Bit, 80 MSPS/105 MSPS ADC
Rev. B | Page 23 of 24
VREF
0.1µF
04679-054
50Ω
3
AD8139
OUTLINE DIMENSIONS
5.00 (0.197)
4.90 (0.193)
4.80 (0.189)
4.00 (0.157)
3.90 (0.154)
3.80 (0.150)
8
5
TOP VIEW
1
4
2.29 (0.090)
2.29 (0.090)
6.20 (0.244)
6.00 (0.236)
5.80 (0.228)
BOTTOM VIEW
1.27 (0.05)
BSC
(PINS UP)
0.50 (0.020)
0.25 (0.010)
1.65 (0.065)
1.25 (0.049)
1.75 (0.069)
1.35 (0.053)
0.10 (0.004)
MAX
COPLANARITY
0.10
0.51 (0.020)
0.31 (0.012)
SEATING
PLANE
0.25 (0.0098)
0.17 (0.0067)
45°
1.27 (0.050)
0.40 (0.016)
8°
0°
COMPLIANT TO JEDEC STANDARDS MS-012-A A
060506-A
CONTROLLING DIMENSIONS ARE IN MILLIMETER; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 65. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP]
Narrow Body (RD-8-1)—Dimensions shown in millimeters and (inches)
3.25
3.00 SQ
2.75
0.60 MAX
5
TOP
VIEW
2.95
2.75 SQ
2.55
8
(BOTTOM VIEW)
4
12° MAX
0.90 MAX
0.85 NOM
SEATING
PLANE
0.50
0.40
0.30
0.70 MAX
0.65 TYP
1.60
1.45
1.30
EXPOSED
PAD
1
1.89
1.74
1.59
PIN 1
INDICATOR
0.05 MAX
0.01 NOM
0.30
0.23
0.18
0.20 REF
061507-B
PIN 1
INDICATOR
0.50
BSC
0.60 MAX
Figure 66. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm × 3 mm Body, Very Thin, Dual Lead (CP-8-2)—Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8139ARD
AD8139ARD-REEL
AD8139ARD-REEL7
AD8139ARDZ 1
AD8139ARDZ-REEL1
AD8139ARDZ-REEL71
AD8139ACP-R2
AD8139ACP-REEL
AD8139ACP-REEL7
AD8139ACPZ-R21
AD8139ACPZ-REEL1
AD8139ACPZ-REEL71
1
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
8-Lead Small Outline Package with Exposed Pad (SOIC_N_EP)
8-Lead Small Outline Package with Exposed Pad (SOIC_N_EP)
8-Lead Small Outline Package with Exposed Pad (SOIC_N_EP)
8-Lead Small Outline Package with Exposed Pad (SOIC_N_EP)
8-Lead Small Outline Package with Exposed Pad (SOIC_N_EP)
8-Lead Small Outline Package with Exposed Pad (SOIC_N_EP)
8-Lead Lead Frame Chip Scale Package (LFCSP_VD)
8-Lead Lead Frame Chip Scale Package (LFCSP_VD)
8-Lead Lead Frame Chip Scale Package (LFCSP_VD)
8-Lead Lead Frame Chip Scale Package (LFCSP_VD)
8-Lead Lead Frame Chip Scale Package (LFCSP_VD)
8-Lead Lead Frame Chip Scale Package (LFCSP_VD)
Z = RoHS Compliant Part, # denotes RoHS product may be top or bottom marked.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04679-0-10/07(B)
Rev. B | Page 24 of 24
Package
Option
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
Branding
HEB
HEB
HEB
HEB#
HEB#
HEB#