September 2006 Advance Information AS7C1025C ® 5V 128K X 8 CMOS SRAM (Center power and ground) Features • Industrial (-40o to 85oC) temperature. • Organization: 131,072 x 8 bits • High speed - 12 ns address access time - 6 ns output enable access time • Low power consumption via chip deselect • Easy memory expansion with CE, OE inputs • Center power and ground • TTL/LVTTL-compatible, three-state I/O • JEDEC-standard package - 32-pin, 400 mil SOJ • ESD protection ≥ 2000 volts Pin arrangement Logic block diagram GND 131,072 x 8 Array (1,048,576) I/O7 Sense amp A0 A1 A2 A3 A4 A5 A6 A7 A8 Address decoder Input buffer I/O0 Control circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 GND VCC I/O5 I/O4 A12 A11 A10 A9 A8 WE OE CE A9 A10 A11 A12 A13 A14 A15 A16 Address decoder A0 A1 A2 A3 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A4 A5 A6 A7 AS7C1025C 32-pin SOJ (400 mil) VCC 12/5/06, v. 1.0 Alliance Memory P. 1 of 9 Copyright © Alliance Memory. All rights reserved. AS7C1025C ® Functional description The AS7C1025C is a 5V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,072 x 8 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 12 ns with output enable access times (tOE) of 6 ns are ideal for highperformance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems. When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1). A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C1025C is packaged in common industry standard packages. Absolute maximum ratings Symbol Min Max Unit Voltage on VCC relative to GND Parameter Vt1 –0.50 +7.0 V Voltage on any pin relative to GND Vt2 –0.50 VCC + 0.5 V Power dissipation PD – 1.25 W Storage temperature (plastic) Tstg –55 +125 oC Ambient temperature with VCC applied Tbias –55 +125 o DC current into outputs (low) IOUT – 50 C mA Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE Data Mode H X X High Z Standby (ISB, ISB1) L H H High Z Output disable (ICC) L H L DOUT Read (ICC) L L X DIN Write (ICC) Key: X = don’t care, L = low, H = high. 12/5/06, v. 1.0 Alliance Memory P. 2 of 9 AS7C1025C ® Recommended operating conditions Parameter Symbol Min Nominal Max Unit VCC 4.5 5.0 5.5 V Supply voltage Input voltage VIH 2.2 – VCC + 0.5 V VIL –0.5 – 0.8 V TA –40 – 85 oC Ambient operating temperature (Industrial) Notes: VIL min = -1.0V for pulse width less than 5ns, once per cycle. VIH max = VCC+2.0V for pulse width less than 5ns, once per cycle. DC operating characteristics (over the operating range)1 AS7C1025C-12 Min Max Unit Input leakage current Parameter Symbol | ILI | VCC = Max, VIN = GND to VCC – 5 μA Output leakage current | ILO | VCC = Max, CE = VIH, Vout = GND to VCC – 5 μA – 160 mA – 40 mA 10 mA Operating power supply current ICC Standby power supply current1 ISB Test conditions VCC = Max CE ≤ VIL, f = fMax, IOUT = 0 mA VCC = Max CE ≥ VIH, f = fMax VCC = Max ISB1 Output voltage CE ≥ VCC–0.2 V, VIN ≤ 0.2 V or VIN ≥ VCC –0.2 V, f=0 VOL IOL = 8 mA, VCC = Min – 0.4 V VOH IOH = –4 mA, VCC = Min 2.4 – V Capacitance (f = 1 MHz, Ta = 25o C, VCC = NOMINAL)2 Symbol Signals Test conditions Max Unit Input capacitance Parameter CIN A, CE, WE, OE VIN = 3dV 8 pF I/O capacitance CI/O I/O VIN = VOUT = 3dV 8 pF Note: This parameter is guaranteed by device characterization, but is not production tested. 12/5/06, v. 1.0 Alliance Memory P. 3 of 9 AS7C1025C ® Read cycle (over the operating range)3,9 AS7C1025C-12 Symbol Min Max Unit Read cycle time Parameter tRC 12 – ns Notes Address access time tAA – 12 ns 3 Chip enable (CE) access time tACE – 12 ns 3 Output enable (OE) access time tOE – 6 ns Output hold from address change tOH 4 – ns 5 CE low to output in low Z tCLZ 3 – ns 4, 5 CE low to output in high Z tCHZ 0 6 ns 4, 5 OE low to output in low Z tOLZ 0 – ns 4, 5 OE high to output in high Z tOHZ 0 5 ns 4, 5 Power up time tPU 0 – ns 4, 5 Power down time tPD – 12 ns 4, 5 Key to switching waveforms Rising input Falling input Undefined/don’t care Read waveform 1 (address controlled)3,6,7,9 tRC Address tAA tOH DOUT Data valid Read waveform 2 (CE and OE controlled)3,6,8,9 tRC1 CE tOE OE DOUT Supply current 12/5/06, v. 1.0 tOHZ tCHZ tOLZ tACE tCLZ tPU Data valid tPD 50% ICC ISB 50% Alliance Memory P. 4 of 9 AS7C1025C ® Write cycle (over the operating range)11 AS7C1025C-12 Parameter Symbol Min Max Unit Notes Write cycle time tWC 12 – ns Chip enable (CE) to write end tCW 8 – ns Address setup to write end tAW 8 – ns Address setup time tAS 0 – ns Write pulse width tWP 8 – ns Write recovery time tWR 0 – ns Address hold from end of write tAH 0 – ns Data valid to write end tDW 6 – ns Data hold time tDH 0 – ns 4, 5 Write enable to output in high Z tWZ – 5 ns 4, 5 Output active from write end tOW 3 – ns 4, 5 Write waveform 1 (WE controlled)10,11 tWC tAW tWR tAH Address tWP WE tAS tDW DIN tDH Data valid tWZ tOW DOUT 12/5/06, v. 1.0 Alliance Memory P. 5 of 9 AS7C1025C ® Write waveform 2 (CE controlled)10,11 tAW tWC tAH tWR Address tAS tCW CE tWP WE tWZ tDW DIN tDH Data valid DOUT AC test conditions – – – – Output load: see Figure B. Input pulse level: GND to 30 V. See Figure A. Input rise and fall times: 3 ns. See Figure A. Input and output timing reference levels: 1.5 V. +5 V Thevenin equivalent: 480 Ω +3.0V GND 90% 10% 90% 3 ns 10% Figure A: Input pulse DOUT 255 Ω C13 DOUT 168 Ω +1.728 V GND Figure B: 5 V Output load Notes: 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A and B. tCLZ and tCHZ are specified with CL = 5 pF, as in Figure B. Transition is measured ±200 mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is high for read cycle. CE and OE are low for read cycle. Address is valid prior to or coincident with CE transition low. All read cycle timings are referenced from the last valid address to the first transitioning address. N/A All write cycle timings are referenced from the last valid address to the first transitioning address. N/A. C = 30 pF, except all high Z and low Z parameters where C = 5 pF. 12/5/06, v. 1.0 Alliance Memory P. 6 of 9 AS7C1025C ® Package dimensions 32-pin SOJ 400 mil Symbol Min Max 0.146 32-pin SOJ 400 mil A 0.132 A1 0.025 - e A2 0.105 0.115 B 0.026 0.032 D E1 E2 B Pin 1 A A1 c b A2 Seating plane b 0.015 0.020 c 0.007 0.013 D 0.820 0.830 E 0.354 0.378 E1 0.395 0.405 E2 0.435 0.445 e 0.050 BSC E Note: This part is compatible with both pin numbering conventions used by various manufacturers. 12/5/06, v. 1.0 Alliance Memory P. 7 of 9 AS7C1025C ® Ordering Codes Package Volt/Temp 12 ns Plastic SOJ, 400 mil 5V industrial AS7C1025C-12JIN Part numbering system AS7C SRAM prefix 12/5/06, v. 1.0 1025C Device number –XX Access time X Package: J = SOJ 400 mil X X Temperature range N = LEAD FREE I = industrial, -40° PART C to 85° C Alliance Memory P. 8 of 9 AS7C1025C ® ® Alliance Memory, Inc. 1116 South Amphlett San Mateo, CA 94402 Tel: 650-525-3737 Fax: 650-525-0449 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved Part Number: AS7C1025C Document Version: v. 1.0 © Copyright 2003 Alliance Memory, Inc. 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