SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 FEATURES D 105kSPS Data Rate D AC Performance: DESCRIPTION The ADS1271 is a 24-bit, delta-sigma analog-to-digital converter (ADC) with a data rate up to 105kSPS. It offers a unique combination of excellent DC accuracy and outstanding AC performance. The high-order, chopper-stabilized modulator achieves very low drift with low in-band noise. The onboard decimation filter suppresses modulator and signal out-of-band noise. The ADS1271 provides a usable signal bandwidth up to 90% of the Nyquist rate with less than 0.005dB of ripple. 51kHz Bandwidth 109dB SNR (High-Resolution Mode) −108dB THD D DC Accuracy: D D D 1.8µV/°C Offset Drift 2ppm/°C Gain Drift Selectable Operating Modes: High-Speed: 105kSPS Data Rate High-Resolution: 109dB SNR Low-Power: 35mW Dissipation Power-Down Control Digital Filter: Linear Phase Response Passband Ripple: ±0.005dB Stop Band Attenuation: 100dB D Internal Offset Calibration On Command D Selectable SPIt or Frame Sync Serial Interface D Designed for Multichannel Systems: D D D D D Daisy-Chainable Serial Interface Easy Synchronization Simple Pin-Driven Control Modulator Output Option Specified from −40°C to +105°C Analog Supply: 5V Digital Supply: 1.8V to 3.3V APPLICATIONS D Vibration/Modal Analysis D Acoustics D Dynamic Strain Gauges D Pressure Sensors D Test and Measurement Traditionally, industrial delta-sigma ADCs offering good drift performance use digital filters with large passband droop. As a result, they have limited signal bandwidth and are mostly suited for DC measurements. High-resolution ADCs in audio applications offer larger usable bandwidths, but the offset and drift specification are significantly weaker than their industrial counterparts. The ADS1271 combines these converters, allowing high-precision industrial measurement with excellent DC and AC specifications ensured over an extended industrial temperature range. Three operating modes allow for optimization of speed, resolution, and power. A selectable SPI or a frame-sync serial interface provides for convenient interfacing to microcontrollers or DSPs. The output from the modulator is accessible for external digital filter applications. All operations, including internal offset calibration, are controlled directly by pins; there are no registers to program. VREFP VREFN AVDD DVDD Control Logic SYNC/PDWN MODE CLK AINP ∆Σ Modulator Digital Filter Serial Interface AINN AGND DRDY/FSYNC SCLK DOUT DIN FORMAT DGND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola Inc. All other trademarks are the property of their respective owners. Copyright 2004−2007, Texas Instruments Incorporated ! "# $ %& $ " '&(% ) &%$ % "# $' %"% $ ' #$ " * $ $&# $ $ +) &% '% $$ $ % $$ + %& $ " ' # $) www.ti.com www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) ADS1271 UNIT AVDD to AGND −0.3 to +6.0 V DVDD to DGND −0.3 to +3.6 V AGND to DGND Input Current −0.3 to +0.3 V 100, Momentary mA 10, Continuous mA Analog Input to AGND −0.3 to AVDD + 0.3 V Digital Input or Output to DGND −0.3 to DVDD + 0.3 V Maximum Junction Temperature +150 °C Operating Temperature Range −40 to +105 °C Storage Temperature Range −60 to +150 °C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. 2 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or refer to our web site at www.ti.com. www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS All specifications at TA = −40°C to +105°C, AVDD = +5V, DVDD = +1.8V, fCLK = 27MHz, VREFP = 2.5V, and VREFN = 0V, unless otherwise noted. Specified values for ADS1271 and ADS1271B (high-grade version) are the same, except where shown in BOLDFACE type. ADS1271 PARAMETER TEST CONDITIONS MIN TYP ADS1271B MAX MIN AVDD + 0.1 AGND – 0.1 TYP MAX UNITS Analog Inputs Full-scale input voltage (FSR(1)) VIN = (AINP – AINN) Absolute input voltage AINP or AINN to AGND Common-mode input voltage VCM = (AINP + AINN)/2 Differential input impedance ±VREF AGND – 0.1 ±VREF V AVDD + 0.1 V 2.5 2.5 V High-Speed mode 16.4 16.4 kΩ High-Resolution mode 16.4 16.4 kΩ Low-Power mode 32.8 32.8 kΩ DC Performance Resolution No missing codes 24 High-Speed mode Data rate (fDATA) 24 105,469 SPS High-Resolution mode 52,734 52,734 SPS Low-Power mode 52,734 52,734 SPS Integral nonlinearity (INL) High-Speed mode Offset error Differential input, VCM = 2.5V ± 0.0006 Without calibration 0.150 With calibration 1.8 Gain error 0.1 Gain error drift ± 0.0006 ± 0.0015 1 0.150 1 %FSR(1) mV Shorted input 9.0 0.5 µV/_C %FSR(1) 9.0 16 µV, rms 1.8 0.5 0.1 20 2 High-Speed mode 2 ppm/°C High-Resolution mode 6.5 6.5 12 µV, rms Low-Power mode 9.0 9.0 16 µV, rms Common-mode rejection Power-supply rejection ± 0.0015 On the level of the noise Offset drift Noise Bits 105,469 fCM = 60Hz 90 AVDD DVDD f = 60Hz 100 95 110 dB 80 80 dB 80 80 dB AC Performance Signal-to-noise ratio (SNR) (2) High-Speed mode 99 High-Resolution mode (unweighted) Low-Power mode Total harmonic distortion (THD)(3) VIN = 1kHz, −0.5dBFS 106 101 106 dB 109 103 109 dB 106 101 106 −105 Spurious-free dynamic range 0.49 fDATA Stop band attenuation Settling time (latency) (1) (2) (3) (4) (5) 100 dB dB ±0.005 0.453 fDATA −3dB Bandwidth dB −100 −109 ±0.005 Passband Group delay −108 −108 Passband ripple Stop band −95 dB 0.453 fDATA Hz 0.49 fDATA Hz 100 dB High-Speed mode 0.547 fDATA 63.453 fDATA 0.547 fDATA 63.453 fDATA Hz High-Resolution mode 0.547 fDATA 127.453 fDATA 0.547 fDATA 127.453 fDATA Hz Low-Power mode 0.547 fDATA 63.453 fDATA 0.547 fDATA 63.453 fDATA Hz High-Speed and Low-Power modes 38/fDATA 38/fDATA s High-Resolution mode 39/fDATA 39/fDATA s High-Speed and Low-Power modes Complete settling 76/fDATA 76/fDATA s High-Resolution mode Complete settling 78/fDATA 78/fDATA s FSR = full-scale range = 2VREF. Minimum SNR is ensured by the limit of the DC noise specification. THD includes the first nine harmonics of the input signal. MODE and FORMAT pins excluded. See the text for more details on SCLK. 3 www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = −40°C to +105°C, AVDD = +5V, DVDD = +1.8V, fCLK = 27MHz, VREFP = 2.5V, and VREFN = 0V, unless otherwise noted. Specified values for ADS1271 and ADS1271B (high-grade version) are the same, except where shown in BOLDFACE type. ADS1271 PARAMETER TEST CONDITIONS MIN TYP 2.0 2.5 ADS1271B MAX MIN TYP 2.5 MAX UNITS Voltage Reference Inputs Reference input voltage (VREF) 2.65 0.5 2.65 V Negative reference input (VREFN) AGND − 0.1 VREFP − 2.0 AGND − 0.1 VREFP − 0.5 V Positive reference input (VREFP) VREFN + 2.0 AVDD − 0.5 VREFN + 0.5 AVDD + 0.1 Reference Input impedance VREF = VREFP – VREFN V High-Speed mode 4.2 4.2 kΩ High-Resolution mode 4.2 4.2 kΩ Low-Power mode 8.4 8.4 kΩ Digital Input/Output VIH 0.7 DVDD DVDD 0.7 DVDD DVDD V VIL DGND 0.3 DVDD DGND 0.3 DVDD V V VOH IOH = 5mA 0.8 DVDD DVDD 0.8 DVDD DVDD VOL IOL = 5mA DGND 0.2 DVDD DGND 0.2 DVDD V Input leakage(4) 0 < VIN DIGITAL < DVDD ±10 µA 27 MHz Master clock rate (fCLK) 0.1 SPI format Serial clock rate (fSCLK)(5) High-Speed mode Frame-Sync format ±10 High-Resolution mode Low-Power mode 27 0.1 24 fDATA fCLK 24 fDATA fCLK MHz 64 fDATA 64 fDATA 64 fDATA 64 fDATA MHz 128 fDATA 128 fDATA 128 fDATA 128 fDATA MHz 64 fDATA 64 fDATA 64 fDATA 64 fDATA MHz 5.25 4.75 3.6 1.65 Power Supply AVDD 4.75 DVDD 1.65 High-Speed mode AVDD current 17 17 5.25 V 3.6 V 25 mA 17 25 17 25 mA Low-Power mode 6.3 9.5 6.3 9.5 mA T > 85°C 1 70 1 70 µA T ≤ 85°C 1 10 1 10 µA High-Speed mode 3.5 6 3.5 6 mA High-Resolution mode 2.5 5 2.5 5 mA Low-Power mode 1.8 3.5 1.8 3.5 mA 1 70 1 70 µA T > 85°C, DVDD = 3.3V Power-Down mode Power dissipation 25 5 High-Resolution mode Power-Down mode DVDD current 5 1 20 1 20 µA High-Speed mode T ≤ 85°C, DVDD = 3.3V 92 136 92 136 mW High-Resolution mode 90 134 90 134 mW Low-Power mode 35 54 35 54 mW Temperature Range Specified −40 +105 −40 +105 _C Operating −40 +105 −40 +105 _C Storage −60 +150 −60 +150 _C (1) (2) (3) (4) (5) 4 FSR = full-scale range = 2VREF. Minimum SNR is ensured by the limit of the DC noise specification. THD includes the first nine harmonics of the input signal. MODE and FORMAT pins excluded. See the text for more details on SCLK. www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 PIN ASSIGNMENTS PW PACKAGE TSSOP-16 (TOP VIEW) AINP 1 16 VREFP AINN 2 15 VREFN AGND 3 14 DGND AVDD 4 13 DVDD ADS1271 MODE 5 12 CLK FORMAT 6 11 SCLK SYNC/PDWN 7 10 DRDY/FSYNC DIN 8 9 DOUT Terminal Functions PIN NAME NO. FUNCTION AINP 1 Analog Input Positive analog input DESCRIPTION AINN 2 Analog Input Negative analog input AGND 3 Analog Input Analog ground AVDD 4 Analog Input Analog supply MODE 5 Digital Input MODE = 0: MODE = float: MODE = 1: High-Speed mode High-Resolution mode Low-Power mode FORMAT 6 Digital Input FORMAT = 0: FORMAT = float: FORMAT = 1: SPI Modulator output (ADS1271B only) Frame-Sync SYNC/PDWN 7 Digital Input Synchronize/Power-down input, active low DIN 8 Digital Input Data input for daisy-chain operation DOUT 9 Digital Output ADC data output, modulator output (modulator mode) DRDY/FSYNC 10 Digital Input/Output If FORMAT = 0 (SPI), then pin 10 = DRDY output If FORMAT = 1 (Frame-Sync), then pin 10 = FSYNC input SCLK 11 Digital Input Serial clock for ADC data retrieval, modulator clock output (modulator mode) CLK 12 Digital Input Master clock DVDD 13 Digital Input Digital supply DGND 14 Digital Input Digital ground VREFN 15 Analog Input Negative reference input VREFP 16 Analog Input Positive reference input 5 www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 TIMING CHARACTERISTICS: SPI FORMAT tCLK t CPW • • tCPW CLK tCD • tCONV DRDY t SD t DS tS tSPW SCLK tSPW t DDO DOUT Bit 23 (MSB) tDOPD t DOHD Bit 22 t DIST Bit 21 t DIHD DIN TIMING REQUIREMENTS: SPI FORMAT For TA = −40°C to +105°C and DVDD = 1.65V to 3.6V. SYMBOL PARAMETER tCLK tCPW CLK period (1/fCLK) tCONV MIN CLK positive or negative pulse width Conversion period (1/fDATA) TYP 37 MAX 10,000 15 UNIT ns ns High-Speed mode 256 CLK periods High-Resolution mode 512 CLK periods Low-Power mode 512 CLK periods tCD(1) tDS(1) Falling edge of CLK to falling edge of DRDY Falling edge of DRDY to rising edge of first SCLK to retrieve data 5 tDDO(1) tSD(1) Valid DOUT to falling edge of DRDY 0 tS(2) tSPW SCLK period tDOHD(1)(3) tDOPD(1) SCLK falling edge to old DOUT invalid (hold time) tDIST tDIHD(3) New DIN valid to falling edge of SCLK (setup time) 6 ns Old DIN valid to falling edge of SCLK (hold time) 6 ns 8 Falling edge of SCLK to rising edge of DRDY SCLK positive or negative pulse width ns ns ns 8 ns tCLK 12 ns ns 5 SCLK falling edge to new DOUT valid (propagation delay) ns 12 ns (1) Load on DRDY and DOUT = 20pF. (2) For best performance, limit fSCLK/fCLK to ratios of 1, 1/2, 1/4, 1/8, etc. (3) tDOHD (DOUT hold time) and tDIHD (DIN Hold time) are specified under opposite worst case conditions (digital supply voltage and ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4nS. 6 www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 TIMING CHARACTERISTICS: FRAME-SYNC FORMAT t CPW tCLK CLK t CPW tCF tFRAME tFPW tFPW FSYNC tFS tS t SPW tSF SCLK tSPW tDDO DOUT Bit 23 (MSB) tDOPD tDOHD Bit 22 tDIST Bit 21 tDIHD DIN TIMING REQUIREMENTS: FRAME-SYNC FORMAT for TA = −40°C to +105°C and DVDD = 1.65V to 3.6V. SYMBOL PARAMETER tCLK tCPW CLK period (1/fCLK) MIN 37 CLK positive or negative pulse width 15 tCF Falling edge of CLK to falling edge of SCLK Frame period (1/fDATA) MAX 10,000 UNIT ns ns −0.35 tCLK High-Speed mode tFRAME TYP 0.35 tCLK High-Resolution mode 256 256 or 512(1) Low-Power mode 256 or 512(1) ns CLK periods CLK periods CLK periods tFPW tFS FSYNC positive or negative pulse width 1 SCLK periods Rising edge of FSYNC to rising edge of SCLK 5 ns tSF Rising edge of SCLK to rising edge of FSYNC 5 tS SCLK period (SCLK must be continuously running) ns τFRAME/64 τFRAME/128 High-Speed mode High-Resolution mode τFRAME periods τFRAME periods τFRAME/64 Low-Power mode SCLK positive or negative pulse width tDDO(2) Valid DOUT to rising edge of FSYNC 0 ns tDIST tDIHD(3) New DIN valid to falling edge of SCLK (setup time) 6 ns Old DIN valid to falling edge of SCLK (hold time) 6 ns SCLK falling edge to old DOUT invalid (hold time) 0.4tSCLK 5 SCLK falling edge to new DOUT valid (propagation delay) 0.6tSCLK τFRAME periods ns tSPW tDOHD(2)(3) tDOPD(2) ns 12 ns (1) The ADS1271 automatically detects either frame period (only 256 or 512 allowed). (2) Load on DOUT = 20pF. (3) tDOHD (DOUT hold time) and tDIHD (DIN Hold time) are specified under opposite worst case conditions (digital supply voltage and ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4nS. 7 www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS TA = 25°C, AVDD = 5V, DVDD = 1.8V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, unless otherwise noted. OUTPUT SPECTRUM OUTPUT SPECTRUM 0 Amplitude (dB) −40 High−Speed Mode fIN = 1kHz, −0.5dBFS 32,768 Points High−Speed Mode fIN = 1kHz, −20dBFS 32,768 Points −20 −40 Amplitude (dB) −20 0 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 10 100 1k 10k 100k 10 100 Frequency (Hz) Figure 1 Figure 2 OUTPUT SPECTRUM −20 Amplitude (dB) −40 High−Speed Mode Shorted Input 2,097,152 Points 360k −80 −100 −120 −140 300k 240k 180k 120k 60k −160 −180 1 10 100 1k 10k −50 −45 −40 −35 −30 −25 −20 −15 −10 −5 0 5 10 15 20 25 30 35 40 45 50 0 0.1 100k Frequency (Hz) Output (µV) Figure 3 Figure 4 OUTPUT SPECTRUM OUTPUT SPECTRUM 0 0 High−Resolution Mode fIN = 1kHz, −0.5dBFS 32,768 Points −20 −40 Amplitude (dB) Amplitude (dB) −40 −60 −80 −100 High−Resolution Mode fIN = 1kHz, −20dBFS 32,768 Points −60 −80 −100 −120 −120 −140 −140 −160 −160 10 8 100k NOISE HISTOGRAM −60 −20 10k 420k High−Speed Mode Shorted Input 2,097,152 Points Number of Occurrences 0 1k Frequency (Hz) 100 1k 10k 100k 10 100 1k Frequency (Hz) Frequency (Hz) Figure 5 Figure 6 10k 100k www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) TA = 25°C, AVDD = 5V, DVDD = 1.8V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, unless otherwise noted. OUTPUT SPECTRUM 0 High−Resolution Mode Shorted Input 1,048,576 Points −40 180k Number of Occurrences −20 Amplitude (dB) NOISE HISTOGRAM 210k −60 −80 −100 −120 −140 High−Resolution Mode Shorted Input 1,048,576 Points 150k 120k 90k 60k 30k −160 −180 1 10 100 1k 10k −30 −28 −26 −24 −22 −20 −18 −16 −14 −12 −10 −8 −6 −4 −2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 0 0.1 100k Frequency (Hz) Output (µV) Figure 7 Figure 8 OUTPUT SPECTRUM OUTPUT SPECTRUM 0 −20 −40 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 10 100 1k 10k 100k 10 Amplitude (dB) −40 1k Frequency (Hz) Figure 9 Figure 10 10k 100k NOISE HISTOGRAM 200k Low−Power Mode Shorted Input 1,048,576 Points 180k Number of Occurrences −20 100 Frequency (Hz) OUTPUT SPECTRUM 0 Low−Power Mode fIN = 1kHz, −20dBFS 32,768 Points −60 −80 −100 −120 −140 −160 160k Low−Power Mode Shorted Input 1,048,576 Points 140k 120k 100k 80k 60k 40k 20k −180 0 0.1 1 10 100 1k 10k 100k −50 −45 −40 −35 −30 −25 −20 −15 −10 −5 0 5 10 15 20 25 30 35 40 45 50 Amplitude (dB) −40 Low−Power Mode fIN = 1kHz, −0.5dBFS 32,768 Points Amplitude (dB) −20 0 Frequency (Hz) Output (µV) Figure 11 Figure 12 9 www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) TA = 25°C, AVDD = 5V, DVDD = 1.8V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, unless otherwise noted. TOTAL HARMONIC DISTORTION vs FREQUENCY −40 −60 −80 THD+N −100 THD −120 10 THD, THD+N Amplitude (dB) 0 −20 100 1k THD+N −100 −120 THD −100 −80 −60 −40 TOTAL HARMONIC DISTORTION vs FREQUENCY TOTAL HARMONIC DISTORTION vs INPUT LEVEL 0 THD+N −100 THD 100 1k 10k −20 THD −100 −80 −60 −40 TOTAL HARMONIC DISTORTION vs INPUT LEVEL 0 THD, THD+N Amplitude (dB) THD −120 100 1k 10k 100k 0 −120 TOTAL HARMONIC DISTORTION vs FREQUENCY THD+N −20 THD+N −100 Figure 16 −80 0 −80 Figure 15 −60 −20 −60 Input Amplitude (dBFS) −40 0 −40 −140 −120 100k −20 High−Resolution Mode fIN = 1kHz Frequency (Hz) Low−Power Mode VIN = −0.5dBFS 10 −80 Figure 14 −80 −100 −60 Figure 13 −60 −20 −40 Input Amplitude (dBFS) −40 0 High−Speed Mode fIN = 1kHz −140 −120 100k High−Resolution Mode VIN = −0.5dBFS 10 THD, THD+N Amplitude (dB) 10k −20 Frequency (Hz) −120 10 THD, THD+N Amplitude (dB) −20 0 High−Speed Mode VIN = −0.5dBFS THD, THD+N Amplitude (dB) THD, THD+N Amplitude (dB) 0 TOTAL HARMONIC DISTORTION vs INPUT LEVEL −20 Low−Power Mode fIN = 1kHz −40 −60 −80 THD+N −100 −120 −140 −120 THD −100 −80 −60 −40 Frequency (Hz) Input Amplitude (dBFS) Figure 17 Figure 18 www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) TA = 25°C, AVDD = 5V, DVDD = 1.8V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, unless otherwise noted. ABSOLUTE OFFSET DRIFT HISTOGRAM GAIN DRIFT HISTOGRAM 60 30 units, based on 20_ C intervals over the range −40_C to +105_C 30 units, based on 20_C intervals over the range −40_C to +105_C Occurrences (%) 50 Occurrences (%) 15 40 30 20 10 5 10 outliers: T < −20_C 0 0 3 5 7 9 11 13 15 17 19 21 −6.0 −5.5 −5.0 −4.5 −4.0 −3.5 −3.0 −2.5 −2.0 −1.5 −1.0 −0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1 Absolute Offset Drift (µV/_ C) Gain Drift (ppm/_ C) Figure 19 Figure 20 OFFSET POWER−ON WARMUP GAIN ERROR POWER−ON WARMUP 40 10 Normalized Offset (µV) Response Band 20 10 0 −10 −20 −30 High−Speed Mode DVDD = 3.3V 8 Normalized Gain Error (ppm) High−Speed Mode DVDD = 3.3V 30 6 Response Band 4 2 0 −2 −4 −6 −8 −40 −10 0 10 20 30 40 Time After Power−On (s) 50 60 0 10 20 30 40 Time After Power−On (s) Figure 21 50 60 Figure 22 UNCALIBRATED OFFSET HISTOGRAM GAIN ERROR HISTOGRAM 30 50 High−Speed Mode 30 Units High−Speed Mode 30 Units 40 Units (%) Units (%) 20 30 20 10 10 Figure 23 −1600 −1650 −1700 −1750 −1800 −1850 −1900 −1950 −2000 −2050 −2100 −2150 −2200 −2250 −2300 300 250 200 150 −2350 Uncalibrated Offset (µV) 100 0 50 −50 −100 −150 −200 −250 −300 −350 −400 −450 0 −500 0 Gain Error (ppm) Figure 24 11 www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) TA = 25°C, AVDD = 5V, DVDD = 1.8V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, unless otherwise noted. REFERENCE INPUT DIFFERENTIAL IMPEDANCE vs TEMPERATURE 8900 High−Speed and High−Resolution Modes Low−Power Mode Reference Input Impedance (Ω) 4260 4240 4220 4200 4180 4160 4140 4120 4100 −40 −20 0 20 40 80 100 8700 8600 8500 8400 8300 8200 −40 120 125 −20 20 40 60 Temperature (_C) Figure 25 Figure 26 ANALOG INPUT DIFFERENTIAL IMPEDANCE vs TEMPERATURE ANALOG INPUT DIFFERENTIAL IMPEDANCE vs TEMPERATURE 0 16450 16400 16350 16300 16250 16200 −20 0 20 40 60 Temperature (_C) 80 100 120 125 32800 32600 32400 32200 32000 −40 −20 0 20 40 60 80 100 120 125 Temperature (_C) Figure 28 INTEGRAL NONLINEARITY vs TEMPERATURE LINEARITY ERROR vs INPUT LEVEL 10 8 12 Linearity Error (ppm) 6 10 INL (ppm) 120 125 Low−Power Mode 14 8 High−Resolution 6 High−Speed 4 Low−Power 2 High−Speed Mode T = +125_ C T = +105_C 4 2 0 −2 T = +25_ C −4 T = −40_ C −6 −8 −20 0 20 40 60 Temperature (_ C) Figure 29 12 100 33000 Figure 27 0 −40 80 33200 High−Speed and High−Resolution Modes 16500 16150 −40 8800 Temperature (_C) 16550 Analog Input Impedance (Ω) 60 Analog Input Impedance (Ω) Reference Input Impedance (Ω) 4280 REFERENCE INPUT DIFFERENTIAL IMPEDANCE vs TEMPERATURE 80 100 120 125 −10 −2.5 −2.0 −1.5 −1.0 −0.5 0 0.5 VIN (V) Figure 30 1.0 1.5 2.0 2.5 www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) TA = 25°C, AVDD = 5V, DVDD = 1.8V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, unless otherwise noted. NOISE vs DVDD 20 18 18 16 16 14 14 12 High−Speed 10 Low−Power 8 High−Resolution 6 RMS Noise (µV) RMS Noise (µV) NOISE vs AVDD 20 Low−Power 10 8 6 4 4 2 2 0 4.75 High−Speed 12 High−Resolution 0 4.85 4.95 5.05 5.15 5.25 1.6 1.8 2.0 2.2 2.6 2.8 DVDD (V) Figure 31 Figure 32 NOISE vs TEMPERATURE 3.0 3.2 3.4 3.6 NOISE vs INPUT LEVEL 20 12 High−Speed 18 10 16 8 Low−Power 6 High−Resolution 4 RMS Noise (µV) RMS Noise (µV) 2.4 AVDD (V) 14 High−Speed Low−Power 12 10 8 High−Resolution 6 4 2 2 0 −40 −20 0 20 40 60 80 100 0 −2.5 −2.0 −1.5 −1.0 −0.5 120 125 Figure 33 Figure 34 AVDD CURRENT vs TEMPERATURE 3.5 High−Speed and High−Resolution DVDD Current (mA) AVDD Current (mA) 1.5 2.0 2.5 DVDD CURRENT vs TEMPERATURE 16 14 12 10 6 1.0 4.0 20 8 0.5 VIN (V) 22 18 0 Temperature (_C) Low−Power High−Speed 3.0 High−Resolution 2.5 2.0 Low−Power 1.5 1.0 4 0.5 2 0 −40 −20 0 20 40 60 80 100 120 125 0 −40 −20 0 20 40 60 Temperature (_C) Temperature (_ C) Figure 35 Figure 36 80 100 120 125 13 www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) TA = 25°C, AVDD = 5V, DVDD = 1.8V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, unless otherwise noted. OFFSET AND GAIN ERROR vs VREF NOISE vs VREF 100 400 75 300 12 200 Offset 25 100 0 0 Gain Error −25 −100 See Electrical Characteristics for VREF Operating Range −50 0.5 1.0 8 Low−Power 6 High−Resolution 4 2 See Electrical Characteristics for VREF Operating Range −200 3.0 0 VREF (V) 1.0 1.5 2.0 2.5 VREF and Common−Mode Input Voltage (V) Figure 37 Figure 38 1.5 2.0 2.5 RMS Noise (µV) 50 Normalized Gain Error (ppm) Normalized Offset (µV) High−Speed 10 0.5 INTEGRAL NONLINEARITY vs VREF TOTAL HARMONIC DISTORTION vs VREF −100 12 3.0 High−Speed Mode f IN = 1kHz, −0.5dBFS 10 −105 THD (dB) INL (ppm) 8 6 −110 4 −115 2 0.5 See Electrical Characteristics for VREF Operating Range −120 VREF (V) 1.5 VREF (V) Figure 39 Figure 40 COMMON−MODE REJECTION RATIO vs FREQUENCY NOISE AND OFFSET vs COMMON−MODE INPUT VOLTAGE 1.0 2.0 1.5 2.5 3.0 1.0 0.5 0 2.0 2.5 70 20 High−Speed Mode 18 −20 High−Speed Mode 50 30 16 RMS Noise (µV) CMRR (dB) −40 −60 −80 −100 −120 −140 10 100 1k 10k 100k Common−Mode Signal Frequency (Hz) Figure 41 14 1M Offset 14 10 12 −10 10 −30 −50 8 Noise 6 −70 4 −90 2 −110 0 −0.5 −130 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Common−Mode Input Voltage (V) Figure 42 4.5 5.0 Normalized Offset (µV) See Electrical Characteristics for VREF Operating Range 0 www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 OVERVIEW The ADS1271 is a 24-bit, delta-sigma ADC. It offers the combination of outstanding DC accuracy and superior AC performance. Figure 43 shows the block diagram for the ADS1271. The ADS1271 converter is comprised of an advanced, 6th-order, chopper-stabilized, delta-sigma modulator followed by a low-ripple, linear phase FIR filter. The modulator measures the differential input signal, VIN = (AINP – AINN), against the differential reference, VREF = (VREFP – VREFN). The digital filter receives the modulator signal and provides a low-noise digital output. To allow tradeoffs among speed, resolution, and power, three modes of operation are supported on the ADS1271: High-Speed, High-Resolution, and Low-Power. Table 1 summarizes the performance of each mode. In High-Speed mode, the data rate is 105kSPS; in High-Resolution mode, the SNR = 109dB; and in Low-Power mode, the power dissipation is only 35mW. The digital filter can be bypassed, enabling direct access to the modulator output. The ADS1271 is configured by simply setting the appropriate IO pins—there are no registers to program. Data is retrieved over a serial interface that supports both SPI and Frame-Sync formats. The ADS1271 has a daisy-chainable output and the ability to synchronize externally, so it can be used conveniently in multichannel systems. VREFP VREFN SYNC/PDWN Σ MODE CLK VREF AINP Σ VIN ∆Σ Modulator Digital Filter AINN SPI or Frame− Sync Serial Interface DRDY/FSYNC SCLK DOUT DIN FORMAT Figure 43. Block Diagram Table 1. Operating Mode Performance Summary MODE DATA RATE (SPS) PASSBAND (Hz) SNR (dB) NOISE (µVRMS) POWER (mW) High-Speed 105,469 47,777 106 9.0 92 High-Resolution 52,734 23,889 109 6.5 90 Low-Power 52,734 23,889 106 9.0 35 15 www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 ANALOG INPUTS (AINP, AINN) The ADS1271 measures the differential input signal VIN = (AINP – AINN) against the differential reference VREF = (VREFP – VREFN). The most positive measurable differential input is +VREF, which produces the most positive digital output code of 7FFFFFh. Likewise, the most negative measurable differential input is −VREF, which produces the most negative digital output code of 800000h. While the ADS1271 measures the differential input signal, the absolute input voltage is also important. This is the voltage on either input (AINP or AINN) with respect to AGND. The range for this voltage is: −0.1V < (AINN or AINP) < AVDD +0.1V If either input is taken below –0.4V or above (AVDD + 0.4), ESD protection diodes on the inputs may turn on. If these conditions are possible, external Schottky clamp diodes or series resistors may be required to limit the input current to safe values (see Absolute Maximum Ratings). The ADS1271 uses switched-capacitor circuitry to measure the input voltage. Internal capacitors are charged by the inputs and then discharged. Figure 44 shows a conceptual diagram of these circuits. Switch S2 represents the net effect of the modulator circuitry in discharging the sampling capacitor; the actual implementation is different. The timing for switches S1 and S2 is shown in Figure 45. The sampling time (tSAMPLE) is the inverse of modulator sampling frequency (fMOD) and is a function of the mode, format, and frequency of CLK, as shown in Table 2. When using the Frame-Sync format with High-Resolution or Low-Power modes, the ratio between fMOD and fCLK depends on the frame period that is set by the FSYNC input. t SAMPLE = 1/f MOD ON S1 OFF ON S2 OFF Figure 45. S1 and S2 Switch Timing for Figure 44 Table 2. Modulator Frequency for the Different Mode and Format Settings MODE INTERFACE FORMAT fMOD High-Speed SPI or Frame-Sync fCLK/4 High-Resolution Low-Power SPI fCLK/4 Frame-Sync fCLK/4 or fCLK/2 SPI fCLK/8 Frame-Sync fCLK/8 or fCLK/4 The average load presented by the switched capacitor input can be modeled with an effective differential impedance, as shown in Figure 46. Note that the effective impedance is a function of fMOD. AINP Zeff = 16.4kΩ × (6.75MHz/fMOD ) AINN AVDD AGND S1 AINP 9pF S2 Figure 46. Effective Input Impedances AINN S1 AGND AVDD ESD Protection Figure 44. Equivalent Analog Input Circuitry 16 The ADS1271 is a very high-performance ADC. For optimum performance, it is critical that the appropriate circuitry be used to drive the ADS1271 inputs. See the Application Information section for the recommended circuits. www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 VOLTAGE REFERENCE INPUTS (VREFP, VREFN) The voltage reference for the ADS1271 ADC is the differential voltage between VREFP and VREFN: VREF = (VREFP−VREFN). The reference inputs use a structure similar to that of the analog inputs with the equivalent circuitry on the reference inputs shown in Figure 47. As with the analog inputs, the load presented by the switched capacitor can be modeled with an effective impedance, as shown in Figure 48. VREFP AVDD VREFP VREFN Zeff = 4.2kΩ × (6.75MHz/f MOD) Figure 48. Effective Reference Impedance ESD diodes protect the reference inputs. To keep these diodes from turning on, make sure the voltages on the reference pins do not go below AGND by more than 0.4V, and likewise do not exceed AVDD by 0.4V. If these conditions are possible, external Schottky clamp diodes or series resistors may be required to limit the input current to safe values (see Absolute Maximum Ratings). VREFN AVDD ESD Protection Note that the valid operating range of the reference inputs is limited to the following: For the ADS1271: −0.1V ≤ VREFN ≤ VREFP − 2V VREFN + 2V ≤ VREFP ≤ AVDD − 0.5V For the ADS1271B: Figure 47. Equivalent Reference Input Circuitry −0.1V ≤ VREFN ≤ VREFP − 0.5V VREFN + 0.5V ≤ VREFP ≤ AVDD + 0.1V A high-quality reference voltage with the appropriate drive strength is essential for achieving the best performance from the ADS1271. Noise and drift on the reference degrade overall system performance. See the Application Information section for example reference circuits. 17 www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 CLOCK INPUT (CLK) The ADS1271 requires an external clock signal to be applied to the CLK input pin. As with any high-speed data converter, a high-quality, low-jitter clock is essential for optimum performance. Crystal clock oscillators are the recommended clock source. Make sure to avoid excess ringing on the clock input; keeping the clock trace as short as possible using a 50Ω series resistor will help. The ratio between the clock frequency and output data rate is a function of the mode and format. Table 3 shows the ratios when the SPI format is selected. Also included in this table is the typical CLK frequency and the corresponding data rate. When High-Speed mode is used, each conversion takes 256 CLK periods. When High-Resolution or Low-Power modes are selected, the conversions take 512 CLK periods. Table 4 shows the ratios when the Frame-Sync format is selected. When using the Frame-Sync format in either High-Resolution or Low-Power mode, the fCLK/fDATA ratio can be 256 or 512. The ADS1271 automatically detects which ratio is being used. Using a ratio of 256 allows the CLK frequency to be reduced by a factor of two while maintaining the same data rate. The output data rate scales with the clock frequency. See the Serial Interface section for more details on the Frame-Sync operation. Table 3. Clock Ratios for SPI Format MODE SELECTION fCLK/fDATA TYPICAL fCLK (MHz) " CORRESPONDING DATA RATE (SPS) High-Speed 256 27 " 105,469 High-Resolution 512 27 " 52,734 Low-Power 512 27 " 52,734 Table 4. Clock Ratios for Frame-Sync Format MODE SELECTION fCLK/fFRAME TYPICAL fCLK (MHz) " CORRESPONDING DATA RATE (SPS) High-Speed 256 27 " 105,469 256 13.5 " 52,734 512 27 " 52,734 256 13.5 " 52,734 512 27 " 52,734 High-Resolution Low-Power 18 www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 MODE SELECTION (MODE) The ADS1271 supports three modes of operation: High-Speed, High-Resolution, and Low-Power. The mode selection is determined by the status of the digital input MODE pin, as shown in Table 5. A high impedance, or floating, condition allows the MODE pin to support a third state. The ADS1271 constantly monitors the status of the MODE pin during operation and responds to a change in status after 12,288 CLK periods. When floating the MODE pin, keep the total capacitance on the pin less than 100pF and the resistive loading greater than 10MΩ to ensure proper operation. Changing the mode clears the internal offset calibration value. If onboard offset calibration is being used, be sure to recalibrate after a mode change. When daisy-chaining multiple ADS1271s together and operating in High-Resolution mode (MODE pin floating), the MODE pin of each device must be isolated from one another; this ensures proper device operation. The MODE pins can be tied together for High-Speed and Low-Power modes. When using the SPI format, DRDY is held high after a mode change occurs until settled (or valid) data is ready, as shown in Figure 49. In Frame-Sync format, the DOUT pin is held low after a mode change occurs until settled data is ready, as shown in Figure 49. Data can be read from the device to detect when DOUT changes to logic 1, indicating valid data. FORMAT SELECTION (FORMAT) To help connect easily to either microcontrollers or DSPs, the ADS1271 supports two formats for the serial interface: an SPI-compatible interface and a Frame-Sync interface. The format is selected by the FORMAT pin, as shown in Table 6. If the status of this pin changes, perform a sync operation afterwards to ensure proper operation. The modulator output mode does not require a sync operation. Table 6. Format Selection Table 5. Mode Selection MODE PIN STATUS MODE SELECTION Logic Low (DGND) High-Speed Float(1) High-Resolution Logic High (DVDD) Low-Power FORMAT PIN STATUS SERIAL INTERFACE FORMAT Logic Low (DGND) SPI Float(1) Modulator Output(2) Logic High (DVDD) Frame-Sync (1) Load on FORMAT: C < 100pF, R > 10MΩ. (2) See Modulator Output section. (1) Load on MODE: C < 100pF, R > 10MΩ. MODE Pin CLK ADS1271 Mode Low−Power High−Speed tMD SPI Format tNDR DRDY Low−Power Mode Valid Data Ready Frame−Sync DOUT Format tNDR Low−Power Mode Valid Data on DOUT SYMBOL DESCRIPTION tMD Time to register MODE changes tNDR Time for new data to be ready MIN TYP 12,288 MAX UNITS CLK periods 128 Conversions (1/f DATA) Figure 49. Mode Change Timing 19 www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 SYNCHRONIZATION Figure 51 shows the timing requirement for Frame-Sync format. The SYNC/PDWN pin has two functions. When pulsed, it synchronizes the start of conversions and, if held low for more than 219 CLK cycles (tSYN), places the ADS1271 in Power-Down mode. The SYNC/PDWN pin can be left high for continuous data acquisition. See the Power-Down and Offset Calibration section for more details. After synchronization, indication of valid data depends on the whether SPI or Frame-Sync format was used. In the SPI format, DRDY goes high as soon as SYNC/PDWN is taken low, as shown in Figure 50. After SYNC/PDWN is returned high, DRDY stays high while the digital filter is settling. Once valid data is ready for retrieval, DRDY goes low. The ADS1271 can be synchronized by pulsing the SYNC/PDWN pin low and then returning the pin high. When the pin goes low, the conversion process is stopped, and the internal counters used by the digital filter are reset. When the SYNC/PDWN pin is returned high, the conversion process is restarted. Synchronization allows the conversion to be aligned with an external event; for example, the changing of an external multiplexer on the analog inputs, or by a reference timing pulse. In the Frame-Sync format, DOUT goes low as soon as SYNC/PDWN is taken low, as shown in Figure 51. After SYNC/PDWN is returned high, DOUT stays low while the digital filter is settling. Once valid data is ready for retrieval, DOUT begins to output valid data. For proper synchronization, FSYNC, SCLK, and CLK must be established before taking SYNC/PDWN high, and must then remain running. The SYNC/PDWN pin is capable of synchronizing multiple ADS1271s to within the same CLK cycle. Figure 50 shows the timing requirement of SYNC/PDWN and CLK in SPI format. tCSHD CLK tSCSU SYNC/PDWN tSYN t NDR DRDY SYMBOL t SCSU DESCRIPTION MIN SYNC/PWDN to CLK setup time 5 tCSHD CLK to SYNC/PWDN hold time 10 tSYN Synchronize pulse width 1 tNDR Time for new data to be ready TYP MAX UNITS ns ns 218 CLK periods Conversions (1/fDATA ) 128 Figure 50. Synchronization Timing for SPI format tCSHD CLK t SCSU SYNC/PDWN tSYN FSYNC tNDR DOUT SYMBOL DESCRIPTION Valid Data MIN TYP MAX UNITS tSCSU SYNC/PWDN to CLK setup time 5 tCSHD CLK to SYNC/PWDN hold time 10 tSYN Synchronize pulse width 1 218 CLK periods t NDR Time for new data to be ready 128 129 Conversions (1/f DATA) ns ns Figure 51. Synchronization Timing for Frame-Sync Format 20 www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 POWER-DOWN AND OFFSET CALIBRATION In addition to controlling synchronization, the SYNC/PDWN pin also serves as the control for Power-Down mode and offset calibration. To enter this mode, hold the SYNC/PDWN pin low for at least 219 CLK periods. While in Power-Down mode, both the analog and digital circuitry are completely deactivated. The digital inputs are internally disabled so that is not necessary to shut down CLK and SCLK. To exit Power-Down mode, return SYNC/PDWN high on the rising edge of CLK. The ADS1271 uses a chopper-stabilized modulator to provide inherently very low offset drift. To further minimize offset, the ADS1271 automatically performs an offset self-calibration when exiting Power-Down mode. When power down completes, the offset self-calibration begins with the inputs AINP and AINN automatically disconnected from the signal source and internally shorted together. There is no need to modify the signal source applied to the analog inputs during this calibration. It is critical for the reference voltage to be stable when exiting Power-Down mode; otherwise, the calibration will be corrupted. • • • CLK The offset self-calibration only removes offset errors internal to the device, not offset errors due to external sources. NOTE: When an offset self-calibration is performed, the resulting offset value will vary each time within the peak-to-peak noise range of the converter. In High-Speed mode, this is typically 178 LSBs. The offset calibration value is cleared whenever the device mode is changed (for example, from High-Speed mode to High-Resolution mode). When using the SPI format, DRDY will stay high after exiting Power-Down mode while the digital filter settles, as shown in Figure 52. When using the Frame-Sync format, DOUT will stay low after exiting Power-Down mode while the digital filter settles, as shown in Figure 53. NOTE: In Power-Down mode, the inputs of the ADS1271 must be driven (do not float) and the device drives the outputs driven to a DC level. • • • tPDWN SYNC/PDWN tOFS Post−Calibration Data Ready DRDY Status Converting Sync Power Down Offset Cal and Filter Settling SYMBOL DESCRIPTION tPDWN tOFS MIN SYNC/PDWN pulse width to enter Power−Down mode TYP Converting MAX 219 Time for offset calibration and filter settling UNITS CLK periods Conversions (1/fDATA) 256 Figure 52. Power-Down Timing for SPI format • • • CLK • • • tPDWN SYNC/PDWN tOFS FSYNC DOUT Status Post−Calibration Data Converting Sync Power Down Offset Cal and Filter Settling SYMBOL DESCRIPTION tPDWN tOFS MIN SYNC/PDWN pulse width to enter Power−Down mode 219 Time for offset calibration and filter settling 256 TYP Converting MAX UNITS CLK periods 257 Conversions (1/fDATA) Figure 53. Power-Down Timing for Frame-Sync Format 21 www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 POWER-UP SEQUENCE 0 FREQUENCY RESPONSE −20 Amplitude (dB) The analog and digital supplies should be applied before any analog or digital input is driven. The power supplies may be sequenced in any order. Once the supplies and the voltage reference inputs have stabilized, data can be read from the device. The digital filter sets the overall frequency response. The filter uses a multi-stage FIR topology to provide linear phase with minimal passband ripple and high stopband attenuation. The oversampling ratio of the digital filter (that is, the ratio of the modulator sampling to the output data rate: fMOD/fDATA) is a function of the selected mode, as shown in Table 7. fMOD is CLK/2, CLK/4, or CLK/8, depending on the mode. Table 7. Oversampling Ratio versus Mode MODE OVERSAMPLING RATIO (fMOD/fDATA) High-Speed 64 High-Resolution 128 Low-Power 64 −40 −60 −80 −100 −120 −140 0 0.2 0.6 0.4 0.8 1.0 Normalized Input Frequency (fIN/fDATA) Figure 54. Frequency Response for High-Speed and Low-Power Modes 0.02 High-Speed and Low-Power Modes The digital filter configuration is the same in both High-Speed and Low-Power modes with the oversampling ratio set to 64. Figure 54 shows the frequency response in High-Speed and Low-Power modes normalized to fDATA. Figure 55 shows the passband ripple. The transition from passband to stop band is illustrated in Figure 56. The overall frequency response repeats at 64x multiples of the modulator frequency fMOD, as shown in Figure 57. These image frequencies, if present in the signal and not externally filtered, will fold back (or alias) into the passband, causing errors. The stop-band of the ADS1271 provides 100dB attenuation of frequencies that begin just beyond the passband and continue out to fMOD. Placing an antialiasing, low-pass filter in front of the ADS1271 inputs is recommended to limit possible high-amplitude out-of-band signals and noise. 22 Amplitude (dB) 0 −0.02 −0.04 −0.06 −0.08 −0.10 0 0.1 0.2 0.3 0.4 0.5 0.6 Normalized Input Frequency (fIN/fDATA) Figure 55. Passband Response for High-Speed and Low-Power Modes www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 High-Resolution Mode 0 −1 Amplitude (dB) −2 −3 −4 −5 −6 −7 −8 −9 −10 0.45 0.47 0.49 0.51 0.53 0.55 Normalized Input Frequency (fIN/f DATA) The oversampling ratio is 128 in High-Resolution mode. Figure 58 shows the frequency response in High-Resolution mode normalized to fDATA. Figure 59 shows the passband ripple, and the transition from passband to stop band is illustrated in Figure 60. The overall frequency response repeats at multiples of the modulator frequency fMOD, (128 × fDATA), as shown in Figure 61. The stop band of the ADS1271 provides 100dB attenuation of frequencies that begin just beyond the passband and continue out to fMOD. Placing an antialiasing, low-pass filter in front of the ADS1271 inputs is recommended to limit possible high-amplitude out-of-band signals and noise. Figure 56. Transition Band Response for High-Speed and Low-Power Modes 0 Amplitude (dB) −20 20 0 −20 Gain (dB) −40 −60 −40 −60 −80 −100 −120 −80 −140 −100 0 −120 0.25 0.75 0.50 1 Normalized Input Frequency (fIN/fDATA ) −140 −160 0 16 32 48 Figure 58. Frequency Response for High-Resolution Mode 64 Input Frequency (f IN/fDATA) Figure 57. Frequency Response Out to fMOD for High-Speed and Low-Power Modes 0.02 Amplitude (dB) 0 −0.02 −0.04 −0.06 −0.08 −0.10 0 0.1 0.2 0.3 0.4 0.5 0.6 Normalized Input Frequency (fIN/fDATA) Figure 59. Passband Response for High-Resolution Mode 23 www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 PHASE RESPONSE 0 The ADS1271 incorporates a multiple stage, linear phase digital filter. Linear phase filters exhibit constant delay time versus input frequency (constant group delay). This means the time delay from any instant of the input signal to the same instant of the output data is constant and is independent of input signal frequency. This behavior results in essentially zero phase errors when analyzing multi-tone signals. −1 Amplitude (dB) −2 −3 −4 −5 −6 −7 −8 −9 −10 0.45 SETTLING TIME 0.47 0.49 0.51 0.53 0.55 As with frequency and phase response, the digital filter also determines settling time. Figure 62 shows the output settling behavior after a step change on the analog inputs normalized to conversion periods. The X axis is given in units of conversion. Note that after the step change on the input occurs, the output data changes very little prior to 30 conversion periods. The output data is fully settled after 76 conversion periods for High-Speed and Low-Power modes, and 78 conversions for High-Resolution mode. Normalized Input Frequency (fIN/f DATA) Figure 60. Transition Band Response for High-Resolution Mode 20 0 −20 Gain (dB) −40 Final Value −60 100 −80 Fully Settled Data at 76 Conversions (78 Conversions for High−Resolution mode) % Settling −100 −120 −140 −160 0 32 64 96 0 Figure 61. Frequency Response out to fMOD for High-Resolution Mode Table 8. Antialiasing Filter Order Image Rejection 24 Initial Value 128 Normalized Input Frequency (fIN/f DATA) IMAGE REJECTION (dB) (f−3dB at fDATA) ANTIALIASING FILTER ORDER HS, LP HR 1 39 45 2 75 87 3 111 129 0 10 20 30 40 50 60 70 80 Conversions (1/fDATA) Figure 62. Settling Time for All Power Modes www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 DATA FORMAT The ADS1271 outputs 24 bits of data in two’s complement format. A positive full-scale input produces an output code of 7FFFFFh, and the negative full-scale input produces an output code of 800000h. The output clips at these codes for signals exceeding full-scale. Table 9 summarizes the ideal output codes for different input signals. Table 9. Ideal Output Code versus Input Signal INPUT SIGNAL VIN (AINP − AINN) IDEAL OUTPUT CODE(1) w +V REF 7FFFFFh +V REF 000001h 2 23 * 1 0 000000h −V REF FFFFFFh 2 23 * 1 ǒ2 2 * 1 Ǔ v −VREF 23 800000h 23 (1) Excludes effects of noise, INL, offset and gain errors. rising edge. Even though the SCLK input has hysteresis, it is recommended to keep SCLK as clean as possible to prevent glitches from accidentally shifting the data. SCLK should be held low after data retrieval. SCLK may be run as fast as the CLK frequency. SCLK may be either in free-running or stop-clock operation between conversions. For best performance, limit fSCLK/fCLK to ratios of 1, 1/2, 1/4, 1/8, etc. When the device is configured for modulator output, SCLK becomes the modulator clock output (see the Modulator Output section). For the fSCLK/fCLK ratio of 1, care must be observed that these signals are not tied together. After Power On, SCLK remains an output until a few clocks have been received on the CLK input. DRDY/FSYNC In the SPI format, this pin functions as the DRDY output. It goes low when data is ready for retrieval and then returns high on the falling edge of the first subsequent SCLK. If data is not retrieved (that is, SCLK is held low), DRDY will pulse high just before the next conversion data is ready, as shown in Figure 63. The new data is loaded within the ADS1271 one CLK cycle before DRDY goes low. All data must be shifted out before this time to avoid being overwritten. SERIAL INTERFACE 1/f DATA 1/f CLK DRDY Data is retrieved from the ADS1271 using the serial interface. To provide easy connection to either microcontrollers or DSPs, two formats are available for the interface: SPI and Frame-Sync. The FORMAT pin selects the interface. The same pins are used for both interfaces (SCLK, DRDY/FSYNC, DOUT and DIN), though their respective functionality depends on the particular interface selected. SPI SERIAL INTERFACE The SPI-compatible format is a simple read-only interface. Data ready for retrieval is indicated by the DRDY output and is shifted out on the falling edge of SCLK, MSB first. The interface can be daisy-chained using the DIN input when using multiple ADS1271s. See the Daisy-Chaining section for more information. SCLK (SPI Format) The serial clock (SCLK) features a Schmitt-triggered input and shifts out data on DOUT on the falling edge. It also shifts in data on the falling edge on DIN when this pin is being used for daisy-chaining. The device shifts data out on the falling edge and the user shifts this data in on the SCLK Figure 63. DRDY Timing with No Readback DOUT The conversion data is shifted out on DOUT. The MSB data is valid on DOUT when DRDY goes low. The subsequent bits are shifted out with each falling edge of SCLK. If daisy-chaining, the data shifted in using DIN will appear on DOUT after all 24 bits have been shifted out. When the device is configured for modulator output, DOUT becomes the modulator data output (see the Modulator Output section). DIN This input is used when multiple ADS1271s are to be daisy-chained together. The DOUT pin of the first device connects to the DIN pin of the next, etc. It can be used with either the SPI or Frame-Sync formats. Data is shifted in on the falling edge of SCLK. When using only one ADS1271, tie DIN low. See the Daisy-Chaining section for more information. 25 www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 FRAME-SYNC SERIAL INTERFACE DRDY/FSYNC Frame-Sync format is similar to the interface often used on audio ADCs. It operates in slave fashion—the user must supply framing signal FSYNC (similar to the left/right clock on stereo audio ADCs) and the serial clock SCLK (similar to the bit clock on audio ADCs). The data is output MSB first or left-justified. When using Frame-Sync format, the CLK, FSYNC and SCLK inputs must be synchronized together, as described in the following sub-sections. In Frame-Sync format, this pin is used as the FSYNC input. The frame-sync input (FSYNC) sets the frame period. The required FSYNC periods are shown in Table 11. For High-Speed mode, the FSYNC period must be 256 CLK periods. For both High-Resolution and Low-Power modes, the FSYNC period can be either 512 or 256 CLK periods; the ADS1271 will automatically detect which is being used. If the FSYNC period is not the proper value, data readback will be corrupted. It is recommended that FSYNC be aligned with the falling edge of SCLK. SCLK (Frame-Sync Format) The serial clock (SCLK) features a Schmitt-triggered input and shifts out data on DOUT on the falling edge. It also shifts in data on the falling edge on DIN when this pin is being used for daisy-chaining. Even though SCLK has hysteresis, it is recommended to keep SCLK as clean as possible to prevent glitches from accidentally shifting the data. When using Frame-Sync format, SCLK must run continuously. If it is shut down, the data readback will be corrupted. Frame-Sync format requires a specific relationship between SCLK and FSYNC, determined by the mode shown in Table 10. When the device is configured for modulator output, SCLK becomes the modulator clock output (see the Modulator Output section). Table 10. SCLK Period When Using Frame-Sync Format 26 Table 11. FSYNC Period MODE REQUIRED FSYNC PERIOD High-Speed 256 CLK Periods High-Resolution 256 or 512 CLK periods Low-Power 256 or 512 CLK periods DOUT The conversion data is shifted out on DOUT. The MSB data becomes valid on DOUT on the CLK rising edge prior to FSYNC going high. The subsequent bits are shifted out with each falling edge of SCLK. If daisy-chaining, the data shifted in using DIN will appear on DOUT after all 24 bits have been shifted out. When the device is configured for modulator output, DOUT becomes the modulator data output (see the Modulator Output section). MODE REQUIRED SCLK PERIOD High-Speed τFRAME/64 DIN High-Resolution τFRAME/128 Low-Power τFRAME/64 This input is used when multiple ADS1271s are to be daisy-chained together. It can be used with either SPI or Frame-Sync formats. Data is shifted in on the falling edge of SCLK. When using only one ADS1271, tie DIN low.See the Daisy-Chaining section for more information. www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 DAISY-CHAINING Multiple ADS1271s can be daisy-chained together to simplify the serial interface connections. The DOUT of one ADS1271 is connected to the DIN of the next ADS1271. The first DOUT provides the output data and the last DIN in the chain is connected to ground. A common SCLK is used for all the devices in the daisy chain. Figure 64 shows an example of a daisy chain with four ADS1271s. Figure 65 shows the timing diagram when reading back in the SPI format. It takes 96 SCLKs to shift out all the data. In SPI format, it is recommended to tie all the SYNC/PDWN inputs together, which forces synchronization of all the devices. It is only necessary to monitor the DRDY output of one device when multiple devices are configured this way. In Frame-Sync format, all of the devices are driven to synchronization by the FSYNC and SCLK inputs. However, to ensure synchronization to the same fCLK cycle, it is recommended to tie all SYNC/PDWN inputs together. The device clocks the SYNC/PDWN pin on the falling edge of fCLK. To ensure exact synchronization, the SYNC/PDWN pin should transition on the rising edge of fCLK Since DOUT and DIN are both shifted on the falling edge of SCLK, the propagation delay on DOUT creates the setup time on DIN. Minimize the skew in SCLK to avoid timing violations. See Mode Selection section for MODE pin use when daisy-chaining. ADS12714 ADS12713 The SPI format offers the most flexibility when daisy-chaining because there is more freedom in setting the SCLK frequency. The maximum number of ADS1271s that can be daisy-chained is determined by dividing the conversion time (1/fDATA) by the time needed to read back all 24 bits (24 × 1/fSCLK). Consider the case where: fCLK = 27MHz mode = High-Resolution (52,734SPS) format = SPI fSCLK = 27MHz The maximum length of the daisy-chain is: 27MHz/(24 × 52,734SPS) = 21.3 Rounding down gives 21 as the maximum number of ADS1271s that can be daisy-chained. Daisy-chaining also works in Frame-Sync format, but the maximum number of devices that can be daisy-chained is less than when using the SPI format. The ratio between the frame period and SCLK period is fixed, as shown in Table 10. Using these values, the maximum number of devices is two for High-Speed and Low-Power modes, and five for High-Resolution mode. ADS12712 ADS12711 SYNC SYNC SYNC DIN DOUT SCLK DIN SYNC DOUT SCLK DIN DOUT SCLK SYNC DRDY DIN DOUT SCLK SCLK Figure 64. Example of SPI-Format, Daisy-Chain Connection for Multiple ADS1271s DRDY SCLK DOUT 1 ADS12711 Bit 23 (MSB) 24 ADS12711 Bit 0 (LSB) 25 ADS1271 2 Bit 23 (MSB) 73 ADS12714 Bit 23 (MSB) 96 ADS12714 Bit 0 (LSB) Figure 65. Timing Diagram for Example in Figure 64 (SPI Format) 27 www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 MODULATOR OUTPUT The ADS1271 incorporates a 6th-order, single-bit, chopper-stabilized modulator followed by a multi-stage digital filter, which yields the conversion results. The data stream output of the modulator is available directly, bypassing the internal digital filter. In this mode, an external digital filter implemented in an ASIC, FPGA, or similar device is required. To invoke the modulator output, float the FORMAT pin and tie DIN to DVDD. DOUT then becomes the modulator data stream output and SCLK becomes the modulator clock output. The DRDY/FSYNC pin becomes an unused output and can be ignored. The normal operation of the Frame-Sync and SPI interfaces is disabled, and the functionality of SCLK changes from an input to an output, as shown in Figure 66. Note that modulator output mode is specified for the B grade device only. DVDD DIN (Float) DOUT Modulator Clock Output Figure 66. Modulator Output (B-Grade Device) 28 Table 12. Modulator Output Clock Frequencies MODE PIN MODULATOR CLOCK OUTPUT (SCLK) 0 fCLK/4 Float fCLK/4 1 fCLK/8 Figure 67 shows the timing relationship of the modulator clock and data outputs. Modulator Clock Output SCLK Modulator Data Output DOUT Modulator Data Output FORMAT SCLK In modulator output mode, the frequency of the SCLK clock output depends on the mode selection of the ADS1271. Table 12 lists the modulator clock output frequency versus device mode. (10ns max) Figure 67. Modulator Output Timing www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 APPLICATION INFORMATION 5. Reference Inputs: It is recommended to use a minimum 10µF tantalum with a 0.1µF ceramic capacitor directly across the reference inputs, VREFP and VREFN. The reference input should be driven by a low-impedance source. For best performance, the reference should have less than 3µVRMS broadband noise. For references with noise higher than this, external reference filtering may be necessary. 6. Analog Inputs: The analog input pins must be driven differentially to achieve specified performance. A true differential driver or transformer (AC applications) can be used for this purpose. Route the analog inputs tracks (AINP, AINN) as a pair from the buffer to the converter using short, direct tracks and away from digital tracks. To obtain the specified performance from the ADS1271, the following layout and component guidelines should be considered. 1. Power Supplies: The device requires two power supplies for operation: DVDD and AVDD. The allowed range for DVDD is 1.65V to 3.6V, and AVDD is restricted to 4.75V to 5.25V. Best performance is achieved when DVDD = 1.8V. For both supplies, use a 10µF tantalum capacitor, bypassed with a 0.1µF ceramic capacitor, placed close to the device pins. Alternatively, a single 10µF ceramic capacitor can be used. The supplies should be relatively free of noise and should not be shared with devices that produce voltage spikes (such as relays, LED display drivers, etc.). If a switching power supply source is used, the voltage ripple should be low (< 2mV). The power supplies may be sequenced in any order. 2. Ground Plane: A single ground plane connecting both AGND and DGND pins can be used. If separate digital and analog grounds are used, connect the grounds together at the converter. 3. Digital Inputs: It is recommended to source terminate the digital inputs to the device with 50Ω series resistors. The resistors should be placed close to the driving end of digital source (oscillator, logic gates, DSP, etc.) This helps to reduce ringing on the digital lines, which may lead to degraded ADC performance. 4. Analog/Digital Circuits: Place analog circuitry (input buffer, reference) and associated tracks together, keeping them away from digital circuitry (DSP, microcontroller, logic). Avoid crossing digital tracks across analog tracks to reduce noise coupling and crosstalk. A 1nF to 10nF capacitor should be used directly across the analog input pins, AINP and AINN. A low-k dielectric (such as COG or film type) should be used to maintain low THD. Capacitors from each analog input to ground should be used. They should be no larger than 1/10 the size of the difference capacitor (typically 100pF) to preserve the AC common-mode performance. 7. Component Placement: Place the power supply, analog input, and reference input bypass capacitors as close as possible to the device pins. This is particularly important for the small-value ceramic capacitors. Surface-mount components are recommended to avoid the higher inductance of leaded components. Figure 68 to Figure 70 illustrate basic connections and interfaces that can be used with the ADS1271. 29 www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 1kΩ 10nF (2) +5V ADS1271 +5V 0.1µF 100Ω 1 AINP Differential Inputs 100pF OPA350 VREFP 16 + 1nF 10µF 100Ω 1kΩ 100µF 2 AINN VREFN 15 3 AGND DGND 14 4 AVDD DVDD 13 + 0.47µF REF3125 0.1µF 0.1µF 100pF +5V 0.1µF + 10µF 1.8V to 3.3V (1) 10µF 0.1µF 50Ω 5 MODE Tie to Either DVDD or GND 27MHz Clock Source CLK 12 50Ω 6 FORMAT SCLK 11 50Ω 7 SYNC/ DRDY/ 10 PDWN FSYNC 50Ω 50Ω 50Ω 8 DIN DOUT NOTE: (1) 1.8V recommended. (2) Recommended circuit for reference noise filtering. 9 Figure 68. Basic Connection Drawing 1kΩ 1kΩ 1kΩ 249Ω VIN 1.5nF(2) 5.6nF(2) +15V(1) +15V(1) 49.9Ω VREF VOCM VIN AINP OPA1632 AINN AINP OPA1632 0.1µF −15V(1) 1.5nF(2) 5.6nF(2) 1kΩ Figure 69. Basic Differential Input Signal Interface 1kΩ 49.9Ω AINN −15V(1) NOTES: (1) Bypass with 10µF and 0.1µF capacitors. (2) 2.7nF for Low−Power mode. 30 VOCM 49.9Ω 0.1µF 1kΩ 49.9Ω VREF VO DIFF = 0.25 × VIN VO COMM = VREF 249Ω NOTES: (1) Bypass with 10µF and 0.1µF capacitors. (2) 10nF for Low−Power mode. Figure 70. Basic Single-Ended Input Signal Interface www.ti.com SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007 Revision History DATE REV PAGE SECTION DESCRIPTION 10/07 F 25 SCLK (SPI Format) Added final paragraph to section. 9/07 E 20 Synchronization Added sentence to 1st paragraph regarding SYNC/PDWN left high. 2 Absolute Maximum Ratings Deleted lead temperature. 7 Timing Characteristics: Frame-Sync Format Changed tDDO parameter from “falling edge” to “rising edge.” 16 Analog Inputs (AINP, AINN) 17 Voltage ReferFence Inputs (VREFP, VREFN) Added “(only 256 or 512 allowed)” to Note 1. Changed “0.1V” to “0.4V” in 3rd paragraph 7/06 Added 4th paragraph about clamp diode and series resistor requirements. Changed “0.1V” to “0.4V” in 1st paragraph of right column. Added sentence about clamp diode and series resistor requirements. D Changed text from 2nd paragraph through end of section. 20 Synchronization Changed Figure 50. Changed Figure 51. 22 Frequency Response Added “or CLK/8” to last sentence of 2nd paragraph. 26 DOUT Changed “SCLK” to “CLK” in 2nd sentence of 3rd paragraph. 29 Application Information Changed “REFP” to “VREFP” in part 5. Changed “REFN” to “VREFN” in part 5. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 31 PACKAGE OPTION ADDENDUM www.ti.com 21-May-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) ADS1271IBPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1271IBPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1271IBPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1271IBPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1271IPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1271IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1271IPWR ACTIVE TSSOP PW 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1271IPWRG4 ACTIVE TSSOP PW 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 21-May-2010 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1271IBPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 ADS1271IPWR TSSOP PW 16 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1271IBPWR TSSOP PW 16 2000 367.0 367.0 35.0 ADS1271IPWR TSSOP PW 16 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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