FUNCTIONAL BLOCK DIAGRAMS Low wideband noise 1 nV/√Hz 1.6 pA/√Hz Low 1/f noise: 2 nV/√Hz at 10 Hz Low distortion (SFDR): −96 dBc at 100 kHz, VOUT = 2 V p-p Low power: 3 mA per amplifier Low input offset voltage: 350 µV maximum High speed 236 MHz, −3 dB bandwidth (G = +10) 943 V/µs slew rate 22 ns settling time to 0.1% Rail-to-rail output Wide supply range: 3 V to 10 V Disable feature NC 1 8 –IN 2 7 +VS +IN 3 6 OUT 5 NC –VS 4 ADA4895-1 DISABLE 10186-102 FEATURES NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. Figure 1. ADA4895-1 Single Amplifier (8-Lead SOIC) OUT1 1 10 +VS –IN1 2 9 OUT2 +IN1 3 8 –IN2 –VS 4 7 +IN2 6 DISABLE2 ADA4895-2 DISABLE1 5 10186-001 Data Sheet Low Power, 1 nV/√Hz, G ≥ 10 Stable, Railto-Rail Output Amplifier ADA4895-1/ADA4895-2 Figure 2. ADA4895-2 Dual Amplifier (10-Lead MSOP) 5 30 4 24 3 18 2 12 Low noise preamplifier Ultrasound amplifiers PLL loop filters High performance analog-to-digital converter (ADC) drivers Digital-to-analog converter (DAC) buffers GENERAL DESCRIPTION The ADA4895-1/ADA4895-2 have a small signal bandwidth of 236 MHz at a gain of +10 with a slew rate of 943 V/µs, and settle to 0.1% in 22 ns. The wide supply voltage range (3 V to 10 V) of the ADA4895-1/ADA4895-2 make these amplifiers ideal candidates for systems that require large dynamic range, high gain, precision, and high speed. The ADA4895-1 is available in 8-lead SOIC and 6-lead SOT-23 packages, and the ADA4895-2 is available in a 10-lead MSOP package. All packages operate over the extended industrial temperature range of −40°C to +125°C. Rev. B 6 CURRENT 0 1 10 100 1k 10k 100k 0 1M FREQUENCY (Hz) 10186-002 The ADA4895-1 (single) and ADA4895-2 (dual) are high speed voltage feedback amplifiers that are gain ≥ 10 stable with low input noise, rail-to-rail output, and a quiescent current of 3 mA per amplifier. With a 1/f noise of 2 nV/√Hz at 10 Hz and a spuriousfree dynamic range (SFDR) of −72 dBc at 2 MHz, the ADA4895-1/ ADA4895-2 are an ideal solution in a variety of applications, including ultrasound, low noise preamplifiers, and drivers of high performance ADCs. The Analog Devices, Inc., proprietary next generation SiGe bipolar process and innovative architecture enables the high performance of these amplifiers. VOLTAGE 1 INPUT CURRENT NOISE (pA/√Hz) INPUT VOLTAGE NOISE (nV/√Hz) APPLICATIONS Figure 3. Input Voltage and Current Noise vs. Frequency Table 1. Other Low Noise Amplifiers1 Part Number(s) AD8021 AD8045 AD8099 ADA4841-1/ADA4841-2 ADA4896-2 ADA4897-1/ADA4897-2 ADA4898-1/ADA4898-2 ADA4899-1 1 ven at 100 kHz Bandwidth Supply (nV/√Hz) 2.1 3 0.95 2.1 1 1 0.9 1 (MHz) 490 1000 510 80 230 230 65 600 Voltage (V) 5 to 24 3.3 to 12 5 to 12 2.7 to 12 3 to 10 3 to 10 10 to 32 5 to 12 See www.analog.com for the latest selection of low noise amplifiers. COMPANION PRODUCTS ADCs: AD7944 (14-bit), AD7985 (16-bit), AD7986 (18-bit) Additional companion products on the ADA4895-1/ADA4895-2 product page Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADA4895-1/ADA4895-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 16 Applications ....................................................................................... 1 Amplifier Description................................................................ 16 General Description ......................................................................... 1 Input Protection ......................................................................... 16 Functional Block Diagrams ............................................................. 1 Disable Operation ...................................................................... 16 Companion Products ....................................................................... 1 DC Errors .................................................................................... 17 Revision History ............................................................................... 2 Bias Current Cancellation ......................................................... 17 Specifications..................................................................................... 3 Noise Considerations ................................................................. 18 ±5 V (or +10 V) Supply ............................................................... 3 Applications Information .............................................................. 19 ±2.5 V (or +5 V) Supply .............................................................. 4 Using the ADA4895-1/ADA4895-2 at a Gain < +10 .............. 19 ±1.5 V (or +3 V) Supply .............................................................. 5 High Gain Bandwidth Application .......................................... 20 Absolute Maximum Ratings ............................................................ 7 Feedback Capacitor Application .............................................. 20 Thermal Resistance ...................................................................... 7 Wideband Photomultiplier Preamplifier ................................ 21 Maximum Power Dissipation ..................................................... 7 Layout Considerations ............................................................... 22 ESD Caution .................................................................................. 7 Outline Dimensions ....................................................................... 23 Pin Configurations and Function Descriptions ........................... 8 Ordering Guide .......................................................................... 24 Typical Performance Characteristics ........................................... 10 REVISION HISTORY 4/15—Rev. A to Rev. B Changes to Amplifier Description Section ................................. 16 Changes to Ordering Guide .......................................................... 24 12/12—Rev. 0 to Rev. A Added ADA4895-1 ............................................................. Universal Changes to Features Section, General Description Section, and Table 1 ............................................................................................................. 1 Added Figure 1; Renumbered Sequentially .................................. 1 Changes to Table 2 ............................................................................ 3 Changes to Table 3 ............................................................................ 4 Changes to Table 4 ............................................................................ 5 Changes to Figure 4 .......................................................................... 7 Added Figure 5, Table 7, Figure 6, and Table 8 ............................. 8 Added Figure 14 and Figure 17..................................................... 11 Changes to Figure 24 ...................................................................... 12 Added Figure 26 and Figure 29..................................................... 13 Changes to Amplifier Description Section ................................. 16 Changes to Noise Considerations Section .................................. 18 Added Feedback Capacitor Applications Section and Figure 54 .......................................................................................... 20 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 24 9/12—Revision 0: Initial Version Rev. B | Page 2 of 24 Data Sheet ADA4895-1/ADA4895-2 SPECIFICATIONS ±5 V (OR +10 V) SUPPLY TA = 25°C, G = +10, RF = 249 Ω, RL = 1 kΩ to midsupply, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE Harmonic Distortion (SFDR) Input Voltage Noise Input Current Noise 0.1 Hz to 10 Hz Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Bias Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection OUTPUT CHARACTERISTICS Output Overdrive Recovery Time Positive Output Voltage Swing Negative Output Voltage Swing Linear Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Positive Power Supply Rejection Negative Power Supply Rejection Test Conditions/Comments Min Typ Max Unit VOUT = 0.2 V p-p VOUT = 2 V p-p VOUT = 0.2 V p-p, G = +20, RF = 1 kΩ VOUT = 2 V p-p, RL = 100 Ω VOUT = 6 V step VOUT = 2 V step 236 146 115 8.9 943 22 MHz MHz MHz MHz V/µs ns fC = 100 kHz, VOUT = 2 V p-p fC = 1 MHz, VOUT = 2 V p-p fC = 2 MHz, VOUT = 2 V p-p fC = 5 MHz, VOUT = 2 V p-p f = 10 Hz, G = +25.9 f = 100 kHz, G = +25.9 f = 10 Hz, RF = 10 kΩ, RG = 1.1 kΩ, RS = 1 kΩ f = 100 kHz, RF = 10 kΩ, RG = 1.1 kΩ, RS = 1 kΩ G = +101, RF = 1 kΩ, RG = 10 Ω −96 −78 −72 −64 2 1 14 1.6 99 dBc dBc dBc dBc nV/√Hz nV/√Hz pA/√Hz pA/√Hz nV p-p −350 −0.6 100 +53 0.15 −11 1.2 −0.02 110 −100 10 M/10 k 3/11 −4.9 to +4.1 −109 Ω pF V dB 80 4.96 4.77 −4.97 −4.85 80 116/111 6 ns V V V V mA rms mA pF −16 VOUT = −4 V to +4 V Common mode/differential mode Common mode/differential mode VCM = −2 V to +2 V VIN = −0.55 V to +0.55 V RL = 1 kΩ RL = 100 Ω RL = 1 kΩ RL = 100 Ω SFDR = −45 dBc Sinking/sourcing 30% overshoot 4.85 4.5 −4.85 −4.5 2.8 DISABLEx = −5 V +VS = 4 V to 6 V, −VS = −5 V +VS = 5 V, −VS = −4 V to −6 V Rev. B | Page 3 of 24 −98 −98 3 to 10 3 0.1 −136 −135 +350 −6 +0.6 3.2 µV µV/°C µA nA/°C µA dB V mA mA dB dB ADA4895-1/ADA4895-2 Parameter DISABLEx PIN DISABLEx Voltage Input Current per Amplifier Device Enabled Device Disabled Switching Speed Device Enabled Device Disabled Data Sheet Test Conditions/Comments Min Typ Max Unit Device enabled Device disabled >+VS − 0.5 <+VS − 2 V V DISABLEx = +5 V DISABLEx = −5 V −1.1 −40 µA µA 0.25 6 µs µs ±2.5 V (OR +5 V) SUPPLY TA = 25°C, G = +10, RF = 249 Ω, RL = 1 kΩ to midsupply, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE Harmonic Distortion (SFDR) Input Voltage Noise Input Current Noise 0.1 Hz to 10 Hz Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Bias Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection OUTPUT CHARACTERISTICS Output Overdrive Recovery Time Positive Output Voltage Swing Negative Output Voltage Swing Linear Output Current Short-Circuit Current Capacitive Load Drive Test Conditions/Comments Min Typ Max Unit VOUT = 0.2 V p-p VOUT = 2 V p-p VOUT = 0.2 V p-p, G = +20, RF = 1 kΩ VOUT = 2 V p-p, RL = 100 Ω VOUT = 3 V step VOUT = 2 V step 216 131 113 7.9 706 21 MHz MHz MHz MHz V/µs ns fC = 100 kHz, VOUT = 2 V p-p fC = 1 MHz, VOUT = 2 V p-p fC = 2 MHz, VOUT = 2 V p-p fC = 5 MHz, VOUT = 2 V p-p f = 10 Hz, G = +25.9 f = 100 kHz, G = +25.9 f = 10 Hz, RF = 10 kΩ, RG = 1.1 kΩ, RS = 1 kΩ f = 100 kHz, RF = 10 kΩ, RG = 1.1 kΩ, RS = 1 kΩ G = +101, RF = 1 kΩ, RG = 10 Ω −94 −75 −69 −61 1.8 1 14 1.7 99 dBc dBc dBc dBc nV/√Hz nV/√Hz pA/√Hz pA/√Hz nV p-p −350 −0.6 97 +53 0.15 −11 1.2 −0.02 108 −98 10 M/10 k 3/11 −2.4 to +1.6 −110 Ω pF V dB 90 2.48 2.38 −2.48 −2.38 64 111/98 6 ns V V V V mA rms mA pF −16 VOUT = −2 V to +2 V Common mode/differential mode Common mode/differential mode VCM = −1.5 V to +1.5 V VIN = −0.275 V to +0.275 V RL = 1 kΩ RL = 100 Ω RL = 1 kΩ RL = 100 Ω SFDR = −45 dBc Sinking/sourcing 30% overshoot Rev. B | Page 4 of 24 2.35 2.3 −2.35 −2.3 +350 −6 +0.6 µV µV/°C µA nA/°C µA dB Data Sheet Parameter POWER SUPPLY Operating Range Quiescent Current per Amplifier Positive Power Supply Rejection Negative Power Supply Rejection DISABLEx PIN DISABLEx Voltage Input Current per Amplifier Device Enabled Device Disabled Switching Speed Device Enabled Device Disabled ADA4895-1/ADA4895-2 Test Conditions/Comments Min 2.6 DISABLEx = −2.5 V +VS = 2 V to 3 V, −VS = −2.5 V +VS = 2.5 V, −VS = −3 V to −2 V −98 −98 Typ 3 to 10 2.8 0.05 −137 −141 Max 3 Unit V mA mA dB dB Device enabled Device disabled >+VS − 0.5 <+VS − 2 V V DISABLEx = +2.5 V DISABLEx = −2.5 V −1.1 −20 µA µA 0.25 6 µs µs ±1.5 V (OR +3 V) SUPPLY TA = 25°C, G = +10, RF = 249 Ω, RL = 1 kΩ to midsupply, unless otherwise noted. Table 4. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE Harmonic Distortion (SFDR) Input Voltage Noise Input Current Noise 0.1 Hz to 10 Hz Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Bias Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Test Conditions/Comments Min Typ Max Unit VOUT = 0.2 V p-p VOUT = 1 V p-p VOUT = 0.2 V p-p, G = +20, RF = 1 kΩ VOUT = 2 V p-p, RL = 100 Ω VOUT = 1 V step VOUT = 2 V step 205 131 111 7.5 384 20 MHz MHz MHz MHz V/µs ns fC = 100 kHz, VOUT = 2 V p-p fC = 1 MHz, VOUT = 2 V p-p fC = 2 MHz, VOUT = 2 V p-p fC = 5 MHz, VOUT = 2 V p-p f = 10 Hz, G = +25.9 f = 100 kHz, G = +25.9 f = 10 Hz, RF = 10 kΩ, RG = 1.1 kΩ, RS = 1 kΩ f = 100 kHz, RF = 10 kΩ, RG = 1.1 kΩ, RS = 1 kΩ G = +101, RF = 1 kΩ, RG = 10 Ω −92 −73 −67 −59 1.9 1 14 1.7 99 dBc dBc dBc dBc nV/√Hz nV/√Hz pA/√Hz pA/√Hz nV p-p −350 −0.6 95 +55 0.15 −11 1.2 −0.02 106 −93 10 M/10 k 3/11 −1.4 to +0.6 −110 −16 VOUT = −1 V to +1 V Common mode/differential mode Common mode/differential mode VCM = −0.4 V to +0.4 V Rev. B | Page 5 of 24 +350 −6 +0.6 µV µV/°C µA nA/°C µA dB Ω pF V dB ADA4895-1/ADA4895-2 Parameter OUTPUT CHARACTERISTICS Output Overdrive Recovery Time Positive Output Voltage Swing Negative Output Voltage Swing Linear Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Positive Power Supply Rejection Negative Power Supply Rejection DISABLEx PIN DISABLEx Voltage Input Current per Amplifier Device Enabled Device Disabled Switching Speed Device Enabled Device Disabled Data Sheet Test Conditions/Comments VIN = −0.165 V to +0.165 V RL = 1 kΩ RL = 100 Ω RL = 1 kΩ RL = 100 Ω SFDR = −45 dBc Sinking/sourcing 30% overshoot Min 1.35 1.3 −1.35 −1.3 2.5 DISABLEx = −1.5 V +VS = 1.2 V to 2.2 V, −VS = −1.5 V +VS = 1.5 V, −VS = −2.2 V to −1.2 V −98 −98 Typ Max 80 1.48 1.43 −1.49 −1.45 46 99/83 6 3 to 10 2.7 0.03 −133 −146 Unit ns V V V V mA rms mA pF 2.9 V mA mA dB dB Device enabled Device disabled >+VS − 0.5 <+VS − 2 V V DISABLEx = +1.5 V DISABLEx = −1.5 V −1.2 −10 µA µA 0.25 6 µs µs Rev. B | Page 6 of 24 Data Sheet ADA4895-1/ADA4895-2 ABSOLUTE MAXIMUM RATINGS PD = Quiescent Power + (Total Drive Power − Load Power) Rating 11 V See Figure 4 −VS − 0.7 V to +VS + 0.7 V ±0.7 V −65°C to +125°C −40°C to +125°C 300°C 150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, θJA is specified for a device soldered in a circuit board for surface-mount packages. Table 6 lists the θJA for the ADA4895-1/ADA4895-2. The quiescent power dissipation is the voltage between the supply pins (±VS) multiplied by the quiescent current (IS). V V PD = (VS × I S ) + S × OUT RL 2 Consider rms output voltages. If RL is referenced to −VS, as in single-supply operation, the total drive power is VS × IOUT. In single-supply operation with RL referenced to −VS, the worst case is VOUT = VS/2. If the rms signal levels are indeterminate, consider the worst case, when VOUT = VS/4 with RL referenced to midsupply. PD = (VS × I S ) + θJA 133 150 210 S 2 RL Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature on a JEDEC standard, 4-layer board. θJA values are approximations. 1.6 Unit °C/W °C/W °C/W MAXIMUM POWER DISSIPATION The maximum safe power dissipation for the ADA4895-1/ ADA4895-2 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the properties of the plastic change. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4895-1/ ADA4895-2. Exceeding a junction temperature of 175°C for an extended period of time can result in changes in silicon devices, potentially causing degradation or loss of functionality. (V / 4 ) Airflow increases heat dissipation, effectively reducing θJA. Also, more metal directly in contact with the package leads reduces θJA. Table 6. Thermal Resistance Package Type 8-Lead Single SOIC 6-Lead Single SOT-23 10-Lead Dual MSOP V 2 − OUT RL 1.4 1.2 ADA4895-1 (SOIC) ADA4895-1 (SOT-23) 1.0 0.8 0.6 ADA4895-2 (MSOP) 0.4 0.2 0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 AMBIENT TEMPERATURE (°C) 90 100 110 120 10186-003 Parameter Supply Voltage Power Dissipation Common-Mode Input Voltage Differential Input Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature MAXIMUM POWER DISSIPATION (W) Table 5. Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board ESD CAUTION The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the die due to the ADA4895-1/ADA4895-2 drive at the output. Rev. B | Page 7 of 24 ADA4895-1/ADA4895-2 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS NC 1 8 –IN 2 7 +VS +IN 3 6 OUT 5 NC ADA4895-1 10186-105 –VS 4 DISABLE NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. Figure 5. 8-Lead SOIC Pin Configuration for the ADA4895-1 Table 7. 8-Lead SOIC Pin Function Descriptions for the ADA4895-1 Mnemonic NC −IN +IN −VS OUT +VS DISABLE Description No Connect. Do not connect to these pins. Inverting Input. Noninverting Input. Negative Supply. Output. Positive Supply. Disable. OUT 1 6 +VS –VS 2 5 DISABLE 4 –IN +IN 3 ADA4895-1 10186-106 Pin No. 1, 5 2 3 4 6 7 8 Figure 6. 6-Lead SOT-23 Pin Configuration for the ADA4895-1 Table 8. 6-Lead SOT-23Pin Function Descriptions for the ADA4895-1 Pin No. 1 2 3 4 5 6 Mnemonic OUT −VS +IN −IN DISABLE +VS Description Output Negative Supply Noninverting Input Inverting Input Disable Positive Supply Rev. B | Page 8 of 24 Data Sheet ADA4895-1/ADA4895-2 –IN1 2 9 OUT2 +IN1 3 8 –IN2 –VS 4 7 +IN2 6 DISABLE2 DISABLE1 5 ADA4895-2 10186-004 10 +VS OUT1 1 Figure 7. 10-Lead MSOP Pin Configuration for the ADA4895-2 Table 9. 10-Lead MSOP Pin Function Descriptions for the ADA4895-2 Pin Number 1 2 3 4 5 6 7 8 9 10 Mnemonic OUT1 −IN1 +IN1 −VS DISABLE1 DISABLE2 +IN2 −IN2 OUT2 +VS Description Output 1 Inverting Input 1 Noninverting Input 1 Negative Supply Disable 1 Disable 2 Noninverting Input 2 Inverting Input 2 Output 2 Positive Supply Rev. B | Page 9 of 24 ADA4895-1/ADA4895-2 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VS = ±2.5 V, G = +10, RF = 249 Ω, RL = 1 kΩ to midsupply, unless otherwise noted. 2 VS = ±5.0V 1 0 –1 –2 –3 –4 VOUT = 200mV p-p 0.1 1 10 100 1000 FREQUENCY (MHz) 0 –1 VS = ±5.0V –2 –3 –4 VOUT = 2V p-p –5 0.1 1 10186-006 Figure 8. Small Signal Frequency Response vs. Supply Voltage NORMALIZED CLOSED-LOOP GAIN (dB) 6 4 G = +10 2 G = –20 0 –2 –4 –6 RF = 1kΩ VOUT = 200mV p-p –10 0.1 1 10 100 1000 FREQUENCY (MHz) 10186-005 NORMALIZED CLOSED-LOOP GAIN (dB) 1000 3 G = –10 G = +10 2 1 G = –10 0 –1 –2 G = –20 –3 –4 RF = 1kΩ VOUT = 2V p-p –5 1 0.1 100 1000 Figure 12. Large Signal Frequency Response vs. Gain 3 4 NORMALIZED CLOSED-LOOP GAIN (dB) –40°C 3 +25°C 2 +125°C 1 0 –1 –2 –3 10 100 1000 FREQUENCY (MHz) 10186-007 –4 VOUT = 200mV p-p –5 0.1 1 10 FREQUENCY (MHz) Figure 9. Small Signal Frequency Response vs. Gain NORMALIZED CLOSED-LOOP GAIN (dB) 100 Figure 11. Large Signal Frequency Response vs. Supply Voltage 8 –8 10 FREQUENCY (MHz) 10186-009 –5 VS = ±1.5V VS = ±2.5V 1 Figure 10. Small Signal Frequency Response vs. Temperature VOUT = 100mV p-p 2 VOUT = 400mV p-p 1 0 –1 VOUT = 2V p-p –2 –3 VOUT = 1V p-p –4 –5 0.1 1 10 100 1000 FREQUENCY (MHz) Figure 13. Frequency Response for Various Output Voltages Rev. B | Page 10 of 24 10186-008 NORMALIZED CLOSED-LOOP GAIN (dB) 2 NORMALIZED CLOSED-LOOP GAIN (dB) VS = ±1.5V VS = ±2.5V 10186-010 3 Data Sheet ADA4895-1/ADA4895-2 4 4 0 ADA4895-1, SOIC –2 –4 –6 –8 1000 FREQUENCY (MHz) –4 –6 –8 Figure 14. Small Signal Frequency Response vs. Package CL = 6pF 1000 120 0 110 –20 4 –40 100 CL = 3pF GAIN 90 2 0 –60 –80 80 CL = 0pF GAIN (dB) NORMALIZED CLOSED-LOOP GAIN (dB) 100 Figure 17. Large Signal Frequency Response vs. Package 6 –2 PHASE 70 –100 60 –120 50 –140 40 –160 30 –180 20 –200 10 –220 –4 –6 –8 VOUT = 200mV p-p 1 10 100 1000 FREQUENCY (MHz) –40 1M 10M 100M 1G VOUT = 2V p-p –50 –50 HD2, RL = 100Ω –60 DISTORTION (dBc) HD2, RL = 1kΩ –70 –80 HD3, RL = 1kΩ –90 HD3, RL = 100Ω –100 –70 –80 HD2 VS = ±5V VS = ±2.5V VS = ±1.5V –90 HD3 –100 –110 –110 –120 1 10 FREQUENCY (MHz) 10186-012 –120 0.1 100k Figure 18. Open-Loop Gain and Phase vs. Frequency VOUT = 2V p-p –60 10k FREQUENCY (Hz) Figure 15. Small Signal Frequency Response vs. Capacitive Load –40 –240 0 1k 10186-011 –10 0.1 DISTORTION (dBc) 10 FREQUENCY (MHz) PHASE (Degrees) 100 ADA4895-1, SOIC –2 10186-017 10 0 VOUT = 2V p-p –10 0.1 1 VOUT = 200mV p-p 1 ADA4895-1, SOT-23 Figure 16. Harmonic Distortion vs. Frequency for Various Loads –130 0.1 VS = ±5V VS = ±2.5V VS = ±1.5V 1 10 FREQUENCY (MHz) Figure 19. Harmonic Distortion vs. Frequency for Various Supplies Rev. B | Page 11 of 24 10186-016 –10 0.1 ADA4895-2, MSOP 2 10186-141 NORMALIZED CLOSED-LOOP GAIN (dB) ADA4895-1, SOT-23 2 10186-138 NORMALIZED CLOSED-LOOP GAIN (dB) ADA4895-2, MSOP ADA4895-1/ADA4895-2 –20 –20 VOUT = 2V p-p G = +20 VS = ±5.0V RG = 27.4Ω 8V p-p 4V p-p –40 RL = 100Ω HD2 DISTORTION (dBc) –40 DISTORTION (dBc) Data Sheet RL = 1kΩ –60 –80 HD3 2V p-p HD2 HD3 –80 8V p-p –100 4V p-p RL = 100Ω –100 –60 2V p-p –120 FREQUENCY (MHz) Figure 20. Harmonic Distortion vs. Frequency, G = +20 100 INPUT CURRENT NOISE (pA/√Hz) 4 3 2 1 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) RF = 10kΩ RG = 1.1kΩ RS = 1kΩ 10 1 1 0.15 0.20 0.15 10k 100k 1M VOUT = 200mV p-p CL = 5.6pF CL = 3.3pF CL = 0pF OUTPUT VOLTAGE (V) 0.10 0.05 0 –0.05 –0.10 0.05 0 –0.05 –0.10 –0.15 –0.15 TIME (5ns/DIV) Figure 22. Small Signal Transient Response for Various Supplies 10186-021 OUTPUT VOLTAGE (V) 0.10 –0.20 1k Figure 24. Input Current Noise vs. Frequency VOUT = 200mV p-p VS = ±1.5V VS = ±2.5V VS = ±5.0V 100 FREQUENCY (Hz) Figure 21. Input Voltage Noise vs. Frequency 0.20 10 –0.20 TIME (5ns/DIV) 10186-023 0 10 Figure 23. Harmonic Distortion vs. Frequency for Various Output Voltages VS = ±5V G = +25.9 RF = 249Ω RG = 10Ω 5 1 FREQUENCY (MHz) 10186-018 INPUT VOLTAGE NOISE (nV/√Hz) 6 –140 0.1 10186-019 10 1 10186-013 –120 0.1 10186-015 RL = 1kΩ Figure 25. Small Signal Transient Response for Various Capacitive Loads Rev. B | Page 12 of 24 Data Sheet 0.20 ADA4895-1/ADA4895-2 0.15 1.5 VOUT = 200mV p-p ADA4895-2, MSOP ADA4895-1, SOIC ADA4895-2, MSOP 1.0 ADA4895-1, SOIC OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 0.10 0.05 0 –0.05 0.5 0 –0.5 –0.10 –1.0 10186-139 ADA4895-1, SOT-23 –0.20 TIME (5ns/DIV) TIME (5ns/DIV) Figure 26. Small Signal Transient Response vs. Package 10 9 Figure 29. Large Signal Transient Response vs. Package 1.5 AVERAGE = 154nV/°C STANDARD DEVIATION = 184nV /°C –40°C TO +125°C G = +10 VOUT = 2V p-p G = +20 1.0 OUTPUT VOLTAGE (V) 8 NUMBER OF SAMPLES ADA4895-1, SOT-23 VOUT = 2V p-p –1.5 10186-142 –0.15 7 6 5 4 3 2 0.5 0 –0.5 –1.0 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 VDRIFT (µV/°C) –1.5 10186-020 0 TIME (5ns/DIV) Figure 27. Input Offset Voltage Drift Distribution 3 Figure 30. Large Signal Transient Response for Various Gains 0.2 90ns RECOVERY TIME VOUT = 2V STEP 2 0.1 SETTLING TIME (%) 10 × VIN 1 0 –1 ERROR 0 –0.1 –3 TIME (100ns/DIV) –0.2 TIME (10ns/DIV) Figure 28. Output Overdrive Recovery Time Figure 31. Settling Time to 0.1% Rev. B | Page 13 of 24 10186-029 –2 10186-026 INPUT AND OUTPUT VOLTAGE (V) VOUT 10186-024 1 ADA4895-1/ADA4895-2 Data Sheet 0 0 –10 –20 –20 –30 –40 –40 –60 –70 CMRR (dB) PSRR (dB) –50 –VS = –2.5V ± 1V p-p –80 –90 –100 –60 +VS = 2.5V ± 1V p-p –80 –110 –120 –130 –100 0.01 0.1 10 1 100 FREQUENCY (MHz) –120 0.001 10186-031 –150 –160 0.001 0.01 Figure 32. PSRR vs. Frequency 800 0.1 1 10 100 FREQUENCY (MHz) 10186-030 –140 Figure 35. CMRR vs. Frequency 160 VOUT = 3V p-p POSITIVE SLOPE 140 750 RECOVERY TIME (ns) SLEW RATE (V/µs) 120 700 RISE 650 FALL NEGATIVE SLOPE 100 80 60 40 600 –20 0 20 60 40 80 100 120 TEMPERATURE (˚C) 0 10186-028 0 100 300 200 Figure 33. Slew Rate vs. Temperature 600 700 800 –10.8 VS = ±5.0V VS = ±5.0V 3.1 INPUT BIAS CURRENT (µA) –11.0 3.0 2.9 VS = ±2.5V 2.8 2.7 VS = ±1.5V –11.2 VS = ±2.5V –11.4 VS = ±1.5V –11.6 –11.8 2.6 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 10186-034 SUPPLY CURRENT (mA) 500 Figure 36. Output Overload Recovery Time vs. Overload Duration 3.2 2.5 –40 400 OVERLOAD DURATION (ns) Figure 34. Supply Current vs. Temperature for Various Supplies –12.0 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 37. Input Bias Current vs. Temperature for Various Supplies Rev. B | Page 14 of 24 10186-035 550 –40 10186-027 20 Data Sheet ADA4895-1/ADA4895-2 0.05 0 –20 0.04 VS = ±5.0V VS = ±1.5V 0.01 –60 –80 –100 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) –120 0.01 10186-033 –25 0.1 1 10 100 FREQUENCY (MHz) Figure 38. Input Offset Voltage vs. Temperature for Various Supplies 10186-036 VOS (mV) 0.02 0 –40 –40 CROSSTALK (dB) VS = ±2.5V 0.03 Figure 41. Crosstalk, OUT1 to OUT2 0 1M –20 100k DISABLED –40 ISOLATION (dB) OUTPUT IMPEDANCE (Ω) 10k 1k 100 10 1 –60 –80 –100 –120 –140 ENABLED 0.1 1 10 100 FREQUENCY (MHz) 1000 –180 0.01 DISABLE DISABLE 2.5 VOLTAGE (V) 2.0 1.5 OUTPUT –40°C +25°C –40°C 1.5 +25°C +125°C 1.0 0.5 +125°C 0 –0.5 TIME (1µs/DIV) OUTPUT –0.5 TIME (40ns/DIV) Figure 43. Output Turn-On Time vs. Temperature Figure 40. Output Turn-Off Time vs. Temperature Rev. B | Page 15 of 24 10186-037 0 10186-038 VOLTAGE (V) 100 3.0 2.0 0.5 10 Figure 42. Forward Isolation vs. Frequency 3.0 1.0 1 FREQUENCY (MHz) Figure 39. Output Impedance vs. Frequency 2.5 0.1 10186-039 0.1 10186-032 0.01 0.01 –160 ADA4895-1/ADA4895-2 Data Sheet THEORY OF OPERATION AMPLIFIER DESCRIPTION The ADA4895-1/ADA4895-2 amplifiers have an input noise of 1 nV/√Hz and consume 3 mA per amplifier from supply voltages of 3 V to 10 V. Using the Analog Devices XFCB3 process, the ADA4895-1/ADA4895-2 have a gain bandwidth product in excess of 1.5 GHz and are gain ≥ 10 stable, with an input structure that results in an extremely low input 1/f noise for a relatively high speed amplifier. The rail-to-rail output stage is designed to drive the heavy feedback load required to achieve an overall low output referred noise. The low input noise and high bandwidth of the ADA4895-1/ ADA4895-2 are achieved with minimal power penalty. For this reason, the maximum offset voltage of 350 µV and voltage drift of 0.15 µV/°C make the ADA4895-1/ADA4895-2 an excellent choice, even when the low noise performance of the amplifier is not needed. For any gain greater than 10, the closed-loop frequency response of a basic noninverting configuration can be approximated by Closed-Loop −3 dB Frequency = (GBP) × RG (RF + RG ) At differential voltages above approximately 0.7 V, the diode clamps begin to conduct. Too much current can cause damage due to excessive heating. If large differential voltages must be sustained across the input terminals, it is recommended that the current through the input clamps be limited to less than 10 mA. Series input resistors that are sized appropriately for the expected differential overvoltage provide the needed protection. The ESD clamps begin to conduct at input voltages that are more than 0.7 V above the positive supply or more than 0.7 V below the negative supply. If an overvoltage condition is expected, it is recommended that the fault current be limited to less than 10 mA. DISABLE OPERATION Figure 45 shows the ADA4895-1/ADA4895-2 power-down circuitry. If the DISABLEx pin is left unconnected, the base of the input PNP transistor is pulled high through the internal pull-up resistor to the positive supply and the device is turned on. Pulling the DISABLEx pin more than 2 V below the positive supply turns the device off, reducing the supply current to approximately 50 µA for a 5 V voltage supply. +VS IBIAS For inverting gain configurations, the source impedance must be considered when sizing RG to maintain the minimum stable gain. For gains lower than 10, see the Using the ADA4895-1/ADA4895-2 at a Gain < +10 section, or use the ADA4897-1/ADA4897-2, which is a unity-gain stable amplifier with 230 MHz bandwidth. ESD DISABLEx ESD TO AMPLIFIER BIAS The ADA4895-1/ADA4895-2 are fully protected from ESD events and can withstand human body model ESD events of 2.5 kV and charged-device model events of 1 kV with no measured performance degradation. The precision input is protected with an ESD network between the power supplies and diode clamps across the input device pair, as shown in Figure 44. +VS BIAS ESD ESD +IN ESD –VS Figure 45. DISABLEx Circuit The DISABLEx pin is protected by ESD clamps, as shown in Figure 45. Voltages beyond the power supplies cause these diodes to conduct. For protection of the DISABLEx pins, the voltage to these pins should not exceed 0.7 V beyond the supply voltage, or the input current should be restricted to less than 10 mA with a series resistor. –IN ESD 10186-040 –VS TO THE REST OF THE AMPLIFIER 10186-041 INPUT PROTECTION Figure 44. Input Stage and Protection Diodes Rev. B | Page 16 of 24 Data Sheet ADA4895-1/ADA4895-2 DC ERRORS The output error due to the input currents can be estimated as follows: Figure 46 shows a typical connection diagram and the major dc error sources. R R VOUTERROR = (RF|| RG ) × 1 + F × I B − − RS × 1 + F × I B + RG RG RF – VIN + + VOS – RG BIAS CURRENT CANCELLATION + VOUT – IB– RS To cancel the output voltage error due to unmatched bias currents at the inputs, Resistors RBP and RBN can be used (see Figure 47). 10186-042 – VIP + (5) IB+ RF RG Figure 46. Typical Connection Diagram and DC Error Sources The ideal transfer function (all error sources set to 0 and infinite dc gain) can be expressed as follows: × V IN RS Figure 47. Using RBP and RBN to Cancel Bias Current Error This equation reduces to the familiar forms for noninverting and inverting op amp gain expressions, as follows: To compensate for the unmatched bias currents at the two inputs, set Resistors RBP and RBN as shown in Table 10. For noninverting gain (VIN = 0 V), VOUT Table 10. Setting RBP and RBN to Cancel Bias Current Error R = 1 + F × VIP R G (2) For inverting gain (VIP = 0 V), − RF VOUT = RG RBP (1) 10186-043 R R VOUT = 1 + F × V IP − F R G RG RBN × VIN Value of RF||RG Greater Than RS Less Than RS (3) The total output voltage error is the sum of the errors due to the amplifier offset voltage and input currents. The output error due to the offset voltage can be estimated as follows: VOUTERROR = (4) V VCM V − VPNOM R V + P + OUT × 1 + F OFFSETNOM + CMRR PSRR A RG where: VOFFSETNOM is the offset voltage at the specified supply voltage, which is measured with the input and output at midsupply. VCM is the common-mode voltage. CMRR is the common-mode rejection ratio. VP is the power supply voltage. VPNOM is the specified power supply voltage. PSRR is the power supply rejection ratio. A is the dc open-loop gain. Rev. B | Page 17 of 24 Value of RBP (Ω) RF||RG − RS 0 Value of RBN (Ω) 0 RS − RF||RG ADA4895-1/ADA4895-2 Data Sheet NOISE CONSIDERATIONS Source resistance noise, amplifier voltage noise (ven), and the voltage noise from the amplifier current noise (iep × RS) are all subject to the noise gain term (1 + RF/RG). Note that with a 1 nV/√Hz input voltage noise and a 1.7 pA/√Hz input current noise, the noise contributions of the amplifier are relatively small for source resistances from approximately 50 Ω to 700 Ω. Figure 48 illustrates the primary noise contributors for the typical gain configurations. The total rms output noise is the root mean square of all the contributions. RF vn _ RG = 4kT × RG vn _ RF = 4kT × RF ven RG + vout_en – ien RS 10186-044 vn _ RS = 4kT × RS iep Figure 48. Noise Sources in Typical Gain Configurations Figure 49 shows the total RTI noise due to the amplifier vs. the source resistance. In addition, the value of the feedback resistors affects the noise. It is recommended that the value of the feedback resistors be maintained between 250 Ω and 1 kΩ to keep the total noise low. 500 The output noise spectral density can be calculated as follows: vout_en = ] 2 4kTRG + ien RF 2 where: k is Boltzmann’s constant. T is the absolute temperature (degrees Kelvin). RF and RG are the feedback network resistances, as shown in Figure 48. RS is the source resistance, as shown in Figure 48. iep and ien represent the amplifier input current noise spectral density (pA/√Hz). ven is the amplifier input voltage noise spectral density (nV/√Hz). Rev. B | Page 18 of 24 50 AMPLIFIER AND RESISTOR NOISE 5 SOURCE RESISTANCE NOISE AMPLIFIER NOISE 0.5 50 500 5k SOURCE RESISTANCE (Ω) Figure 49. RTI Noise vs. Source Resistance 50k 10186-045 [ R 2 4kTRS + iep RS 2 + ven2 + F R G 2 NOISE (nV/√Hz) R 4kTRF + 1 + F RG (6) 2 Data Sheet ADA4895-1/ADA4895-2 APPLICATIONS INFORMATION RO 50Ω RT 50Ω RF 200Ω R1 50Ω C1 60pF VOUT CL 150pF RG 50Ω VOUT = 30mV p-p VOUT = 250mV p-p 14 10186-046 VIN 17 Figure 50. Configuring the ADA4895-1/ADA4895-2 for a Gain of +5 Stable VOUT = 2V p-p 11 8 5 2 This circuit has a gain of +9 at high frequency and a gain of +5 at frequencies lower than the resonance frequency of 53 MHz (1/2πR1C1). With a noise gain of approximately +9 at high frequency, the total output noise increases unless an antialiasing filter is used to block the high frequency content. VS = ±5V G = +5 –1 0.1 1 10 100 1000 FREQUENCY (MHz) Figure 51. Frequency Response for G = +5 Table 11. Component Values Used with the ADA4895-1/ADA4895-2 for Gain < +10 Gain +5 +6 +7 +8 +9 RT (Ω) 49.9 49.9 49.9 49.9 49.9 R1 (Ω) 49.9 66.5 110 205 Not applicable C1 (pF) 60 45 27 15 Not applicable RG (Ω) 49.9 40.2 37.4 32.4 30.9 Rev. B | Page 19 of 24 RF (Ω) 200 200 226 226 249 RO (Ω) 49.9 49.9 49.9 49.9 49.9 CL (pF) 150 150 150 120 100 10186-047 The ADA4895-1/ADA4895-2 are minimum gain 10 stable when used in normal gain configurations. However, the ADA4895-1/ ADA4895-2 can be configured to work at lower gains down to a gain of +5. Figure 50 shows how to add a simple RC circuit (R1 = 49.9 Ω and C1 = 60 pF) to allow the ADA4895-1/ADA4895-2 to operate at a gain of +5. Figure 51 shows the small and large signal frequency response of the circuit shown in Figure 50 into a 50 Ω analyzer (G = +5 V/V or 14 dB). As shown in Figure 51, the circuit is very stable, and the peaking is a little over 2 dB. This configuration is scalable to accommodate any gain from +5 to +10, as shown in Table 11. CLOSED-LOOP GAIN (dB) USING THE ADA4895-1/ADA4895-2 AT A GAIN < +10 ADA4895-1/ADA4895-2 Data Sheet HIGH GAIN BANDWIDTH APPLICATION FEEDBACK CAPACITOR APPLICATION The circuit in Figure 52 shows cascaded dual amplifier stages using the ADA4895-1/ADA4895-2. Each stage has a gain of +10 (20 dB), making the output 100 times (40 dB) the input. The total gain bandwidth product is approximately 9 GHz with the device operating on 6 mA of quiescent current (3 mA per amplifier). For applications where frequency response flatness is necessary, or a larger feedback resistor value is desired, a small feedback capacitor in parallel with the feedback resistor can be used to reduce peaking and increase flatness. RF 226Ω RG 25.5Ω CF 2pF C1 5pF RL 1kΩ RF 226Ω RG 25.5Ω 6 VOUT CF 2pF Figure 52. Cascaded Amplifier Stages for High Gain Applications (G = +100) Figure 53 shows the large signal frequency response for two cases. The first case is with installed feedback capacitors (CF = 2 pF), and the second case is without these capacitors. Removing the 2 pF feedback capacitors from this circuit increases the bandwidth, but adds about 0.5 dB of peaking. NORMALIZED CLOSED-LOOP GAIN (dB) RT 50Ω Figure 54 shows the small signal frequency response with and without a feedback capacitor. 44 NO CF GAIN (dB) RF = 499Ω, CF = 1pF RF = 1kΩ, CF = 0.5pF –3 –6 –9 –12 1 10 100 24 20 16 12 100 1000 FREQUENCY (MHz) 10186-049 8 10 1000 Figure 54. Small Signal Frequency Response With and Without a Feedback Capacitor CF = 2pF 28 4 VOUT = 2V p-p G = +100 0 0.1 1 0 RF = 449Ω FREQUENCY (MHz) 36 32 3 –15 40 RF = 1kΩ VS = ±2.5V VOUT = 200mV p-p RL = 1kΩ G = +10 ADA4895-1 SOIC 10186-153 R1 249Ω 10186-048 VIN Figure 53. Large Signal Frequency Response, G = +100, VS = ±5 V To better balance the second stage and remove the current offset contribution, an R1C1 circuit can be sized to correct for any mis-match between the source impedance and the feedback network impedance on the input amplifier. (In the example shown in Figure 52, R1 = 249 Ω and C1 = 5 pF.) The offset of each amplifier is within the same statistical range. As configured, the offset of the output amplifier is not statistically significant to the overall offset of the system. Figure 53 was captured using a ±5 V supply; however, this circuit also operates with supplies from ±1.5 V to ±5 V as long as the input and output headroom values are not violated. Rev. B | Page 20 of 24 Data Sheet ADA4895-1/ADA4895-2 WIDEBAND PHOTOMULTIPLIER PREAMPLIFIER A decompensated amplifier can provide significantly greater speed in transimpedance applications than a unity-gain stable amplifier. The speed increases by the square root of the ratio of the bandwidth of the two amplifiers; that is, a 1 GHz GBP amplifier is 10 times faster than a 10 MHz amplifier in the same transimpedance application if all other parameters are kept constant. Additionally, the input voltage noise normally dominates the total output rms noise because it is multiplied by the capacitive noise gain network. C S C M CF CD CF In the case of the ADA4895-1/ADA4895-2, the input noise is low, but the capacitive noise gain network must be kept greater than 10 for stability reasons. RF and the total capacitance produce a pole in the loop transmission of the amplifier that can result in peaking and instability. Adding CF creates a zero in the loop transmission that compensates for the pole effect and reduces the signal bandwidth. It can be shown that the signal bandwidth resulting in a 45° phase margin (f(45)) is defined as follows: GBP 2π RF CS f 45 where: GBP is the gain bandwidth product. RF is the feedback resistance. CS is the total capacitance at the amplifier summing junction (amplifier + photomultiplier + board parasitics). The value of CF that produces f(45) is One disadvantage of using the ADA4895-1/ADA4895-2 in transimpedance applications is that the input current and input current noise can create large offsets and output voltage noise when coupled with an excessively high feedback resistance. Despite these two issues, the ADA4895-1/ADA4895-2 noise and gain bandwidth can provide a significant increase in performance within certain transimpedance ranges. Figure 55 shows an I/V converter with an electrical model of a photomultiplier. CF CS 2π RF GBP The frequency response in this case shows approximately 2 dB of peaking and 15% overshoot. Doubling CF and reducing the bandwidth by half results in a flat frequency response with approximately 5% transient overshoot. The output noise over frequency for the preamplifier is shown in Figure 56. CF f1 = 2 π R RF 1 F (CS + CM + CF + CD) 1 VOUT CD RSH + CM CF + CS RF 10186-050 VB RF NOISE f2 ven (CS + CM + CF + CD)/CF f3 f1 Figure 55. Wideband Photomultiplier Preamplifier ven The basic transfer function is VOUT GBP f3 = (C + C + C + C )/C S M F D F NOISE DUE TO AMPLIFIER I PHOTO RF 10186-051 CM CS IPHOTO VOLTAGE NOISE (nV/ Hz) – f2 = 2 π R C F F FREQUENCY (Hz) 1 sCF RF Figure 56. Photomultiplier Voltage Noise Contributions where IPHOTO is the output current of the photomultiplier, and the parallel combination of RF and CF sets the signal bandwidth. Table 12. RMS Noise Contributions of Photomultiplier Preamplifier The stable bandwidth attainable with this preamplifier is a function of RF, the gain bandwidth product of the amplifier, and the total capacitance at the summing junction of the amplifier, including CS and the amplifier input capacitance. Contributor RF Amplifier ven Amplifier ien Rev. B | Page 21 of 24 Expression 4kT RF f 2 1.57 ven CS C M CF C D ien RF CF f 2 1.57 f 3 1.57 ADA4895-1/ADA4895-2 Data Sheet LAYOUT CONSIDERATIONS To ensure optimal performance, careful and deliberate attention must be paid to the board layout, signal routing, power supply bypassing, and grounding. Ground Plane It is important to avoid ground in the areas under and around the input and output of the ADA4895-1/ADA4895-2. Stray capacitance created between the ground plane and the input and output pads of a device is detrimental to high speed amplifier performance. Stray capacitance at the inverting input, along with the amplifier input capacitance, lowers the phase margin and can cause instability. Stray capacitance at the output creates a pole in the feedback loop, which can reduce phase margin and can cause the circuit to become unstable. Power Supply Bypassing Power supply bypassing is a critical aspect in the performance of the ADA4895-1/ADA4895-2. A parallel connection of capacitors from each power supply pin to ground works best. Smaller value capacitor electrolytics offer better high frequency response, whereas larger value capacitor electrolytics offer better low frequency performance. Paralleling different values and sizes of capacitors helps to ensure that the power supply pins are provided with low ac impedance across a wide band of frequencies. This is important for minimizing the coupling of noise into the amplifier—especially when the amplifier PSRR begins to roll off—because the bypass capacitors can help lessen the degradation in PSRR performance. Place the smallest value capacitor on the same side of the board as the amplifier and as close as possible to the amplifier power supply pins. Connect the ground end of the capacitor directly to the ground plane. It is recommended that a 0.1 µF ceramic capacitor with a 0508 case size be used. The 0508 case size offers low series inductance and excellent high frequency performance. Place a 10 µF electrolytic capacitor in parallel with the 0.1 µF capacitor. Depending on the circuit parameters, some enhancement to performance can be realized by adding additional capacitors. Each circuit is different and should be analyzed individually for optimal performance. Rev. B | Page 22 of 24 Data Sheet ADA4895-1/ADA4895-2 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 5.15 4.90 4.65 6 1 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.70 0.55 0.40 0.23 0.13 6° 0° 0.30 0.15 091709-A 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 57. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 1 5 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 58. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. B | Page 23 of 24 012407-A 8 4.00 (0.1574) 3.80 (0.1497) ADA4895-1/ADA4895-2 Data Sheet 3.00 2.90 2.80 1.70 1.60 1.50 6 5 4 1 2 3 3.00 2.80 2.60 PIN 1 INDICATOR 0.95 BSC 1.90 BSC 1.45 MAX 0.95 MIN 0.15 MAX 0.05 MIN 0.50 MAX 0.30 MIN 0.20 MAX 0.08 MIN SEATING PLANE 10° 4° 0° 0.60 BSC 0.55 0.45 0.35 12-16-2008-A 1.30 1.15 0.90 COMPLIANT TO JEDEC STANDARDS MO-178-AB Figure 59. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADA4895-1ARZ ADA4895-1ARZ-R7 ADA4895-1ARZ-RL ADA4895-1ARJZ-R2 ADA4895-1ARJZ-R7 ADA4895-1AR-EBZ ADA4895-1ARJ-EBZ ADA4895-2ARMZ ADA4895-2ARMZ-R7 ADA4895-2ARMZ-RL ADA4895-2ARM-EBZ 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 6-Lead SOT-23 6-Lead SOT-23 Evaluation Board for the 8-Lead SOIC_N Evaluation Board for the 6-Lead SOT-23 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] Evaluation Board Z = RoHS Compliant Part. ©2012–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10186-0-4/15(B) Rev. B | Page 24 of 24 Package Option R-8 R-8 R-8 RJ-6 RJ-6 Ordering Quantity 98 1,000 2,500 250 3,000 RM-10 RM-10 RM-10 50 1,000 3,000 Branding H3D H3D H35 H35 H35