ESD7008, SZESD7008 ESD Protection Diodes Low Capacitance ESD Protection for High Speed Data The ESD7008 ESD protection diode is designed specifically to protect four high speed differential pairs. Ultra−low capacitance and low ESD clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. The flow−through style package allows for easy PCB layout and matched trace lengths necessary to maintain consistent impedance for the high speed lines. Features • • • • • • • Integrated 4 Pairs (8 Lines) High Speed Data Single Connect, Flow through Routing Low Capacitance (0.12 pF Typical, I/O to GND) Protection for the Following IEC Standards: IEC 61000−4−2 Level 4 UL Flammability Rating of 94 V−0 SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable This is a Pb−Free Device Typical Applications • • • • • • V−by−One HS Thunderbolt (Light Peak) USB 3.0 HDMI Display Port LVDS www.onsemi.com MARKING DIAGRAM 18 1 7008MG G UDFN18 CASE 517BV 7008 M G = Specific Device Code = Date Code = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device Package Shipping ESD7008MUTAG UDFN18 (Pb−Free) 3000 / Tape & Reel SZESD7008MUTAG UDFN18 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Operating Junction Temperature Range TJ −55 to +125 °C Storage Temperature Range Tstg −55 to +150 °C Lead Solder Temperature − Maximum (10 Seconds) TL 260 °C ESD ESD ±15 ±15 kV kV IEC 61000−4−2 Contact (ESD) IEC 61000−4−2 Air (ESD) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. See Application Note AND8308/D for further description of survivability specs. © Semiconductor Components Industries, LLC, 2016 August, 2016 − Rev. 6 1 Publication Order Number: ESD7008/D ESD7008, SZESD7008 I/O Pin 1 I/O Pin 2 GND Pin 3 I/O Pin 4 GND Pin 6 I/O Pin 5 I/O Pin 7 GND Pin 9 I/O Pin 8 GND Pin 13 I/O Pin 10 GND Pin 15 Note: Only Minimum of 1 GND connection required = Figure 1. Pin Schematic I/O 1 I/O 2 GND 3 I/O 4 I/O 5 GND 6 I/O 7 I/O 8 GND 9 I/O 10 I/O 11 18 N/C 17 GND 16 N/C N/C 15 GND 14 N/C N/C N/C 13 GND 12 N/C Figure 2. Pin Configuration Note: Only minimum of one pin needs to be connected to ground for functionality of all pins. All pins labeled “N/C” should have no electrical connection. www.onsemi.com 2 I/O Pin 11 GND Pin 17 ESD7008, SZESD7008 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Symbol Reverse Working Voltage VRWM Breakdown Voltage VBR Conditions Min Typ Max Unit 5.0 V I/O Pin to GND (Note 1) IT = 1 mA, I/O Pin to GND 5.5 6.7 V Reverse Leakage Current IR VRWM = 5 V, I/O Pin to GND 1.0 mA Clamping Voltage (Note 1) VC IPP = 1 A, I/O Pin to GND (8 x 20 ms pulse) 10 V Clamping Voltage (Note 2) VC IEC61000−4−2, ±8 kV Contact Clamping Voltage TLP (Note 3) See Figures 8 through 11 VC IPP = ±8 A IPP = ±16 A 13.2 18.2 Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins and GND 0.12 Junction Capacitance Difference DCJ VR = 0 V, f = 1 MHz between I/O Pins and GND 0.02 See Figures 3 and 4 V 0.15 pF pF 1. Surge current waveform per Figure 7. 2. For test procedure see Figures 5 and 6 and application note AND8307/D. 3. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns. 90 0 80 −10 60 VOLTAGE (V) VOLTAGE (V) 70 50 40 30 −20 −30 20 10 −40 0 −10 −20 0 20 40 60 80 TIME (ns) 100 120 −50 −20 140 Figure 3. IEC61000−4−2 +8 KV Contact Clamping Voltage 0 20 40 60 80 TIME (ns) 100 120 Figure 4. IEC61000−4−2 −8 KV Contact Clamping Voltage www.onsemi.com 3 140 ESD7008, SZESD7008 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 5. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 6. Diagram of ESD Clamping Voltage Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger % OF PEAK PULSE CURRENT 100 PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 7. 8 X 20 ms Pulse Waveform www.onsemi.com 4 80 22 −22 20 −20 18 −18 16 −16 CURRENT (A) CURRENT (A) ESD7008, SZESD7008 14 12 10 8 −14 −12 −10 −8 6 −6 4 −4 2 −2 0 0 2 4 6 8 10 12 14 16 18 20 0 22 0 2 4 6 8 10 12 14 16 18 VOLTAGE (V) VOLTAGE (V) Figure 8. Positive TLP I−V Curve Figure 9. Negative TLP I−V Curve Transmission Line Pulse (TLP) Measurement L Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 10. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 11 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I−V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. 10 MW IM VM DUT VC Oscilloscope Figure 10. Simplified Schematic of a Typical TLP System Figure 11. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms www.onsemi.com 5 22 50 W Coax Cable S Attenuator ÷ 50 W Coax Cable 20 ESD7008, SZESD7008 Without ESD With ESD7008 Figure 12. HDMI1.4 Eye Diagram with and without ESD7008. 3.4 Gb/s, 400 mVPP Without ESD With ESD7008 Figure 13. USB3.0 Eye Diagram with and without ESD7008. 5.0 Gb/s, 400 mVPP Without ESD With ESD7008 Figure 14. Thunderbolt Eye Diagram with and without ESD7008. 10 Gb/s, 400 mVPP www.onsemi.com 6 ESD7008, SZESD7008 S21 INSERTION LOSS (dB) 4 2 ESD7008 IO−GND 0 −2 −4 −6 −8 −10 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 FREQUENCY (Hz) Figure 15. ESD7008 Insertion Loss USB 3.0 Type A Connector StdA_SSTX+ Vbus ESD7008 N/C StdA_SSTX− N/C D− N/C Vbus GND_DRAIN N/C Iden or N/C N/C D+ N/C StdA_SSRX+ N/C GND StdA_SSRX− Figure 16. USB3.0 Layout Diagram www.onsemi.com 7 ESD7008, SZESD7008 Thunderbolt Connector ESD9X GND Hot Plug Detect D3− CONFIG1 ESD7008 D3+ CONFIG2 GND GND D2− D0− D2+ D0+ GND GND D1− AUX_CH+ D1+ AUX_CH− GND DP_PWR CONFIG 1 AUX_CH+ CONFIG 2 NUP4114 Figure 17. Thunderbolt Layout Diagram www.onsemi.com 8 ESD7008, SZESD7008 HDMI Type A Connector ESD7008 D 2+ GND D 2− D 1+ GND D 1− D 0+ GND D 0− CLK + GND CLK − CEC N/ C (or HEC _DAT – HDMI 1.4) SCL SDA GND 5V HPD (and HEC _DAT – HDMI 1.4) NUP4114 Figure 18. HDMI Layout Diagram V−by−One HS Connector Timing Controller ESD7008 Figure 19. V−by−One HS Layout Diagram (for LCD Panel) www.onsemi.com 9 ESD7008, SZESD7008 PACKAGE DIMENSIONS UDFN18, 5.5x1.5, 0.5P CASE 517BV ISSUE A L2 D PIN ONE REFERENCE 0.10 C 2X ÉÉ 0.10 C 2X L L1 E DETAIL A OPTIONAL CONSTRUCTIONS TOP VIEW (A3) DETAIL B 0.05 C A NOTE 4 A1 SIDE VIEW C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.10 AND 0.20 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. EXPOSED ENDS OF TERMINALS ARE ELECTRICALLY ACTIVE. ÉÉ ÇÇ ÇÇ EXPOSED Cu 0.10 C DETAIL A L A B DIM A A1 A3 b D D2 E E2 eA eB L L1 L2 MOLD CMPD DETAIL B SEATING PLANE OPTIONAL CONSTRUCTION D2 eA 1 18 11 NOTE 5 E2 12 eB 18X BOTTOM VIEW MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.15 0.25 5.50 BSC 0.45 0.55 1.50 BSC 0.35 0.45 0.50 BSC 0.75 BSC 0.20 0.40 0.00 0.05 0.10 REF RECOMMENDED SOLDERING FOOTPRINT* L b 0.10 M C A B 0.05 M C 1.50 PITCH END VIEW NOTE 3 3X 0.75 PITCH 0.60 18X 0.50 3X 0.50 1.80 0.50 PITCH 18X 0.30 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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