FEATURES FUNCTIONAL BLOCK DIAGRAM 2 pF off capacitance 1 pC charge injection 33 V supply range 120 Ω on resistance Fully specified at +12 V, ±15 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 16-lead TSSOP and 12-lead LFCSP packages Typical power consumption: <0.03 µW ADG1236 S1A D1 S1B IN1 IN2 S2A D2 S2B APPLICATIONS SWITCHES SHOWN FOR A LOGIC 1 INPUT Automatic test equipment Data aquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Communication systems 04776-0-001 Preliminary Technical Data 2 pF Off Capacitance, 1 pC Charge Injection, ±15 V/12 V iCMOS™ Dual SPDT Switch ADG1236 Figure 1. GENERAL DESCRIPTION The ADG1236 is a monolithic CMOS device containing two independently selectable SPDT switches. It is designed on an iCMOS process. iCMOS (industrial-CMOS) is a modular manufacturing process combining high voltage CMOS (complementary metal-oxide semiconductor) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 30 V operation in a footprint that no previous generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages, while providing increased performance, dramatically lower power consumption, and reduced package size. The ultralow capacitance and charge injection of the part make it an ideal solution for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. Fast switching speed coupled with high signal bandwidth make the part suitable for video signal switching. iCMOS construction ensures ultralow power dissipation, making the part ideally suited for portable and battery-powered instruments. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. Both switches exhibit break-before-make switching action for use in multiplexer applications. PRODUCT HIGHLIGHTS 1. 2 pF off capacitance (±15 V supply). 2. 1 pC charge injection. 3. 3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V. 4. No VL logic power supply required. 5. Ultralow power dissipation: <0.03 µW. 6. 16-lead TSSOP and 12-lead 3 mm × 3 mm LFCSP packages. Rev. PrD Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. ADG1236 Preliminary Technical Data TABLE OF CONTENTS Specifications..................................................................................... 3 Pin Configurations and Function Descriptions ............................7 Dual Supply ................................................................................... 3 Terminology .......................................................................................8 Single Supply ................................................................................. 4 Typical Performance Characteristics ..............................................9 Absolute Maximum Ratings............................................................ 6 Test Circuits..................................................................................... 12 Truth Table For Switches ............................................................. 6 Outline Dimensions ....................................................................... 14 ESD Caution.................................................................................. 6 Ordering Guide .......................................................................... 14 REVISION HISTORY 11/04—Revision PrD: Preliminary Version Rev. PrD | Page 2 of 16 Preliminary Technical Data ADG1236 SPECIFICATIONS DUAL SUPPLY VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameters ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match between Channels (∆RON) On Resistance Flatness (RFLAT(ON)) 25°C 120 5 85°C 220 Y Version1 Unit VDD to VSS V Ω typ Ω max Ω typ 260 25 50 LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH ±0.01 ±0.5 ±0.01 ±0.5 ±0.04 ±1 ±1 ±5 ±1 ±5 ±2 ±5 2.0 0.8 0.005 ±0.5 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS2 tON 5 50 tOFF 20 100 Break-before-Make Time Delay, tD 15 40 1 Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise −3 dB Bandwidth CS (Off) CD(Off) CD, CS (On) POWER REQUIREMENTS IDD 1 75 85 0.002 700 2 2 5 0.001 5.0 IDD 150 300 ISS 0.001 5.0 Rev. PrD | Page 3 of 16 Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max V min V max µA typ µA max pF typ ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ pF typ pF typ pF typ µA typ µA max µA typ µA max µA typ µA max Test Conditions/Comments VS = ±10 V, IS = −10 mA; Figure 21 VS = ±10 V, IS = −10 mA VS = −5 V/0 V/+5 V; IS = −10 mA VDD = +10 V, VSS = −10 V VS = 0 V/10 V, VD = 10 V/0 V; Figure 22 VS = 0 V/10 V, VD = 10 V/0 V; Figure 22 VS = VD = 0 V or 10 V; Figure 23 VIN = VINL or VINH RL = 50 Ω, CL = 35 pF VS = ±10 V; Figure 24 RL = 50 Ω, CL = 35 pF VS = ±10 V; Figure 24 RL = 50 Ω, CL = 35 pF VS1 = VS2 = 10 V; Figure 25 VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 26 RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27 RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 28 RL = 600 Ω, 5 V rms, f = 20 Hz to 20 kHz RL = 50 Ω, CL = 5 pF; Figure 29 VDD = +16.5 V, VSS = −16.5 V Digital Inputs = 0 V or VDD Digital Input = 5 V Digital Inputs = 0 V or VDD ADG1236 Parameters IGND Preliminary Technical Data 25°C 0.001 85°C Y Version1 Unit µA typ µA max µA typ µA max Test Conditions/Comments Digital Inputs = 0 V or VDD Y Version1 Unit Test Conditions/Comments 0 V to VDD 5.0 IGND 150 300 1 2 Digital Input = 5 V Temperature range for Y Version is −40°C to +125°C. Guaranteed by design, not subject to production test. SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2. Parameters ANALOG SWITCH Analog Signal Range On Resistance (RON) 25°C 85°C On Resistance Match between Channels (∆RON) 10 V Ω typ Ω max Ω typ On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) 40 Ω max Ω typ Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 220 ±0.01 ±0.5 ±0.01 ±0.5 ±0.04 ±1 ±1 ±5 ±1 ±5 ±2 ±5 2.0 0.8 0.001 ±0.5 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS2 tON 5 50 tOFF 15 Break-before-Make Time Delay, tD 15 Charge Injection 5 Off Isolation Channel-to-Channel Crosstalk −3 dB Bandwidth CS (Off) CD (Off) CD, CS (On) 75 85 700 2 2 5 1 Rev. PrD | Page 4 of 16 nA typ nA max nA typ nA max nA typ nA max V min V max µA typ µA max pF typ ns typ ns max ns typ ns max ns typ ns min pC typ pC typ dB typ dB typ MHz typ pF typ pF typ pF typ VS = +10 V, IS = −10 mA; Figure 21 VS = +10 V, IS = −10 mA VS = +3 V/+6 V/+9 V, IS = −10 mA VDD = 12 V VS = 1 V/10 V, VD = 10 V/1 V; Figure 22 VS = 1 V/10 V, VD = 10 V/1 V; Figure 22 VS = VD = 1 V or 10 V, Figure 23 VIN = VINL or VINH RL = 50 Ω, CL = 35 pF VS = 8 V; Figure 24 RL = 50 Ω, CL = 35 pF VS = 8 V; Figure 24 RL = 50 Ω, CL = 35 pF VS1 = VS2 = 8 V; Figure 25 VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 26 RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27; RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 28 RL = 50 Ω, CL = 5 pF; Figure 29 Preliminary Technical Data Parameters POWER REQUIREMENTS IDD 25°C ADG1236 85°C Y Version1 0.001 5.0 IDD 150 300 1 2 Temperature range for Y Version is −40°C to +125°C. Guaranteed by design, not subject to production test. Rev. PrD | Page 5 of 16 Unit µA typ µA max µA typ µA max Test Conditions/Comments VDD = 13.2 V Digital Inputs = 0 V or VDD Digital Inputs = 5 V ADG1236 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs 1 Peak Current, S or D Continuous Current, S or D Operating Temperature Range Industrial (B Version) Automotive (Y Version) Storage Temperature Range Junction Temperature 16-Lead TSSOP, θJA Thermal Impedance 12-Lead LFCSP, θJA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 s) Infrared (15 s) 1 Ratings 38 V −0.3 V to +25 V +0.3 V to −25 V VSS − 0.3 V to VDD + 0.3 V GND − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 100 mA (pulsed at 1 ms, 10% duty cycle max) 30 mA −40°C to +85°C −40°C to +125°C −65°C to +150°C 150°C 150.4°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TRUTH TABLE FOR SWITCHES Table 4. IN 0 1 Switch A Off On TBD°C/W 215°C 220°C Over voltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrD | Page 6 of 16 Switch B On Off Preliminary Technical Data ADG1236 15 NC D1 3 14 NC NC 7 10 S2A NC 8 9 IN2 NC = NO CONNECT 04776-0-002 11 D2 Mnemonic IN1 S1A D1 S1B VSS GND NC IN2 S2A D2 S2B VDD ADG1236 8 S2B VSS 3 TOP VIEW (Not to Scale) 7 D2 Figure 3. LFCSP Pin Configuration Table 5. Pin Function Descriptions Pin No. TSSOP LFCSP 1 11 2 12 3 1 4 2 5 3 6 4 7, 8, 14–16 10 9 5 10 6 11 7 12 8 13 9 9 VDD S1B 2 NC = NO CONNECT Figure 2.TSSOP Pin Configuration PIN 1 INDICATOR Function Logic Control Input. Source Terminal. Can be an input or output. Drain Terminal. Can be an input or output. Source Terminal. Can be an input or output. Most Negative Power Supply Potential. Ground (0 V) Reference. No Connect. Logic Control Input. Source Terminal. Can be an input or output. Drain Terminal. Can be an input or output. Source Terminal. Can be an input or output. Most Positive Power Supply Potential. Rev. PrD | Page 7 of 16 04776-0-003 GND 6 D1 1 S2A 6 13 VDD TOP VIEW VSS 5 (Not to Scale) 12 S2B IN2 5 ADG1236 GND 4 S1B 4 11 IN1 16 NC 10 NC IN1 1 S1A 2 12 S1A PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADG1236 Preliminary Technical Data TERMINOLOGY IDD The positive supply current. CD (Off) The off switch drain capacitance, measured with reference to ground. ISS The negative supply current. CD, CS (On) The on switch capacitance, measured with reference to ground. VD (VS) The analog voltage on Terminals D and S. CIN The digital input capacitance. RON The ohmic resistance between D and S. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. tON The delay between applying the digital control input and the output switching on. See Figure 24. tOFF The delay between applying the digital control input and the output switching off. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. ID (Off) The drain leakage current with the switch off. Off Isolation A measure of unwanted signal coupling through an off switch. ID, IS (On) The channel leakage current with the switch on. VINL The maximum input voltage for Logic 0. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. VINH The minimum input voltage for Logic 1. Bandwidth The frequency at which the output is attenuated by 3 dB. IINL (IINH) The input current of the digital input. On Response The frequency response of the on switch. CS (Off) The off switch source capacitance, measured with reference to ground. Insertion Loss The loss due to the on resistance of the switch. Rev. PrD | Page 8 of 16 Preliminary Technical Data ADG1236 TYPICAL PERFORMANCE CHARACTERISTICS Figure 4. On Resistance as a Function of VD (VS) for Single Supply Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply Figure 5, On Resistance as a Function of VD (VS) for Dual Supply Figure 8, On Resistance as a Function of VD (VS) for Different Temperatures, Dual Supply Figure 6. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply Figure 9. Leakage Current as a Function of VD (VS) Rev. PrD | Page 9 of 16 ADG1236 Preliminary Technical Data Figure 10. Leakage Currents as a Function of VD (VS) Figure 13. Leakage Currents as a Function of Temperature Figure 11. Leakage Current as a Function of VD (VS) Figure 14. Supply Currents vs. Input Switching Frequency Figure 12. Leakage Currents as a Function of Temperature Figure 15. Charge Injection vs. Source Voltage Rev. PrD | Page 10 of 16 Preliminary Technical Data ADG1236 Figure 16. tON/tOFF Times vs. Temperature Figure 19. On Response vs. Frequency Figure 17. Off Isolation vs. Frequency Figure 20. THD + N vs. Frequency Figure 18. Crosstalk vs. Frequency Rev. PrD | Page 11 of 16 ADG1236 Preliminary Technical Data TEST CIRCUITS V A 04776-0-020 IDS VS VDD VSS VD 0.1µF D NC = NO CONNECT VIN 50% 50% VOUT VIN 50% 50% RL 50Ω IN CL 35pF GND 90% 90% VOUT tON tOFF 04776-0-023 D SA Figure 24. Test Circuit 4—Switching Times 0.1µF VDD VSS VDD VSS SB VS 0.1µF VIN D SA VOUT RL 50Ω IN VOUT CL 35pF 80% tBBM 04776-0-024 tBBM VIN GND Figure 25. Test Circuit 5—Break-before-Make Time Delay VDD VSS VDD VSS 0.1µF VIN (NORMALLY CLOSED SWITCH) ON SB VS VOUT SA CL 1nF IN VIN GND OFF NC D VIN (NORMALLY OPEN SWITCH) VOUT ∆VOUT QINJ = CL × ∆VOUT Figure 26. Test Circuit 6—Charge Injection Rev. PrD | Page 12 of 16 04776-0-025 0.1µF A VD Figure 23. Test Circuit 3—On Leakage VSS SB VIN S NC A Figure 22. Test Circuit 2— Off Resistance VDD VS D VS Figure 21. Test Circuit 1—On Resistance 0.1µF ID (ON) ID (OFF) S 04776-0-022 D 04776-0-021 IS (OFF) S Preliminary Technical Data ADG1236 VDD VDD VSS 0.1µF 0.1µF VDD NC SA IN NETWORK ANALYZER NETWORK ANALYZER VSS SB 50Ω VDD RL 50Ω 50Ω SB VS D VIN RL 50Ω OFF ISOLATION = 20 LOG GND CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG VS VOUT VS Figure 29. Test Circuit 9— Bandwidth Figure 27. Test Circuit 7—Off Isolation VDD R 50Ω VS 04776-0-026 VOUT D IN VOUT GND VSS SA VOUT 04776-0-028 0.1µF VSS 0.1µF VDD NC SA SB VDD NETWORK ANALYZER VSS VSS 0.1µF 0.1µF 50Ω AUDIO PRECISION VDD 50Ω VSS RS VS S D VIN RL 50Ω IN VOUT GND VOUT WITH SWITCH VOUT WITHOUT SWITCH 04776-0-027 VIN INSERTION LOSS = 20 LOG VS V p-p D RL 600Ω VOUT GND Figure 30. Test Circuit 10—THD + Noise Figure 28. Test Circuit 8—Channel-to-Channel Crosstalk Rev. PrD | Page 13 of 16 04776-0-029 0.1µF IN VSS 0.1µF ADG1236 Preliminary Technical Data OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153AB Figure 31. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in inches and (millimeters 3.00 BSC SQ 0.60 MAX 0.45 PIN 1 INDICATOR 0.75 0.55 0.35 9 2.75 BSC SQ TOP VIEW 10 11 12 8 12 MAX 1.00 0.85 0.80 *1.45 1 1.30 SQ 1.15 2 7 6 EXPOSED PAD (BOTTOM VIEW) PIN 1 INDICATOR 5 4 3 0.25 MIN 0.50 BSC 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1 EXCEPT FOR EXPOSED PAD DIMENSION. Figure 32. 12-Lead Lead Frame Chip Scale Package [VQ_LFCSP] 3 mm × 3 mm Body, Very Thin Quad (CP-12-1) Dimensions shown in millimeters ORDERING GUIDE Model ADG1236YRU ADG1236YCP Temperature Range −40°C to +125°C −40°C to +125°C Package Description Thin Shrink Small Outline Package (TSSOP) Lead Frame Chip Scale Package (LFCSP) Rev. PrD | Page 14 of 16 Package Option RU-16 CP-12-1 Preliminary Technical Data ADG1236 NOTES Rev. PrD | Page 15 of 16 ADG1236 Preliminary Technical Data NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR04776–0–11/04(PrD) Rev. PrD | Page 16 of 16