PulseCore ASM2P5T905A 2.5v single data rate 1:5 clock buffer terabuffer Datasheet

ASM2P5T905A
November 2006
rev 0.2
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Features
to five single-ended outputs buffer built on advanced metal
•
Guaranteed Low Skew < 25pS (max)
CMOS technology. The SDR Clock buffer fanout from a
•
Very low duty cycle distortion
single or differential input to five single-ended outputs
•
High speed propagation delay < 2.5nS. (max)
reduces the loading on the preceding driver and provides
•
Up to 250MHz operation
an efficient clock distribution network. The ASM2P5T905A
•
Very low CMOS power levels
can act as a translator from a differential HSTL, eHSTL,
•
1.5V VDDQ for HSTL interface
1.8V/2.5V LVTTL, LVEPECL or single-ended 1.8V/2.5V
•
Hot insertable and Over-voltage tolerant inputs
LVTTL input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs.
•
3 level inputs for selectable interface
Selectable interface is controlled by 3 level input signals
•
Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or
that may be hard-wired to appropriate high-mid-low levels.
LVEPECL input interface
Multiple power and grounds reduce noise.
•
Selectable differential or single-ended inputs and
five single ended outputs
•
2.5V Supply Voltage
•
Available in TSSOP Package
Applications:
ASM2P5T905A is targeted towards Clock and signal
distribution.
Functional Description
The ASM2P5T905A 2.5V single data rate (SDR) Clock
buffer is a user-selectable single-ended or differential input
Block Diagram
TxS
GL
G
RxS
OUTPUT
CONTROL
Q1
OUTPUT
CONTROL
Q2
OUTPUT
CONTROL
Q3
OUTPUT
CONTROL
Q4
OUTPUT
CONTROL
Q5
A
A/VREF
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
ASM2P5T905A
November 2006
rev 0.2
Pin Configuration
Top View-TSSOP Package
GL
1
28
GND
VDD
2
27
VDDQ
GND
3
26
GND
G
4
25
GND
VDDQ
5
24
VDDQ
Q1
6
23
Q2
A/VRE
7
22
GND
A
8
21
Q3
Q5
9
20
Q4
VDDQ
10
19
VDDQ
GND
11
18
GND
VDD
12
17
GND
VDD
13
16
VDDQ
RxS
14
15
TxS
ASM2P5T905A
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
2 of 19
ASM2P5T905A
November 2006
rev 0.2
Pin Description
Symbol
A
A / VREF
I/O
I
Type
Description
1
Adjustable
I
Adjustable1
G
I
LVTTL5
GL
I
LVTTL5
Qn
O
Adjustable2
RxS
I
3 Level3
TxS
I
3 Level3
VDD
PWR
VDDQ
PWR
GND
PWR
Clock input. A is the "true" side of the differential clock input. If operating in single-ended
mode, A is the clock input.
Complementary clock input. A / VREF is the "complementary" side of A if the input is in
differential mode. If operating in single-ended mode, A/VREF is connected to GND. For
single-ended operation in differential mode, A/VREFshould be set to the desired toggle
voltage for A:
2.5V LVTTL
VREF = 1250mV
1.8V LVTTL, eHSTL VREF = 900mV
HSTL
VREF= 750mV
LVEPECL
VREF= 1082mV
Gate control for Qn outputs. When G is LOW, these outputs are enabled. When G is
HIGH, these outputs are asynchronously disabled to the level designated by GL4.
Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs
disable LOW.
Clock outputs
Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) clock input or differential
(LOW) clock input
Sets the drive strength of the output drivers to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID)
or HSTL (LOW) compatible. Used in conjunction with VDDQ to set the interface levels.
Power supply for the device core and inputs
Power supply for the device outputs. When utilizing 2.5V LVTTL outputs, VDDQ should be
connected to VDD.
Power supply return for all power
NOTES: 1. Inputs are capable of translating the following interface standards. User can select between:
Single-ended 2.5V LVTTL levels
Single-ended 1.8V LVTTL levels
or
Differential 2.5V/1.8V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL levels
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQ voltage.
3. 3 level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are not hot-insertable or over-voltage tolerant.
4. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize
the possibility of runt pulses or be able to tolerate them in down stream circuitry.
5. Pins listed as LVTTL inputs will accept 2.5V signals when RxS = HIGH or 1.8V signals when RxS = LOW or MID.
Absolute Maximum Ratings1
Symbol
VDD
VDDQ
VI
VO
VREF
TSTG
TJ
Description
Power Supply Voltage2
Output Power Supply 2
Input Voltage
Output Voltage 3
Reference Voltage 3
Storage Temperature
Junction Temperature
Max
Unit
-0.5 to +3.6
-0.5 to +3.6
-0.5 to +3.6
-0.5 to VDDQ +0.5
-0.5 to +3.6
-65 to +165
150
V
V
V
V
V
°C
°C
Note:
1.These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device
reliability.
2. VDDQ and VDD internally operate independently. No power sequencing requirements need to be met.
3. Not to exceed 3.6V.
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
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ASM2P5T905A
November 2006
rev 0.2
Capacitance1,2 (TA = +25°C, F = 1.0MHz)
Symbol
CIN
Parameter
Min
Typ
Input Capacitance
Max
Unit
3.5
pF
Notes:
1. This parameter is measured at characterization but not tested.
2. Capacitance applies to all inputs except RxS and TxS.
Recommended Operating Range
Symbol
TA
Description
Ambient Operating Temperature
Min
Typ
Max
Unit
-40
+25
+85
°C
VDD1
Internal Power Supply Voltage
2.4
2.5
2.6
V
1.4
1.5
1.6
V
VDDQ1
HSTL Output Power Supply Voltage
Extended HSTL and 1.8V LVTTL Output Power
Supply Voltage
2.5V LVTTL Output Power Supply Voltage
1.65
1.8
1.95
V
VT
Termination Voltage
VDD
V
VDDQ/ 2
V
NOTE:
1. All power supplies should operate in tandem. If VDD or VDDQ is at maximum, then VDDQ or VDD (respectively) should be at maximum, and vice-versa.
Input/Output Selection1
Input
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
Output
2.5V LVTTL
1.8V LVTTL
Input
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
Output
eHSTL
HSTL
NOTE:
1. The INPUT/OUTPUT SELECTION Table describes the total possible combinations of input and output interfaces. Single-Ended (SE) inputs in a single-ended
mode require the A/VREF pin to be connected to GND. Differential Single-Ended (DSE) is for single-ended operation in differential mode, requiring a VREF.
Differential (DIF) inputs are used only in differential mode.
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
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ASM2P5T905A
November 2006
rev 0.2
DC Electrical Characteristics over Operating Range
Symbol
Parameter
Test Conditions
1
VIHH
VIMM
VILL
Input HIGH Voltage Level
Input MID Voltage Level1
Input LOW Voltage Level1
I3
3-Level Input DC Current
(RxS, TxS)
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
VIN= VDD
HIGH Level
VIN= VDD/2
MID Level
VIN= GND
Min
Max
VDD- 0.4
VDD/2- 0.2
VDD/2 + 0.2
0.4
200
+50
-50
LOW Level
Unit
V
V
V
µA
-200
NOTE:
1. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias unconnected inputs to VDD/2.
DC Electrical Characteristics over Operating Range for HSTL1
Symbol
Parameter
Input Characteristics
IIH
IIL
VIK
VIN
VDIF
VCM
VIH
VIL
VREF
Input HIGH Current9
Test Conditions
VDD= 2.6V
9
Input LOW Current
Clamp Diode Voltage
DC Input Voltage
DC Differential Voltage2,8
DC Common Mode Input
Voltage3,8
DC Input HIGH4,5,8
DC Input LOW4,6,8
Single-Ended Reference
4,8
Voltage
Min
Typ7
VI = VDDQ/GND
Max
±5
VDD= 2.6V
VI = GND/VDDQ
VDD= 2.4V, IIN = -18mA
µA
-0.7
±5
- 1.2
+3.6
750
900
mV
VREF-100
mV
mV
-0.3
0.2
680
Unit
VREF+ 100
750
V
V
V
mV
Output Characteristics
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
IOH= -8mA
VDDQ- 0.4
IOH= -100µA
IOL= 8mA
IOL= 100µA
VDDQ- 0.1
V
0.4
V
V
0.1
V
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input
level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential
voltage must be achieved to guarantee switching to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation, in differential mode, A/VREF is tied to the DC voltage VREF.
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at VDD = 2.5V, VDDQ = 1.5V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface
table should be referenced.
9. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
5 of 19
ASM2P5T905A
November 2006
rev 0.2
Power Supply Characteristics for HSTL Outputs1
Symbol
Test Conditions2
Parameter
Typ
Max
Unit
3
IDDQ
Quiescent VDD Power Supply
Current
VDDQ= Max., Reference Clock = LOW
Outputs enabled, All outputs unloaded
20
30
mA
IDDQQ
Quiescent VDDQ Power Supply
Current
VDDQ= Max., Reference Clock = LOW3
Outputs enabled, All outputs unloaded
0.1
0.3
mA
IDDD
Dynamic VDD Power Supply
Current per Output
VDD= Max., VDDQ= Max., CL= 0pF
10
20
µA/MHz
IDDDQ
Dynamic VDDQ Power Supply
Current per Output
VDD= Max., VDDQ= Max., CL= 0pF
15
30
µA/MHz
20
30
25
40
15
30
30
60
ITOT
ITOTQ
Total Power VDD Supply
Current
Total Power VDDQ Supply
Current
VDDQ= 1.5V, FREFERENCE CLOCK= 100MHz,
CL= 15pF
VDDQ= 1.5V, FREFERENCE CLOCK= 250MHz,
CL= 15pF
VDDQ= 1.5V, FREFERENCE CLOCK= 100MHz,
CL= 15pF
VDDQ= 1.5V, FREFERENCE CLOCK= 250MHz,
CL= 15pF
mA
mA
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
Differential Input AC Test Conditions for HSTL
Symbol
VDIF
VX
VTHI
tR, tF
Parameter
Value
1
Input Signal Swing
1
V
750
mV
Crossing Point
V
1
V/nS
Differential Input Signal Crossing Point2
Input Timing Measurement Reference Level3
Units
4
Input Signal Edge Rate
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in automatic test equipment (ATE) environment. Compliant devices
must meet the VDIF (AC) specification under actual use conditions.
2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must
meet the VX specification under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/nS or greater is to be maintained in the 20% to 80% range of the input waveform.
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
6 of 19
ASM2P5T905A
November 2006
rev 0.2
DC Electrical Characteristics over Operating Range for eHSTL1
Symbol
Parameter
Input Characteristics
IIH
Input HIGH Current9
9
IIL
Input LOW Current
VIK
Clamp Diode Voltage
VIN
DC Input Voltage
VDIF
VCM
VIH
VIL
VREF
Test Conditions
Min
Typ7
Max
VDD = 2.6V
VI = VDDQ/GND
±5
VDD = 2.6V
VI = GND/VDDQ
±5
VDD = 2.4V, IIN = -18mA
- 0.7
-0.3
2,8
DC Differential Voltage
DC Common Mode Input
3,8
Voltage
DC Input HIGH4,5,8
Unit
µA
- 1.2
V
+3.6
V
0.2
800
V
900
VREF+ 100
DC Input LOW4,6,8
Single-Ended Reference
4,8
Voltage
1000
mV
-
mV
VREF-100
mV
900
mV
Output Characteristics
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IOH= -8mA
VDDQ- 0.4
VDDQ- 0.1
IOH= -100µA
V
V
IOL= 8mA
IOL= 100µA
0.4
V
0.1
V
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input
level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential
voltage must be achieved to guarantee switching to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation, in a differential mode, A/VREF is tied to the DC voltage VREF.
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface
table should be referenced.
9. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
Power Supply Characteristics for eHSTL Outputs1
Symbol
IDDQ
IDDQQ
IDDD
IDDDQ
ITOT
ITOTQ
Parameter
Quiescent VDD Power Supply
Current
Quiescent VDDQ Power Supply
Current
Dynamic VDD Power Supply
Current per Output
Dynamic VDDQ Power Supply
Current per Output
Total Power VDD Supply
Current
Total Power VDDQ Supply
Current
Test Conditions2
Typ
Max
Unit
20
30
mA
0.1
0.3
mA
VDD= Max., VDDQ= Max., CL= 0pF
10
20
µA/MHz
VDD= Max., VDDQ= Max., CL= 0pF
20
30
µA/MHz
20
30
25
40
20
40
40
80
VDDQ= Max., Reference Clock = LOW3
Outputs enabled, All outputs unloaded
VDDQ= Max., Reference Clock = LOW3
Outputs enabled, All outputs unloaded
VDDQ= 1.8V, FREFERENCE CLOCK= 100MHz,
CL= 15pF
VDDQ= 1.8V, FREFERENCE CLOCK= 250MHz,
CL= 15pF
VDDQ= 1.8V, FREFERENCE CLOCK= 100MHz,
CL= 15pF
VDDQ= 1.8V, FREFERENCE CLOCK= 250MHz,
CL= 15pF
mA
mA
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
7 of 19
ASM2P5T905A
November 2006
rev 0.2
Differential Input AC Test Conditions for eHSTL
Symbol
VDIF
VX
Parameter
Value
Input Signal Swing1
Differential Input Signal Crossing Point2
VTHI
Input Timing Measurement Reference Level3
tR, tF
Input Signal Edge Rate4
Units
1
V
900
mV
Crossing Point
V
1
V/nS
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in automatic test equipment (ATE) environment. Compliant devices
must meet the VDIF (AC) specification under actual use conditions.
2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must
meet the VX specification under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/nS or greater is to be maintained in the 20% to 80% range of the input waveform.
DC Electrical Characteristics over Operating Range for LVEPECL1
Symbol
Parameter
Input Characteristics
IIH
IIL
VIK
VIN
VCM
VREF
VIH
VIL
Test Conditions
Input HIGH Current6
Input LOW Current6
Clamp Diode Voltage
DC Input Voltage
DC Common Mode Input
Voltage3,5
Single-Ended Reference
4,5
Voltage
DC Input HIGH
DC Input LOW
Typ2
Min
VDD= 2.6V
VI = VDDQ/GND
VDD= 2.6V
VI = GND/VDDQ
VDD= 2.4V, IIN = -18mA
- 0.7
- 0.3
915
1082
Max
±5
±5
- 1.2
3.6
1248
1082
1275
555
Unit
µA
V
V
mV
mV
1620
875
mV
mV
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. Typical values are at VDD = 2.5V, +25°C ambient.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation while in differential mode, A/VREF is tied to the DC voltage VREF.
5. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface
table should be referenced.
6. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
Differential Input AC Test Conditions for LVEPECL
Symbol
VDIF
VX
VTHI
tR, tF
Parameter
Value
1
Units
Input Signal Swing
732
mV
Differential Input Signal Crossing Point2
1082
mV
Crossing Point
V
1
V/nS
Input Timing Measurement Reference Level3
4
Input Signal Edge Rate
NOTES:
1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant
devices must meet the VDIF (AC) specification under actual use conditions.
2. A 1082mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must
meet the VX specification under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/nS or greater is to be maintained in the 20% to 80% range of the input waveform.
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
8 of 19
ASM2P5T905A
November 2006
rev 0.2
DC Electrical Characteristics over Operating Range for 2.5V LVTTL1
Symbol
Parameter
Input Characteristics
IIH
IIL
VIK
VIN
Input HIGH Current10
Input LOW Current10
Clamp Diode Voltage
DC Input Voltage
VIH
VIL
DC Input HIGH
DC Input LOW
Test Conditions
Min
VDD= 2.6V
VI = VDDQ/GND
VDD= 2.6V
VI = GND/VDDQ
VDD= 2.4V, IIN = -18mA
Typ8
- 0.7
-0.3
Max
Unit
±5
±5
- 1.2
+3.6
µA
V
V
Single-Ended Inputs2
1.7
V
V
0.7
Differential Inputs
VDIF
VCM
VIH
VIL
VREF
DC Differential Voltage3,9
DC Common Mode Input
4,9
Voltage
DC Input HIGH5,6,9
DC Input LOW5,7,9
Single-Ended Reference
5,9
Voltage
0.2
1150
V
1250
1350
mV
VREF- 100
mV
mV
VREF+ 100
1250
mV
Output Characteristics
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IOH= -12mA
IOH= -100µA
IOL= 12mA
IOL= 100µA
VDDQ- 0.4
VDDQ- 0.1
0.4
0.1
V
V
V
V
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. For 2.5V LVTTL single-ended operation, the RxS pin is tied HIGH and A/VREF is tied to GND.
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input
level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential
voltage must be achieved to guarantee switching to a new state.
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
5. For single-ended operation, in differential mode, A/VREF is tied to the DC voltage VREF.
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
8. Typical values are at VDD = 2.5V, VDDQ = VDD, +25°C ambient.
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface
table should be referenced.
10. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
9 of 19
ASM2P5T905A
November 2006
rev 0.2
Power Supply Characteristics for 2.5V LVTTL Outputs1
Symbol
IDDQ
IDDQQ
IDDD
IDDDQ
ITOT
ITOTQ
Parameter
Quiescent VDD Power Supply
Current
Quiescent VDDQ Power Supply
Current
Dynamic VDD Power Supply
Current per Output
Dynamic VDDQ Power Supply
Current per Output
Total Power VDD Supply
Current
Total Power VDDQ Supply
Current
Test Conditions2
Typ
Max
Unit
20
30
mA
0.1
0.3
mA
VDD= Max., VDDQ= Max., CL= 0pF
15
20
µA/MHz
VDD= Max., VDDQ= Max., CL= 0pF
30
40
µA/MHz
20
40
30
50
30
50
70
100
VDDQ= Max., Reference Clock = LOW3
Outputs enabled, All outputs unloaded
VDDQ= Max., Reference Clock = LOW3
Outputs enabled, All outputs unloaded
VDDQ= 2.5V, FREFERENCE CLOCK= 100MHz,
CL= 15pF
VDDQ= 2.5V, FREFERENCE CLOCK= 200MHz,
CL= 15pF
VDDQ= 2.5V, FREFERENCE CLOCK= 100MHz,
CL= 15pF
VDDQ= 2.5V, FREFERENCE CLOCK= 200MHz,
CL= 15pF
mA
mA
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
Differential Input AC Test Conditions for 2.5V LVTTL
Symbol
VDIF
VX
Parameter
1
Input Signal Swing
Differential Input Signal Crossing Point2
VTHI
Input Timing Measurement Reference Level
tR, tF
Input Signal Edge Rate4
3
Value
Units
VDD
V
VDD/2
V
Crossing Point
V
2.5
V/nS
NOTES:
1. A nominal 2.5V peak-to-peak input pulse level is specified to allow consistent, repeatable results in automatic test equipment (ATE) environment. Compliant
devices must meet the VDIF (AC) specification under actual use conditions.
2. A nominal 1.25V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices
must meet the VX specification under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2.5V/nS or greater is to be maintained in the 20% to 80% range of the input waveform.
Single-Ended Input AC Test Conditions for 2.5V LVTTL
Symbol
Parameter
Value
Units
VIH
Input HIGH Voltage
VDD
V
VIL
Input LOW Voltage
0
V
VTHI
Input Timing Measurement Reference Level
tR, tF
Input Signal Edge Rate2
1
VDD/2
V
2
V/nS
NOTES:
1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.
2. The input signal edge rate of 2V/nS or greater is to be maintained in the 10% to 90% range of the input waveform.
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
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DC Electrical Characteristics over Operating Range for 1.8V LVTTL1
Symbol
Parameter
Input Characteristics
Test Conditions
Min.
Typ8
Max
IIH
Input HIGH Current12
VDD = 2.6V
VI = VDDQ/GND
±5
IIL
Input LOW Current12
VDD = 2.6V
VI = GND/VDDQ
±5
VIK
Clamp Diode Voltage
DC Input Voltage
VDD = 2.4V, IIN= -18mA
VIN
-0.7
- 0.3
Unit
µA
- 1.2
V
VDDQ+ 0.3
V
0.68311
V
Single-Ended Inputs2
VIH
DC Input HIGH
VIL
DC Input LOW
1.07310
V
Differential Inputs
VDIF
VCM
VIH
VIL
VREF
DC Differential Voltage3,9
DC Common Mode Input
4,9
Voltage
DC Input HIGH5,6,9
0.2
825
V
900
975
mV
VREF- 100
mV
VREF+ 100
DC Input LOW5,7,9
Single-Ended Reference
5,9
Voltage
mV
900
mV
Output Characteristics
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IOH= -6mA
VDDQ- 0.4
IOH= -100µA
VDDQ- 0.1
IOL= 6mA
IOL= 100µA
V
V
0.4
V
0.1
V
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. For 1.8V LVTTL single-ended operation, the RxS pin is allowed to float or tied to VDD/2 and A/VREF is tied to GND.
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input
level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential
voltage must be achieved to guarantee switching to a new state.
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
5. For single-ended operation in differential mode, A/VREF is tied to the DC voltage VREF. The input is guaranteed to toggle within ±200mV of VREF when VREF is
constrained within +600mV and VDDI-600mV, where VDDI is the nominal 1.8V power supply of the device driving the A input. To guarantee switching in voltage
range specified in the JEDEC 1.8V LVTTL interface specification, VREF must be maintained at 900mV with appropriate tolerances.
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
8. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface
table should be referenced.
10. This value is the worst case minimum VIH over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIH = 0.65 • VDD where VDD
is 1.8V ±0.15V. However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator
was designed to accept the calculated worst case value (VIH = 0.65 • [1.8 - 0.15V]) rather than reference against a nominal 1.8V supply.
11. This value is the worst case maximum VIL over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIL = 0.35 • VDD where VDD
is 1.8V ± 0.15V. However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator
was designed to accept the calculated worst case value (VIH = 0.35 • [1.8 + 0.15V]) rather than reference against a nominal 1.8V supply.
12. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
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Power Supply Characteristics for 1.8V LVTTL Outputs1
Symbol
Test Conditions2
Parameter
Typ
Max
Unit
3
IDDQ
Quiescent VDD Power Supply
Current
VDDQ= Max., Reference Clock = LOW
Outputs enabled, All outputs unloaded
20
30
mA
IDDQQ
Quiescent VDDQ Power Supply
Current
VDDQ= Max., Reference Clock = LOW3
Outputs enabled, All outputs unloaded
0.1
0.3
mA
IDDD
Dynamic VDD Power Supply
Current per Output
VDD= Max., VDDQ= Max., CL= 0pF
20
30
µA/MHz
IDDDQ
Dynamic VDDQ Power Supply
Current per Output
VDD= Max., VDDQ= Max., CL= 0pF
20
30
µA/MHz
20
30
30
40
20
40
45
80
ITOT
ITOTQ
Total Power VDD Supply
Current
Total Power VDDQ Supply
Current
VDDQ= 1.8V, FREFERENCE CLOCK= 100MHz,
CL= 15pF
VDDQ= 1.8V, FREFERENCE CLOCK= 200MHz,
CL= 15pF
VDDQ= 1.8V, FREFERENCE CLOCK= 100MHz,
CL= 15pF
VDDQ= 1.8V, FREFERENCE CLOCK= 200MHz,
CL= 15pF
mA
mA
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
Differential Input AC Test Conditions for 1.8V LVTTL
Symbol
VDIF
VX
VTHI
tR, tF
Parameter
Value
1
Input Signal Swing
VDDI
V
VDDI /2
mV
Crossing Point
V
1.8
V/nS
Differential Input Signal Crossing Point2
Input Timing Measurement Reference Level3
Units
4
Input Signal Edge Rate
NOTES:
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input. A nominal 1.8V peak-to-peak input pulse level is specified to allow
consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use
conditions.
2. A nominal 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant
devices must meet the VX specification under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1.8V/nS or greater is to be maintained in the 20% to 80% range of the input waveform.
Single-Ended Input AC Test Conditions for 1.8V LVTTL
Symbol
Parameter
1
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VTHI
Input Timing Measurement Reference Level2
tR, tF
Input Signal Edge Rate3
Value
Units
VDDI
V
0
V
VDDI /2
mV
2
V/nS
NOTES:
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input.
2. A nominal 900mV timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.
3. The input signal edge rate of 2V/nS or greater is to be maintained in the 10% to 90% range of the input waveform.
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
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AC Electrical Characteristics over Operating Range6
Symbol
Parameter
Skew Parameters
tSK(O)
tSK(P)2
dT
4
tSK(PP)
1
Same Device Output Pin-to-Pin Skew
Pulse Skew3
Min
Typ
Single-Ended and Differential
Modes
Single-Ended in Differential
Mode (DSE)
Single-Ended and Differential
Modes
Single-Ended in Differential
Mode (DSE)
Duty Cycle
Max
25
pS
25
300
pS
300
-
40
60
Single-Ended and Differential
Modes
Single-Ended in Differential
Mode (DSE)
Part-to-Part Skew5
Unit
%
300
pS
300
Propagation Delay
tPLH, tPHL
Propagation Delay A to Qn
2.5V /1.8V LVTTL Outputs
HSTL / eHSTL Outputs
2.5V / 1.8V LVTTL Outputs
HSTL / eHSTL Outputs
tR
Output Rise Time (20% to 80%)
tF
Output Fall Time (20% to 80%)
fO
Frequency Range (HSTL/eHSTL outputs)
Frequency Range (2.5V/1.8V LVTTL outputs)
2.5
1050
1350
1050
1350
250
200
350
350
350
350
nS
pS
pS
MHz
Output Gate Enable/Disable Delay
tPGE
tPGD
Output Gate Enable to Qn
Output Gate Enable to Qn Driven to GL Designated Level
3.5
3
nS
nS
NOTES:
1. Skew measured between all outputs under identical input and output interfaces, transitions, and load conditions on any one device.
2. For only 1.8V/2.5V LVTTL and eHSTL outputs.
3. Skew measured is difference between propagation times tPLH and tPHL of any output under identical input and output interfaces, transitions, and load
conditions on any one device.
4. For only HSTL outputs.
5. Skew measured is the magnitude of the difference in propagation times between any outputs of two devices, given identical transitions and load conditions at
identical VDD/VDDQ levels and temperature.
6. Guaranteed by design.
AC Differential Input Specifications1
Symbol Parameter
tW
Reference Clock Pulse Width HIGH or LOW
2
(HSTL/eHSTL outputs)
Reference Clock Pulse Width HIGH or LOW
(2.5V / 1.8V LVTTL outputs)2
Min.
Typ.
Max
Unit
1.73
nS
2.17
HSTL/eHSTL/1.8V LVTTL/2.5V LVTTL
VDIF
VIH
VIL
LVEPECL
VDIF
VIH
VIL
AC Differential Voltage3
AC Input HIGH4,5
AC Input LOW4,6
400
VX + 200
AC Differential Voltage3
AC Input HIGH4
AC Input LOW4
400
1275
VX - 200
mV
mV
mV
875
mV
mV
mV
NOTES:
1. For differential input mode, RxS is tied to GND.
2. Both differential input signals should not be driven to the same level simultaneously. The input will not change state until the inputs have crossed and the
voltage range defined by VDIF has been met or exceeded.
3. Differential mode only. VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the
"complement" input level. The AC differential voltage must be achieved to guarantee switching to a new state.
4. For single-ended operation, A/VREF is tied to DC voltage (VREF). Refer to each input interface's DC specification for the correct VREF range
5. Voltage required to switch to a logic HIGH, single-ended operation only.
6. Voltage required to switch to a logic LOW, single-ended operation only.
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
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AC Timing Waveforms
Propagation and Skew Waveforms
NOTES:
1. tPHL and tPLH signals are measured from the input passing through VTHI or input pair crossing to Qn passing through VTHO.
2. Pulse Skew is calculated using the following expression:
tSK(P) = | tPHL - tPLH |
where tPHL and tPLH are measured on the controlled edges of any one output from rising and falling edges of a single pulse.
Please note that the tPHL and tPLH shown are not valid measurements for this calculation because they are not taken from the same pulse.
Gate Disable/Enable Showing Runt Pulse Generation
NOTE:
As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their Gx signals to avoid this
problem.
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
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Test Circuits and Conditions
Test Circuit for Differential Input1
Differential Input Test Conditions
Symbol
R1
R2
VDDI
VTHI
VDD= 2.5V ± 0.1V
100
100
VCM*2
HSTL: Crossing of A and A
eHSTL: Crossing of A and A
LVEPECL: Crossing of A and A
1.8V LVTTL: VDDI/2
2.5V LVTTL: VDD/2
Unit
Ω
Ω
V
V
NOTE:
1. This input configuration is used for all input interfaces. For single-ended testing,the VIN input is tied to GND. For testing single-ended in differential input mode,
the VIN is left floating.
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Notice: The information in this document is subject to change without notice.
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Test Circuit for SDR Outputs
SDR Output Test Conditions
Symbol
VDD= 2.5V ± 0.1V
VDDQ= Interface Specified
Unit
CL
15
pF
R1
100
Ω
R2
100
Ω
VTHO
VDDQ/ 2
V
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
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Package Diagram
28L TSSOP (173 mil)
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A
….
0.043
…
1.2
A1
0.0020
0.0059
0.05
0.15
A2
0.031
0.041
0.80
1.05
D
0.3779
0.3858
9.60
9.80
L
0.020
0.030
0.50
0.75
E
0.252 BSC
6.40 BSC
E1
0.169
0.177
4.30
4.50
R
0.004
….
0.09
…..
R1
0.004
….
0.09
…..
b
0.007
0.012
0.19
0.30
b1
0.007
0.010
0.19
0.25
c
0.004
0.008
0.09
0.20
c1
0.004
0.006
0.09
0.16
L1
0.039 REF
1.0 REF
e
0.026 BSC
0.65 BSC
θ1
θ2
θ3
0°
8°
0°
8°
12° REF
12° REF
12° REF
12° REF
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Notice: The information in this document is subject to change without notice.
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Ordering Information
Part Number
Marking
ASM2P5T905AF-28TT
2P5T905AF
ASM2P5T905AF-28TR
ASM2I5T905AF-28TT
Package Type
Operating Range
28 Pin TSSOP, Tube, Pb Free
Commercial
2P5T905AF
28 Pin TSSOP, Tape and Reel, Pb Free
Commercial
2I5T905AF
28 Pin TSSOP, TUBE, Pb Free
Industrial
ASM2I5T905AF-28TR
2I5T905AF
28 Pin TSSOP, Tape and Reel, Pb Free
Industrial
ASM2P5T905AG-28TT
2P5T905AG
28 Pin TSSOP, Tube, Green
Commercial
ASM2P5T905AG-28TR
2P5T905AG
28 Pin TSSOP, Tape and Reel, Green
Commercial
ASM2I5T905AG-28TT
2I5T905AG
28 Pin TSSOP, TUBE, Green
Industrial
ASM2I5T905AG-28TR
2I5T905AG
28 Pin TSSOP, Tape and Reel, Green
Industrial
Ordering Information
A S M 2 P 5 T 9 0 5 A F - 2 8 T R
OR – TSOT23 -6,T/R
TT – TSSOP, TUBE
TR – TSSOP, T/R
VT – TVSOP, TUBE
VR – TVSOP, T/R
ST – SOIC, TUBE
AR – SSOP, T/R
AT – SSOP, TUBE
SR
QR
QT
BT
BR
UR
DR
DT
– SOIC, T/R
– QFN, T/R
– QFN, TRAY
– BGA, TRAY
– BGA, T/R
– SOT-23, T/R
– QSOP, T/R
– QSOP, TUBE
PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE LEAD FREE and RoHS
LEAD FREE PART
X = Automotive
(-40C to +125C)
I = Industrial
P or n/c = Commercial
(-40C to +85C)
(0C to +70C)
1 – reserved
2 – Non PLL based
3 – EMI Reduction
4 – DDR support products
5 – STD Zero Delay Buffer
6 – power management
7 – power management
8 – power management
9 – Hi performance
0 - reserved
PulseCore Semiconductor Mixed Signal Product
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
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PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200
Campbell, CA 95008
Tel: 408-879-9077
Fax: 408-879-9018
www.pulsecoresemi.com
Copyright © PulseCore Semiconductor
All Rights Reserved
Preliminary Information
Part Number: ASM2P5T905A
Document Version: 0.2
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
© Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or
registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their
respective companies. PulseCore reserves the right to make changes to this document and its products at any time without
notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein
represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct
this data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from
PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale.
The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights,
trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products
for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result
in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the
manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use.
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