CY7C68023/CY7C68024 EZ-USB NX2LP™ USB 2.0 NAND Flash Controller EZ-USB NX2LP™ USB 2.0 NAND Flash Controller Features ■ 43 mA Typical Active Current ■ Space Saving and Pb-free 56-QFN Package (8 mm × 8 mm) ■ Support for Board-level Manufacturing test through USB Interface ■ 3.3 V NAND Flash Operation Eight Chip Enable Pins ❐ Up to 8 NAND Flash Single Device Chips ❐ Up to 4 NAND Flash Dual Device Chips ■ NAND Flash Power Management Support ■ Industry Standard ECC NAND Flash Correction ❐ 1 bit per 256 correction ❐ 2 bit error detection ■ Industry Standard (SmartMedia) Page Management for Wear Leveling Algorithm, Bad Block Handling, and Physical to Logical management The EZ-USB NX2LPNX2LPimplements a USB 2.0 NAND Flash controller. This controller adheres to the Mass Storage Class Bulk-Only Transport Specification. The USB port of the NX2LP is connected to a host computer directly or through the downstream port of a USB hub. Host software issues commands and data to the NX2LP and receives status and data from the NX2LP using standard USB protocol. ■ Supports 8-bit NAND Flash Interfaces ■ Supports 30 ns, 50 ns, and 100 ns NAND Flash Timing ■ Complies with USB Mass Storage Class Specification rev 1.0 The NX2LP supports industry leading 8-bit NAND Flash interfaces and both common NAND page sizes of 512 and 2k bytes. Eight chip enable pins allow the NX2LP to be connected to up to eight single or four dual device NAND Flash chips. ■ CY7C68024 Complies with USB 2.0 Specification for Bus-Powered Devices (TID# 40460274) Certain NX2LP features are configurable, enabling the NX2LP to meet the needs of different design requirements. ■ High (480-Mbps) or Full (12-Mbps) Speed USB Support ■ Both Common NAND Page Sizes Supported ❐ 512 bytes — Up to 1 Gbit Capacity ❐ 2K bytes — Up to 8 Gbit Capacity ■ Introduction NX2LP Block Diagram Write Protect Chip Reset LED2# 24 MHz Xtal LED1# PLL EZ-USB NX2LP Internal Control Logic Control NAND Control Signals NAND Flash Interface Logic VBUS D+ D- Smart HS/ FS USB Engine USB 2.0 Xceiver Cypress Semiconductor Corporation Document #: 38-08055 Rev. *E • 198 Champion Court Data • Chip Enable Signals 8-bit Data Bus San Jose, CA 95134-1709 • 408-943-2600 Revised March 29, 2011 [+] Feedback CY7C68023/CY7C68024 Pin Assignments GND VCC N/C GND CE7# CE6# CE5# CE4# CE3# CE2# CE1# CE0# Reserved VCC 56 55 54 53 52 51 50 49 48 47 46 45 44 43 Figure 1. 56-pin QFN R_B1# 1 42 RESET# R_B2# 2 41 GND AVCC 3 40 N/C XTALOUT 4 39 N/C XTALIN 5 38 WP_SW# AGND 6 37 WP_NF# 25 26 27 28 DD7 GND VCC GND WE# 24 RE0# 29 23 30 14 DD6 13 DD5 N/C GND 22 RE1# 21 31 DD4 12 DD3 VCC GND 20 CLE 32 DD2 33 11 19 10 VCC 18 AGND DD1 ALE DD0 34 17 9 VCC LED1# DMINUS 16 LED2# 35 15 36 8 Reserved 7 Reserved AVCC DPLUS Pin Descriptions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name R_B1#[1] R_B2# AVCC XTALOUT XTALIN AGND AVCC DPLUS DMINUS AGND VCC GND N/C GND Reserved Type I I PWR Xtal Xtal GND PWR I/O I/O GND PWR GND N/A GND N/A Default State at Startup Z Z PWR N/A N/A GND PWR Z Z GND PWR GND N/A GND N/A Description Ready/Busy 1 (2.2k to 4k pull up resistor is required) Ready/Busy 2 (2.2k to 4k pull up resistor is required) Analog 3.3 V supply Crystal output Crystal input Ground Analog 3.3 V supply USB D+ USB DGround 3.3 V supply Ground No connect Ground Must be tied HIGH (no pull up resistor required) Note 1. A # sign after the pin name indicates that it is an active LOW signal. Document #: 38-08055 Rev. *E Page 2 of 10 [+] Feedback CY7C68023/CY7C68024 Pin Descriptions (continued) Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Name Reserved VCC DDO DD1 DD2 DD3 DD4 DD5 DD6 DD7 GND VCC GND WE# RE0# RE1# VCC CLE ALE LED1# LED2# WP_NF# WP_SW# N/C N/C GND RESET# VCC Reserved CE0# CE1# CE2# CE3# CE4# CE5# CE6# CE7# GND N/C VCC GND Type N/A PWR I/O I/O I/O I/O I/O I/O I/O I/O GND PWR GND O O O PWR O O O O O I N/A N/A GND I PWR N/A O O O O O O O O GND N/A PWR GND Default State at Startup N/A PWR Z Z Z Z Z Z Z Z GND PWR GND H H H PWR Z Z Z Z Z Z N/A N/A GND Z PWR N/A Z Z Z Z Z Z Z Z GND N/A PWR GND Document #: 38-08055 Rev. *E Description Must be tied HIGH (no pull up resistor required) 3.3 V supply Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Ground 3.3 V supply Ground Write enable Read Enable 0 Read Enable 1 3.3 V supply Command latch enable Address latch enable Data activity LED sink Chip active LED sink Write-protect NAND Flash Write-protect switch input No connect No connect Ground NX2LP chip reset 3.3 V supply Must be tied HIGH Chip enable 0 Chip enable 1 Chip enable 2 Chip enable 3 Chip enable 4 Chip enable 5 Chip enable 6 Chip enable 7 Ground No connect 3.3 V supply Ground Page 3 of 10 [+] Feedback CY7C68023/CY7C68024 Additional Pin Descriptions CLE DPLUS, DMINUS DPLUS and DMINUS are the USB signaling pins, and they should be tied to the D+ and D– pins of the USB connector. Because they operate at high frequencies, the USB signals require special consideration when designing the layout of the PCB. General guidelines are given at the end of this document. Figure 2. XTALIN, XTALOUT Diagram The Command Latch Enable output pin is used to indicate that the data on the I/O bus is a command. The data is latched into the NAND Flash control register on the rising edge of WE# when CLE is HIGH. ALE The Address Latch Enable output pin is used to indicate that the data on the I/O bus is an address. The data is latched into the NAND Flash address register on the rising edge of WE# when ALE is HIGH. LED1# 24-MHz Xtal 12 pF 12 pF 12-pF capacitor values assume a trace capacitance of 3 pF per side on a four-layer FR4 PCB The Data Activity LED output pin is used to indicate data transfer activity. LED1# is asserted LOW at the beginning of a data transfer, and set to a high Z state when the transfer is complete. If this functionality is not utilized, leave LED1# floating. LED2# The Chip Active LED output pin is used to indicate proper device operation. LED2# is asserted LOW when the NX2LP is powered and initialized. It is placed in a high Z state under all other conditions. If this functionality is not used, leave LED2# floating. WP_NF# XTALIN XTALOUT The NX2LP requires a 24 MHz (±100 ppm) signal to derive internal timing. Typically, a 24 MHz (20 pF, 500 W, parallel-resonant fundamental mode) crystal is used, but a 24 MHz square wave from another source can also be used. If a crystal is used, connect its pins to XTALIN and XTALOUT, and also through 12 pF capacitors to GND. If an alternate clock source is used, apply it to XTALIN and leave XTALOUT open. Data[7-0] The Data[7-0] I/O pins provide an 8-bit interface to a NAND Flash device. These pins are used to transfer address, command, and read/write data between the NX2LP and NAND Flash. R_B[2-1]# The Ready/Busy input pins are used to determine the state of the currently selected NAND Flash device. These pins must be pulled HIGH through a 2k-4k resistor. These pins are pulled LOW by the NAND Flash when it is busy. WE# The Write Enable output pin is used by the NAND Flash to latch commands, address, and data during the rising edge of the pulse. RE[1-0]# The Write-protect NAND Flash output pin is used to control the write-protect pins on NAND Flash devices. This pin should be tied to the Write Protect pins of the NAND Flash devices. If WP_SW# is asserted LOW during a data transfer, or if internal operations are still pending, the NX2LP waits until the operation is complete before asserting WP_NF# to ensure that there is no data loss or risk of OS error. WP_SW# The Write-protect Switch input pin is used to select whether or not NAND Flash write-protection is enabled by the NX2LP. When the pin is asserted LOW, the NX2LP reports to the host that the NAND Flash is write-protected, the WP_NF# is driven LOW, and any attempts to write to the configuration data memory area are blocked by the NX2LP. If this pin is asserted LOW during a data transfer, or if internal operations are still pending, the NX2LP waits until the operation is complete before asserting WP_NF# to ensure that there is no data loss or risk of OS error. CE[7-0]# The Chip Enable output pins are used to select the NAND Flash that the NX2LP interfaces. Unused Chip Enable pins should be left floating. RESET# Asserting RESET# for 10 ms resets the NX2LP. A reset and/or watchdog chip is recommended to ensure that startup and brownout conditions are properly handled. The Read Enable output pins are used to control the data flow from the NAND Flash devices. The device presents valid data and increments its internal column address counter by one step on each falling edge of the Read Enable pulse. A 10k pull up is an option For RE1-0#. Document #: 38-08055 Rev. *E Page 4 of 10 [+] Feedback CY7C68023/CY7C68024 Applications Manufacturing Mode The NX2LP is a high speed USB 2.0 peripheral device that connects NAND Flash devices to a USB host using the USB Mass Storage Class protocol. In Manufacturing mode, the NX2LP enumerates using the default descriptors and configuration data that are stored in internal ROM. This mode enables first-time programming of the configuration data memory area, and board-level manufacturing tests. Additional Resources ■ CY3685 EZ-USB NX2LP Development Kit ■ CY4618 EZ-USB NX2LP Reference Design Kit ■ USB Specification version 2.0 ■ USB Mass Storage Class Bulk Only Transport Specification, http://www.usb.org/developers/devclass_docs/usbmassbulk_10.pdf . Functional Overview A unique USB serial number is required for each device in order to comply with the USB Mass Storage specification. Cypress also requires designers to use their own Vendor ID for final products. The Vendor ID is obtained through registration with the USB Implementor’s Forum (USB-IF), and the Product ID is determined by the designer. Cypress provides all the software tools and drivers necessary for properly programming and testing the NX2LP. Refer to the documentation in the development or reference design kit for more information on these topics. Figure 3. NX2LP Enumeration Process USB Signaling Speed The NX2LP operates at two of the three rates defined in the USB Specification Revision 2.0 dated April 27, 2000: ■ Full speed, with a signaling bit rate of 12 Mbits/sec ■ High speed, with a signaling bit rate of 480 Mbits/sec. Start-up The NX2LP does not support the low speed signaling rate of 1.5 Mbits/sec. Yes NAND Flash Interface NAND Flash Present? No During normal operation the NX2LP supports an 8-bit I/O interface, eight chip enable pins, and other control signals compatible with industry standard NAND Flash devices. Enumeration During the startup sequence, internal logic checks for the presence of NAND Flash with valid configuration data in the configuration data memory area. If valid configuration data is found, the NX2LP uses the values stored in NAND Flash to configure the USB descriptors for normal operation as a USB mass storage device. If no NAND Flash is detected, or if no valid configuration data is found in the configuration data memory area, the NX2LP uses the default values from internal ROM space for manufacturing mode operation. The two modes of operation are described in the following sections. NAND Flash Programmed? No Yes Load Custom Descriptors and Configuration Data Load Default Descriptors and Configuration Data Enumerate As USB Mass Storage Device Enumerate As Generic NX2LP Device Normal Operation Mode Manufacturing Mode Normal Operation Mode In Normal Operation Mode, the NX2LP behaves as a USB 2.0 Mass Storage Class NAND Flash controller. This includes all typical USB device states (powered, configured, and so on). The USB descriptors are returned according to the data stored in the configuration data memory area. Normal read and write access to the NAND Flash is available in this mode. Document #: 38-08055 Rev. *E Page 5 of 10 [+] Feedback CY7C68023/CY7C68024 Configuration Data Certain features in the NX2LP can be configured by the designer to disable unneeded features, and to comply with the USB 2.0 specification’s descriptor requirements for mass storage devices. Table 1 lists the variable configuration data and the default values that are stored in internal ROM space. The default ROM values are returned by an unprogrammed NX2LP device. Table 1. Variable Configuration Data And Default ROM Values Configuration Data Description Default ROM Value Vendor ID USB Vendor ID (Assigned by USB-IF) Product ID USB Product ID (Assigned by designer) Serial Number Manufacturer String 0x04B4 (Cypress) 0x6813 USB serial number N/A Manufacturer string in USB descriptors N/A Product String Product string in USB descriptors N/A Enable Write Protection Enables write protection capability Enabled SCSI Device Name String shown in the device manager properties Design Notes For The Quad Flat No Lead (QFN) Package The NX2LP comes in a 56-pin QFN package, which utilizes a metal pad on the bottom to aid in heat dissipation. The low-power operation of the NX2LP makes the thermal pad on the bottom of the QFN package unnecessary. Because of this, PCB layout may utilize the space under the NX2LP for routing signals as needed, provided that any traces or vias under the thermal pad are covered by solder mask or other material to prevent shorting. Standard PCB layout recommendations for USB devices still apply. For further information on this package design, please refer to the application note from AMKOR titled “Surface Mount Assembly of AMKOR’s MicroLeadFrame (MLF) Technology.” This application note provides detailed information on board mounting guidelines, soldering flow, rework process, etc. N/A PCB Layout Recommendations The following recommendations should be followed to ensure reliable High-speed USB performance operation. ■ A four-layer impedance controlled board is recommended to ensure best signal quality. ■ Specify impedance targets (ask your board vendor what they can achieve). ■ Maintain trace widths and trace spacing to control impedance. ■ Minimize stubs on DPLUS and DMINUS to avoid reflected signals. ■ Place any connections between the USB connector shell and signal ground near the USB connector. ■ Use bypass/flyback caps on VBUS, placed near connector. ■ Keep DPLUS and DMINUS trace lengths to within 2 mm of each other in length, with preferred length of 20–30 mm. ■ Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not allow the plane to be split under these traces. ■ Place no vias on the DPLUS or DMINUS trace routing. ■ Isolate the DPLUS and DMINUS traces from all other signal traces (use >10 mm. spacing for best signal quality). Source for recommendations: Document #: 38-08055 Rev. *E ■ EZ-USB FX2 PCB Design www.cypress.com/?docID=4696. Recommendations, ■ High-speed USB Platform Design Guidelines, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf. Page 6 of 10 [+] Feedback CY7C68023/CY7C68024 Absolute Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Power Dissipation..................................................... 300 mW Storage Temperature ................................ –65 °C to +150 °C Max Output Current per IO port................................... 10 mA Ambient Temperature with Power Supplied.......................................................... 0 °C to +70 °C Static Discharge Voltage............................................. 2000 V Operating Conditions[2] Supply Voltage to Ground Potential..............–0.5 V to +4.0 V TA (Ambient Temperature Under Bias) ........... 0 °C to +70 °C DC Input Voltage to Any Input Pin ............................... 5.25 V Supply Voltage..........................................+3.00 V to +3.60 V DC Voltage Applied to Outputs in High Z State .................................... –0.5 V to VCC + 0.5 V Ground Voltage................................................................. 0 V DC Characteristics Parameter Description Conditions Min Typ Max Unit VCC Supply Voltage 3.0 3.3 3.6 V VCC Ramp Supply Ramp-up 0 V to 3.3 V 200 – – s VIH Input High Voltage 2 – 5.25 V VIL Input Low Voltage –0.5 – 0.8 V II Input Leakage Current – – ±10 A VIH_X Crystal Input HIGH Voltage 2 – 5.25 V VIL_X Crystal Input LOW Voltage –0.5 – 0.8 V VOH Output Voltage High IOUT = 4 mA 2.4 – – V VOL Output Voltage Low IOUT = –4 mA – – 0.4 V IOH Output Current High – – 4 mA IOL Output Current Low – – 4 mA CIN Input Pin Capacitance All but D+/D– – – 10 pF Only D+/D– – – 15 pF ICC Supply Current USB High Speed – 50 – mA USB Full Speed – 35 – mA ISUSP Suspend Current Connected – 0.5 1.2[3] mA mA A CY7C68023 CY7C68024 0 < VIN < VCC Disconnected – 0.3 1.0[3] Connected – 300 380[3] A Disconnected – 100 150[3] IUNCONFIG Unconfigured Current Before current requested in USB descriptors is granted by the host – 43 – mA TRESET Reset Time After Valid Power VCC > 3.0 V 5.0 – – mS 200 – – S Pin Reset After Valid Startup AC Electrical Characteristics USB Transceiver The NX2LP’s USB interface complies with the USB 2.0 specification for bus-powered devices. NAND Flash Timing The NX2LP supports 30-ns, 50-ns, and 100-ns NAND Flash devices. Notes 2. If an alternate clock source is input on XTALIN, it must be supplied with standard 3.3 V signaling characteristics and XTALOUT must be left floating. 3. Measured at Max VCC, 25 C. Document #: 38-08055 Rev. *E Page 7 of 10 [+] Feedback CY7C68023/CY7C68024 Ordering Information Part Number Package Type CY7C68023-56LTXC 56-pin QFN - Sawn type Package Diagrams Figure 4. 56-pin Quad Flatpack No Lead (8 × 8 mm) LF56 SOLDERABLE EXPOSED PAD 51-85144 *I Document #: 38-08055 Rev. *E Page 8 of 10 [+] Feedback CY7C68023/CY7C68024 Figure 5. 56-pin QFN (8 × 8 × 0.9 mm) - Sawn 001-53450 *B Document #: 38-08055 Rev. *E Page 9 of 10 [+] Feedback CY7C68023/CY7C68024 Document History Page Description Title: CY7C68023/CY7C68024 EZ-USB NX2LP™ USB 2.0 NAND Flash Controller Document Number: 38-08055 REV. ECN NO. Submission Date ** 286009 SEE ECN Orig. of Change GIR Description of Change New Data Sheet (Preliminary Information). *A 334796 SEE ECN GIR Adjusted default VID/PID; released as final. *B 397024 SEE ECN GIR Changed Vcc to ±10% in DC Characteristics table. Changed the supply voltage tolerance to ±10% in the Operating Conditions section. Added new logo. *C 2717536 06/11/2009 DPT Added 56 QFN (8 X 8 mm) package diagram and added CY7C68023-56LTXC part information in the Ordering Information table *D 2896245 03/19/2010 CPPK Updated ordering information and package diagrams. *E 3208866 03/29/2011 CPPK Updated Ordering Information. Updated Package Diagrams. Updated in new template. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-08055 Rev. *E Revised March 29, 2011 Page 10 of 10 EZ-USB NX2LP is a trademark and EZ-USB is a registered trademark of Cypress Semiconductor Corp. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback