TI1 DLP480REFXG 0.48 wuxga dmd Datasheet

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DLP480RE
DLPS092 – AUGUST 2017
DLP480RE 0.48 WUXGA DMD
1 Features
3 Description
•
The TI DLP480RE digital micromirror device (DMD) is
a digitally controlled micro-electromechanical system
(MEMS) spatial light modulator (SLM) that enables
high resolution WUXGA display systems. The
DLP480RE DMD, together with the DLPC4422
display controller and DLPA100 power and motor
driver, comprise the DLP® 0.48” WUXGA chipset.
This chipset serves as an optimal solution for any
system that demands a cost-effective, high-resolution
display.
1
•
•
0.48-Inch Diagonal Micromirror Array
– WUXGA (1920 × 1200)
– 5.4 Micron Micromirror Pitch
– ±17° Micromirror Tilt (Relative to Flat Surface)
– Bottom Illumination
2 × LVDS Input Data Bus
Dedicated DLPC4422 Display Controller,
DLPA100 Power Management IC and Motor
Driver for reliable operation
Device Information(1)
2 Applications
•
•
•
•
•
PART NUMBER
DLP480RE
WUXGA Display
Smart Display
Digital Signage
Business Projector
Education Projector
PACKAGE
FXG (257)
BODY SIZE (NOM)
32 mm × 22 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
DLP480RE 0.48 WUXGA DMD
ASIC Power
Control Signals
DLPA100
Colorwheel Motor Control
DAD control
DLPC4422
ASIC
SCP control
DMD RSTZ
3.3-V to 1.8-V
Translators
PG_OFFSET
VBIAS
3.3 V
TPS65145
(Voltage
Regulator)
DLP480RE
DMD
VOFFSET
VRESET
EN_OFFSET
VREG
1.8 V
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLP480RE
DLPS092 – AUGUST 2017
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Table of Contents
1
2
3
4
5
6
7.4
7.5
7.6
7.7
Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions ......................... 3
Specifications....................................................... 10
8
23
23
25
26
Application and Implementation ........................ 29
8.1 Application Information............................................ 29
8.2 Typical Application ................................................. 29
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Absolute Maximum Ratings .................................... 10
Storage Conditions.................................................. 10
ESD Ratings............................................................ 11
Recommended Operating Conditions..................... 11
Thermal Information ................................................ 13
Electrical Characteristics......................................... 14
Capacitance at Recommended Operating
Conditions ................................................................ 14
6.8 Timing Requirements .............................................. 15
6.9 System Mounting Interface Loads .......................... 17
6.10 Micromirror Array Physical Characteristics ........... 18
6.11 Micromirror Array Optical Characteristics ............. 20
6.12 Window Characteristics......................................... 21
6.13 Chipset Component Usage Specification ............. 21
7
Device Functional Modes........................................
Window Characteristics and Optics ........................
Micromirror Array Temperature Calculation............
Micromirror Landed-On/Landed-Off Duty Cycle .....
9
Power Supply Recommendations...................... 32
9.1 DMD Power Supply Power-Up Procedure .............. 32
9.2 DMD Power Supply Power-Down Procedure ......... 32
10 Layout................................................................... 35
10.1 Layout Guidelines ................................................. 35
10.2 Layout Example .................................................... 35
11 Device and Documentation Support ................. 37
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Detailed Description ............................................ 22
Device Support......................................................
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
37
37
38
38
38
38
38
12 Mechanical, Packaging, and Orderable
Information ........................................................... 39
7.1 Overview ................................................................. 22
7.2 Functional Block Diagram ....................................... 22
7.3 Feature Description................................................. 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
August 2017
*
Initial release.
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5 Pin Configuration and Functions
Series 410
257-pin FXG
Bottom View
2
1
4
3
6
5
8
7
10
9
12
14
11 13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
Z
W
V
U
T
R
P
N
M
L
K
J
H
G
E
C
F
D
B
A
CAUTION
To ensure reliable, long-term operation of the .48” WUXGA s410 DMD, it is critical to
properly manage the layout and operation of the signals identified in the table below.
For specific details and guidelines, refer to the PCB Design Requirements for TI DLP
Standard TRP Digital Micromirror Devices application report before designing the
board.
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Pin Functions (1)
PIN
NAME
NO.
D_AN(0)
C6
D_AN(1)
C3
D_AN(2)
E1
D_AN(3)
C4
D_AN(4)
D1
D_AN(5)
B8
D_AN(6)
F4
D_AN(7)
E3
D_AN(8)
C11
D_AN(9)
F3
D_AN(10)
K4
D_AN(11)
H3
D_AN(12)
J3
D_AN(13)
C13
D_AN(14)
A5
D_AN(15)
A3
D_AP(0)
C7
D_AP(1)
C2
D_AP(2)
E2
D_AP(3)
B4
D_AP(4)
C1
D_AP(5)
B7
D_AP(6)
E4
D_AP(7)
D3
D_AP(8)
C12
D_AP(9)
F2
D_AP(10)
J4
D_AP(11)
G3
D_AP(12)
J2
D_AP(13)
C14
D_AP(14)
A6
D_AP(15)
A4
(1)
(2)
4
INTERNAL
TERMINATION
TRACE
LENGTH
(mil)
I/O (2)
SIGNAL
DATA
RATE
NC
LVDS
DDR
Differential
No connect
805.0
NC
LVDS
DDR
Differential
No connect
805.0
DESCRIPTION
The .48” WUXGA TRP 2xLVDS Series 410 DMD is a component of one or more DLP chipsets. Reliable function and operation of the
.48” WUXGA TRP 2xLVDS Series 410 DMD requires that it be used in conjunction with the other components of the applicable DLP
chipset, including those components that contain or implement TI DMD control technology. TI DMD control technology is the TI
technology and devices for operating or controlling a DLP DMD.
I = Input, O = Output, P = Power, G = Ground, NC = No connect
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Pin Functions(1) (continued)
PIN
NAME
NO.
D_BN(0)
N4
D_BN(1)
Z11
D_BN(2)
W4
D_BN(3)
W10
D_BN(4)
L1
D_BN(5)
V8
D_BN(6)
W6
D_BN(7)
M1
D_BN(8)
R4
D_BN(9)
W1
D_BN(10)
U4
D_BN(11)
V2
D_BN(12)
Z5
D_BN(13)
N3
D_BN(14)
Z2
D_BN(15)
L4
D_BP(0)
M4
D_BP(1)
Z12
D_BP(2)
Z4
D_BP(3)
Z10
D_BP(4)
L2
D_BP(5)
V9
D_BP(6)
W7
D_BP(7)
N1
D_BP(8)
P4
D_BP(9)
V1
D_BP(10)
T4
D_BP(11)
V3
D_BP(12)
Z6
D_BP(13)
N2
D_BP(14)
Z3
D_BP(15)
L3
INTERNAL
TERMINATION
TRACE
LENGTH
(mil)
I/O (2)
SIGNAL
DATA
RATE
NC
LVDS
DDR
Differential
No connect
805.0
NC
LVDS
DDR
Differential
No connect
805.0
DESCRIPTION
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Pin Functions(1) (continued)
PIN
NAME
NO.
D_CN(0)
H27
D_CN(1)
A20
D_CN(2)
H28
D_CN(3)
K28
D_CN(4)
K30
D_CN(5)
C23
D_CN(6)
G27
D_CN(7)
J30
D_CN(8)
B24
D_CN(9)
A21
D_CN(10)
A27
D_CN(11)
C29
D_CN(12)
A26
D_CN(13)
C25
D_CN(14)
A29
D_CN(15)
C30
D_CP(0)
J27
D_CP(1)
A19
D_CP(2)
H29
D_CP(3)
K27
D_CP(4)
K29
D_CP(5)
C22
D_CP(6)
F27
D_CP(7)
H30
D_CP(8)
B25
D_CP(9)
B21
D_CP(10)
B27
D_CP(11)
C28
D_CP(12)
A25
D_CP(13)
C24
D_CP(14)
A28
D_CP(15)
B30
6
INTERNAL
TERMINATION
TRACE
LENGTH
(mil)
I/O (2)
SIGNAL
DATA
RATE
I
LVDS
DDR
Differential
Data negative
805.0
I
LVDS
DDR
Differential
Data positive
805.0
DESCRIPTION
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Pin Functions(1) (continued)
PIN
NAME
NO.
D_DN(0)
V25
D_DN(1)
V28
D_DN(2)
T30
D_DN(3)
V27
D_DN(4)
U30
D_DN(5)
W23
D_DN(6)
R27
D_DN(7)
T28
D_DN(8)
V20
D_DN(9)
R28
D_DN(10)
L27
D_DN(11)
N28
D_DN(12)
M28
D_DN(13)
V18
D_DN(14)
Z26
D_DN(15)
Z28
D_DP(0)
V24
D_DP(1)
V29
D_DP(2)
T29
D_DP(3)
W27
D_DP(4)
V30
D_DP(5)
W24
D_DP(6)
T27
D_DP(7)
U28
D_DP(8)
V19
D_DP(9)
R29
D_DP(10)
M27
D_DP(11)
P28
D_DP(12)
M29
D_DP(13)
V17
D_DP(14)
Z25
D_DP(15)
Z27
SCTRL_AN
G1
I/O (2)
SIGNAL
DATA
RATE
INTERNAL
TERMINATION
DESCRIPTION
TRACE
LENGTH
(mil)
805.0
I
LVDS
DDR
Differential
Data negative
805.0
I
LVDS
DDR
Differential
Data positive
NC
LVDS
DDR
Differential
No connect
805.0
SCTRL_AP
F1
SCTRL_BN
V5
SCTRL_BP
V4
SCTRL_CN
C26
I
LVDS
DDR
Differential
Serial control negative
805.0
SCTRL_CP
C27
I
LVDS
DDR
Differential
Serial control positive
805.0
SCTRL_DN
P30
I
LVDS
DDR
Differential
Serial control negative
805.0
SCTRL_DP
R30
I
LVDS
DDR
Differential
Serial control positive
805.0
DCLK_AN
H2
DCLK_AP
H1
DCLK_BN
V6
NC
LVDS
Differential
No connect
805.0
DCLK_BP
V7
DCLK_CN
D27
I
LVDS
Differential
Clock negative
805.0
DCLK_CP
E27
I
LVDS
Differential
Clock positive
805.0
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Pin Functions(1) (continued)
PIN
NAME
NO.
I/O (2)
SIGNAL
DATA
RATE
INTERNAL
TERMINATION
DESCRIPTION
TRACE
LENGTH
(mil)
DCLK_DN
N29
I
LVDS
Differential
Clock negative
805.0
DCLK_DP
N30
I
LVDS
Differential
Clock positive
805.0
SCPCLK
A10
I
LVCMOS
Pull down
Serial communications port clock. Active only
when SCPENZ is logic low.
SCPDI
A12
I
LVCMOS
Pull down
Serial communications port Data Input.
Synchronous to SCPCLK rising edge.
SCPENZ
C10
I
LVCMOS
Pull down
Serial communications port enable active low.
SCPDO
A11
O
LVCMOS
RESET_ADDR(0)
Z13
RESET_ADDR(1)
W13
RESET_ADDR(2)
V10
I
LVCMOS
Pull down
RESET_ADDR(3)
W14
I
LVCMOS
Pull down
SDR
SDR
Serial communications port Output.
Reset driver address select
RESET_MODE(0)
W9
RESET_SEL(0)
V14
RESET_SEL(1)
Z8
RESET_STROBE
Z9
I
LVCMOS
Pull down
Rising edge latches in RESET_ADDR,
RESET_MODE, & RESET_SEL
PWRDNZ
A8
I
LVCMOS
Pull down
Active low device reset
RESET_OEZ
W15
I
LVCMOS
Pull up
Active low Output enable for internal reset
driver circuits
RESET_IRQZ
V16
O
LVCMOS
Active low Output interrupt to DLP display
controller
EN_OFFSET
C9
O
LVCMOS
Active high enable for external VOFFSET
regulator
PG_OFFSET
A9
I
LVCMOS
TEMP_N
B18
Analog
Temperature sensor diode cathode
B17
Analog
Temperature sensor diode anode
TEMP_P
Reset driver mode select
Reset driver level select
RESERVED
D12, D13,
D14, D15,
D16, D17,
D18, D19,
U12, U13,
U14, U15
NC
No Connect
U16, U17,
U18, U19
NC
RESERVED_BA
W11
RESERVED_BB
B11
RESERVED_BC
Z20
RESERVED_BD
C18
RESERVED_PFE
A18
RESERVED_TM
C8
No connect. No electrical connection from
CMOS bond pad to package pin.
LVCMOS
I
Analog
Do not connect on DLP system board
C15, C16,
V11, V12
P
Analog
Supply voltage for Positive Bias level of
micromirror reset signal.
G4, H4,
J1, K1
P
Analog
Supply voltage for Negative Reset level of
micromirror reset signal
Z19
RESERVED_TP2
W19
8
Do not connect on DLP system board. No
connect. No electrical connections from
CMOS bond pad to package pin.
I
W20
(3)
Pull Down
Active low fault from external VOFFSET
regulator
LVCMOS
RESERVED_TP1
VRESET (3)
Analog
Pull up
O
RESERVED_TP0
VBIAS (3)
Reset driver level select
Do not connect on DLP system board
Pull down
Connect to ground on DLP system board.
VBIAS, VCC, VOFFSET, and VRESET power supplies must be connected for proper DMD operation.
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Pin Functions(1) (continued)
PIN
NAME
VOFFSET (3)
NO.
A30, B2,
M30, Z1,
Z30
INTERNAL
TERMINATION
SIGNAL
P
Analog
Supply voltage for HVCMOS logic. Supply
voltage for positive offset level of micromirror
reset signal. Supply voltage for stepped high
voltage at micromirror address electrodes.
Analog
Supply voltage for LVCMOS core. Supply
voltage for positive offset level of micromirror
reset signal during Power down. Supply
voltage for normal high level at micromirror
address electrodes.
VCC (3)
A24, A7,
B10, B13,
B16, B19,
B22, B28,
B5, C17,
C20, D4,
J29, K2,
L29, M2,
N27, U27,
V13, V15,
V22, W17,
W21,
W26,
W29, W3,
Z18, Z23,
Z29, Z7
P
VSS (4)
A13, A22,
A23, B12,
B14, B15,
B20, B23,
B26, B29,
B3, B6,
B9, C19,
C21, C5,
D2, G2,
J28, K3,
L28, L30,
M3, P27,
P29, U29,
V21, V23,
V26, W12,
W16,
W18, W2,
W22,
W25,
W28,
W30, W5,
W8, Z21,
Z22, Z24
G
(4)
DATA
RATE
I/O (2)
DESCRIPTION
TRACE
LENGTH
(mil)
Device ground. Common return for all power.
VSS must be connected for proper DMD operation.
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
SUPPLY VOLTAGES
VCC
Supply voltage for LVCMOS core logic (1)
–0.5
2.3
V
VOFFSET
Supply voltage for HVCMOS and micromirror electrode (1) (2)
–0.5
11
V
VBIAS
Supply voltage for micromirror electrode (1)
–0.5
19
V
(1)
–15
VRESET
Supply voltage for micromirror electrode
-0.3
V
|VBIAS – VOFFSET|
Supply voltage difference (absolute value) (3)
11
V
|VBIAS – VRESET|
Supply voltage difference (absolute value) (4)
34
V
INPUT VOLTAGES
Input voltage for all other LVCMOS input pins (1)
VCC + 0.5
V
|VID|
Input differential voltage (absolute value) (5)
–0.5
500
mV
IID
Input differential current (6)
6.3
mA
ƒCLOCK
Clock frequency for LVDS interface, DCLK_C
400
MHz
ƒCLOCK
Clock frequency for LVDS interface, DCLK_D
400
MHz
0
90
°C
–40
90
°C
Clocks
ENVIRONMENTAL
TARRAY and
TWINDOW
Temperature, operating (7)
Temperature, non–operating (7)
|TDELTA|
Absolute Temperature difference between any point on the window edge and
the ceramic test point TP1 (8)
30
°C
TDP
Dew Point Temperature, operating and non–operating (noncondensing)
81
°C
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
All voltages are referenced to common ground VSS. VBIAS, VCC, VOFFSET, and VRESET power supplies are all required for proper DMD
operation. VSS must also be connected.
VOFFSET supply transients must fall within specified voltages.
Exceeding the recommended allowable voltage difference between VBIAS and VOFFSET may result in excessive current draw.
Exceeding the recommended allowable voltage difference between VBIAS and VRESET may result in excessive current draw.
This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.
LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.
The highest temperature of the active array (as calculated using Micromirror Array Temperature Calculation) or of any point along the
window edge as defined in Figure 10. The locations of thermal test points TP2, TP3, TP4 and TP5 in Figure 10 are intended to measure
the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature,
that point should be used.
Temperature difference is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in
Figure 10. The window test points TP2, TP3, TP4 and TP5 shown in Figure 10 are intended to result in the worst case difference. If a
particular application causes another point on the window edge to result in a larger difference temperature, that point should be used.
6.2 Storage Conditions
Applicable for the DMD as a component or non-operating in a system
Tstg
DMD storage temperature
TDP-AVG
Average dew point temperature, (non-condensing)
TDP-MAX
Elevated dew point temperature range , (non-condensing)
CTELR
Cumulative time in elevated dew point temperature range
(1)
(2)
10
MIN
MAX
–40
80
°C
28
°C
(1)
(2)
28
UNIT
36
°C
24
Months
The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative
time of CTELR.
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6.3 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.4 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this
data sheet is achieved when operating the device within the limits defined by this table. No level of performance is implied
when operating the device above or below these limits.
MIN
NOM
MAX
UNIT
1.65
1.8
1.95
V
VOLTAGE SUPPLY
LVCMOS logic supply voltage (1)
VCC
(1) (2)
VOFFSET
Mirror electrode and HVCMOS voltage
9.5
10
10.5
V
VBIAS
Mirror electrode voltage (1)
17.5
18
18.5
V
VRESET
Mirror electrode voltage (1)
–14.5
–14
–13.5
V
|VBIAS –
VOFFSET|
Supply voltage difference (absolute value) (3)
10.5
V
(4)
33
V
0.7 × VCC
VCC + 0.3
V
–0.3
0.3 × VCC
V
0.8 × VCC
VCC + 0.3
V
–0.3
0.2 × VCC
|VBIAS – VRESET| Supply voltage difference (absolute value)
LVCMOS INTERFACE
VIH(DC)
DC input high voltage (5)
VIL(DC)
DC input low voltage (5)
VIH(AC)
AC input high voltage (5)
(5)
VIL(AC)
AC input low voltage
tPWRDNZ
PWRDNZ pulse duration (6)
10
V
ns
SCP INTERFACE
ƒSCPCLK
SCP clock frequency (7)
tSCP_PD
Propagation delay, Clock to Q, from rising–edge of SCPCLK to valid
SCPDO (8)
0
tSCP_NEG_ENZ
Time between falling-edge of SCPENZ and the first rising- edge of
SCPCLK
1
µs
tSCP_POS_ENZ
Time between falling-edge of SCPCLK and the rising-edge of SCPENZ
1
µs
tSCP_DS
SCPDI Clock setup time (before SCPCLK falling edge) (8)
800
ns
tSCP_DH
SCPDI Hold time (after SCPCLK falling edge) (8)
900
ns
tSCP_PW_ENZ
SCPENZ inactive pulse duration (high level)
2
µs
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
500
kHz
900
ns
All voltages are referenced to common ground VSS. VBIAS, VCC, VOFFSET, and VRESET power supplies are all required for proper
DMD operation. VSS must also be connected.
VOFFSET supply transients must fall within specified max voltages.
To prevent excess current, the supply voltage difference |VBIAS – VOFFSET| must be less than specified limit. See Power Supply
Recommendations, Figure 13, and Table 8.
To prevent excess current, the supply voltage difference |VBIAS – VRESET| must be less than specified limit. See Power Supply
Recommendations, Figure 13, and Table 8.
Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard
No. 209B, “Low-Power Double Data Rate (LPDDR)” JESD209B.Tester Conditions for VIH and VIL.
(a) Frequency = 60 MHz. Maximum Rise Time = 2.5 ns @ (20% - 80%)
(b) Frequency = 60 MHz. Maximum Fall Time = 2.5 ns @ (80% - 20%)
PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tristates the
SCPDO output pin.
The SCP clock is a gated clock. Duty cycle must be 50% ± 10%. SCP parameter is related to the frequency of DCLK.
See Figure 2.
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Recommended Operating Conditions (continued)
Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this
data sheet is achieved when operating the device within the limits defined by this table. No level of performance is implied
when operating the device above or below these limits.
MIN
NOM
MAX
UNIT
400
MHz
LVDS INTERFACE
Clock frequency for LVDS interface (all channels), DCLK (9)
ƒCLOCK
(10)
|VID|
Input differential voltage (absolute value)
VCM
Common mode voltage (10)
150
300
440
mV
1100
1200
1300
VLVDS
LVDS voltage (10)
mV
1520
mV
tLVDS_RSTZ
Time required for LVDS receivers to recover from PWRDNZ
ZIN
Internal differential termination resistance
80
100
2000
ns
120
ZLINE
Line differential impedance (PWB/trace)
90
100
Ω
110
Ω
10
40 to
70 (13)
°C
0
10
°C
85
°C
14
°C
28
°C
880
ENVIRONMENTAL
Array temperature, Long–term operational (11) (12) (13) (14)
TARRAY
Array temperature, Short–term operational (12) (15)
(16)
TWINDOW
Window temperature – operational
|TDELTA|
Absolute temperature difference between any point on the window
edge and the ceramic test point TP1 (17) (18)
TDP -AVG
Average dew point average temperature (non–condensing) (19)
TDP-MAX
Elevated dew point temperature range (non-condensing) (20)
CTELR
Cumulative time in elevated dew point temperature range
L
Operating system luminance
28
(18)
(11)
°C
24
Months
4000
lm
2.00
mW/cm2
ILLUV
Illumination Wavelengths < 395 nm
ILLVIS
Illumination Wavelengths between 395 nm and 800 nm
ILLIR
Illumination Wavelengths > 800 nm
10
mW/cm2
(16)
55
deg
ILLθ
Illumination Marginal Ray Angle
0.68
36
mW/cm2
Thermally limited
(9) See LVDS Timing Requirements in Timing Requirements and Figure 6.
(10) See Figure 5 LVDS Waveform Requirements.
(11) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination reduces
device lifetime.
(12) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1
(TP1) shown in Figure 10 and the package thermal resistance Micromirror Array Temperature Calculation.
(13) Per Figure 1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD
experiences in the end application. See Micromirror Landed-On/Landed-Off Duty Cycle for a definition of micromirror landed duty cycle.
(14) Long-term is defined as the usable life of the device.
(15) Array temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up). Short-term is
defined as cumulative time over the usable life of the device and is less than 500 hours.
(16) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors
(POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily been
designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not been tested
nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM) will
contribute to thermal limitations described in this document, and may negatively affect lifetime.
(17) Temperature difference is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown
in Figure 10. The window test points TP2, TP3, TP4 and TP5 shown in Figure 10 are intended to result in the worst case difference
temperature. If a particular application causes another point on the window edge to result in a larger difference in temperature, that point
should be used.
(18) DMD is qualified at the combination of the maximum temperature and maximum lumens specified. Operation of the DMD outside of
these limits has not been tested.
(19) The average over time (including storage and operating) that the device is not in the ‘elevated dew point temperature range.
(20) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR.
12
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Maximum Recommended Array Temperature - Operational (¹C)
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80
70
60
50
40
30
0/100
5/95
10/90
15/85
20/80
25/75
30/70
35/65
40/60
45/55 50/50
100/0
95/5
90/10
85/15
80/20
75/25
70/30
65/35
60/40
55/45
50/50
Micromirror Landed Duty Cycle
Figure 1. Maximum Recommended Array Temperature - Derating Curve
6.5 Thermal Information
DLP480RE
THERMAL METRIC
FXG Package
UNIT
257 PINS
Thermal resistance, active area to test point 1 (TP1) (1)
(1)
0.90
°C/W
The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of
maintaining the package within the temperature range specified in the Recommended Operating Conditions. The total heat load on the
DMD is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by the
window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling
outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.
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6.6 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High level output voltage
VCC = 1.8 V, IOH = –2 mA
VOL
Low level output voltage
VCC = 1.95 V, IOL = 2 mA
IOZ
High impedance output current VCC = 1.95 V
IIL
Low level input current
VCC = 1.95 V, VI = 0
(1) (2)
IIH
High level input current
ICC
Supply current VCC
IOFFSET
Supply current VOFFSET
(2)
(2) (3)
TYP
MAX
0.8 x VCC
UNIT
V
–40
0.2 x VCC
V
25
µA
–1
µA
VCC = 1.95 V, VI = VCC
110
µA
VCC = 1.95 V
715
mA
7
mA
2.75
mA
VOFFSET = 10.5 V
IBIAS
Supply current VBIAS
IRESET
Supply current VRESET
PCC
Supply power dissipation VCC
VCC = 1.95 V
POFFSET
Supply power dissipation
VOFFSET (2)
PBIAS
(3)
MIN
VBIAS = 18.5 V
-5
mA
1394.25
mW
VOFFSET = 10.5 V
73.50
mW
Supply power dissipation
VBIAS (2) (3)
VBIAS = 18.5 V
50.87
mW
PRESET
Supply power dissipation
VRESET (3)
VRESET = –14.5 V
72.5
mW
PTOTAL
Supply power dissipation
VTOTAL
1591.12
mW
(1)
(2)
(3)
VRESET = –14.5 V
Applies to LVCMOS pins only. Excludes LVDS pins and MBRST (15:0) pins.
To prevent excess current, the supply voltage difference |VBIAS – VOFFSET| must be less than the specified limits listed in the
Recommended Operating Conditions table.
To prevent excess current, the supply voltage difference |VBIAS – VRESET| must be less than specified limit in Recommended
Operating Conditions.
6.7 Capacitance at Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CI_lvds
LVDS input capacitance 2× LVDS
ƒ = 1 MHz
20
pF
CI_nonlvds
Non-LVDS input capacitance 2×
LVDS
ƒ = 1 MHz
20
pF
CI_tdiode
Temperature diode input
capacitance 2× LVDS
ƒ = 1 MHz
30
pF
CO
Output capacitance
ƒ = 1 MHz
20
pF
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6.8 Timing Requirements
MIN
NOM
MAX
UNIT
SCP (1)
tr
Rise slew rate
20% to 80% reference points
1
3
V/ns
tf
Fall slew rate
80% to 20% reference points
1
3
V/ns
tr
Rise slew rate
20% to 80% reference points
0.7
1
V/ns
tf
Fall slew rate
80% to 20% reference points
0.7
1
V/ns
tC
Clock cycle
DCLK_C,LVDS pair
2.5
DCLK_D, LVDS pair
2.5
DCLK_C LVDS pair
1.19
1.25
ns
1.19
1.25
ns
LVDS
(2)
tW
Pulse duration
tSu
Setup time
th
Hold time
DCLK_D LVDS pair
ns
ns
D_C(15:0) before DCLK_C, LVDS pair
0.275
ns
D_D(15:0) before DCLK_D, LVDS pair
0.275
ns
SCTRL_C before DCLK_C, LVDS pair
0.275
ns
SCTRL_D before DCLK_D, LVDS pair
0.275
ns
D_C(15:0) after DCLK_C, LVDS pair
0.195
ns
D_D(15:0) after DCLK_D, LVDS pair
0.195
ns
SCTRL_C after DCLK_C, LVDS pair
0.195
ns
SCTRL_D after DCLK_D, LVDS pair
0.195
ns
Channel D relative to Channel C (3) (4), LVDS pair
–1.25
LVDS (2)
tSKEW
(1)
(2)
(3)
(4)
Skew time
1.25
ns
See Figure 3 for Rise Time and Fall Time for SCP.
See Figure 5 for Timing Requirements for LVDS.
Channel C (Bus C) includes the following LVDS pairs: DCLK_CN and DCLK_CP, SCTRL_CN and SCTRL_CP, D_CN(15:0) and
D_CP(15:0).
Channel D (Bus D) includes the following LVDS pairs: DCLK_DN and DCLK_DP, SCTRL_DN and SCTRL_DP, D_DN(15:0) and
D_DP(15:0).
fSCPCLK = 1 / t C
t SCP_NEG_ENZ
tC
SCPENZ
t SCP_POS_ENZ
Falling Edge Capture for SCPDI
Rising Edge Launch for SCPDO
50%
50%
t SCP_DS
xxx
xxx
xxxx
xxxx
SCPCLK
50%
50%
SCPDI
SCPDO
t SCP_DH
DI
50%
50%
50%
50%
DO
t SCP_PD
50%
xx
xx
xx
Figure 2. SCP Timing Requirements
See Recommended Operating Conditions for fSCPCLK, tSCP_DS, tSCP_DH and tSCP_PD specifications.
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Voltage (V)
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VCC
0
tr.
Not to Scale
tf.
Time
Figure 3. SCP Requirements for Rise and Fall
See Timing Requirements for tr and tf specifications and conditions.
Device pin
output under test
Tester channel
CLOAD
Figure 4. Test Load Circuit for Output Propagation Measurement
For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account.
System designers should use IBIS or other simulation tools to correlate the timing reference load to a system
environment.
VLVDS max = VCM max + | 1/2 * VID max |
tf
VCM
VID
tr
VLVDS min = VCM min ± | 1/2 * VID max |
Figure 5. LVDS Waveform Requirements
See Recommended Operating Conditions for VCM, VID, and VLVDS specifications and conditions.
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tc
tw
tw
DCLK_P
DCLK_N
50%
th
th
tsu
tsu
D_P(?:0)
D_N(?:0)
50%
th
th
tsu
tsu
SCTRL_P
SCTRL_N
50%
tskew
tc
tw
tw
DCLK_P
DCLK_N
50%
th
th
tsu
tsu
D_P(?:0)
D_N(?:0)
50%
th
th
tsu
tsu
SCTRL_P
SCTRL_N
50%
Figure 6. Timing Requirements
See Timing Requirements for timing requirements and LVDS pairs per channel (bus) defining D_P(?:0) and
D_N(?:0).
6.9 System Mounting Interface Loads
Table 1. System Mounting Interface Loads
PARAMETER
MIN
NOM
MAX
UNIT
Thermal interface area
12
kg
Electrical interface area
25
kg
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Electrical interface area
Thermal interface area
Figure 7. System Mounting Interface Loads
6.10 Micromirror Array Physical Characteristics
Table 2. Micromirror Array Physical Characteristics
PARAMETER DESCRIPTION
Number of active columns
Number of active rows
(1)
(1)
Micromirror (pixel) pitch
(1)
Micromirror active array width
(1)
Micromirror active array height
(1)
Micromirror active border (Top / Bottom)
Micromirror active border (Right / Left)
(1)
(2)
18
(2)
(2)
VALUE
UNIT
M
1920
micromirrors
N
1200
micromirrors
P
5.4
µm
Micromirror Pitch × number of active columns
10.368
mm
Micromirror Pitch × number of active rows
6.48
mm
Pond of micromirrors (POM)
20
micromirrors/side
Pond of micromirrors (POM)
84
micromirrors/side
See Figure 8.
The structure and qualities of the border around the active array includes a band of partially functional micromirrors referred to as the
Pond Of Mirrors (POM). These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state but
still require an electrical bias to tilt toward the OFF state.
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0
1
2
3
M
M
M
M
±
±
±
±
4
3
2
1
Off-State
Light Path
0
1
2
3
Active Micromirror Array
NxP
M x N Micromirrors
N± 4
N± 3
N± 2
N± 1
MxP
P
Incident
Illumination
Light Path
P
P
Pond Of Micromirrors (POM) omitted for clarity.
Details omitted for clarity.
Not to scale.
P
Figure 8. Micromirror Array Physical Characteristics
Refer to section Micromirror Array Physical Characteristics table for M, N, and P specifications.
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6.11 Micromirror Array Optical Characteristics
Table 3. Micromirror Array Optical Characteristics
PARAMETER
Mirror Tilt angle, variation device to device (1)
MIN
(2)
NOM
15.6
Adjacent micromirrors
Number of out-of-specification micromirrors
(1)
(2)
(3)
(4)
(3) (4)
17.0
MAX
UNIT
18.4
degrees
0
Non-Adjacent
micromirrors
10
micromirrors
Limits on variability of micromirror tilt angle are critical in the design of the accompanying optical system. Variations in tilt angle within a
device may result in apparent non-uniformities, such as line pairing and image mottling, across the projected image. Variations in the
average tilt angle between devices may result in colorimetric and system contrast variations.
See Figure 9.
Efficiency numbers assume 34-degree illumination angle, F/1.7 illumination and collection cones, uniform source spectrum, and uniform
pupil illumination. Efficiency numbers assume 100% electronic micromirror duty cycle and do not include optical overfill loss. The
efficiency is a photopically-weighted number corresponding to 17.5degree tilt angle. Note that this number is specified under conditions
described above and deviations from the specified conditions could result in decreased efficiency.
An out-of-specification micromirror is defined as a micromirror that is unable to transition between the two landed states within the
specified micromirror switching time.
Not to scale.
0
1
2
3
M
M
M
M
±
±
±
±
Details omitted for clarity.
4
3
2
1
Border micromirrors omitted for clarity
Off State
Light Path
0
1
2
3
Tilted Axis of
Pixel Rotation
Off-State
Landed Edge
On-State
Landed Edge
N± 4
N± 3
N± 2
N± 1
Incident
Illumination
Light Path
(1)
Pond of Mirrors (POM) omitted for clarity.
(2)
Refer to section Micromirror Array Physical Characteristics table for M, N, and P specifications.
Figure 9. Micromirror Landed Orientation and Tilt
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6.12 Window Characteristics
Table 4. DMD Window Characteristics
DESCRIPTION
MIN
Window Material Designation
Window Refractive Index at 546.1 nm
1.5119
Window Transmittance, minimum within the wavelength range between 420 nm and 680 nm. Applies to all
angles between 0° and 30° AOI. (1) (2)
97%
Window Transmittance, average over the wavelength range 420 nm and 680 nm. Applies to all angles 30°
and 45° AOI. (1) (2)
97%
(1)
(2)
NOM
Corning
Eagle XG
Single-pass through both surfaces and glass.
Angle of incidence (AOI) is the angle between an incident ray and the normal to a reflecting or refracting surface.
6.13 Chipset Component Usage Specification
Reliable function and operation of the DLP480RE DMD requires that it be used in conjunction with the other
components of the applicable DLP chipset, including those components that contain or implement TI DMD
control technology. TI DMD control technology is the TI technology and devices for operating or controlling a DLP
DMD.
NOTE
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical
system operating conditions exceeding limits described previously.
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7 Detailed Description
7.1 Overview
The DMD is a 0.48 inch diagonal spatial light modulator which consists of an array of highly reflective aluminum
micromirrors. The DMD is an electrical input, optical output micro-optical-electrical-mechanical system (MOEMS).
The electrical interface is Low Voltage Differential Signaling (LVDS). The DMD consists of a two-dimensional
array of 1-bit CMOS memory cells. The array is organized in a grid of M memory cell columns by N memory cell
rows. Refer to the Functional Block Diagram. The positive or negative deflection angle of the micromirrors can be
individually controlled by changing the address voltage of underlying CMOS addressing circuitry and micromirror
reset signals (MBRST).
The DLP480RE DMD is part of the chipset comprising of the DLP480RE DMD, the DLPC4422 display controller
and the DLPA100 power and motor driver. To ensure reliable operation, the DLP480RE DMD must always be
used with the DLPC4422 display controller and the DLPA100 power and motor driver.
DATA_C
SCTRL_C
DCLK_C
VSS
VCC
VOFFSET
VRESET
MBRST
VBIAS
PWRDNZ
SCP
7.2 Functional Block Diagram
Channel C Interface
Column Read and Write
Control
Bit Lines
Control
(0,0)
Voltages
Word Lines
Bit Lines
Micromirror Array
Row
(M-1, N-1)
Bit Lines
Voltage
Generators
Column Read and Write
Control
Control
DATA_D
SCTRL_D
DCLK_D
VSS
VCC
VOFFSET
VRESET
VBIAS
MBRST
RESET_CTRL
Channel D Interface
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For pin details on Channels C, and D, refer to Pin Configurations and Functions and LVDS Interface section of Timing
Requirements.
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7.3 Feature Description
7.3.1 Power Interface
The DMD requires 5 DC voltages: DMD_P3P3V, DMD_P1P8V, VOFFSET, VRESET, and VBIAS. DMD_P3P3V
is created by the DLPA100 power and motor driver and is used on the DMD board to create the other 4 DMD
voltages, as well as powering various peripherals (TMP411, I2C, and TI level translators). DMD_P1P8V is
created by the TI PMIC LP38513S and provides the VCC voltage required by the DMD. VOFFSET (10V),
VRESET (-14V), and VBIAS(18V) are made by the TI PMIC TPS65145 and are supplied to the DMD to control
the micromirrors.
7.3.2 Timing
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. Figure 4 shows an equivalent test load circuit for the output
under test. Timing reference loads are not intended as a precise representation of any particular system
environment or depiction of the actual load presented by a production test. System designers should use IBIS or
other simulation tools to correlate the timing reference load to a system environment. The load capacitance value
stated is only for characterization and measurement of AC timing signals. This load capacitance value does not
indicate the maximum load the device is capable of driving.
7.4 Device Functional Modes
DMD functional modes are controlled by the DLPC4422 display controller. See the DLPC4422 display controller
data sheet or contact a TI applications engineer.
7.5 Window Characteristics and Optics
7.5.1 Optical Interface and System Image Quality
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
Optimizing system optical performance and image quality strongly relate to optical system design parameter
trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described in the following
sections.
7.5.1.1 Numerical Aperture and Stray Light Control
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area
should be the same. This angle should not exceed the nominal device micromirror tilt angle unless appropriate
apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the
projection lens. The micromirror tilt angle defines DMD capability to separate the "ON" optical path from any
other light path, including undesirable flat-state specular reflections from the DMD window, DMD border
structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture
exceeds the micromirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger
than the illumination numerical aperture angle, objectionable artifacts in the display border and/or active area
could occur.
7.5.1.2 Pupil Match
TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally
centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable
artifacts in the display border and/or active area, which may require additional system apertures to control,
especially if the numerical aperture of the system exceeds the pixel tilt angle.
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Window Characteristics and Optics (continued)
7.5.1.3 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks
structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating
conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window
aperture opening and other surface anomalies that may be visible on the screen. The illumination optical system
should be designed to limit light flux incident anywhere on the window aperture from exceeding approximately
10% of the average flux level in the active area. Depending on the particular system optical architecture, overfill
light may have to be further reduced below the suggested 10% level in order to be acceptable.
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7.6 Micromirror Array Temperature Calculation
TP2
Array
2 × 11.75
TP5
TP4
2 × 16.10.
TP3
TP5
TP3 (TP2)
WindowEdge (4 surfaces)
TP4
TP1
5.05
16.10.
TP1
Figure 10. DMD Thermal Test Points
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Micromirror Array Temperature Calculation (continued)
Micromirror array temperature can be computed analytically from measurement points on the outside of the
package, the package thermal resistance, the electrical power, and the illumination heat load. The relationship
between micromirror array temperature and the reference ceramic temperature is provided by the Equation 1 and
Equation 2.
TARRAY = TCERAMIC + (QARRAY × RARRAY-TO-CERAMIC)
QARRAY = QELECTRICAL + QILLUMINATION
(1)
where
•
•
•
•
•
•
•
•
TARRAY = computed array temperature (°C)
TCERAMIC = measured ceramic temperature (°C) (TP1 location)
RARRAY-TO-CERAMIC = thermal resistance of package from array to ceramic TP1 (°C/Watt)
QARRAY = Total DMD power on the array (Watts) (electrical + absorbed)
QELECTRICAL = nominal electrical power
QILLUMINATION = (CL2W × SL)
CL2W = Conversion constant for screen lumens to power on DMD (Watts/Lumen)
SL = measured screen Lumens
(2)
The electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating
frequencies. A nominal electrical power dissipation to use when calculating array temperature is 0.9 Watts. The
absorbed power from the illumination source is variable and depends on the operating state of the micromirrors
and the intensity of the light source. The equations shown above are valid for a 1-Chip DMD system with
projection efficiency from the DMD to the screen of 87%.
The conversion constant CL2W is based on array characteristics. It assumes a spectral efficiency of 300
lumens/Watt for the projected light and illumination distribution of 83.7% on the active array, and 16.3% on the
array border.
Equation 3 through Equation 8 show sample calculations for typical projection application:
CL2W = 0.00266
SL = 4000 lm
QELECTRICAL = 0.9 W
TCERAMIC = 55.0°C
QARRAY = 0.9 W + (0.00266 × 4000 lm) = 11.54 W
TARRAY = 55.0°C + (11.54 W × 0.90°C/W) = 65.39°C
(3)
(4)
(5)
(6)
(7)
(8)
7.7 Micromirror Landed-On/Landed-Off Duty Cycle
7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the On state versus the amount of time the same
micromirror is landed in the OFF state.
As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the ON state 100% of the
time (and in the Off state 0% of the time); whereas 0/100 would indicate that the pixel is in the OFF state 100%
of the time. Likewise, 50/50 indicates that the pixel is ON for 50% of the time (and OFF for 50% of the time).
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other
state (OFF or ON) is considered negligible and is thus ignored.
Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)
always add to 100.
26
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Micromirror Landed-On/Landed-Off Duty Cycle (continued)
7.7.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the DMD micromirror array (also called the active array) to an asymmetric landed
duty cycle for a prolonged period of time can reduce the DMD usable life.
Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed
duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed
duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly
asymmetrical.
7.7.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD temperature and landed duty cycle interact to affect DMD usable life, and this interaction can
be exploited to reduce the impact that an asymmetrical landed duty cycle has on the DMD usable life. This is
quantified in the de-rating curve shown in Figure 1. The importance of this curve is that:
• All points along this curve represent the same usable life.
• All points above this curve represent lower usable life (and the further away from the curve, the lower the
usable life).
• All points below this curve represent higher usable life (and the further away from the curve, the higher the
usable life).
In practice, this curve specifies the Maximum Operating DMD Temperature that the DMD should be operated at
for a given long-term average Landed Duty Cycle.
7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the Landed Duty Cycle of a given pixel follows from the image content being
displayed by that pixel.
For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel
operates under a 100/0 Landed Duty Cycle during that time period. Likewise, when displaying pure-black, the
pixel operates under a 0/100 Landed Duty Cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an
incoming image), the Landed Duty Cycle tracks one-to-one with the gray scale value, as shown in Table 5.
Table 5. Grayscale Value and Landed Duty Cycle
GRAYSCALE VALUE
LANDED DUTY CYCLE
0%
0/100
10%
10/90
20%
20/80
30%
30/70
40%
40/60
50%
50/50
60%
60/40
70%
70/30
80%
80/20
90%
90/10
100%
100/0
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Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from
0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color
cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a given
primary must be displayed in order to achieve the desired white point.
Use Equation 9 to calculate the landed duty cycle of a given pixel during a given time period
Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_%
× Blue_Scale_Value)
where
•
•
•
Red_Cycle_%, represents the percentage of the frame time that red s displayed to achieve the desired white
point
Green_Cycle_% represents the percentage of the frame time that green s displayed to achieve the desired
white point
Blue_Cycle_%, represents the percentage of the frame time that blue is displayed to achieve the desired white
point
(9)
For example, assume that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (in
order to achieve the desired white point), then the Landed Duty Cycle for various combinations of red, green,
blue color intensities would be as shown in Table 6 and Table 7.
Table 6. Example Landed Duty Cycle for Full-Color,
Color Percentage
CYCLE PERCENTAGE
RED
GREEN
BLUE
50%
20%
30%
Table 7. Example Landed Duty Cycle for Full-Color
SCALE VALUE
28
RED
GREEN
BLUE
LANDED DUTY
CYCLE
0%
0%
0%
0/100
100%
0%
0%
50/50
0%
100%
0%
20/80
0%
0%
100%
30/70
12%
0%
0%
6/94
0%
35%
0%
7/93
0%
0%
60%
18/82
100%
100%
0%
70/30
0%
100%
100%
50/50
100%
0%
100%
80/20
12%
35%
0%
13/87
0%
35%
60%
25/75
12%
0%
60%
24/76
100%
100%
100%
100/0
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Texas Instruments DLP technology is a micro-electro-mechanical systems (MEMS) technology that modulates
light using a digital micromirror device (DMD). The DMD is a spatial light modulator, which reflects incoming light
from an illumination source to one of two directions, towards the projection optics or collection optics. The new
TRP pixel with a higher tilt angle increases brightness performance and enables smaller system electronics for
size constrained applications. Typical applications using the DLP480RE include business, education, and large
venue projectors, interactive displays, and portable smart displays.
The most recent class of chipsets from Texas Instruments is based on a breakthrough micromirror technology,
called TRP. With a smaller pixel pitch of 5.4 μm and increased tilt angle of 17 degrees, TRP chipsets enable
higher resolution in a smaller form factor and enhanced image processing features while maintaining high optical
efficiency. DLP chipsets are a great fit for any system that requires high resolution and high brightness displays.
8.2 Typical Application
The DLP480RE DMD combined with a DLPC4422 digital controller and DLPA100 power management device
provides full HD resolution for bright, colorful display applications. A typical display system using the DLP480RE
and additional system components is shown in Figure 11.
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Flash
1.1 V
12 V
1.8 V
16
DATA
DLPA100
(ASIC Voltages)
FE control
Control
signals
DATA
(TTL)
Connector
Field, H/ V-Sync, DE, CLK
Input from
Front End
Board:
1920 × 1200
±14 V
2.5 V
DATA, 30-bit, 1920 × 1200
3.3 V
3.3 V
TPS65145
(DMD Voltages)
10 V
To DMD
18 V
5V
Colorwheel motor control
2 × LVDS (1920 × 1200)
Connector
23
ADDR
Level
Translators
DLP480RE
DMD
DAD control and SCP control
DLPC4422
Master ASIC
Illumination Control (LED, laser,
and lamp control)
TMP411
Temperature
Sensor
GPIO lines
2
USB 1.0, IR, I C, SPI
JTAG
Peripherals
2
I C
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Figure 11. Typical WUXGA Application Diagram
30
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8.2.1 Design Requirements
A DLP480RE projection system is created by using the DMD chipset, including the DLP480RE, DLPC4422, and
DLPA100. The DLP480RE is used as the core imaging device in the display system and contains a 0.48-inch
array of micromirrors. The DLPC4422 controller is the digital interface between the DMD and the rest of the
system, taking digital input from front end receiver and driving the DMD over a high speed interface. The
DLPA100 power management device provides voltage regulators for the DMD, controller, and illumination
functionality.
Other core components of the display system include an illumination source, an optical engine for the illumination
and projection optics, other electrical and mechanical components, and software. The illumination source options
include lamp, LED, laser or laser phosphor. The type of illumination used and desired brightness will have a
major effect on the overall system design and size.
8.2.2 Detailed Design Procedure
For connecting the DLPC4422 display controller and the DLP480RE DMD, see the reference design schematic.
For a complete the DLP system, an optical module or light engine is required that contains the DLP480RE DMD,
associated illumination sources, optical elements, and necessary mechanical components.
To ensure reliable operation, the DLP480RE DMD must always be used with the DLPC4422 display controllers
and a DLPA100 PMIC driver. Refer to PCB Design Requirements for DLP Standard TRP Digital Micromirror
Devices for the DMD board design and manufacturing handling of the DMD sub assemblies.
8.2.3 Application Curves
When LED illumination is utilized, typical LED-current-to-Luminance relationship is shown in Figure 12
Figure 12. Luminance vs. Current
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9 Power Supply Recommendations
The following power supplies are all required to operate the DMD:
• VSS
• VBIAS
• VCC
• VOFFSET
• VRESET
DMD power-up and power-down sequencing is strictly controlled by the DLP display controller.
CAUTION
For reliable operation of the DMD, the following power supply sequencing
requirements must be followed. Failure to adhere to any of the prescribed power-up
and power-down requirements may affect device reliability. See Figure 13 DMD Power
Supply Sequencing Requirements.
VBIAS, VCC, VOFFSET, and VRESET power supplies must be coordinated during
power-up and power-down operations. Failure to meet any of the below requirements
will result in a significant reduction in the DMD reliability and lifetime. Common ground
VSS must also be connected.
9.1 DMD Power Supply Power-Up Procedure
•
•
•
•
•
During power-up, VCC must always start and settle before VOFFSET plus Delay1 specified in Table 8,
VBIAS, and VRESET voltages are applied to the DMD.
During power-up, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be
within the specified limit shown in Recommended Operating Conditions.
During power-up, there is no requirement for the relative timing of VRESET with respect to VBIAS.
Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the
requirements specified in Absolute Maximum Ratings, in Recommended Operating Conditions, and in
Figure 13.
During power-up, LVCMOS input pins must not be driven high until after VCC have settled at operating
voltages listed in Recommended Operating Conditions.
9.2 DMD Power Supply Power-Down Procedure
•
•
•
•
•
32
During power-down, VCC must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to
within the specified limit of ground. See Table 8.
During power-down, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must
be within the specified limit shown in Recommended Operating Conditions.
During power-down, there is no requirement for the relative timing of VRESET with respect to VBIAS.
Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the
requirements specified in Absolute Maximum Ratings, in Recommended Operating Conditions, and in
Figure 13.
During power-down, LVCMOS input pins must be less than specified in Recommended Operating Conditions.
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DMD Power Supply Power-Down Procedure (continued)
Not to scale. Details omitted for clarity
Note 1
VCC
VSS
VOFFSET
Note 4
Delay 1
Note 2
ûV < Specification
VSS
VBIAS
VSS
Note 3
ûV < Specification
VRESET
VSS
EN_OFFSET
VSS
Note 9
Delay 2
PG_OFFSET
Note 5
Note 7
VSS
RESET_OEZ
VSS
Note 6
Note 8
PWRDNZ
and RESETZ
VSS
(1)
See Recommended Operating Conditions, and .
(2)
To prevent excess current, the supply voltage difference |VOFFSET – VBIAS| must be less than specified limit in
Recommended Operating Conditions.
(3)
To prevent excess current, the supply voltage difference |VBIAS – VRESET| must be less than specified limit in
Recommended Operating Conditions.
(4)
VBIAS should power up after VOFFSET has powered up, per the Delay1 specification in Table 8
(5)
PG_OFFSET should turn off after EN_OFFSET has turned off, per the Delay2 specification in Table 8.
(6)
DLP controller software enables the DMD power supplies to turn on after RESET_OEZ is at logic high.
(7)
DLP controller software initiates the global VBIAS command.
(8)
After the DMD micromirror park sequence is complete, the DLP controller software initiates a hardware power-down
that activates PWRDNZ and disables VBIAS, VRESET and VOFFSET.
(9)
Under power-loss conditions where emergency DMD micromirror park procedures are being enacted by the DLP
controller hardware, EN_OFFSET may turn off after PG_OFFSET has turned off. The OEZ signal goes high prior to
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DMD Power Supply Power-Down Procedure (continued)
PG_OFFSET turning off to indicate the DMD micromirror has completed the emergency park procedures.
Figure 13. DMD Power Supply Requirements
Table 8. DMD Power-Supply Requirements
PARAMETER
DESCRIPTION
Delay1
Delay from VOFFSET settled at recommended operating voltage to
VBIAS and VRESET power up
Delay2
PG_OFFSET hold time after EN_OFFSET goes low
34
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MIN
NOM
1
2
100
MAX
UNIT
ms
ns
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10 Layout
10.1 Layout Guidelines
The DLP480RE DMD is part of a chipset that is controlled by the DLPC4422 display controller in conjunction with
the DLPA100 power and motor driver. These guidelines are targeted at designing a PCB board with the
DLP480RE DMD. The DLP480RE DMD board is a high-speed multi-layer PCB, with primarily high-speed digital
logic utilizing dual edge clock rates up to 400MHz for DMD LVDS signals. The remaining traces are comprised of
low speed digital LVTTL signals. TI recommends that mini power planes are used for VOFFSET, VRESET, and
VBIAS. Solid planes are required for DMD_P3P3V(3.3V), DMD_P1P8V and Ground. The target impedance for
the PCB is 50 Ω ±10% with the LVDS traces being 100 Ω ±10% differential. TI recommends using an 8 layer
stack-up as described in Table 9.
10.2 Layout Example
10.2.1 Layers
The layer stack-up and copper weight for each layer is shown in Table 9. Small sub-planes are allowed on signal
routing layers to connect components to major sub-planes on top/bottom layers if necessary.
Table 9. Layer Stack-Up
LAYER
NO.
COPPER WT.
(oz.)
LAYER NAME
1.5
COMMENTS
1
Side A - DMD only
2
Ground
1
3
Signal
0.5
4
Ground
1
Solid ground plane (net GND)
5
DMD_P3P3V
1
+3.3-V power plane (net DMD_P3P3V)
6
Signal
0.5
7
Ground
1
8
Side B - All other Components
1.5
DMD, escapes, low frequency signals, power sub-planes.
Solid ground plane (net GND).
50 Ω and 100 Ω differential signals
50 Ω and 100 Ω differential signals
Solid ground plane (net GND).
Discrete components, low frequency signals, power sub-planes
10.2.2 Impedance Requirements
TI recommends that the board has matched impedance of 50 Ω ±10% for all signals. The exceptions are listed in
Table 10.
Table 10. Special Impedance Requirements
Signal Type
Signal Name
Impedance (ohms)
DDCP(0:15), DDCN(0:15)
C channel LVDS differential pairs
DCLKC_P, DCLKC_N
100 ±10% differential across
each pair
SCTRL_CP, SCTRL_CN
DDDP(0:15), DDDN(0:15)
D channel LVDS differential pairs
DCLKD_P, DCLKD_N
100 ±10% differential across
each pair
SCTRL_DP, SCTRL_DN
10.2.3 Trace Width, Spacing
Unless otherwise specified, TI recommends that all signals follow the 0.005”/0.005” design rule. Minimum trace
clearance from the ground ring around the PWB has a 0.1” minimum. An analysis of impedance and stack-up
requirements determine the actual trace widths and clearances.
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10.2.3.1 Voltage Signals
Table 11. Special Trace Widths, Spacing Requirements
SIGNAL NAME
MINIMUM TRACE WIDTH TO
PINS (MIL)
LAYOUT REQUIREMENT
GND
15
Maximize trace width to connecting pin
DMD_P3P3V
15
Maximize trace width to connecting pin
DMD_P1P8V
15
Maximize trace width to connecting pin
VOFFSET
15
Create mini plane from U2 to U3
VRESET
15
Create mini plane from U2 to U3
VBIAS
15
Create mini plane from U2 to U3
All U3 control
connections
10
Use 10 mil etch to connect all signals/voltages to DMD pads
36
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
DLP480RE FXG
Package Type
Device Descriptor
Figure 14. Part Number Description
11.1.2 Device Markings
The device marking includes both human-readable information and a 2-dimensional matrix code. The humanreadable information is described in Figure 15. The 2-dimensional matrix code is an alpha-numeric character
string that contains the DMD part number, part 1 of serial number, and part 2 of serial number. The first
character of the DMD Serial Number (part 1) is the manufacturing year. The second character of the DMD Serial
Number (part 1) is the manufacturing month. The last character of the DMD Serial Number (part 2) is the bias
voltage bin letter.
Example: *1912-503AB GHXXXXX LLLLLLM
2-Dimension matrix code
(device number and serial number)
TI internal numbering
DMD part number
YYYYYYY
*1912-5bbcB
GHXXXXX
LLLLLLM
Part 1 of serial number
(7 characters)
Part 2 of serial number
(7 characters)
Figure 15. DMD Marking Locations
11.2 Documentation Support
11.2.1 Related Documentation
The following documents contain additional information related to the chipset components used with the
DLP480RE.
• DLPC4422 Display Controller Data Sheet
• DLPA100 Power and Motor Driver Data Sheet
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11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
DLP is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
38
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
DLP480REFXG
PREVIEW
Package Type Package Pins Package
Drawing
Qty
CLGA
FXG
257
33
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
RoHS & Green
(In Work)
Call TI
Call TI
Op Temp (°C)
Device Marking
(4/5)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
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remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
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