D/A Converter Series for Electronic Adjustments High-precision 10bit 4ch・6ch Type D/A Converters BU2508FV, BU2507FV No.09052EAT02 ●Description BU2508FV and BU2507FV ICs are high performance 10bit R-2R-type DACs with 4ch and 6ch outputs, respectively. Each channel incorporates a full swing output-type buffer amplifier with high speed output response characteristics, resulting in a greatly shortened wait time. The ICs also utilize the TTL level input method. ●Features 1) High performance, multi-channels R-2R-type 10bit D/A converter built-in (BU2508FV: 4 channels, BU2507FV: 6 channels) 2) Full swing output type buffer amplifier incorporated at each output channel 3) The RESET terminal can keep the voltage of all channels within the lower reference voltage range 4) Digital input compatible with TTL levels 5) 14bit 3-line serial data + RESET signal input (address 4bit + data 10bit) 6) Compact package: 14 pins, 0.65mm pitch (SSOP-B14) ●Applications DVDs, CD-Rs, CD-RWs, digital cameras ●Lineup Parameter Power source voltage range Number of channels Differential non linearity error Integral non linearity error Data transfer frequency Package ●Absolute Maximum Ratings（Ta=25℃） Parameter Power source voltage D/A converter upper standard voltage Input voltage Output voltage Storage temperature range Power dissipation * BU2507FV BU2508FV 4.5 to 5.5V 6ch ±1.0LSB ±3.5LSB 10MHz SSOP-B14 4.5 to 5.5V 4ch ±1.0LSB ±3.5LSB 10MHz SSOP-B14 Symbol VCC VDD VIN VOUT Tstg Pd Limits -0.3 to 6.0 -0.3 to 6.0 -0.3 to 6.0 -0.3 to 6.0 -55 to 125 350 ＊ Unit V V V V ℃ mW Derated at 3.5mW/℃ at Ta>25℃, mounted on a 70x70x1.6mm FR4 glass epoxy board (copper foil area less than 3%) Note: These products are not robust against radiation ●Recommended Operating Conditions (Ta=25℃） Parameter Power supply voltage range Operating temperature range www.rohm.com © 2009 RzOHM Co., Ltd. All rights reserved. Symbol VCC Topr 1/8 Limits 4.5 to 5.5 -30 to 85 Unit V ℃ 2009.06 - Rev.A Technical Note BU2508FV,BU2507FV ●Electrical Characteristics（Unless otherwise specified, VCC＝5V, VrefH＝5V, VrefL＝0V, Ta＝25℃） Limits Parameter Symbol Unit Conditions MIN. TYP. MAX. <Digital unit> Power source current ICC 0.85 2.8 mA At CLK = 10MHz, IAO = 0uA Input leak current IILK -5 5 μA VIN=0 to VCC Input voltage L VIL 0.8 V Input voltage H VIH 2.0 V Output voltage L VOL 0 0.4 V IOL=2.5mA Output voltage H VOH 4.6 5 V IOH=-2.5mA <Analog unit> 4.5 7.5 mA Consumption current IrefH Data condition : at maximum current 2.0 3.4 mA(*1) D/A converter upper standard voltage setting range VrefH 3.0 - 5 V D/A converter lower standard voltage setting range VrefL 0 - 1.5 V Buffer amplifier output voltage range VO 0.1 0.2 - 4.9 4.75 V Buffer amplifier output drive range IO -2 - 2 mA Differential non-linearity error DNL -1.0 Integral non-linearity error INL -3.5 Precision Zero point error SZERO -25 Full scale error SFULL -25 Buffer amplifier output impedance RO - 5 1.0 3.5 25 25 15 Pull-up I/O internal resistance value 25 37.5 Rup 12.5 LSB mV Ω kΩ Outputs does not necessarily take a value in standard voltage setting range. Value that output may take is in the buffer amplifier output voltage range (VO). IO=±100μA IO=±1.0mA Upper saturation voltage =0.35V Lower saturation voltage =0.23V VrefH =4.796V VrefL=0.7V VCC=5.5V (4mV/LSB) No load (IO = +0mA) Input voltage 0V (Resistance value changes according to voltage to be impressed.) *1: Value in the case where CH1 ~ CH4 are set to maximum current ●Timing Characteristics (Unless otherwise specified, VCC＝5V, VrefH＝5V, VrefL＝0V, Ta＝25℃） Limits Conditions Parameter Symbol Unit Judgment level is 80% / 20% of VCC. MIN. TYP. MAX. Reset L pulse width Clock L pulse width Clock H pulse width Clock rise time Clock fall time Data setup time Data hold time Load setup time Load hold time Load H pulse width tRTL tCKL tCKH tcr tcf tDCH tCHD tCHL tLDC tLDH 50 50 50 20 40 50 50 50 - 50 50 - nS DA output settling time tLDD - 7 20 μS CL≦1000pF, VO:0.5V⇔4.5V . Until output becomes the final value 1/2LSB RESET tRTL tcr tCKH tcf CLK tCKL tLDC DI tLDH LD tDCH tCHD tCHL tLDD Output www.rohm.com © 2009 RzOHM Co., Ltd. All rights reserved. 2/8 2009.06 - Rev.A Technical Note BU2508FV,BU2507FV ●DAC Variable Output Range Function With the variable output range function, the upper / lower limits of the output voltage as well as the power supply voltage can be set. The upper limit value setting terminal VrefH is used as the power supply terminal, while the lower limit value setting terminal VrefL is used as the GND terminal (1LSB ≒ 5mV). In the example below, VrefH = 3.5V / VrefL = 1.5V. Further adjustments can be made in order to achieve greater accuracy (1LSB ≒ 2mV). VOUT VOUT 5V 5V 3.5V VrefH 1024 step ステップ 1024 step ステップ VrefL 1.5V 0V 3FFh Input Code 0V 3FFh Input Code 1LSB≒5.0mV 1LSB≒2.0mV ●Block Diagrams VDD (VrefH) 7 6 AO3 TEST2 5 4 Reset D/A L 3 L Address ｱﾄﾞﾚｽ ﾃﾞｺｰﾀﾞ decoder ・・・ 4 D13 12 11 D10 D9 8 7 6 5 4 14bit Shift register シフトレジスタ 3 2 3 2 AO2 1 VSS (VrefL) Buffer ﾊﾞｯﾌｧ operation ｵﾍﾟｱﾝﾌﾟ amplifier 10bit R-2R D/Aｺﾝﾊﾞｰﾀ DA converter 10bit Latch CH2 10bit Latch CH1 TEST1 1 10bit R-2R D/Aｺﾝﾊﾞｰﾀ DA converter 13 12 AO1 14 DI 3/8 GND 3 2 AO2 1 VSS (VrefL) 10bit R-2R D/Aｺﾝﾊﾞｰﾀ DA converter Buffer operation ﾊﾞｯﾌｧ amplifier ｵﾍﾟｱﾝﾌﾟ AO3 D/A L 3 10bit Latch CH2 10bit Latch CH1 10bit R-2R DAD/Aｺﾝﾊﾞｰﾀ converter 13 14 www.rohm.com © 2009 RzOHM Co., Ltd. All rights reserved. D0 1 D0 DI 12 AO1 GND D/A 8 7 VCC AO4 9 10 LD CLK 11 AO5 6 5 AO4 D/A 4 Reset D/A L 5 L 4 ・・・ 12 11 D10 D9 8 7 6 5 4 2 14bit Shift register シフトレジスタ ｱﾄﾞﾚｽ Address ﾃﾞｺｰﾀﾞ decoder D13 6 L D/A 8 VDD (VrefH) BU2508FV 3 AO6 9 10 LD CLK 11 VCC BU2507FV 2009.06 - Rev.A Technical Note BU2508FV,BU2507FV ●Terminal Description No Terminal name Analog / Digital I/O Equivalent circuit 1 VSS Analog - DA converter lower standard voltage (VrefL) input terminal 6 2 AO2 Analog O 10bit D/A output (CH2) 4 3 AO3(TEST1) Analog O 10bit D/A output (CH3) (BU2508FV : test terminal) 4 4 Reset Digital I All ch analog output L fixed 2 5 AO4(TEST2) Digital I 10bit D/A output (CH4) (BU2508FV : test terminal) 4 6 AO5 (AO3) Analog O 10bit D/A output (CH5) (BU2508FV : 10bit D/A output (CH3)) 4 7 VDD Analog - DA converter upper standard voltage (VrefH) input terminal 5 8 VCC - - Power source terminal - 9 AO6 (AO4) Analog O 10bit D/A output (CH6) (BU2508FV : 10bit D/A output (CH4)) 4 10 LD Digital I When High level is input to LD terminal, the value of 14bit shift register is loaded to decoder and D/A output register. 1 11 CLK Digital I Shift clock input terminal. At rise of shift clock, the signal from DI terminal is input to 14bit shift register. 1 12 DI Digital I Serial data input terminal. Serial data whose data length is 14bit (address 4bit + data 10bit) is input. 1 13 AO1 Analog O 10bit D/A output (CH1) 4 14 GND - - GND terminal - Description of terminal *In the case of BU2508FV, be sure to open TEST1 and TEST2 terminals. www.rohm.com © 2009 RzOHM Co., Ltd. All rights reserved. 4/8 2009.06 - Rev.A Technical Note BU2508FV,BU2507FV ●Command Sending 1) In the case of BU2507FV (1) Data format [data : LSB first] Last MSB First LSB Ｄ13 Ｄ12 Ｄ11 Ｄ10 Ｄ9 Ｄ8 Ｄ7 Ｄ6 Ｄ5 Ｄ4 Ｄ3 Ｄ2 Ｄ1 Ｄ0 For address selection ｱﾄﾞﾚｽ選択用 For D/A converter output setting Ｄ／Ａｺﾝﾊﾞｰﾀ出力設定用 (2) Data timing diagram LSB Ｄ0 DI Ｄ1 Ｄ2 Ｄ3 Ｄ11 Ｄ12 MSB Ｄ13 CLK LD output DA出力 D13 0 0 0 0 ： 1 1 D12 0 0 0 0 ： 1 1 D11 0 0 0 0 ： 1 1 D10 0 0 0 0 ： 1 1 D9 0 0 0 0 ： 1 1 D8 0 0 0 0 ： 1 1 D7 0 0 0 0 ： 1 1 D6 0 0 0 0 ： 1 1 Ｄ3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Ｄ2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D5 0 0 1 1 ： 1 1 D4 0 1 0 1 ： 0 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Ｄ1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Ｄ0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address selection Inconsequential Inconsequential AO1 selection AO2 selection Inconsequential AO3 selection AO4 selection Inconsequential AO5 selection AO6 selection Inconsequential Inconsequential Inconsequential Inconsequential Inconsequential Inconsequential D/A output (VrefH=VDD, VrefL=VSS) VrefL (VrefH-VrefL)/1024×1+VrefL (VrefH-VrefL)/1024×2+VrefL (VrefH-VrefL)/1024×3+VrefL : (VrefH-VrefL)/1024×1022+VrefL (VrefH-VrefL)/1024×1023+VrefL 2) In the case of BU2508FV (1) Data format [Data: LSB first ] Last MSB First LSB Ｄ13 Ｄ12 Ｄ11 Ｄ10 Ｄ9 Ｄ8 Ｄ7 Ｄ6 Ｄ5 Ｄ4 For D/A converter output setting Ｄ／Ａｺﾝﾊﾞｰﾀ出力設定用 Ｄ3 Ｄ2 Ｄ1 Ｄ0 For address selection ｱﾄﾞﾚｽ選択用 (2) Data timing diagram LSB Ｄ0 DI Ｄ1 Ｄ2 Ｄ3 Ｄ11 Ｄ12 MSB Ｄ13 CLK LD output DA出力 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 0 1 0 1 : 0 1 0 0 1 1 : 1 1 0 0 0 0 : 1 1 0 0 0 0 : 1 1 0 0 0 0 : 1 1 0 0 0 0 : 1 1 0 0 0 0 : 1 1 0 0 0 0 : 1 1 0 0 0 0 : 1 1 0 0 0 0 : 1 1 www.rohm.com © 2009 RzOHM Co., Ltd. All rights reserved. 5/8 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address selection Don’t Care Don’t Care AO1 selection AO2 selection Don’t Care Don’t Care Don’t Care Don’t Care AO3 selection AO4 selection Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care D/A output（VrefH=VDD, VrefL=VSS） VrefL (VrefH-VrefL)/1024×1+VrefL (VrefH-VrefL)/1024×2+VrefL (VrefH-VrefL)/1024×3+VrefL : (VrefH-VrefL)/1024×1022+VrefL (VrefH-VrefL)/1024×1023+VrefL 2009.06 - Rev.A Technical Note BU2508FV,BU2507FV 6 6 5 5 5 4 4 4 3 2 1 0 VOUT [V] 6 VOUT [V] VOUT [V] ●Electrical Characteristics Curves 3 2 2 1 1 0 0 0 200 400 600 800 1000 1200 0 200 Input Code [decimal] 400 600 800 1000 0 1200 Fig.2 Output voltage linearity （25℃） 1 1 0.5 0.5 0.5 DNL [LSB] 1 DNL [LSB] 1.5 0 -0.5 -0.5 -1 -1 -1 400 600 800 1000 0 1200 200 600 800 1000 0 1200 1.5 1 1 1 0.5 0.5 0.5 INL [LSB] 1.5 0 -0.5 -0.5 -1 -1 -1 -1.5 -1.5 200 400 600 800 1000 1200 200 400 600 800 1000 1200 0 200 Input Code [decimal] 1000 1200 400 600 800 1000 1200 Fig.9 Integral linearity error （85℃） 2.52 1.5 1 5 Ta=85℃ 2.51 Ta=25℃ VOUT [V] Ta=-30℃ code=1FFh 3 2 code=000h 0.5 DNL [LSB] 4 ICC [mA] 800 Input Code [decimal] Fig.8 Integral linearity error （25℃） 6 600 -1.5 0 Input Code [decimal] Fig.7 Integral linearity error （-30℃） 400 0 -0.5 0 200 Fig.6 Differential linearity error （85℃） 1.5 0 1200 Input Code [decimal] Fig.5 Differential linearity error （25℃） INL [LSB] INL [LSB] 400 Input Code [decimal] Input Code [decimal] Fig.4 Differential linearity error （-30℃） 1000 -1.5 -1.5 200 800 0 -0.5 -1.5 600 Fig.3 Output voltage linearity （85℃） 1.5 0 400 Input Code [decimal] 1.5 0 200 Input Code [decimal] Fig.1 Output voltage linearity （-30℃） DNL [LSB] 3 2.5 Ta=85℃ Ta=25℃ 0 -0.5 Ta=-30℃ 2.49 -1 1 code=3FFh 0 -1.5 -40 10 60 2.48 0 -2.5 Temp. [℃] Fig.10 Circuit current temperature characteristic www.rohm.com © 2009 RzOHM Co., Ltd. All rights reserved. -1.5 -0.5 0.5 1.5 IOUT [mA] Fig.11 Output load fluctuation characteristic (input code : 1FFh) 6/8 200 400 600 800 1000 1200 2.5 Input Code [decimal] Fig.12 Pull-up built in resistance characteristic 2009.06 - Rev.A Technical Note BU2508FV,BU2507FV ●Equivalent Circuits *1 1 to inside to inside 2 4 ・ 3 from inside 5 4 5 ・ 6 6 *1: 25kΩ at Vcc = 5.0V (changes according to voltage supplied) ●Standard Example Application Circuit V refH VCC V refL AO1 CH1 AO2 CH2 AO3 CH3 AO6 CH6 R eset C ontroller LD C LK DI GND ●Operation Notes Ensure that a constant voltage is supplied to each of the 1 ground and 3 power supply terminals. Insert a bypass capacitor between each power supply terminal and ground in order to prevent deterioration of the D/A conversion accuracy due to ripple and noise signals. A capacitor should be inserted between the output and ground in order to eliminate jitter and noise. A capacitance up to 100pF is recommended (including the capacitance of the wire). Inserting a capacitor between the RESET terminal and GND and utilizing a time constant enables power ON reset functionality. Furthermore, when inputting the reset signal from the controller, it is possible to fix the output of all channels to Low at the low area of pulse. www.rohm.com © 2009 RzOHM Co., Ltd. All rights reserved. 7/8 2009.06 - Rev.A Technical Note BU2508FV,BU2507FV ●Ordering part number B U 2 Part No. 5 0 8 F Part No. 2507 2508 V - E Package FV: SSOP-B14 2 Packaging and forming specification E2: Embossed tape and reel SSOP-B14 <Tape and Reel information> 5.0 ± 0.2 8 0.3Min. 4.4 ± 0.2 6.4 ± 0.3 14 1 Tape Embossed carrier tape Quantity 2500pcs Direction of feed E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 7 0.10 1.15 ± 0.1 0.15 ± 0.1 0.65 0.1 0.22 ± 0.1 1pin Reel (Unit : mm) www.rohm.com © 2009 RzOHM Co., Ltd. All rights reserved. 8/8 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2009.06 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. 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