ON CS3842AGDR14 Off-line current mode pwm control circuit with undervoltage lockout Datasheet

CS2842A, CS3842A,
CS2843A, CS3843A
Off−Line Current Mode
PWM Control Circuit with
Undervoltage Lockout
The CS284XA, CS384XA provides all the necessary features to
implement off−line fixed frequency current−mode control with a
minimum number of external components.
The CS384XA family incorporates a new precision
temperature−controlled oscillator with an internally trimmed
discharge current to minimize variations in frequency. A precision
duty−cycle clamp eliminates the need for an external oscillator when a
50% duty−cycle is used. Duty−cycles greater than 50% are also
possible. On board logic ensures that VREF is stabilized before the
output stage is enabled. Ion implant resistors provide tighter control of
undervoltage lockout.
Other features include low startup current, pulse−by−pulse current
limiting, and a high−current totem pole output for driving capacitive
loads, such as the gate of power MOSFET. The output is LOW in the
off state, consistent with N−channel devices.
The CS384XA series of current−mode control ICs are available in
8 and14 lead packages for surface mount (SO) applications as well as
8 lead PDIP packages.
Features
• Optimized for Off−line Control
• Internally Trimmed Temperature Compensated Oscillator
• Maximum Duty−Cycle Clamp
• VREF Stabilized Before Output Stage is Enabled
• Low Startup Current
• Pulse−By−Pulse Current Limiting
• Improved Undervoltage Lockout
• Double Pulse Suppression
• 1.0% Trimmed Bandgap Reference
• High Current Totem Pole Output
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 4
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MARKING
DIAGRAM
8
x84yA
AWL
YYWW
DIP−8
N SUFFIX
CASE 626
8
1
8
1
8
1
SO−8
D SUFFIX
CASE 751
x84yA
ALYWX
14
14
1
SO−14
D SUFFIX
CASE 751A
1
CSx84yA
AWLYWW
1
x
y
A
WL, L
YY, Y
WW, W
= 2 or 3
= 2 or 3
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
1
Publication Order Number:
CS2842A/D
CS2842A, CS3842A, CS2843A, CS3843A
PIN CONNECTIONS
DIP−8 & SO−8
COMP
1
8
VFB
SO−14
COMP
NC
VFB
NC
Sense
NC
OSC
VREF
VCC
VOUT
GND
Sense
OSC
VCC
1
14
VCC Pwr
Undervoltage
Lock−out Circuit
34 V
Set/
Reset
GND
5.0 V
Reference
VREF
16 V/10 V
(8.4 V/7.6 V)
Internal
Bias
2.50 V
OSC
VREF
NC
VCC
VCC Pwr
VOUT
Pwr GND
GND
Output
Enable
NOR
Oscillator
VOUT
+
VFB
COMP
Sense
−
Error
Amplifier
S
2R
VC
R
R
1.0 V
Current
Sensing
Comparator
( ) Indicates CS2843A/3843A
Figure 1. Block Diagram
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2
PWM
Latch
Pwr GND
CS2842A, CS3842A, CS2843A, CS3843A
MAXIMUM RATINGS*
Rating
Value
Unit
Self Limiting
−
30
V
Output Current
±1.0
A
Output Energy (Capacitive Load)
5.0
μJ
−0.3 to + 5.5
V
Error Amp Output Sink Current
10
mA
Package Thermal Resistance, PDIP−8
Junction−to−Case, RθJC
Junction−to−Ambient, RθJA
52
100
°CW
°CW
Package Thermal Resistance, SO−8
Junction−to−Case, RθJC
Junction−to−Ambient, RθJA
45
165
°CW
°CW
Package Thermal Resistance, SO−14
Junction−to−Case, RθJC
Junction−to−Ambient, RθJA
30
125
°CW
°CW
260 peak
230 peak
°C
°C
Supply Voltage (ICC < 30 mA)
Supply Voltage (Low Impedance Source)
Analog Inputs (VFB, Sense)
Lead Temperature Soldering:
Wave Solder (through hole styles only) (Note 1)
Reflow (SMD styles only) (Note 2)
1. 10 second maximum.
2. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
ELECTRICAL CHARACTERISTICS (−25° ≤ TA ≤ 85° for CS2842A/CS2843A, 0° ≤ TA ≤ 70° for CS3842A/CS3843A.
VCC = 15 V*; RT = 680 Ω, CT = 0.022 μF for triangular mode, RT = 10 kΩ, CT = 3.3 nF for sawtooth mode (see Figure 7);
unless otherwise stated.)
Characteristic
Test Conditions
CS2842A/CS2843A
CS3842A/CS3843A
Min
Typ
Max
Min
Typ
Max
Unit
4.95
5.00
5.05
4.90
5.00
5.10
V
Reference Section
Output Voltage
TJ = 25°C, IOUT = 1.0 mA
Line Regulation
12 ≤ VIN ≤ 25 V
−
6.0
20
−
6.0
20
mV
Load Regulation
1.0 ≤ IOUT ≤ 20 mA
−
6.0
25
−
6.0
25
mV
Temperature Stability
Note 3.
−
0.2
0.4
−
0.2
0.4
mV/°C
Total Output Variation
Line, Load, Temperature (Note 3.)
4.90
−
5.10
4.82
−
5.18
V
Output Noise Voltage
10 Hz ≤ f ≤ 10 kHz, TJ = 25°C (Note 3.)
−
50
−
−
50
−
μV
Long Term Stability
TA = 125°C, 1.0 kHrs. (Note 3.)
−
5.0
25
−
5.0
25
mV
Output Short Circuit
TA = 25°C
−30
−100
−180
−30
−100
−180
mA
Initial Accuracy
Sawtooth Mode (see Figure 7), TJ = 25°C
Triangular Mode (see Figure 7), TJ = 25°C
47
47
52
52
57
57
47
44
52
52
57
60
kHz
kHz
Voltage Stability
12 ≤ VCC ≤ 25 V
−
0.2
1.0
−
0.2
1.0
%
Temperature Stability
Sawtooth Mode TMIN ≤ TA ≤ TMAX (Note 3.)
Triangular Mode TMIN ≤ TA ≤ TMAX (Note 3.)
−
−
5.0
8.0
−
−
−
−
5.0
8.0
−
−
%
%
Amplitude
OSC peak to peak
−
1.7
−
−
1.7
−
V
Discharge Current
TJ = 25°C
TMIN ≤ TA ≤ TMAX
7.5
7.2
8.3
−
9.3
9.5
7.5
7.2
8.3
−
9.3
9.5
mA
mA
Oscillator Section
3. These parameters, although guaranteed, are not 100% tested in production.
*Adjust VCC above the start threshold before setting at 15 V.
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3
CS2842A, CS3842A, CS2843A, CS3843A
ELECTRICAL CHARACTERISTICS (continued) (−25° ≤ TA ≤ 85° for CS2842A/CS2843A, 0° ≤ TA ≤ 70° for CS3842A/CS3843A.
VCC = 15 V*; RT = 680 Ω, CT = 0.022 μF for triangular mode, RT = 10 kΩ, CT = 3.3 nF for sawtooth mode (see Figure 7);
unless otherwise stated.)
Characteristic
Test Conditions
CS2842A/CS2843A
CS3842A/CS3843A
Min
Typ
Max
Min
Typ
Max
Unit
2.45
2.50
2.55
2.42
2.50
2.58
V
Error Amp Section
Input Voltage
VCOMP = 2.5 V
Input Bias Current
VFB = 0
−
−0.3
−1.0
−
−0.3
−2.0
μA
AVOL
2.0 ≤ VOUT ≤ 4.0 V
65
90
−
65
90
−
dB
Unity Gain Bandwidth
Note 4.
0.7
1.0
−
0.7
1.0
−
MHz
PSRR
12 ≤ VCC ≤ 25 V
60
70
−
60
70
−
dB
Output Sink Current
VFB = 2.7 V, VCOMP = 1.1 V
2.0
6.0
−
2.0
6.0
−
mA
Output Source Current
VFB = 2.3 V, VCOMP = 5.0 V
−0.5
−0.8
−
−0.5
−0.8
−
mA
VOUT High
VFB = 2.3 V, 15 kΩ to ground
5.0
6.0
−
5.0
6.0
−
V
VOUT Low
VFB = 2.7 V, 15 kΩ to VREF
−
0.7
1.1
−
0.7
1.1
V
Current Sense Section
Gain
Notes 5 & 6.
2.85
3.00
3.15
2.85
3.00
3.15
V/V
Maximum Input Signal
VCOMP = 5.0 V (Note 5.)
0.9
1.0
1.1
0.9
1.0
1.1
V
PSRR
12 ≤ VCC ≤ 25 V (Note 5.)
−
70
−
−
70
−
dB
Input Bias Current
VSENSE = 0
−
−2.0
−10
−
−2.0
−10
μA
Delay to Output
TJ = 25°C (Note 4.)
−
150
300
−
150
300
ns
Output Low Level
ISINK = 20 mA
ISINK = 200 mA
−
−
0.1
1.5
0.4
2.2
−
−
0.1
1.5
0.4
2.2
V
V
Output High Level
ISOURCE = 20 mA
ISOURCE = 200 mA
13
12
13.5
13.5
−
−
13
12
13.5
13.5
−
−
V
V
Rise Time
TJ = 25°C, CL = 1.0 nF (Note 4.)
−
50
150
−
50
150
ns
Fall Time
TJ = 25°C, CL = 1.0 nF (Note 4.)
−
50
150
−
50
150
ns
Output Leakage
UVLO Active, VOUT = 0
−
−0.01
−10.00
−
−0.01
−10.00
μA
−
0.5
1.0
−
0.5
1.0
mA
Output Section
Total Standby Current
−
Startup Current
Operating Supply Current
VFB = VSENSE = 0 V,
RT = 10 kΩ, CT = 3.3 nF
11
17
−
11
17
−
mA
VCC Zener Voltage
ICC = 25 mA
−
34
−
−
34
−
V
4. These parameters, although guaranteed, are not 100% tested in production.
5. Parameters measured at trip point of latch with VFB = 0.
6. Gain defined as: A = ΔVCOMP/ΔVSENSE; 0 ≤ VSENSE ≤ 0.8 V.
*Adjust VCC above the start threshold before setting at 15 V.
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4
CS2842A, CS3842A, CS2843A, CS3843A
ELECTRICAL CHARACTERISTICS (continued) (−25° ≤ TA ≤ 85° for CS2842A/CS2843A, 0° ≤ TA ≤ 70° for CS3842A/CS3843A.
VCC = 15 V*; RT = 680 Ω, CT = 0.022 μF for triangular mode, RT = 10 kΩ, CT = 3.3 nF for sawtooth mode (see Figure 7);
unless otherwise stated.)
CS2842A
Characteristic
Test Conditions
CS3842A
CS2843A/CS3843A
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
15
16
17
14.5
16
17.5
7.8
8.4
9.0
V
9.0
10
11
8.5
10
11.5
7.0
7.6
8.2
V
Undervoltage Lockout Section
−
Start Threshold
Min. Operating Voltage
After Turn On
*Adjust VCC above the start threshold before setting at 15 V.
PACKAGE PIN DESCRIPTION
Package Pin Number
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DIP−8
SO−8
SO−14
Symbol
1
1
1
COMP
2
2
3
VFB
3
3
5
Sense
4
4
7
OSC
Oscillator timing network with capacitor to ground, resistor to VREF.
5
5
8
GND
Ground.
−
−
9
Pwr GND
6
6
10
VOUT
−
−
11
VCC Pwr
7
7
12
VCC
Positive power supply.
8
8
14
VREF
Output of 5.0 V internal reference.
−
−
2, 4, 6, 13
NC
Description
Error amp output, used to compensate error amplifier.
Error amp inverting input.
Noninverting input to Current Sense Comparator.
Output driver ground.
Output drive pin.
Output driver positive supply.
No connection.
TYPICAL PERFORMANCE CHARACTERISTICS
100
900
90
RT = 680 Ω
700
Duty Cycle (%)
600
300
40
30
20
RT = 10 kΩ
RT (Ω)
Figure 2. Oscillator Frequency vs. CT
7k
.02 .03 .04 .05
10 k
.01
CT (μF)
3k
4k
5k
.002 .003 .005
2k
.001
10
1k
100
700
200
.0005
60
50
300
400
500
400
RT = 1.5 kΩ
70
200
500
80
100
Frequency (kHz)
800
Figure 3. Oscillator Duty Cycle vs. RT
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5
CS2842A, CS3842A, CS2843A, CS3843A
VREF
RT
A
VCC
2N2222
4.7 kΩ
COMP
100 kΩ
1.0 kΩ
ERROR AMP
ADJUST
4.7 kΩ
VREF
0.1 μF
VFB
VCC
1.0 kΩ
1.0 W
0.1 μF
5.0 kΩ
Sense
ADJUST
Sense
VOUT
OSC
GND
VOUT
GND
CT
Figure 4. Test Circuit
CIRCUIT DESCRIPTION
VCC
OSC
ON/OFF Command
to reset of IC
CSX842A
CSX843A
VON
16 V
8.4 V
VOFF
10 V
7.6 V
OSC
RESET
EA Output
Switch
Current
VCC
ICC
IO
< 15 mA
VO
< 1.0 mA
VON VOFF
VCC
Figure 6. Timing Diagram for Key CS2841B
Parameters
Figure 5. Typical Undervoltage Characteristics
When the power supply sees a sudden large output current
increase, the control voltage will increase allowing the duty
cycle to momentarily increase. Since the duty cycle tends to
exceed the maximum allowed to prevent transformer
saturation in some power supplies, the internal oscillator
waveform provides the maximum duty cycle clamp as
programmed by the selection of oscillator components.
Undervoltage Lockout
During Undervoltage Lockout (Figure 5), the output
driver is biased to a high impedance state. The output should
be shunted to ground with a resistor to prevent output
leakage current from activating the power switch.
PWM Waveform
To generate the PWM waveform, the control voltage from
the error amplifier is compared to a current sense signal which
represents the peak output inductor current (Figure 6). An
increase in VCC causes the inductor current slope to increase,
thus reducing the duty cycle. This is an inherent feed−forward
characteristic of current mode control, since the control
voltage does not have to change during changes of input
supply voltage.
Setting the Oscillator
Oscillator timing capacitor, CT, is charged by VREF
through RT and discharged by an internal current source.
During the discharge time, the internal clock signal blanks
out the output to the Low state, thus providing a user selected
maximum duty cycle clamp. Charge and discharge times are
determined by the formula:
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6
CS2842A, CS3842A, CS2843A, CS3843A
ǒ
V
* Vlower
tc + RTCT ln REF
VREF * Vupper
Ǔ
ǒ
V
* IdRT * Vlower
td + RTCT ln REF
VREF * IdRT * Vupper
VREF
Ǔ
RT
OSC
Substituting in typical values for the parameters in the
above formulas:
VREF = 5.0 V
Vupper = 2.7 V
Vlower = 1.0 V
Id = 8.3 mA
tc ≈ 0.5534RTCT
ǒ
2.3 * 0.0083RT
td + RTCT ln
4.0 * 0.0083RT
CT
GND
Timing Parameters
Vupper
Ǔ
Vlower
The frequency and maximum duty cycle can be
determined using the Typical Performance Characteristic
graphs.
tc
td
Sawtooth Mode
Large RT (≈ 10 kΩ)
Grounding
High peak currents associated with capacitive loads
necessitate careful grounding techniques. Timing and
bypass capacitors should be connected close to GND pin in
a single point ground.
The transistor and 5.0 kΩ potentiometer, shown in the test
circuit, are used to sample the oscillator waveform and apply
and adjustable ramp to Sense.
VOSC
Internal Clock
Triangular Mode
Small RT (≈ 700 kΩ)
VOSC
Internal Clock
Figure 7. Oscillator Timing Network and
Parameters
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7
CS2842A, CS3842A, CS2843A, CS3843A
ORDERING INFORMATION
Device
Temperature Range
Package
Shipping
DIP−8
50 Units/Rail
DIP−8
50 Units/Rail
SO−14
55 Units/Rail
CS2842ALDR14
SO−14
2500 Tape & Reel
CS3842AGN8
DIP−8
50 Units/Rail
CS3842AGD8
SO−8
98 Units/Rail
CS3842AGDR8
SO−8
2500 Tape & Reel
CS3842AGD14
SO−14
55 Units/Rail
SO−14
2500 Tape & Reel
DIP−8
50 Units/Rail
CS2842ALN8
CS2843ALN8
CS2842ALD14
CS3842AGDR14
CS3843AGN8
−25°C to 85°C
0°C to 70°C
CS3843AGD8
SO−8
98 Units/Rail
CS3843AGDR8
SO−8
2500 Tape & Reel
CS3843AGD14
SO−14
55 Units/Rail
CS3843AGDR14
SO−14
2500 Tape & Reel
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8
CS2842A, CS3842A, CS2843A, CS3843A
PACKAGE DIMENSIONS
DIP−8
N SUFFIX
CASE 626−05
ISSUE L
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
−B−
1
4
DIM
A
B
C
D
F
G
H
J
K
L
M
N
F
−A−
NOTE 2
L
C
J
−T−
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
−−−
10_
0.76
1.01
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
−−−
10_
0.030
0.040
N
SEATING
PLANE
D
M
K
G
H
0.13 (0.005)
M
T A
M
B
M
SO−8
D SUFFIX
CASE 751−07
ISSUE W
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
A
8
5
S
B
1
0.25 (0.010)
M
Y
M
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
H
0.10 (0.004)
D
0.25 (0.010)
M
Z Y
S
X
M
S
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9
J
DIM
A
B
C
D
G
H
J
K
M
N
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0_
8_
0.010
0.020
0.228
0.244
CS2842A, CS3842A, CS2843A, CS3843A
PACKAGE DIMENSIONS
SO−14
D SUFFIX
CASE 751A−03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−A−
14
8
−B−
1
0.25 (0.010)
7
G
D 14 PL
0.25 (0.010)
T B
B
M
F
J
M
K
M
M
R X 45 _
C
−T−
SEATING
PLANE
P 7 PL
S
A
S
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.228
0.244
0.010
0.019
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CS2842A/D