AD AD14060L Dsp multiprocessor family Datasheet

Quad-SHARC®
DSP Multiprocessor Family
AD14060/AD14060L
CS
TIMEXP
LINK 1
LINK 3
LINK 4
IRQ2–0
FLAG2, 0
CPA
SPORT 1
SPORT 0
TCK, TMS, TRST
FLAG1
FLAG3
TDO
LINK 0
LINK 2
LINK 5
TDI
SHARC_B
EBOOT,
LBOOT, BMS
EMU
CLKIN
RESET
SPORT 0
TCK, TMS, TRST
FLAG1
FLAG3
EBOOT,
LBOOT, BMS
EMU
CLKIN
RESET
SHARC_A
(ID2–0 = 1)
LINK 0
LINK 2
LINK 5
TDO
(ID2–0 = 2)
SHARC BUS (ADDR31–0, DATA47–0, MS3-0, RD, WR, PAGE, ADRCLK,
,
SW, ACK, SBTS, HBR, HBG, REDY, BR
, RPBA, DMAR , DMAG )
SHARC_C
LINK 0
LINK 2
LINK 5
TDO
(ID2–0 = 3)
CPA
SPORT 1
CS
TIMEXP
LINK 1
LINK 3
LINK 4
IRQ2–0
FLAG2, 0
LINK 0
LINK 2
LINK 5
TDI
1.2
SPORT 0
TCK,TMS, TRST
FLAG1
FLAG3
TDI
SHARC_D
CPA
(ID2–0 = 4)
SPORT 1
TDO
1.2
EBOOT,
LBOOT, BMS
EMU
CLKIN
RESET
6–1
SPORT 0
TCK,TMS, TRST
FLAG1
FLAG3
308-lead ceramic quad flatpack (CQFP)
2.05" (52 mm) body size
Cavity up or down, configurable
Low profile, 0.160" height
Hermetic
25 Mil (0.65 mm) lead pitch
29 grams (typical)
θJC = 0.36°C/W
CPA
SPORT 1
TDI
CS
TIMEXP
LINK 1
LINK 3
LINK 4
IRQ2–0
FLAG2, 0
PACKAGING FEATURES
FUNCTIONAL BLOCK DIAGRAM
EBOOT,
LBOOT, BMS
EMU
CLKIN
RESET
ADSP-21060 core processor ( × 4)
480 MFLOPS peak, 320 MFLOPS sustained
25 ns instruction rate, single-cycle
instruction execution—each of four processors
16 Mbit shared SRAM (internal to SHARCs)
4 gigawords addressable off-module memory
Twelve 40 Mbyte/s link ports (3 per SHARC)
Four 40 Mbit/s independent serial ports
(one from each SHARC)
One 40 Mbit/s common serial port
5 V and 3.3 V operation
32-bit single precision and 40-bit extended
precision IEEE floating point data formats, or
32-bit fixed point data format
IEEE JTAG Standard 1149.1 test access port and
on-chip emulation
CS
TIMEXP
LINK 1
LINK 3
LINK 4
IRQ2–0
FLAG2, 0
PERFORMANCE FEATURES
AD14060/AD14060L
00667-001
Figure 1.
GENERAL DESCRIPTION
The AD14060/AD14060L Quad-SHARC is the first in a family
of high performance DSP multiprocessor modules. The core of
the multiprocessor is the ADSP-21060 DSP microcomputer. The
AD14060/AD14060L has the highest performance-to-density
and lowest cost-to-performance ratios of any in its class. It is
ideal for applications requiring higher levels of performance
and/or functionality per unit area.
32 address) is also brought off-module for interfacing with
expansion memory or other peripherals.
The AD14060/AD14060L takes advantage of the built-in
multiprocessing features of the ADSP-21060 to achieve
480 peak MFLOPS with a single chip type in a single package.
The on-chip SRAM of the DSPs provides 16 Mbits of onmodule shared SRAM. The complete shared bus (48 data,
Multiprocessor performance is enhanced with embedded power
and ground planes, matched impedance interconnect, and
optimized signal routing lengths and separation. The fully
tested and ready-to-insert multiprocessor also significantly
reduces board space.
The ADSP-21060 link ports are interconnected to provide direct
communication among the four SHARCs, as well as high speed
off-module access. Internally, each SHARC has a direct link port
connection. Externally, each SHARC has a total of 120 Mbytes/s
link port bandwidth.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD14060/AD14060L
TABLE OF CONTENTS
Specifications..................................................................................... 3
Link Port I/O............................................................................... 38
Electrical Characteristics (3.3 V, 5 V Supply)............................ 3
Serial Ports .................................................................................. 38
Explanation of Test Levels........................................................... 4
Program Booting ........................................................................ 38
Timing Specifications....................................................................... 5
Host Processor Interface ........................................................... 39
Memory Read—Bus Master........................................................ 8
Direct Memory Access (DMA) Controller ............................. 39
Memory Write—Bus Master ....................................................... 9
Applications..................................................................................... 40
Synchronous Read/Write—Bus Master................................... 10
Development Tools .................................................................... 40
Synchronous Read/Write—Bus Slave ...................................... 12
Quad-SHARC Development Board......................................... 40
Multiprocessor Bus Request and Host Bus Request .............. 13
Other Package Details................................................................ 40
Asynchronous Read/Write—Host to AD14060/AD14060L. 15
Target Board Connector for Emulator Probe......................... 40
Three-State Timing—Bus Master, Bus Slave, HBR, SBTS ..... 17
Output Drive Currents .............................................................. 42
DMA Handshake........................................................................ 18
Power Dissipation ...................................................................... 42
Absolute Maximum Ratings.......................................................... 27
Test Conditions........................................................................... 43
ESD Caution................................................................................ 27
Assembly Recommendations.................................................... 45
Pin Configuration and Function Descriptions........................... 28
PCB Layout Guidelines.............................................................. 46
Pin Function Descriptions ........................................................ 30
Mechanical Characteristics ....................................................... 47
Detailed Description ...................................................................... 34
Additional Information ............................................................. 47
Architectural Features................................................................ 34
Outline Dimensions ....................................................................... 48
Shared Memory Multiprocessing ............................................. 34
Ordering Guide .......................................................................... 48
Off-Module Memory and Peripherals Interface .................... 36
REVISION HISTORY
12/04—Rev. A to Rev. B
Format Updated..................................................................Universal
Changes to Specifications Section.................................................. 3
Changes to Development Tools Section ...................................... 40
Changes to Target Board for Emulator Probe Section .............. 40
Changes to Figure 27...................................................................... 42
Updated Outline Dimensions ....................................................... 48
Changes to Ordering Guide .......................................................... 48
10/97—Rev. 0 to Rev. A
4/97—Revision 0: Initial Version
Rev. B | Page 2 of 48
AD14060/AD14060L
SPECIFICATIONS
Table 1. Recommended Operating Conditions
Parameter
VDD
TCASE
Min
4.75
3.15
−40
Supply Voltage (5 V)
Supply Voltage (3.3 V)
Case Operating Temperature
B Grade
Max
5.25
3.6
+100
Min
4.75
3.15
0
K Grade
Max
5.25
3.6
+85
Unit
V
V
°C
ELECTRICAL CHARACTERISTICS (3.3 V, 5 V SUPPLY)
Table 2.
Full
Full
Full
Full
Full
I
I
@ VDD = min, IOH = −2.0 mA
@ VDD = min, IOL = 4.0 mA
IIH
IIL
High Level Input Voltage1
High Level Input Voltage2
Low Level Input Voltage1, 2
High Level Output Voltage3, 4
Low Level Output Voltage3, 4
High Level Input Current5, 6, 7
Low Level Input Current5
Test
Level
I
I
I
Full
Full
I
I
IILP
Low Level Input Current6
Full
IILPX4
Low Level Input Current7
Three-State Leakage Current8, 9, 10, 11
Three-State Leakage Current8, 12
Full
Full
Full
Full
IOZLC
IOZLA
Three-State Leakage Current12
Three-State Leakage Current13
Three-State Leakage Current14
Full
Full
IOZLAR
Three-State Leakage Current10
Full
IOZLS
Three-State Leakage Current9
Full
IOZLSX4
Three-State Leakage Current11
Supply Current (Internal)15
Supply Current (Idle)16
Input Capacitance17, 18
Full
I
@ VDD = max, VIN = 0 V
Full
Full
25°C
IV
I
V
tCK = 25 ns, VDD = max
VDD = max
Parameter
VIH1
VIH2
VIL
VOH
VOL
IOZH
IOZL
IOZHP
IDDIN
IDDIDLE
CIN
Case
Temp
Test Condition
Min
2.0
2.2
@ VDD = max
@ VDD = max
@ VDD = min
5V
Typ Max
VDD + 0.5
VDD + 0.5
0.8
3.3 V
Typ Max
VDD + 0.5
VDD + 0.5
0.8
2.4
Unit
V
V
V
0.4
0.4
V
V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
10
10
10
10
µA
µA
I
@ VDD = max, VIN = 0 V
150
150
µA
I
@ VDD = max, VIN = 0 V
600
600
µA
I
I
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
10
10
10
10
µA
µA
I
@ VDD = max, VIN = VDD max
350
350
µA
I
I
1.5
350
1.5
350
mA
µA
I
@ VDD = max, VIN = 0 V
@ VDD = max,
VIN = 1.5 V (5 V), 2 V (3.3 V)
@ VDD = max, VIN = 0 V
4.2
4.2
mA
I
@ VDD = max, VIN = 0 V
150
150
µA
4
4.1
Min
2.0
2.2
4
600
1.4
15
1
2.92
800
1.0
15
600
µA
2.2
760
A
mA
pF
Applies to input and bidirectional pins: DATA47-0, ADDR31-0, RD, WR, SW, ACK, STBS, IRQy2-0, FLAGy0, FLAG1, FLAGy2, HBG, CSy, DMAR1, DMAR2, BR6-1, RPBA, CPAy, TFS0,
TFSy1, RFS0, RFSy1, LyxDAT3-0, LyxCLK, LyxACK, EBOOTA, LBOOTA, EBOOTBCD, LBOOTBCD, BMSA, BMSBCD, TMS, TDI, TCK, HBR, DR0, DRy1, TCLK0, TCLKy1, RCLK0,
RCLKy1.
2
Applies to input pins: CLKIN, RESET, TRST.
3
Applies to output and bidirectional pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, TIMEXPy, HBG, REDY, DMAG1, DMAG2,
BR6-1, CPAy, DTO, DTy1, TCLK0, TCLKy1, RCLK0, RCLKy1, TFS0, TFSy1, RFS0, RFSy1, LyxDAT3-0, LyxCLK, LyxACK, BMSA, BMSBCD, TDO, EMU.
4
See the Output Drive Currents section for typical drive current capabilities.
5
Applies to input pins: STBS, IRQy2-0, HBR, CSy, DMAR1, DMAR2, RPBA, EBOOTA, LBOOTA, EBOOTBCD, LBOOTBCD, CLKIN, RESET, TCK.
6
Applies to input pins with internal pull-ups: DR0, DRy1, TDI.
7
Applies to bused input pins with internal pull-ups: TRST, TMS.
8
Applies to three-statable pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, REDY, HBG, DMAG1, DMAG2, BMSA, BMSBCD, TDO,
EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2-0 = 001 and another ADSP-2106x is not requesting bus
mastership. HBG and EMU are not tested for leakage current.)
9
Applies to three-statable pins with internal pull-ups: DTy1, TCLKy1, RCLKy1.
10
Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2-0 = 001 and another
ADSP-2106x is not requesting bus mastership.)
11
Applies to bused three-statable pins with internal pull-ups: DT0, TCLK0, RCLK0.
12
Applies to three-statable pins with internal pull-downs: LyxDAT3-0, LyxCLK, LyxACK.
13
Applies to CPAy pin.
14
Applies to ACK pin, when the keeper latch is enabled.
15
Applies to VDD pins. Conditions of operation: each processor is executing radix-2 FFT butterfly with instruction in cache, one data operand is fetched from each
internal memory block, and one DMA transfer is occurring from/to internal memory at tCK = 25 ns.
16
Applies to VDD pins. Idle denotes AD14060/AD14060L state during execution of IDLE instruction.
17
Applies to all signal pins.
18
Guaranteed, but not tested.
Rev. B | Page 3 of 48
AD14060/AD14060L
EXPLANATION OF TEST LEVELS
Test
I
II
III
IV
V
VI
1
Level
100% production tested.1
100% production tested at 25°C, and sample tested at
specified temperatures.
Sample tested only.
Parameter is guaranteed by design and analysis, and
characterization testing on discrete SHARCs.
Parameter is typical value only.
All devices are 100% production tested at 25°C, and
sample tested at temperature extremes.
Link and serial ports: All are 100% tested at die level prior to assembly. All are
100% ac tested at module level; Link 4 and Serial 0 are also dc tested at the
module level. See the Timing Specifications section.
Rev. B | Page 4 of 48
AD14060/AD14060L
TIMING SPECIFICATIONS
reflect statistical variations and worst cases. Consequently, one
cannot meaningfully add parameters to derive longer times.
This data sheet represents production-released specifications
for the AD14060 (5 V), and for the AD14060L (3.3 V). The
ADSP-21060 die components are 100% tested, and the
assembled AD14060/AD14060L units are again extensively
tested at speed and across temperature. Parametric limits were
established from the ADSP-21060 characterization followed by
further design and analysis of the AD14060/AD14060L package
characteristics.
Switching Characteristics specify how the processor changes its
signals. The user has no control over this timing—circuitry
external to the processor must be designed for compatibility
with these signal characteristics. Switching characteristics
specify what the processor does in a given circumstance. The
user can also use switching characteristics to ensure that any
timing requirement of a device connected to the processor
(such as memory) is satisfied.
The specifications are based on a CLKIN frequency of 40 MHz
(tCK = 25 ns). The DT derating allows specifications at other
CLKIN frequencies (within the minimum to maximum range
of the tCK specification; see Table 3). DT is the difference
between the actual CLKIN period and a CLKIN period of 25 ns:
Timing Requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the
processor operates correctly with other devices.
DT = tCK − 25 ns
(O/D) = Open Drain
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
(A/D) = Active Drive
Table 3. Clock Input
Parameter
Clock Input
Timing Requirements:
tCK
CLKIN Period
tCKL
CLKIN Width Low
tCKH
CLKIN Width High
tCKRF
CLKIN Rise/Fall (0.4 V to 2.0 V)
40 MHz (5 V)
Max
Min
25
7
5
100
Min
25
9.5
5
3
tCKL
Figure 2. Clock Input
Rev. B | Page 5 of 48
00667-011
tCKH
100
3
tCK
CLKIN
40 MHz (3.3 V)
Max
Unit
ns
ns
ns
ns
AD14060/AD14060L
Table 4. Reset
5V
Parameter
Reset
Timing Requirements:
tWRST
RESET Pulse Width Low1
tSRST
RESET Setup before CLKIN High2
Min
Max
Min
4 tCK
14 + DT/2
tCK
4 tCK
14 + DT/2
3.3 V
Max
tCK
Unit
ns
ns
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET is
low, assuming stable VDD and CLKIN (not including start-up time of the external clock oscillator).
2
Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (that is, for a SIMD system). Not required for
multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.
CLKIN
tSRST
00667-012
tWRST
RESET
Figure 3. Reset
Table 5. Interrupts
Parameter
Interrupts
Timing Requirements:
tSIR
IRQ2-0 Setup before CLKIN High1
tHIR
IRQ2-0 Hold before CLKIN High1
tIPW
IRQ2-0 Pulse Width2
2
Min
18 + 3 DT/4
Min
3.3 V
Max
18 + 3 DT/4
11.5 + 3 DT/4
2 + tCK
11.5 + 3 DT/4
2 + tCK
Only required for IRQx recognition in the following cycle.
Applies only if tSIR and tHIR requirements are not met.
CLKIN
tSIR
tHIR
IRQ2–0
tIPW
Figure 4. Interrupts
Rev. B | Page 6 of 48
00667-013
1
5V
Max
Unit
ns
ns
ns
AD14060/AD14060L
Table 6. Timer
Parameter
Timer
Switching Characteristic:
tDTEX
CLKIN High to TIMEXP
5V
Max
Min
Min
3.3 V
Max
16
Unit
16
ns
CLKIN
tDTEX
00667-014
tDTEX
TIMEXP
Figure 5. Timer
Table 7. Flags
Parameter
Flags
Timing Requirements:
tSFI
FLAG2-0IN Setup before CLKIN High1
tHFI
FLAG2-0IN Hold after CLKIN High1
tDWRFI
FLAG2-0IN Delay after RD/WR Low1
tHFIWR
FLAG2-0IN Hold after RD/WR De-asserted1
Switching Characteristics:
tDFO
FLAG2-0OUT Delay after CLKIN High
tHFO
FLAG2-0OUT Hold after CLKIN High
tDFOE
CLKIN High to FLAG2-0OUT Enable
tDFOD
CLKIN High to FLAG2-0OUT Disable
8 + 5 DT/16
0.5 − 5 DT/16
Min
3.3 V
Max
8 + 5 DT/16
0.5 − 5 DT/16
4.5 + 7 DT/16
0.5
4.5 + 7 DT/16
0.5
17
4
3
17
4
3
15
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Flag inputs that meet these setup and hold times affect conditional instructions in the following instruction cycle.
CLKIN
tDFOE
tDFO
tHFO
tDFO
tDFOD
FLAG2–0OUT
FLAG OUTPUT
CLKIN
tSFI
tHFI
FLAG2–0IN
tDWRFI
tHFIWR
RD, WR
00667-015
1
5V
Max
Min
FLAG INPUT
Figure 6. Flags
Rev. B | Page 7 of 48
AD14060/AD14060L
MEMORY READ—BUS MASTER
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN.
These specifications apply when the AD14060/AD14060L is the bus master accessing external memory space.
These switching characteristics also apply for bus master synchronous read/write timing (see the Synchronous Read/Write—Bus Master
section). If these timing requirements are met, the synchronous read/write timing can be ignored (and vice versa).
Table 8. Specifications
Parameter
Timing Requirements:
tDAD
Address, Delay to Data Valid1, 2
tDRLD
RD Low to Data Valid1
tHDA
Data Hold from Address3
tHDRH
Data Hold from RD High3
tDAAK
ACK Delay from Address2, 4
tDSAK
ACK Delay from RD Low4
Switching Characteristics:
tDRHA
Address Hold after RD High
tDARL
Address to RD Low2
tRW
RD Pulse Width
tRWR
RD High to WR, RD, DMAGx Low
tSADADC
Address Setup before ADRCLK High2
5V
Max
Min
Min
3.3 V
Max
17.5 + DT + W
11.5 + 5 DT/8 + W
1
2.5
Unit
17.5 + DT + W
11.5 + 5 DT/8 + W
1
2.5
13.5 + 7 DT/8 + W
7.5 + DT/2 + W
−0.5 + H
1.5 + 3 DT/8
12.5 + 5 DT/8 + W
8 + 3 DT/8 + HI
−0.5 + DT/4
13.5 + 7 DT/8 + W
7.5 + DT/2 + W
−0.5 + H
1.5 + 3 DT/8
12.5 + 5 DT/8 + W
8 + 3 DT/8 + HI
−0.5 + DT/4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
W = number of wait states specified in WAIT register × tCK.
HI = tCK, if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise, HI = 0.
H = tCK, if an address hold cycle occurs as specified in WAIT register; otherwise, H = 0.
1
Data delay/setup: User must meet tDAD, tDRLD, or synchronous specification, tSSDATI.
For MSx, SW, BMS, the falling edge is referenced.
3
Data hold: User must meet tHDA, tHDRH, or synchronous specification, tHDATI. See the System Hold Time Calculation Example section for the calculation of hold times given
capacitive and dc loads.
4
ACK delay/setup: User must meet tDSAK, tDAAK, or synchronous specification, tSACKC.
2
ADDRESS
MSx, SW
BMS
tDARL
tRW
tDRHA
RD
tDRLD
tDAD
tHDA
tHDRH
DATA
tDSAK
tRWR
tDAAK
ACK
tSADADC
00667-016
WR, DMAG
ADRCLK
(OUT)
Figure 7. Memory Read—Bus Master
Rev. B | Page 8 of 48
AD14060/AD14060L
MEMORY WRITE—BUS MASTER
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN.
These specifications apply when the AD14060/AD14060L is the bus master accessing external memory space.
These switching characteristics also apply for bus master synchronous read/write timing (see the Synchronous Read/Write—Bus Master
section). If these timing requirements are met, the synchronous read/write timing can be ignored (and vice versa).
Table 9. Specifications
5V
Parameter
Timing Requirements:
tDAAK
ACK Delay from Address, Selects1, 2
tDSAK
ACK Delay from WR Low1
Switching Characteristics:
tDAWH
Address, Selects to WR
De-asserted2
tDAWL
Address, Selects to WR Low2
tWW
WR Pulse Width
tDDWH
Data Setup before WR High
tDWHA
Address Hold after WR De-asserted
tDATRWH Data Disable after WR De-asserted3
tWWR
WR High to WR, RD, DMAGx Low
tDDWR
Data Disable before WR or RD Low
tWDE
WR Low to Data Enabled
tSADADC Address, Selects to ADRCLK High2
Min
3.3 V
Max
Min
13.5 + 7 DT/8 + W
8 + DT/2 + W
Max
Unit
13.5 + 7 DT/8 + W
8 + DT/2 + W
ns
ns
16.5 + 15 DT/16 + W
16.5 + 15 DT/16 + W
ns
2.5 + 3 DT/8
12 + 9 DT/16 + W
6.5 + DT/2 + W
0 + DT/16 + H
0.5 + DT/16 + H
8 + 7 DT/16 + H
4.5 + 3 DT/8 + 1
−1.5 + DT/16
−0.5 + DT/4
2.5 + 3 DT/8
12 + 9 DT/16 + W
6.5 + DT/2 + W
0 + DT/16 + H
0.5 + DT/16 + H
8 + 7 DT/16 + H
4.5 + 3 DT/8 + 1
−1.5 + DT/16
−0.5 + DT/4
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.5 + DT/16 + H
6.5 + DT/16 + H
W = number of wait states specified in WAIT register × tCK.
H = tCK, if an address hold cycle occurs, as specified in WAIT register; otherwise, H = 0.
I = tCK, if a bus idle cycle occurs, as specified in WAIT register; otherwise, I = 0.
1
ACK delay/setup: User must meet tDAAK, tDSAK, or synchronous specification, tSACKC.
For MSx, SW, BMS, the falling edge is referenced.
3
See the System Hold Time Calculation Example section for the calculation of hold times given capacitive and dc loads.
2
ADDRESS
MSx, SW
BMS
tDAWH
tDAWL
tDWHA
tWW
WR
tWWR
tWDE
tDDWH
tDATRWH
tDDWR
DATA
tDSAK
tDAAK
ACK
tSADADC
00667-017
RD, DMAG
ADRCLK
(OUT)
Figure 8. Memory Write—Bus Master
Rev. B | Page 9 of 48
AD14060/AD14060L
SYNCHRONOUS READ/WRITE—BUS MASTER
Use these specifications for interfacing to external memory systems that require CLKIN—relative timing or for accessing a slave
ADSP 2106x in multiprocessor memory space. These synchronous switching characteristics are also valid during asynchronous memory
reads and writes (see the Memory Read—Bus Master and Memory Write—Bus Master sections).
When accessing a slave ADSP-2106x, these switching characteristics must meet the slave’s timing requirements for synchronous
read/writes (see the Synchronous Read/Write—Bus Slave section). The slave ADSP-2106x must also meet these bus master timing
requirements for data and acknowledge setup and hold times.
Table 10. Specifications
Parameter
Timing Requirements:
tSSDATI
Data Setup before CLKIN
tHSDATI
Data Hold after CLKIN
tDAAK
ACK Delay after Address, MSx, SW, BMS1, 2
tSACKC
ACK Setup before CLKIN2
tHACKC
ACK Hold after CLKIN
Switching Characteristics:
tDADRO
Address, MSx, BMS, SW, Delay after CLKIN1
tHADRO
Address, MSx, BMS, SW, Hold after CLKIN
tDPGC
PAGE Delay after CLKIN
tDRDO
RD High Delay after CLKIN
tDWRO
WR High Delay after CLKIN
tDRWL
RD/WR Low Delay after CLKIN
tSDDATO
Data Delay after CLKIN
tDATTR
Data Disable after CLKIN3
tDADCCK
ADRCLK Delay after CLKIN
tADRCK
ADRCLK Period
tADRCKH
ADRCLK Width High
tADRCKL
ADRCLK Width Low
Min
5V
Max
3 + DT/8
4 − DT/8
Min
3 + DT/8
4 − DT/8
13.5 + 7 DT/8 + W
6.5 + DT/4
−0.5 − DT/4
13.5 + 7 DT/8 + W
6.5 + DT/4
−0.5 − DT/4
8 − DT/8
−1 − DT/8
9 + DT/8
−2 − DT/8
−3 − 3 DT/16
8 + DT/4
0 − DT/8
4 + DT/8
tCK
(tCK/2 − 2)
(tCK/2 − 2)
3.3 V
Max
17 + DT/8
+5 − DT/8
+5 − 3 DT/16
13.5 + DT/4
20 + 5 DT/16
8 − DT/8
11 + DT/8
8 − DT/8
−1 − DT/8
9 + DT/8
−2 − DT/8
−3 − 3 DT/16
8 + DT/4
0 − DT/8
4 + DT/8
tCK
(tCK/2 − 2)
(tCK/2 − 2)
W = number of wait states specified in WAIT register × tCK.
1
For MSx, SW, BMS, the falling edge is referenced.
ACK delay/setup: User must meet tDAAK, tDSAK, or synchronous specification, tSACKC.
3
See the System Hold Time Calculation Example section for the calculation of hold times given capacitive and dc loads.
2
Rev. B | Page 10 of 48
17 + DT/8
+5 − DT/8
+5 − 3 DT/16
13.5 + DT/4
20.25 + 5 DT/16
8 – DT/8
11 + DT/8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AD14060/AD14060L
CLKIN
tADRCK
tDADCCK
tADRCKH
tADRCKL
ADRCLK
tDADRO
tHADRO
tDAAK
ADDRESS
SW
tDPGC
PAGE
tHACKC
tSACKC
ACK
(IN)
READ CYCLE
tDRWL
tDRDO
RD
tSSDATI
tHSDATI
DATA
(IN)
WRITE CYCLE
tDWRO
tDRWL
WR
tSDDATO
00667-018
tDATTR
DATA
(OUT)
Figure 9. Synchronous Read/Write—Bus Master
Rev. B | Page 11 of 48
AD14060/AD14060L
SYNCHRONOUS READ/WRITE—BUS SLAVE
Use these specifications for bus master access to a slave’s IOP registers or internal memory in multiprocessor memory space. The bus
master must meet these bus slave timing requirements.
Table 11. Specifications
Parameter
Timing Requirements:
tSADRI
Address, SW Setup before CLKIN
tHADRI
Address, SW Hold before CLKIN
tSRWLI
RD/WR Low Setup before CLKIN1
tHRWLI
RD/WR Low Hold after CLKIN
tRWHPI
RD/WR Pulse High
tSDATWH
Data Setup before WR High
tHDATWH
Data Hold after WR High
Switching Characteristics:
tSDDATO
Data Delay after CLKIN
tDATTR
Data Disable after CLKIN2
tDACKAD
ACK Delay after Address, SW3
tACKTR
ACK Disable after CLKIN3
5V
Max
Min
3.3 V
Max
Min
15.5 + DT/2
15.5 + DT/2
4.5 + DT/2
9.5 + 5 DT/16
−3.5 − 5 DT/16
3
5.5
1.5
0 − DT/8
−1 − DT/8
+8 + 7 DT/16
20 + 5 DT/16
8 − DT/8
10
+7 − DT/8
+8 + 7 DT/16
ns
ns
ns
ns
ns
ns
ns
20.25 + 5 DT/16
8 − DT/8
10
+7 − DT/8
ns
ns
ns
ns
4.5 + DT/2
9.5 + 5 DT/16
−3.25 − 5 DT/16
3
5.5
1.5
0 − DT/8
−1 − DT/8
Unit
1
tSRWLI (min) = 9.5 + 5 DT/16 when the multiprocessor memory space wait state (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, tSRWLI (min) =
4 + DT/8.
2
See the System Hold Time Calculation Example section for the calculation of hold times given capacitive and dc loads.
3
tDACKAD is true only if the address and SW inputs have setup times (before CLKIN) greater than 10.5 + DT/8 and less than 18.5 + 3 DT/4. If the address and SW inputs have
setup times greater than 19 + 3 DT/4, then ACK is valid 15 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match responds with ACK regardless
of the state of MMSWS or strobes. A slave three-states ACK every cycle with tACKTR.
CLKIN
tSADRI
tHADRI
ADDRESS
SW
tDACKAD
tACKTR
ACK
READ ACCESS
tSRWLI
tHRWLI
tRWHPI
RD
tDATTR
tSDDATO
DATA
(OUT)
WRITE ACCESS
tSRWLI
tHRWLI
tRWHPI
WR
DATA
(IN)
Figure 10. Synchronous Read/Write—Bus Slave
Rev. B | Page 12 of 48
tHDATWH
00667-019
tSDATWH
AD14060/AD14060L
MULTIPROCESSOR BUS REQUEST AND HOST BUS REQUEST
Use these specifications for passing of the bus mastership among multiprocessing ADSP-2106xs (BRx) or a host processor (HBR, HBG).
Table 12. Specifications
5V
Parameter
Timing Requirements:
tHBGRCSV HBG Low to RD/WR/CS Valid1
tSHBRI
HBR Setup before CLKIN2
tHHBRI
HBR Hold before CLKIN2
tSHBGI
HBG Setup before CLKIN
tHHBGI
HBG Hold before CLKIN High
tSBRI
BRx, CPA Setup before CLKIN3
tHBRI
BRx, CPA Hold before CLKIN High
tSRPBAI
RPBA Setup before CLKIN
tHRPBAI
RPBA Hold before CLKIN
Switching Characteristics:
tDHBGO
HBG Delay after CLKIN
tHHBGO
HBG Hold after CLKIN
tDBRO
BRx Delay after CLKIN
tHBRO
BRx Hold after CLKIN
tDCPAO
CPA Low Delay after CLKIN
tTRCPA
CPA Disable after CLKIN
tDRDYCS
REDY (O/D) or (A/D) Low from CS and HBR Low4
tTRDYHG
REDY (O/D) Disable or REDY (A/D) High from HBG4
tARDYTR
REDY (A/D) Disable from CS or HBR High4
Min
Max
Min
3.3 V
Max
19.5 + 5 DT/4
20 + 3 DT/4
19.5 + 5 DT/4
20 + 3 DT/4
13.5 + 3 DT/4
13 + DT/2
13.5 + 3 DT/4
13 + DT/2
5.5 + DT/2
13 + DT/2
5.5 + DT/2
13 + DT/2
5.5 + DT/2
21 + 3 DT/4
5.5 + DT/2
21 + 3 DT/4
11.5 + 3 DT/4
11.5 + 3 DT/4
8 − DT/8
8 − DT/8
−2 − DT/8
−2 − DT/8
8 − DT/8
−2 − DT/8
–2 − DT/8
9 − DT/8
+5.5 − DT/8
9.5
40 + 27 DT/16
−2 − DT/8
9.5 − DT/8
+5.5 − DT/8
12
40 + 27 DT/16
11
1
8 − DT/8
−2 − DT/8
11
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
For first asynchronous access after HBR and CS asserted, ADDR31–0 must be a non-MMS value 1/2 tCK before RD or WR goes low, or by tHBGRCSV after HBG goes low. This is
easily accomplished by driving an upper address signal high when HBG is asserted.
2
Required only for recognition in the current cycle.
3
CPA assertion must meet the setup to CLKIN; de-assertion does not need to meet the setup to CLKIN.
4
(O/D) = open drain; (A/D) = active drive.
Rev. B | Page 13 of 48
AD14060/AD14060L
CLKIN
tSHBRI
tHHBRI
HBR
tDHBGO
tHHBGO
HBG
(OUT)
tDBRO
tHBRO
BRx
(OUT)
tDCPAO
CPA (OUT)
(O/D)
tTRCPA
tSHBGI
tHHBGI
HBG (IN)
tSBRI
tHBRI
BRx (IN)
CPA (IN) (O/D)
HBR
CS
tTRDYHG
tDRDYCS
REDY (O/D)
tARDYTR
REDY (A/D)
tHBGRCSV
HBG (OUT)
RD
WR
CS
tSRPBAI
tHRPBAI
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
HBG IS DELAYED BY n CLOCK CYCLES WHEN WAIT STATES OR BUS LOCK ARE IN EFFECT.
Figure 11. Multiprocessor Bus Request and Host Bus Request
Rev. B | Page 14 of 48
00667-020
RPBA
AD14060/AD14060L
ASYNCHRONOUS READ/WRITE—HOST TO AD14060/AD14060L
Use these specifications for asynchronous host processor access to an AD14060/AD14060L, after the host has asserted CS and HBR (low).
After HBG is returned by the AD14060/AD14060L, the host can drive the RD and WR pins to access the AD14060/AD14060L’s internal
memory or IOP registers. HBR and HBG are assumed low for this timing.
Table 13. Specifications
Parameter
Read Cycle
Timing Requirements:
tSADRDL
Address Setup/CS Low before RD Low1
tHADRDH
Address Hold/CS Hold Low after RD
tWRWH
RD/WR High Width
tDRDHRDY
RD High Delay after REDY (O/D) Disable
tDRDHRDY
RD High Delay after REDY (A/D) Disable
Switching Characteristics:
tSDATRDY
Data Valid before REDY Disable from Low
tDRDYRDL
REDY (O/D) or (A/D) Low Delay after RD Low
tRDYPRD
REDY (O/D) or (A/D) Low Pulse Width for Read
tHDARWH
Data Disable after RD High
Min
0.5
0.5
6
0
0
3.3 V
Max
Min
0.5
0.5
6
0
0
1.5
45 + DT
1.5
1.5
9
0.5
0.5
5.5
2.5
7
6
0.5
5.5
1.5
13.5
45 + DT
1.5
9.5
0.5
0.5
5.5
2.5
7
6
0.5
5.5
1.5
8 + 7 DT/16
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
15
0 + 7 DT/16
Unit
ns
ns
ns
ns
ns
11
Write Cycle
Timing Requirements:
tSCSWRL
CS Low Setup before WR Low
tHCSWRH
CS Low Hold after WR High
tSADWRH
Address Setup before WR High
tHADWRH
Address Hold after WR High
tWWRL
WR Low Width
tWRWH
RD/WR High Width
tDWRHRDY
WR High Delay after REDY (O/D) or (A/D) Disable
tSDATWH
Data Setup before WR High
tHDATWH
Data Hold After WR High
Switching Characteristics:
tDRDYWRL
REDY (O/D) or (A/D) Low Delay after WR/CS Low
tRDYPWR
REDY (O/D) or (A/D) Low Pulse Width for Write
tSRDYCK
REDY (O/D) or (A/D) Disable to CLKIN
13.5
15
0 + 7 DT/16
8 + 7 DT/16
ns
ns
ns
Not required, if RD and address are valid tHBGRCSV after HBG goes low. For first access after HBR is asserted, ADDR31–0 must be a non-MMS value 1/2 tCLK before RD or WR
goes low or by tHBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. For address bits to be driven
during asynchronous host accesses, see the ADSP-2106x SHARC User’s Manual.
CLKIN
tSRDYCK
REDY (O/D)
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 12. Synchronous REDY Timing
Rev. B | Page 15 of 48
00667-021
1
5V
Max
AD14060/AD14060L
READ CYCLE
ADDRESS/CS
tHADRDH
tWRWH
tSADRDL
RD
tHDARWH
DATA (OUT)
tSDATRDY
tDRDYRDL
tDRDHRDY
tRDYPRD
REDY (O/D)
REDY (A/D)
WRITE CYCLE
ADDRESS
tSADWRH
tSCSWRL
tHADWRH
tHCSWRH
CS
tWWRL
tWRWH
WR
tSDATWH
tHDATWH
DATA (IN)
tDRDYWRL
tRDYPWR
tDWRHRDY
00667-022
REDY (O/D)
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 13. Asynchronous Read/Write—Host to ADSP-2106x
Rev. B | Page 16 of 48
AD14060/AD14060L
THREE-STATE TIMING—BUS MASTER, BUS SLAVE, HBR, SBTS
These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and the
SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as the SBTS pin.
Table 14. Specifications
5V
Parameter
Timing Requirements:
tSTSCK
SBTS Setup before CLKIN
tHTSCK
SBTS Hold before CLKIN
Switching Characteristics:
tMIENA
Address/Select Enable after CLKIN
tMIENS
Strobes Enable after CLKIN1
tMIENHG
HBG Enable after CLKIN
tMITRA
Address/Select Disable after CLKIN
tMITRS
Strobes Disable after CLKIN1
tMITRHG
HBG Disable after CLKIN
tDATEN
Data Enable after CLKIN2
tDATTR
Data Disable after CLKIN2
tACKEN
ACK Enable after CLKIN2
tACKTR
ACK Disable after CLKIN2
tADCEN
ADRCLK Enable after CLKIN
tADCTR
ADRCLK Disable after CLKIN
tMTRHBG
Memory Interface Disable before HBG Low3
tMENHBG
Memory Interface Enable after HBG High3
Min
3.3 V
Max
12.5 + DT/2
Min
Unit
5.5 + DT/2
ns
ns
12.5 + DT/2
5.5 + DT/2
−1.5 − DT/8
−1.5 − DT/8
−1.5 − DT/8
−1.25 − DT/8
−1.5 − DT/8
−1.5 − DT/8
1 − DT/4
2.5 − DT/4
3 − DT/4
9 + 5 DT/16
0 − DT/8
7.5 + DT/4
−1 − DT/8
−2 − DT/8
Max
8 − DT/8
+7 − DT/8
1.25 − DT/4
2.5 − DT/4
3 − DT/4
9 + 5 DT/16
0 − DT/8
7.5 + DT/4
−1 − DT/8
−2 − DT/8
9 − DT/4
−1 + DT/8
18.5 + DT
8 − DT/8
+7 − DT/8
9 − DT/4
−1 + DT/8
18.5 + DT
1
Strobes = RD, WR, SW, PAGE, DMAG.
In addition to bus master transition cycles, these specifications also apply to bus master and bus slave synchronous read/write.
3
Memory interface = address, RD, WR, MSx, SW, HBG, PAGE,DMAGx, BMS (in EPROM boot mode).
2
CLKIN
tSTSCK
tHTSCK
SBTS
tMIENA, tMIENS, tMIENHG
tMITRA, tMITRS, tMITRHG
MEMORY
INTERFACE
tDATEN
tDATTR
DATA
tACKEN
tACKTR
ACK
tADCEN
tADCTR
ADRCLK
HBG
tMTRHBG
MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, HBG, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)
Figure 14. Three-State Timing
Rev. B | Page 17 of 48
00667-023
tMENHBG
MEMORY
INTERFACE
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AD14060/AD14060L
DMA HANDSHAKE
These specifications describe the three DMA handshake modes. In all three modes, DMAR is used to initiate transfers. For handshake
mode, DMAG controls the latching or enabling of data externally. For external handshake mode, the data transfer is controlled by the
ADDR31-0, RD, WR, SW, PAGE, MS3-0, ACK, and DMAG signals. For paced master mode, the data transfer is controlled by ADDR31-0, RD,
WR, MS3-0, and ACK (not DMAG). For paced master mode, the memory read—bus master, memory write—bus master, and synchronous
read/write—bus master timing specifications for ADDR31-0, RD, WR, MS3-0, SW, PAGE, DATA47-0, and ACK also apply.
Table 15. Specifications
5V
Parameter
Timing Requirements:
tSDRLC
DMARx Low Setup before CLKIN1
tSDRHC
DMARx High Setup before CLKIN1
tWDR
DMARx Width Low (Nonsynchronous)
tSDATDGL
Data Setup after DMAGx Low2
tHDATIDG
Data Hold after DMAGx High
tDATDRH
Data Valid after DMAGx High2
tDMARLL
DMAGx Low Edge to Low Edge
tDMARH
DMAGx Width High
Switching Characteristics:
tDDGL
DMAGx Low Delay after CLKIN
tWDGH
DMAGx High Width
tWDGL
DMAGx Low Width
tHDGC
DMAGx High Delay after CLKIN
tVDATDGH
Data Valid before DMAGx High3
tDATRDGH
Data Disable after DMAGx High4
tDGWRL
WR Low before DMAGx Low
tDGWRH
DMAGx Low before WR High
tDGWRR
WR High before DMAGx High
tDGRDL
RD Low before DMAGx Low
tDRDGH
RD Low before DMAGx High
tDGRDR
RD High before DMAGx High
tDGWR
DMAGx High to WR, RD, DMAGx Low
tDADGH
Address/Select Valid to DMAGx High
tDDGHA
Address/Select Hold after DMAGx High
Min
3.3 V
Max
5
5
6
Min
Max
5
5
6
9 + 5 DT/8
2
9 + 5 DT/8
2
15.5 + 7 DT/8
23 + 7 DT/8
6
9 + DT/4
6 + 3 DT/8
12 + 5 DT/8
−2 − DT/8
7.5 + 9 DT/16
−1
−0.5
9.5 + 5 DT/8 + W
0.5 + DT/16
−0.25
11 + 9 DT/16 + W
0
4.5 + 3 DT/8 + HI
16 + DT
−1.5
15.5 + 7 DT/8
23 + 7 DT/8
6
16 + DT/4
+7 − DT/8
+7.5
+2.5
3.5 + DT/16
+2.5
3.5
9 + DT/4
6 + 3 DT/8
12 + 5 DT/8
−2 − DT/8
7.5 + 9 DT/16
−1
−0.75
9.5 + 5 DT/8 + W
0.5 + DT/16
0
11 + 9 DT/16 + W
0
4.5 + 3 DT/8 + HI
16 + DT
−1.5
16 + DT/4
+7 − DT/8
+7.5
+2.5
3.5 + DT/16
2.5
3.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
W = number of wait states specified in WAIT register × tCK.
HI = tCK, if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise, HI = 0.
1
Required only for recognition in the current cycle.
tSDATDGL is the data setup requirement, if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the data
can be driven tDATDRH after DMARx is brought high.
3
tVDATDGH is valid, if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then tVDATDGH = 7.5 + 9 DT/16 + (n × tCK), where n
equals the number of extra cycles that the access is prolonged.
4
See the System Hold Time Calculation Example section for the calculation of hold times given capacitive and dc loads.
2
Rev. B | Page 18 of 48
AD14060/AD14060L
CLKIN
tSDRLC
tDMARLL
tSDRHC
tDMARH
tWDR
DMARx
tHDGC
tWDGL
tDDGL
tWDGH
DMAGx
TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE
tVDATDGH
tDATRDGH
DATA (FROM
ADSP-2106x TO
EXTERNAL DRIVE)
tDATDRH
tHDATIDG
tSDATDGL
DATA (FROM
EXTERNAL DRIVE
TO ADSP-2106x)
TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY1 (EXTERNAL HANDSHAKE MODE)
tDGWRL
RD
(EXTERNAL MEMORY
TO EXTERNAL DEVICE)
tDGRDL
tDGWRH
tDGWRR
tDGRDR
tDRDGH
tDADGH
ADDRESS
MSX, SW
1 MEMORY READ – BUS MASTER, MEMORY WRITE – BUS MASTER, AND SYNCHRONOUS READ/WRITE – BUS MASTER.
TIMING SPECIFICATIONS FOR ADDR31–0, RD, WR, SW, MS3-0, AND ACK ALSO APPLY HERE.
Figure 15. DMA Handshake Timing
Rev. B | Page 19 of 48
tDDGHA
00667-024
WR
(EXTERNAL DEVICE TO
EXTERNAL MEMORY)
AD14060/AD14060L
Table 16. 1× CLK Speed Operation
Parameter
Receive
Timing Requirements:
tSLDCL
Data Setup before LCLK Low
tHLDCL
Data Hold after LCLK Low
tLCLKIW
LCLK Period (1× Operation)
tLCLKRWL
LCLK Width Low
tLCLKRWH
LCLK Width High
Switching Characteristics:
tDLAHC
LACK High Delay after CLKIN High
tDLALC
LACK Low Delay after LCLK High1
tENDLK
LACK Enable from CLKIN
tTDLK
LACK Disable from CLKIN
Transmit
Timing Requirements:
tSLACH
LACK Setup before LCLK High
tHLACH
LACK Hold after LCLK High
Switching Characteristics:
tDLCLK
LCLK Delay after CLKIN (1× Operation)
tDLDCH
Data Delay after LCLK High
tHLDCH
Data Hold after LCLK High
tLCLKTWL
LCLK Width Low
tLCLKTWH
LCLK Width High
tDLACLK
LCLK Low Delay after LACK High
tENDLK
LDAT, LCLK Enable after CLKIN
tTDLK
LDAT, LCLK Disable after CLKIN
Link Port Service Request Interrupts:
1× and 2× Speed Operations
Timing Requirements:
tSLCK
LACK/LCLK Setup before CLKIN Low2
tHLCK
LACK/LCLK Hold after CLKIN Low2
1
2
5V
Max
Min
3.5
3
tCK
6
5
Min
3.3 V
Max
3
3
tCK
6
5
18 + DT/2
−3
5 + DT/2
29.5 + DT/2
+13.5
18 + DT/2
−3
5 + DT/2
21 + DT/2
18
−7
ns
ns
ns
ns
ns
30 + DT/2
+13.5
21 + DT/2
20
−7
16.5
3.5
−3
(tCK/2) − 2
(tCK/2) − 2
(tCK/2) + 8.5
(tCK/2) + 2
(tCK/2) + 2
(3 × tCK/2) + 17.5
5 + DT/2
(tCK/2) + 2.25
(tCK/2) + 1
(3 × tCK/2) +
18.25
5 + DT/2
21 + DT/2
10
2.5
21 + DT/2
10
2.5
LACK goes low with tDLALC relative to the rising edge of LCLK after the first nibble is received. LACK does not go low, if the receiver’s link buffer is not about to fill.
Required only for interrupt recognition in the current cycle.
Rev. B | Page 20 of 48
ns
ns
ns
ns
ns
ns
17.5
3
−3
(tCK/2) − 1
(tCK/2) − 2.25
(tCK/2) + 8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AD14060/AD14060L
Table 17. 2× CLK Speed Operation
Parameter
Receive
Timing Requirements:
tSLDCL
Data Setup before LCLK Low
tHLDCL
Data Hold after LCLK Low
tLCLKIW
LCLK Period (2× Operation)
tLCLKRWL
LCLK Width Low
tLCLKRWH
LCLK Width High
Switching Characteristics:
tDLAHC
LACK High Delay after CLKIN High
tDLALC
LACK Low Delay after LCLK High1
Transmit
Timing Requirements:
tSLACH
LACK Setup before LCLK High
tHLACH
LACK Hold after LCLK High
Switching Characteristics:
tDLCLK
LCLK Delay after CLKIN
tDLDCH
Data Delay after LCLK High
tHLDCH
Data Hold after LCLK High
tLCLKTWL
LCLK Width Low
tLCLKTWH
LCLK Width High
tDLACLK
LCLK Low Delay after LACK High
1
5V
Max
Min
2.75
2.25
tCK/2
4.6
4.25
Min
3.3 V
Max
2.25
2.25
tCK/2
5.25
4.5
18 + DT/2
6
31.5 + DT/2
17.8
20.25
−6.5
18 + DT/2
6
ns
ns
ns
ns
ns
30.5 + DT/2
19
19
−6.5
9
3.25
−2
(tCK/4) − 1
(tCK/4) − 1.5
(tCK/4) + 9
(tCK/4) + 1.5
(tCK/4) + 1
(3 × tCL/4) + 17
ns
ns
ns
ns
9
2.75
−2
(tCK/4) − 0.75
(tCK/4) − 1.5
(tCK/4) + 9
Unit
(tCK/4) + 1.5
(tCK/4) + 1
(3 × tCL/4) + 17
ns
ns
ns
ns
ns
ns
LACK goes low with tDLALC relative to the rising edge of LCLK after the first nibble is received. LACK does not go low, if the receiver’s link buffer is not about to fill.
Rev. B | Page 21 of 48
AD14060/AD14060L
TRANSMIT
CLKIN
tDLCLK
tLCLKTWH
LAST NIBBLE
TRANSMITTED
tLCLKTWL
FIRST NIBBLE
TRANSMITTED
LCLK INACTIVE
(HIGH)
LCLK 1x
OR
LCLK 2x
tDLDCH
tHLDCH
LDAT(3:0)
OUT
tSLACH
tHLACH
tDLACLK
LACK (IN)
THE tSLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.
RECEIVE
CLKIN
tLCLKIW
tLCLKRWH
LCLK 1x
OR
LCLK 2x
tLCLKRWL
tHLDCL
tSLDCL
LDAT(3:0)
IN
tDLAHC
tDLALC
LACK (OUT)
LACK GOES LOW ONLY AFTER THE SECOND NIBBLE IS RECEIVED.
LINK PORT ENABLE/THREE-STATE DELAY FROM INSTRUCTION
CLKIN
tENDLK
tTDLK
LCLK
LDAT(3:0)
LACK
LINK PORT ENABLE OR THREE-STATE TAKES EFFECT 2 CYCLES AFTER A WRITE TO A LINK PORT CONTROL REGISTER.
LINK PORT INTERRUPT SETUP TIME
CLKIN
tHLCK
tSLCK
LCLK
00667-025
LACK
Figure 16. Link Ports
Rev. B | Page 22 of 48
AD14060/AD14060L
Table 18. Serial Ports
Parameter
External Clock
Timing Requirements:
tSFSE
TFS/RFS Setup before TCLK/RCLK1
tHFSE
TFS/RFS Hold after TCLK/RCLK1, 2
tSDRE
Receive Data Setup before RCLK1
tHDRE
Receive Data Hold after RCLK1
tSCLKW
TCLK/RCLK Width
tSCLK
TCLK/RCLK Period
Internal Clock
Timing Requirements:
tSFSI
TFS Setup before TCLK1; RFS Setup before RCLK1
tHFSI
TFS/RFS Hold after TCLK/RCLK1, 2
tSDRI
Receive Data Setup before RCLK1
tHDRI
Receive Data Hold after RCLK1
External or Internal Clock
Switching Characteristics:
tDFSE
RFS Delay after RCLK (Internally Generated RFS)3
tHFSE
RFS Hold after RCLK (Internally Generated RFS)3
External Clock
Switching Characteristics:
tDFSE
TFS Delay after TCLK (Internally Generated TFS)3
tHFSE
TFS Hold after TCLK (Internally Generated TFS)3
tDDTE
Transmit Data Delay after TCLK3
tHDTE
Transmit Data Hold after TCLK3
Internal Clock
Switching Characteristics:
tDFSI
TFS Delay after TCLK (Internally Generated TFS)3
tHFSI
TFS Hold after TCLK (Internally Generated TFS)3
tDDTI
Transmit Data Delay after TCLK3
tHDTI
Transmit Data Hold after TCLK3
tSCLKIW
TCLK/RCLK Width
Enable and Three-State
Switching Characteristics:
tDDTEN
Data Enable from External TCLK3
tDDTTE
Data Disable from External TCLK3
tDDTIN
Data Enable from Internal TCLK3
tDDTTI
Data Disable from Internal TCLK3
tDCLK
TCLK/RCLK Delay from CLKIN
tDPTR
SPORT Disable after CLKIN
Gated SCLK with External TFS (Mesh Multiprocessing)
Timing Requirements:
tSTFSCK
TFS Setup before CLKIN
tHTFSCK
TFS Hold after CLKIN
Min
5V
Max
Min
3.3 V
Max
Unit
4
4.5
2
4.5
9.5
tCK
4
4.5
2
4.5
9.5
tCK
ns
ns
ns
ns
ns
ns
9.5
1
4.5
3
9.5
1
4.5
3
ns
ns
ns
ns
14.5
2.5
14.5
3
17.5
ns
ns
ns
ns
17.5
5
5
−1.5
7.5
(SCLK/2) + 2
3.5
7.5
−0.5
(SCLK/2) − 2.5
(SCLK/2) + 2.5
4
12
−0.5
12
−0.5
3
23.5 + 3 DT/8
18.5
Rev. B | Page 23 of 48
14.5
5
−1.5
5.5
(TCK/2) + 0.5
ns
ns
3
5
−0.5
(SCLK/2) − 2
14.5
2.5
3
23.5 + 3 DT/8
18.5
5.5
(TCK/2) + 0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AD14060/AD14060L
Parameter
External Late Frame Sync
Switching Characteristics:
tDDTLFSE
Data Delay from Late External TFS or External RFS
with MCE = 1, MFD = 04
tDDTENFS
Data Enable from Late FS or MCE = 1, MFD = 04
5V
Max
Min
3.3 V
Max
Min
14.1
3.0
14.3
3.5
Unit
ns
ns
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame
sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.
1
Referenced to sample edge.
RFS hold after RCK when MCE = 1, MFD = 0 is 0.5 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0.5 ns minimum from drive edge.
3
Referenced to drive edge.
4
MCE = 1, TFS enable and TFS valid follow tDDTLFSE and tDDTENFS.
2
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
RCLK
tHFSE/I1
tSFSE/I
RFS
tDDTE/I
tDDTENFS
tHDTE/I
DT
FIRST BIT
SECOND BIT
tDDTLFSE
LATE EXTERNAL TFS
DRIVE
SAMPLE
DRIVE
TCLK
tHFSE/I1
tSFSE/I
TFS
tDDTE/I
tDDTENFS
DT
tHDTE/I
FIRST BIT
SECOND BIT
1RFS
HOLD AFTER RCK WHEN MCE = 1, MFD = 0 IS 0.5ns MINIMUM FROM DRIVE EDGE.
TFS HOLD AFTER TCK FOR LATE EXTERNAL TFS IS 0.5ns MINIMUM FROM DRIVE EDGE.
Figure 17. External Late Frame Sync
Rev. B | Page 24 of 48
00667-026
tDDTLFSE
AD14060/AD14060L
DATA RECEIVE– INTERNAL CLOCK
DRIVE
EDGE
DATA RECEIVE– EXTERNAL CLOCK
SAMPLE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKW
RCLK
RCLK
tDFSE
tHFSE
tSFSI
tDFSE
tHFSE
tHFSI
RFS
tSFSE
tHFSE
tSDRE
tHDRE
RFS
tSDRI
tHDRI
DR
DR
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT– INTERNAL CLOCK
DRIVE
EDGE
DATA TRANSMIT– EXTERNAL CLOCK
SAMPLE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKW
TCLK
TCLK
tDFSI
tHFSI
tSFSI
tDFSE
tHFSE
tHFSI
TFS
tSFSE
tHFSE
TFS
tDDTI
tDDTE
tHDTE
tHDTI
DT
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE
EDGE
DRIVE
EDGE
TCLK/RCLK
TCLK (EXT)
tDDTEN
tDDTTE
DT
DRIVE
EDGE
DRIVE
EDGE
TCLK (INT)
TCLK/RCLK
tDDTIN
tDDTTI
DT
CLKIN
tDPTR
TCLK, RCLK
TFS, RFS, DT
TCLK (INT)
SPORT DISABLE DELAY
FROM INSTRUCTION
tSTFSCK
SPORT ENABLE AND
THREE-STATE LATENCY
IS TWO CYCLES
tHTFSCK
TFS (EXT)
tDCLK
NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH
EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O
FOR MESH MULTIPROCESSING.
RCLK (INT)
LOW TO HIGH ONLY
Figure 18. Serial Ports
Rev. B | Page 25 of 48
00667-027
CLKIN
AD14060/AD14060L
Table 19. JTAG Test Access Port and Emulation
Parameter
Timing Requirements:
tTCK
TCK Period
tSTAP
TDI, TMS Setup before TCK High
tHTAP
TDI, TMS Hold after TCK High
tSSYS
System Inputs Setup before TCK Low1
tHSYS
System Inputs Hold after TCK Low1
tTRSTW
TRST Pulse Width
Switching Characteristics:
tDTDO
TDO Delay from TCK Low
tDSYS
System Outputs Delay after TCK Low2
Min
5V
Max
tCK
5
6
7
18.5
4 tCK
Min
3.3 V
Max
tCK
ns
ns
ns
ns
ns
ns
6
8
19
4 tCK
13.5
20
Unit
13.5
20
1
ns
ns
System Inputs = DATA47-0, ADDR31-0, RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR1, DMAR2, BR6-1, RPBA, IRQ2-0, FLAG2-0, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0,
TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET.
2
System Outputs = DATA47-0, ADDR31-0, MS3-0, RD, WR, ACK, PAGE, ADRCLK, SW, HBG, REDY, DMAG1, DMAG2, BR6-1, CPA, FLAG2-0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0,
RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, BMS.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
00667-028
tDSYS
SYSTEM
OUTPUTS
Figure 19. IEEE 11499.1 JTAG Test Access Port
Rev. B | Page 26 of 48
AD14060/AD14060L
ABSOLUTE MAXIMUM RATINGS
Table 20.
Parameters
Supply Voltage (5 V)
Supply Voltage (3.3 V)
Input Voltage
Output Voltage Swing
Load Capacitance
Junction Temperature under Bias
Storage Temperature Range
Lead
Ratings
−0.3 V to +7 V
−0.3 V to +4.6 V
−0.5 V to VDD + 0.5 V
−0.5 V to VDD + 0.5 V
200 pF
130°C
−65°C to +150°C
280°C
Stresses greater than those listed above may cause permanent
damage to the device. These are stress ratings only; functional
operation of the device at these or any other conditions greater
than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 27 of 48
AD14060/AD14060L
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
308
232
231
1
AD14060/AD14060L
155
154
77
78
Figure 20. 308-Lead CQFP Pin Configuration
Rev. B | Page 28 of 48
00667-043
TOP VIEW
AD14060/AD14060L
Table 21. Pin Numbers and Mnemonics
Pin
No.
1
Mnemonic
WR
Pin
No.
45
Pin
No.
89
Mnemonic
ADDR13
Pin
No.
133
Mnemonic
IRQB0
Pin
No.
177
Mnemonic
LC4DAT2
Pin
No.
221
Mnemonic
GND
Pin
No.
265
Mnemonic
GND
2
RD
46
3
GND
47
RFSD1
90
ADDR12
134
IRQB1
178
LC4DAT3
222
LA3ACK
266
DATA24
RCLKD1
91
ADDR11
135
IRQB2
179
GND
223
LA3CLK
267
4
CSA
48
DATA25
DRD1
92
GND
136
GND
180
LC3ACK
224
LA3DAT0
268
5
CSB
DATA26
49
TFSD1
93
ADDR10
137
IRQC0
181
LC3CLK
225
LA3DAT1
269
DATA27
6
7
CSC
50
TCLKD1
94
ADDR9
138
IRQC1
182
LC3DAT0
226
LA3DAT2
270
VDD
CSD
51
DTD1
95
ADDR8
139
IRQC2
183
LC3DAT1
227
LA3DAT3
271
DATA28
8
GND
52
VDD
96
VDD
140
IRQD0
184
LC3DAT2
228
VDD
272
DATA29
9
HBG
53
HBR
97
ADDR7
141
IRQD1
185
LC3DAT3
229
LA1ACK
273
DATA30
10
REDY
54
DMAR1
98
ADDR6
142
IRQD2
186
VDD
230
LA1CLK
274
DATA31
11
ADRCLK
55
DMAR2
99
ADDR5
143
VDD
187
LC1ACK
231
LA1DAT0
275
GND
12
VDD
56
SBTS
100
GND
144
EBOOTA
188
LC1CLK
232
LA1DAT1
276
DATA32
13
RFS0
57
BMSA
101
ADDR4
145
LBOOTA
189
LC1DAT0
233
LA1DAT2
277
DATA33
14
RCLK0
58
BMSBCD
102
ADDR3
146
EBOOTBCD
190
LC1DAT1
234
LA1DAT3
278
DATA34
15
DR0
59
SW
103
ADDR2
147
LBOOTBCD
191
LC1DAT2
235
GND
279
DATA35
16
17
TFS0
TCLK0
60
61
GND
MS0
104
105
VDD
ADDR1
148
149
GND
RESET
192
193
LC1DAT3
GND
236
237
DATA0
DATA1
280
281
VDD
DATA36
18
DT0
62
MS1
106
ADDR0
150
RPBA
194
LB4ACK
238
DATA2
282
DATA37
19
GND
63
MS2
107
FLAGA0
151
GND
195
LB4CLK
239
DATA3
283
DATA38
20
CPAA
64
MS3
108
GND
152
LD4ACK
196
LB4DAT0
240
VDD
284
DATA39
21
22
23
24
25
26
27
28
29
30
CPAB
CPAC
CPAD
VDD
RFSA1
RCLKA1
DRA1
TFSA1
TCLKA1
DTA1
65
66
67
68
69
70
71
72
73
74
VDD
ADDR31
ADDR30
ADDR29
GND
ADDR28
ADDR27
ADDR26
VDD
ADDR25
109
110
111
112
113
114
115
116
117
118
FLAGA2
FLAGB0
FLAGB2
FLAGC0
FLAGC2
FLAGD0
FLAGD2
VDD
FLAG1
EMU
153
154
155
156
157
158
159
160
161
162
LD4CLK
LD4DAT0
LD4DAT1
LD4DAT2
LD4DAT3
VDD
LD3ACK
LD3CLK
LD3DAT0
LD3DAT1
197
198
199
200
201
202
203
204
205
206
LB4DAT1
LB4DAT2
LB4DAT3
VDD
LB3ACK
LB3CLK
LB3DAT0
LB3DAT1
LB3DAT2
LB3DAT3
241
242
243
244
245
246
247
248
249
250
DATA4
DATA5
DATA6
DATA7
GND
DATA8
DATA9
DATA10
DATA11
VDD
285
286
287
288
289
290
291
292
293
294
GND
DATA40
DATA41
CLKIN
GND
DATA42
DATA43
VDD
DATA44
DATA45
31
32
33
34
GND
RFSB1
RCLKB1
DRB1
75
76
77
78
ADDR24
ADDR23
ADDR22
ADDR21
119
120
121
122
TIMEXPA
TIMEXPB
TIMEXPC
TIMEXPD
163
164
165
166
LD3DAT2
LD3DAT3
GND
LD1ACK
207
208
209
210
GND
LB1ACK
LB1CLK
LB1DAT0
251
252
253
254
DATA12
DATA13
DATA14
DATA15
295
296
297
298
DATA46
DATA47
GND
BR1
Mnemonic
GND
35
TFSB1
79
ADDR20
123
GND
167
LD1CLK
211
LB1DAT1
255
GND
299
BR2
36
TCLKB1
80
VDD
124
TDO
168
LD1DAT0
212
LB1DAT2
256
DATA16
300
BR3
37
DTB1
81
ADDR19
125
TRST
169
LD1DAT1
213
LB1DAT3
257
DATA17
301
BR4
38
VDD
82
ADDR18
126
TDI
170
LD1DAT2
214
VDD
258
DATA18
302
BR5
39
RFSC1
83
ADDR17
127
TMS
171
LD1DAT3
215
LA4ACK
259
DATA19
303
BR6
40
41
42
RCLKC1
DRC1
TFSC1
84
85
86
GND
ADDR16
ADDR15
128
129
130
TCK
VDD
IRQA0
172
173
174
VDD
LC4ACK
LC4CLK
216
217
218
LA4CLK
LA4DAT0
LA4DAT1
260
261
262
VDD
DATA20
DATA21
304
305
306
PAGE
VDD
DMAG1
43
TCLKC1
8
ADDR14
131
IRQA1
175
LC4DAT0
219
LA4DAT2
263
DATA22
307
DMAG2
44
DTC1
88
VDD
132
IRQA2
176
LC4DAT1
220
LA4DAT3
264
DATA23
308
ACK
Rev. B | Page 29 of 48
AD14060/AD14060L
PIN FUNCTION DESCRIPTIONS
AD14060/AD14060L pin function descriptions are listed in
Table 22. Inputs identified as synchronous (S) must meet timing
requirements with respect to CLKIN (or with respect to TCK
for TMS, TDI). Inputs identified as asynchronous (A) can be
asserted asynchronously to CLKIN (or to TCK for TRST).
Unused inputs should be tied or pulled to VDD or GND, except
for ADDR31-0, DATA47-0, FLAG2-0, SW, and inputs that have
internal pull-up or pull-down resistors (CPA, ACK, DTx, DRx,
TCLKx, RCLKx, LxDAT3-0, LxCLK, LxACK, TMS, and TDI)—
these pins can be left floating. These pins have a logic-level hold
circuit that prevents the input from floating internally.
Table 22. Pin Function Descriptions
Pin
ADDR31-0
Type1
I/O/T
DATA47-0
I/O/T
MS3-0
O/T
RD
I/O/T
WR
I/O/T
PAGE
O/T
ADRCLK
SW
O/T
I/O/T
ACK
I/O/S
Function
External Bus Address (common to all SHARCs). The AD14060/AD14060L outputs addresses for external memory
and peripherals on these pins. In a multiprocessor system, the bus master outputs addresses for read/writes on the
internal memory or IOP registers of slave ADSP-2106xs. The AD14060/AD14060L inputs addresses when a host
processor or multiprocessing bus master is reading or writing the internal memory or IOP registers of internal
ADSP-21060s.
External Bus Data (common to all SHARCs). The AD14060/AD14060L inputs and outputs data and instructions on
these pins. 32-bit single-precision floating-point data and 32-bit fixed-point data is transferred over Bits 47–16 of
the bus. 40-bit extended-precision floating-point data is transferred over Bits 47–48 of the bus. 16-bit short word
data is transferred over Bits 31–16 of the bus. In PROM boot mode, 8-bit data is transferred over Bits 23–16. Pull-up
resistors on unused DATA pins are not necessary.
Memory Select Lines (common to all SHARCs). These lines are asserted (low) as chip selects for the corresponding
banks of external memory. Memory bank size must be defined in the individual ADSP-21060’s system control
registers (SYSCON). The MS3-0 lines are decoded memory address lines that change at the same time as the other
address lines. When no external memory access is occurring, the MS3-0 lines are inactive. They are active, however,
when a conditional memory access instruction is executed, whether or not the condition is true. MS0 can be used
with the PAGE signal to implement a bank of DRAM memory (Bank 0). In a multiprocessing system, the MS3-0 lines
are output by the bus master.
Memory Read Strobe (common to all SHARCs). This pin is asserted (low) when the AD14060/AD14060L reads from
external devices or when the internal memory of internal ADSP-2106xs is being accessed. External devices
(including other ADSP-2106xs) must assert RD to read from the AD14060/AD14060L’s internal memory. In a
multiprocessing system, RD is output by the bus master and is input by all other ADSP-2106xs.
Memory Write Strobe (common to all SHARCs). This pin is asserted (low) when the AD14060/AD14060L writes to
external devices or when the internal memory of internal ADSP-2106xs is being accessed. External devices
(including other ADSP-2106xs) must assert WR to write to the AD14060/ AD14060L’s internal memory. In a
multiprocessing system, WR is output by the bus master and is input by all other ADSP-2106xs.
DRAM Page Boundary. The AD14060/AD16060L asserts this pin to signal that an external DRAM page boundary has
been crossed. DRAM page size must be defined in the individual ADSP-21060’s memory control register (WAIT).
DRAM can be implemented only in external memory Bank 0. The PAGE signal can be activated only for Bank 0
accesses. In a multiprocessing system, PAGE is output by the bus master.
Clock Output Reference (common to all SHARCs). In a multiprocessing system, ADRCLK is output by the bus master.
Synchronous Write Select (common to all SHARCs). This signal is used to interface the AD14060/AD14060L to
synchronous memory devices (including other ADSP-2106xs). The AD14060/AD14060L asserts SW (low) to provide
an early indication of an impending write cycle, which can be aborted, if WR is not later asserted (for example, in a
conditional write instruction). In a multiprocessing system, SW is output by the bus master and is input by all other
ADSP-2106xs to determine if the multiprocessor memory access is a read or write. SW is asserted at the same time
as the address output. A host processor using synchronous writes must assert this pin when writing to the
AD14060/AD14060L.
Memory Acknowledge (common to all SHARCs). External devices can de-assert ACK (low) to add wait states to an
external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access. The AD14060/AD14060L de-asserts ACK, as an output, to add wait states to a
synchronous access of its internal memory. In a multiprocessing system, a slave ADSP-2106x de-asserts the bus
master’s ACK input to add wait state(s) to an access of its internal memory. The bus master has a keeper latch on its
ACK pin that maintains the input at the level to which it was last driven.
Rev. B | Page 30 of 48
AD14060/AD14060L
Pin
SBTS
Type1
I/S
HBR
I/A
HBG
I/O
CSA
CSB
CSC
CSD
REDY
(O/D)
I/A
I/A
I/A
I/A
O
BR6-1
I/O/S
RPBA
I/S
CPAy (O/D)
I/O
DT0
DR0
TCLK0
RCLK0
TFS0
RFS0
DTy1
O/T
I
I/O
I/O
I/O
I/O
O/T
DRy1
I
TCLKy1
I/O
RCLKy1
I/O
TFSy1
RFSy1
FLAGy0
I/O
I/O
I/O/A
Function
Suspend Bus Three-State (common to all SHARCs). External devices can assert SBTS (low) to place the external bus
address, data, selects, and strobes in a high impedance state for the following cycle. If the AD14060/AD14060L
attempts to access external memory while SBTS is asserted, the processor halts and the memory access does not
complete until SBTS is de-asserted. SBTS should be used only to recover from host processor/AD14060/AD14060L
deadlock, or used with a DRAM controller.
Host Bus Request (common to all SHARCs). Must be asserted by a host processor to request control of the
AD14060/AD14060L’s external bus. When HBR is asserted in a multiprocessing system, the ADSP-2106x that is bus
master relinquishes the bus and asserts HBG. To relinquish the bus, the ADSP-2106x places the address, data, select,
and strobe lines in a high impedance state. HBR has priority over all ADSP-2106x bus requests (BR6-1) in a
multiprocessing system.
Host Bus Grant (common to all SHARCs). Acknowledges an HBR bus request, indicating that the host processor can
take control of the external bus. HBG is asserted (held low) by the AD14060/AD14060L until HBR is released. In a
multiprocessing system, HBG is output by the ADSP-2106x bus master and is monitored by all others.
Chip Select. Asserted by host processor to select SHARC_A.
Chip Select. Asserted by host processor to select SHARC_B.
Chip Select. Asserted by host processor to select SHARC_C.
Chip Select. Asserted by host processor to select SHARC_D.
Host Bus Acknowledge (common to all SHARCs). The AD14060/AD14060L de-asserts REDY (low) to add wait states
to an asynchronous access of its internal memory or IOP registers by a host. Open-drain output (O/D) by default;
can be programmed in ADREDY bit of SYSCON register of individual ADSP-21060s to be active drive (A/D). REDY is
output only if the CS and HBR inputs are asserted.
Multiprocessing Bus Requests (common to all SHARCs). Used by multiprocessing ADSP-2106xs to arbitrate for bus
mastership. An ADSP-2106x drives only its own BRx line (corresponding to the value of its ID2-0 inputs) and
monitors all others. In a multiprocessor system with less than six ADSP-2106xs, the unused BRx pins should be
pulled high; BR4-1 must not be pulled high or low, because they are outputs.
Rotating Priority Bus Arbitration Select (common to all SHARCs). When RPBA is high, rotating priority for multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system
configuration selection that must be set to the same value on every ADSP-2106x. If the value of RPBA is changed
during system operation, it must be changed in the same CLKIN cycle on every ADSP-2106x.
Core Priority Access (y = SHARC_A, B, C, D). Asserting its CPA pin allows the core processor of an ADSP-2106x bus
slave to interrupt background DMA transfers and gain access to the external bus. CPA is an open-drain output that
is connected to all ADSP-2106xs in the system, if this function is required. The CPA pin of each internal ADSP-21060
is brought out individually. The CPA pin has an internal 5 kΩ pull-up resistor. If core access priority is not required in
a system, the CPA pin should be left unconnected.
Data Transmit (common Serial Ports 0 to all SHARCs, TDM). The DT pin has a 50 kΩ internal pull-up resistor.
Data Receive (common Serial Ports 0 to all SHARCs, TDM). The DR pin has a 50 kΩ internal pull-up resistor.
Transmit Clock (common Serial Ports 0 to all SHARCs, TDM). The TCLK pin has a 50 kΩ internal pull-up resistor.
Receive Clock (common Serial Ports 0 to all SHARCs, TDM). The RCLK pin has a 50 kΩ internal pull-up resistor.
Transmit Frame Sync (common Serial Ports 0 to all SHARCs, TDM).
Receive Frame Sync (common Serial Ports 0 to all SHARCs, TDM).
Data Transmit (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). The DT pin has a 50 kΩ
internal pull-up resistor.
Data Receive (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). The DR pin has a 50 kΩ
internal pull-up resistor.
Transmit Clock (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). The TCLK pin has a 50 kΩ
internal pull-up resistor.
Receive Clock (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). The RCLK pin has a 50 kΩ
internal pull-up resistor.
Transmit Frame Sync (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D).
Receive Frame Sync (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D).
Flag Pins (FLAG0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). Each pin is configured via control bits
as either an input or an output. As an input, it can be tested as a condition. As an output, it can be used to signal
external peripherals.
Rev. B | Page 31 of 48
AD14060/AD14060L
Pin
FLAG1
Type1
I/O/A
FLAGy2
I/O/A
IRQy2-0
I/A
DMAR1
DMAR2
DMAG1
DMAG2
LyxCLK
I/A
I/A
O/T
O/T
I/O
LyxDAT3-0
I/O
LyxACK
I/O
EBOOTA
I
LBOOTA
I
BMSA
I/O/T3
EBOOTBCD
I
LBOOTBCD
I
BMSBCD
I/O/T3
TIMEXPy
O
CLKIN
I
RESET
I/A
TCK
TMS
I
I/S
Function
Flag Pins (FLAG1 common to all SHARCs). This pin is configured via control bits internal to individual ADSP-21060s
as either an input or an output. As an input, it can be tested as a condition. As an output, it can be used to signal
external peripherals.
Flag Pins (FLAG2 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). Each pin is configured via control bits
as either an input or an output. As an input, it can be tested as a condition. As an output, it can be used to signal
external peripherals.
Interrupt Request Lines (individual IRQ2-0 from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D). Can be either edgetriggered or level-sensitive.
DMA Request 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMA Request 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMA Grant 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMA Grant 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
Link Port Clock (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)2. Each LyxCLK pin has a 50 kΩ internal pull-down resistor
that is enabled or disabled by the LPDRD bit of the LCOM register of the ADSP-20160.
Link Port Data (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)2. Each LyxDAT pin has a 50 kΩ internal pull-down resistor
that is enabled or disabled by the LPDRD bit of the LCOM register of the ADSP-21060.
Link Port Acknowledge (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)2. Each LyxACK pin has a 50 kΩ internal pulldown resistor that is enabled or disabled by the LPDRD bit of the LCOM register of the ADSP-21060.
EPROM Boot Select (SHARC_A). When EBOOTA is high, SHARC_A is configured for booting from an 8-bit EPROM.
When EBOOTA is low, the LBOOTA and BMSA inputs determine booting mode for SHARC_A. See the following
table. This signal is a system configuration selection that should be hardwired.
Link Boot. When LBOOTA is high, SHARC_A is configured for link port booting. When LBOOTA is low, SHARC_A is
configured for host processor booting or no booting. See the following table. This signal is a system configuration
selection that should be hardwired.
Boot Memory Select. When this pin is an output, it is used as chip select for boot EPROM devices (when EBOOTA =
1, LBOOTA = 0). In a multiprocessor system, BMS is output by the bus master. As an input, when low, this pin
indicates that no booting is to occur and that SHARC_A is to begin executing instructions from external memory.
See the following table. This input is a system configuration selection that should be hardwired.
EPROM Boot Select (common to SHARC_B, SHARC_C, SHARC_D). When EBOOTBCD is high, SHARC_B, C, and D are
configured for booting from an 8-bit EPROM. When EBOOTBCD is low, the LBOOTBCD and BMSBCD inputs
determine booting mode for SHARC_B, C, and D. See the following table. This signal is a system configuration
selection that should be hardwired.
LINK Boot (common to SHARC_B, SHARC_C, SHARC_D). When LBOOTBCD is high, SHARC_B, C, and D are configured
for link port booting. When LBOOTBCD is low, SHARC_B, C, and D are configured for host processor booting or no
booting. See the following table. This signal is a system configuration selection that should be hardwired.
Boot Memory Select. When this pin is an output, it is used as chip select for boot EPROM devices (when EBOOTBCD
= 1, LBOOTBCD = 0). In a multiprocessor system, BMS is output by the bus master. As an input, when low, this pin
indicates that no booting is to occur and that SHARC_B, C, and D are to begin executing instructions from external
memory. See table below. This input is a system configuration selection that should be hardwired.
Booting Mode
EBOOT LBOOT BMS
1
0
Output
EPROM (connect BMS to EPROM chip select).
0
0
1 (Input)
Host processor.
0
1
1 (Input)
Link port.
0
0
0 (Input)
No booting. Processor executes from external memory.
0
1
0 (Input)
Reserved.
1
1
x (Input)
Reserved.
Timer Expired (individual TIMEXP from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D). Asserted for four cycles when
the timer is enabled and TCOUNT decrements to 0.
Clock In (common to all SHARCs). External clock input to the AD14060/AD14060L. The instruction cycle rate is equal
to CLKIN. CLKIN cannot be halted, changed, or operated below the minimum specified frequency.
Module Reset (common to all SHARCs). Resets the AD14060/AD14060L to a known state. This input must be
asserted (low) at power-up.
Test Clock (JTAG) (common to all SHARCs). Provides an asynchronous clock for JTAG boundary scan.
Test Mode Select (JTAG) (common to all SHARCs). Used to control the test state machine. TMS has a 20 kΩ internal
pull-up resistor.
Rev. B | Page 32 of 48
AD14060/AD14060L
Pin
TDI
Type1
I/S
TDO
TRST
O
I/A
EMU (O/D)
O
VDD
GND
P
G
Function
Test Data Input (JTAG). Provides serial data for the boundary scan logic chain starting at SHARC_A. TDI has a 20 kΩ
internal pull-up resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan chain path, from SHARC_D.
Test Reset (JTAG) (common to all SHARCs). Resets the test state machine. TRST must be asserted (pulsed low) after
power-up or held low for proper operation of the AD14060/AD14060L. TRST has a 20 kΩ internal pull-up resistor.
Emulation Status (common to all SHARCs). Must be connected to the ADSP-2106x EZ-ICE target board connector
only.
Power Supply. Nominally 5.0 V dc for 5 V devices or 3.3 V dc for 3.3 V devices (26 pins).
Power Supply Return (28 pins).
FLAG3 is connected internally, common to SHARC_A, B, C, and D.
ID pins are hardwired internally as shown in Figure 1.
1
I = input; P = power supply; (A/D) = active drive; O = output; S = synchronous; (O/D) = open drain; G = ground; A = asynchronous; T = three-state, when SBTS is
asserted, or when the AD14060/AD14060L is a bus slave.
2
Link Ports 0, 2, and 5 are connected internally, as described in the Link Port I/O section.
3
Three-statable only in EPROM boot mode (when BMS is an output).
Rev. B | Page 33 of 48
AD14060/AD14060L
DETAILED DESCRIPTION
ARCHITECTURAL FEATURES
SHARED MEMORY MULTIPROCESSING
ADSP-21060 Core
The AD14060/AD14060L takes advantage of the powerful
multiprocessing features built into the SHARC. The SHARCs
are connected to maximize the performance of this cluster-offour architecture, and still allow for off-module expansion. The
AD14060/AD14060L in itself is a complete shared memory
multiprocessing system, as shown in Figure 22. The unified
address space of the SHARCs allows direct interprocessor
accesses of each SHARCs’ internal memory. In other words,
each SHARC can directly access the internal memory and IOP
registers of each of the other SHARCs by simply reading or
writing to the appropriate address in multiprocessor memory
space (see Figure 23)—this is called a direct read or direct write.
The AD14060/AD14060L is based on the powerful
ADSP-21060 (SHARC) DSP chip. The ADSP-21060 SHARC
combines a high performance floating-point DSP core with
integrated, on-chip system features, including a 4-Mbit SRAM
memory, host processor interface, DMA controller, serial ports,
and both link port and parallel bus connectivity for glueless
DSP multiprocessing (see Figure 21). It is fabricated in a high
speed, low power CMOS process, and has a 25 ns instruction
cycle time. The arithmetic/logic unit (ALU), multiplier, and
shifter all perform single-cycle instructions, and the three units
are arranged in parallel, maximizing computational throughput.
The SHARC features an enhanced Harvard architecture, in
which the data memory (DM) bus transfers data and the
program memory (PM) bus transfers both instructions and
data. An on-chip instruction cache selectively caches only those
instructions whose fetches conflict with the PM bus data
accesses. This combines with the separate program and data
memory buses to enable 3-bus operation for fetching an
instruction and two operands, all in a single cycle. The SHARC
also contains a general-purpose data register file, which is a
10-port, 32-register (16 primary, 16 secondary) file. Each
SHARC’s core also implements two data address generators
(DAGs), implementing circular data buffers in hardware. The
DAGs contain sufficient registers to allow the creation of up to
32 circular buffers. The 48-bit instruction word accommodates
a variety of parallel operations for concise programming. For
example, the ADSP-21060 can conditionally execute a multiply,
an add, a subtract, and a branch, all in a single instruction.
The SHARCs contain 4 Mbits of on-chip SRAM each, organized
as two blocks of 2 Mbits, which can be configured for different
combinations of code and data storage. The memory can be
configured as a maximum of 128k words of 32-bit data, 256k
words of 16-bit data, 80k words of 48-bit instructions (or 40-bit
data), or combinations of different word sizes up to 4 Mbits. A
16-bit floating-point storage format is supported, which
effectively doubles the amount of data that can be stored onchip. Conversion between the 32-bit floating-point and 16-bit
floating-point formats is done in a single instruction. Each
memory block is dual-ported for single-cycle, independent
access by the core processor and I/O processor or DMA
controller. The dual-ported memory and separate on-chip buses
allow two data transfers from the core and one from the I/O, all
in a single cycle.
Bus arbitration is accomplished with the on-SHARC arbitration
logic. Each SHARC has a unique ID, and drives the bus-request
(BR) line corresponding to its ID, while monitoring all others.
BR1 to BR4 are used within the AD14060/AD14060L, while
BR5 andBR6 can be used for expansion. All bus requests (BR1
to BR6) are included in the module I/O. Two different priority
schemes, fixed and rotating, are available to resolve competing
bus requests. The RPBA pin selects which scheme is used. When
RPBA is high, rotating priority bus arbitration is selected; when
RPBA is low, fixed priority is selected.
Bus mastership is passed from one SHARC to another during a
bus transition cycle. A bus transition cycle occurs only when the
current bus master de-asserts its BR line and one of the slave
SHARCs asserts its BR line. The bus master can, therefore,
retain bus mastership by keeping its BR line asserted. When the
bus master de-asserts its BR line and no other BR line is
asserted, then the master does not lose any bus cycles. When
more than one SHARC asserts its BR line, the SHARC with the
highest priority request becomes bus master on the following
cycle. Each SHARC observes all the BR lines, and, therefore,
tracks when a bus transition cycle has occurred, and which
processor has become the new bus master. Master processor
changeover incurs only one cycle of overhead. Table 23 shows
an example of a bus transition sequence.
Table 23. Rotating Priority Arbitration Example
Cycle
1
ID1
M
Hardware Processor IDs
ID2
ID3
ID4
ID5
1
2 BR
3
4
ID6
5
2
3
4
5
4
4
5 BR
1 BR
5 BR
5 BR
M
2
3
3
4 BR
M
M-BR
M
1
3
1
1
2
4
1–5 = Assigned priority.
M = Bus mastership (in that cycle).
BR = Requesting bus mastership with BRx.
Rev. B | Page 34 of 48
2
2
3
5
Priority
Initial priority
assignments
Final priority
assignments
AD14060/AD14060L
DAG1
8 x 4 x 32
DAG2
8 x 4 x 24
BUS
CONNECT
(PX)
INSTRUCTION
CACHE
32 x 48-BIT
TWO INDEPENDENT
DUAL-PORTED BLOCKS
JTAG
BLOCK 1
TIMER
DUAL-PORTED SRAM
BLOCK 0
CORE PROCESSOR
7
TEST AND
EMULATION
PROCESSOR PORT
I/O PORT
ADDR
DATA
DATA
ADDR
ADDR
DATA
DATA
ADDR
PROGRAM
SEQUENCER
PM ADDRESS BUS
24
DM ADDRESS BUS
32
PM DATA BUS
48
DM DATA BUS
40/32
IOA
17
IOD
48
EXTERNAL
PORT
ADDR BUS
MUX
32
MULTIPROCESSOR
INTERFACE
DATA BUS
MUX
48
HOST PORT
ALU
6
SERIAL PORTS
(2)
CONTROL,
STATUS, AND
DATA BUFFERS
6
36
LINK PORTS
(6)
00667-003
BARREL
SHIFTER
4
DMA
CONTROLLER
IOP
REGISTERS
(MEMORY MAPPED)
I/O PROCESSOR
Figure 21. ADSP-21060 Processor Block Diagram (Core of AD10460)
SYSTEM EXPANSION
1× CLOCK
CLKIN
RESET
RPBA
SHARC_A
LINKS 1, 3, AND 4;
IRQ2–0;
FLAGS 2 AND 0;
TIMEXP,
SPORT1
CPA
SHARC_B
ADDR31–0
LINKS 1, 3, AND 4;
DATA47–0
IRQ2–0;
FLAGS 2 AND 0;
RD
TIMEXP,
WR
SPORT1
ACK
MS3-0
BOOTSELECT A
PAGE
SBTS
BOOTSELECT BCD
DMAR1, 2
AD14060/AD14060L
(QUAD PROCESSOR CLUSTER)
DMAG1, 2
SPORT0
FLAG1
JTAG
SW
ADRCLK
CS
SHARC_D
SHARC_C
LINKS 1, 3, AND 4;
IRQ2–0;
FLAGS 2 AND 0;
TIMEXP,
SPORT1
LINKS 1, 3, AND 4;
IRQ2–0;
FLAGS 2 AND 0;
TIMEXP,
SPORT1
HBR
HBG
REDY
BR1–6
00667-005
MULTIPLIER
DATA
REGISTER
FILE
16 x 40-BIT
Figure 22. Complete Shared Memory Multiprocessing System
Rev. B | Page 35 of 48
AD14060/AD14060L
0x0040 0000
0x0000 0000
IOP REGISTERS
INTERNAL
MEMORY SPACE
(INDIVIDUAL
SHARCs)
0x0002 0000
BANK 0
0x0004 0000
DRAM
(OPTIONAL)
MS0
NORMAL WORD ADDRESSING
SHORT WORD ADDRESSING
0x0008 0000
INTERNAL MEMORY SPACE
OF SHARC_A
ID = 001
BANK 1
MS1
BANK 2
MS2
BANK 3
MS3
0x0010 0000
INTERNAL
TO AD14060
INTERNAL MEMORY SPACE
OF SHARC_B
ID = 010
0x0018 0000
INTERNAL MEMORY SPACE
OF SHARC_C
ID = 011
0x0020 0000
INTERNAL MEMORY SPACE
OF SHARC_D
ID = 100
MULTIPROCESSOR
MEMORY SPACE
EXTERNAL
MEMORY
SPACE
0x0028 0000
INTERNAL MEMORY SPACE
OF ADSP-2106x
ID = 101
BANK SIZE IS
SELECTED BY
MSIZE BIT FIELD
OF SYSCON
REGISTER
0x0030 0000
EXTERNAL
TO AD14060
INTERNAL MEMORY SPACE
OF ADSP-2106x
ID = 110
0x0038 0000
BROADCAST WRITE
TO ALL
ADSP-2106xs
NONBANKED
0xFFFF FFFF
00667-004
0x003F FFFF
NORMAL WORD ADDRESSING: 32-BIT DATA WORDS
48-BIT INSTRUCTION WORDS
SHORT WORD ADDRESSING: 16-BIT DATA WORDS
Figure 23. AD14060/AD14060L Memory Map
Bus locking is possible, allowing indivisible read-modify-write
sequences for semaphores. In either the fixed or rotating
priority scheme, it is also possible to limit the number of cycles
that the master can use to control the bus. The AD14060/
AD14060L provides the option of using the core priority access
(CPA) mode of the SHARC. Using the CPA signal allows
external bus accesses by the core processor of a slave SHARC to
take priority over ongoing DMA transfers. Also, each SHARC
can broadcast write to all other SHARCs simultaneously,
allowing the implementation of reflective semaphores.
The bus master can communicate with slave SHARCs by
writing messages to their internal IOP registers. The MSRG0 to
MSRG7 registers are general-purpose registers that can be used
for convenient message passing, semaphores, and resource
sharing among the SHARCs. For message passing, the master
communicates with a slave by writing and/or reading any of the
eight message registers on the slave. For vector interrupts, the
master can issue a vector interrupt to a slave by writing the
address of an interrupt service routine to the slave’s VIRPT
register. This causes an immediate high priority interrupt on the
slave, which, when serviced, causes it to branch to the specified
service routine.
OFF-MODULE MEMORY AND PERIPHERALS
INTERFACE
The AD14060/AD14060L’s external port provides the interface
to off-module memory and peripherals (see Figure 24). This
port consists of the complete external port bus of the SHARC,
bused in common among the four SHARCs.
The 4-gigaword off-module address space is included in the
ADSP-14060’s unified address space. Addressing of external
memory devices is facilitated by each SHARC internally
decoding the high-order address lines to generate memorybank select signals. Separate control lines are also generated for
simplified addressing of page-mode DRAM. The AD14060/
AD14060L also supports programmable memory wait states
and external memory acknowledge controls to allow interfacing
to DRAM and peripherals with variable access, hold, and
disable time requirements.
Rev. B | Page 36 of 48
AD14060/AD14060L
AD14060/
AD14060L
1x
CLOCK
CLKIN
RESET
RESET
RPBA
CONTROL
ADDR31–0
ADDR
DATA47–0
DATA
RD
OE
WR
WE
ACK
ACK
MS3–0
CS
BMS
CS
PAGE
ADDR
SBTS
DATA
GLOBAL
MEMORY
AND
PERIPHERALS
(OPTIONAL)
BOOT
EPROM
(OPTIONAL)
SW
ADRCLK
CS
HBR
HBG
REDY
SERIALS
CPA
LINKS
BR2–6
DISCRETES
5
ADDR
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
DATA
BR1
ADSP-2106x #5
CLKIN
(OPTIONAL)
ADDR31–0
DATA47–0
RESET
RPBA
3
101
ID 2–0
CONTROL
CPA
BR1–4, 6
5
BR5
ADSP-2106x #6
CLKIN
(OPTIONAL)
ADDR31–0
DATA47–0
RESET
RPBA
3
ID 2–0
CONTROL
CPA
BR1–5
5
BR6
Figure 24. Optional System Interconnections
Rev. B | Page 37 of 48
00667-007
110
AD14060/AD14060L
LINK PORT I/O
SERIAL PORTS
Each individual SHARC features six 4-bit link ports that
facilitate SHARC-to-SHARC communication and external I/O
interfacing. Each link port can be configured for either 1× or 2×
operation, allowing each to transfer either four or eight bits
per cycle.
The SHARC serial ports provide an inexpensive interface to a
wide variety of digital and mixed-signal peripheral devices.
Each SHARC has two serial ports. The AD14060/AD14060L
provides direct access to Serial Port 1 of each SHARC. Serial
Port 0 is bused in common to each SHARC, and brought offmodule.
The link ports can operate independently and simultaneously,
with a maximum bandwidth of 40 MBytes/s each, or a total of
240 MBytes/s per SHARC.
The AD14060/AD14060L optimizes the link port connections
internally, and brings a total of 12 of the link ports off-module
for user-defined system connections. Internally, each SHARC
has a connection to the other three SHARCs with a dedicated
link port interface. Thus, each SHARC can directly interface
with its nearest and next-nearest neighbor. The remaining three
link ports from each SHARC are brought out independently
from each SHARC. A maximum of 480 MBytes/s link port
bandwidth is then available off of the AD14060/AD14060L.
The link port connections are shown in Figure 25.
1
3
5
5
2
2
SHARC_A
4
0
0
0
1
3
2
2
5
5
SHARC_C
•
From an 8-bit EPROM
•
From a host processor
1
•
Through the link ports
3
•
No boot
4
In no-boot mode, the SHARC starts executing instructions
from Address 0x0040 0004 in external memory. The boot mode
is selected by the state of the following signals: BMS, EBOOT,
and LBOOT.
00667-006
4
SHARC_D
The AD14060/AD14060L supports automatic downloading of
programs following power-up or a software reset. The SHARC
offers the following options for program booting:
3
4
0
The serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from 3 bits
to 32 bits. They offer selectable synchronization and transmit
modes as well as optional µ-law or A-law companding. Serial
port clocks and frame syncs can be internally or externally
generated.
PROGRAM BOOTING
1
SHARC_B
The serial ports can operate at the full clock rate of the module,
providing each with a maximum data rate of 40 Mbit/s.
Independent transmit and receive functions provide more
flexible communications. Serial port data can be automatically
transferred to and from on-SHARC memory via DMA, and
each of the serial ports offers time-division-multiplexed (TDM)
multichannel mode.
Figure 25. Link Port Connections
Link Port 4, the boot-link port, is brought off independently
from each SHARC. Individual booting is then allowed, or
chained link-port booting is possible, as described in the
Multiprocessor Link-Port Booting section.
On the AD14060/AD14060L, SHARC_A’s boot mode is separately controlled, while SHARC_B, C, and D are controlled as a
group. With this flexibility, the AD14060/AD14060L can be
configured to boot using any of the following methods.
Link port data is packed into 32-bit or 48-bit words, and can be
directly read by the SHARC core processor or DMA transferred
to on-SHARC memory.
Each link port has its own double-buffered input and output
registers. Clock/acknowledge handshaking controls link port
transfers. Transfers are programmable as either transmit or
receive.
Multiprocessor Host Booting
To boot multiple ADSP-21060 processors from a host, each
ADSP-21060 must have its EBOOT, LBOOT, and BMS pins
configured for host booting: EBOOT = 0, LBOOT = 0, and
BMS = 1. After system power-up, each ADSP-21060 is in the
idle state and the BRx bus request lines are de-asserted. The
host must assert the HBR input and boot each ADSP-21060 by
asserting its CS pin and downloading instructions.
Rev. B | Page 38 of 48
AD14060/AD14060L
Multiprocessor EPROM Booting
HOST PROCESSOR INTERFACE
The following methods boot the multiprocessor system from an
EPROM:
The AD14060/AD14060L’s host interface allows easy connection to standard microprocessor buses, both 16-bit and 32-bit,
with little additional hardware required. Asynchronous transfers
at speeds of up to the full clock rate of the module are supported. The host interface is accessed through the AD14060/
AD14060L external port and is memory-mapped into the
unified address space. Four channels of DMA are available for
the host interface; code and data transfers are accomplished
with low software overhead.
•
SHARC_A is booted, which then boots the others.
The EBOOT pin on the SHARC_A must be set high for
EPROM booting. All other ADSP-21060s should be
configured for host booting (EBOOT = 0, LBOOT = 0, and
BMS = 1), which leaves them in the idle state at startup and
allows SHARC_A to become bus master and boot itself.
Only the BMS pin of SHARC_A is connected to the chip
select of the EPROM. When SHARC_A has finished
booting, it can boot the remaining ADSP-21060s by writing
to their external port DMA Buffer 0 (EPB0) via multiprocessor memory space.
•
All ADSP-21060s boot in turn from a single EPROM.
The BMS signals from each ADSP-21060 can be wire-OR’ed
together to drive the chip select pin of the EPROM. Each
ADSP-21060 can boot in turn, according to its priority.
When the last one has finished booting, it must inform the
others (which can be in the idle state) that program
execution can begin.
Multiprocessor Link-Port Booting
Booting can also be accomplished from a single source through
the link ports. Link Buffer 4 must always be used for booting. To
simultaneously boot all the ADSP-21060s, a parallel common
connection is available through Link Port 4 on each of the
processors. Or, using the daisy-chain connection that exists
between the processors’ link ports, each ADSP-21060 can boot
the next one in turn. In this case, the link assignment register
(LAR) must be programmed to configure the internal link ports
with Link Buffer 4.
Multiprocessor Booting from External Memory
If external memory contains a program after reset, then
SHARC_A should be set up for no-boot mode. It begins executing from Address 0x0040 0004 in external memory. When
booting has completed, the other ADSP-21060s can be booted
by SHARC_A, if they are set up for host booting; or they can
begin executing out of external memory, if they are set up for
no-boot mode. Multiprocessor bus arbitration allows this
booting to occur in an orderly manner.
The host processor requests the AD14060/AD14060L’s external
bus with the host bus request (HBR), host bus grant (HBG), and
ready (REDY) signals. The host can directly read and write the
internal memory of the SHARCs, and can access the DMA
channel setup and mailbox registers. Vector interrupt support is
provided for efficient execution of host commands.
DIRECT MEMORY ACCESS (DMA) CONTROLLER
The SHARCs’ on-chip DMA control logic allows zero-overhead
data transfers without processor intervention. The DMA
controller operates independently and invisibly to each
SHARC’s processor core, allowing DMA operations to occur
while the core is simultaneously executing its program
instructions.
DMA transfers can occur between SHARC internal memory
and either external memory, external peripherals, or a host
processor. DMA transfers can also occur between the SHARC’s
internal memory and its serial ports or link ports. DMA
transfers between external memory and external peripheral
devices are another option. External bus packing to 16-, 32- or
48-bit words is performed during DMA transfers.
Ten channels of DMA are available on the SHARCs: two via the
link ports, four via the serial ports, and four via the processor’s
external port (for either host processor, other SHARCs,
memory, or I/O transfers). Four additional link port DMA
channels are shared with Serial Port 1 and the external port.
Programs can be downloaded to the SHARCs using DMA
transfers. Asynchronous off-module peripherals can control two
DMA channels using DMA request/grant lines (DMAR1-2,
DMAG1-2). Other DMA features include interrupt generation
upon completion of DMA transfers and DMA chaining for
automatic linked DMA transfers.
Rev. B | Page 39 of 48
AD14060/AD14060L
APPLICATIONS
DEVELOPMENT TOOLS
The AD14060/AD14060L is supported with a complete set of
software and hardware development tools, including an
in-circuit emulator and development software.
Analog Devices, Inc. (ADI) uses VisualDSP++®, which is an
easy-to-use integrated software development and debugging
environment (IDDE) that efficiently manages projects from
start to finish from within a single interface.
The HP USB-based emulator supports the background
telemetry channel (BTC), a nonintrusive method for exchanging data between the host and target application without
affecting the target system's real-time characteristics. Nonintrusive in-circuit emulation is assured by the use of the processor’s
JTAG interface. The emulator does not affect target system
loading or timing.
Further details and ordering information are available on the
analog.com Web site.
The ADSP-21262 EZ-KIT LITE™ provides developers with a
cost-effective method for initial evaluation of the ADSP-2106x
SHARC processor architecture for applications via a USB-based
PC-hosted tool set. With this EZ-KIT LITE, users can learn
about ADI’s ADSP-2106x hardware and software development
and can quickly prototype applications.
The EZ-KIT LITE includes an ADSP-2106x processor desktop
evaluation board, along with an evaluation suite of the
VisualDSP++ development and debugging environment with
the C/C++ compiler, assembler, and linker. VisualDSP++
development and debugging software, along with the USBbased debugger interface, enables users to perform standard
debugging functions (such as read and write memory, read and
write registers, load and execute executables, set and clear
breakpoints, and single-step assembly, C, and C++ source
code).
The ADI cost-effective universal serial bus (USB)-based
emulator and high performance (HP) universal serial bus
(USB)-based emulator each provide an easy, portable, nonintrusive, target-based debugging solution for ADI JTAG
processors and DSPs. These powerful USB-based emulators
perform a wide range of emulation functions, including singlestep and full speed execution with predefined breakpoints, and
viewing and altering of register and memory contents. With the
ability to automatically detect and support multiple I/O
voltages, the USB and HP USB emulators enable users to
communicate with all the ADI JTAG processors and DSPs
using either a full speed USB 1.1 or high speed USB 2.0 port on
the host PC. Applications and data can be easily and rapidly
tested and transferred between the emulators and the separately
available VisualDSP++ development and debugging environment (sold separately).
The plug-and-play architecture of the USB allows the host
operating system to automatically detect and configure the
emulators. The USB can be connected to and disconnected
from the host without opening the PC or turning off the power
to the PC. A 3-meter cable is included to connect the emulators
to the host PC, providing abundant accessibility to hard-toreach targets.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family.
Hardware tools include SHARC PC plug-in cards, multiprocessor SHARC VME boards, and daughter card modules
with multiple SHARCs and additional memory. These modules
are based on the SHARCPAC module specification. Third-party
software tools include an Ada compiler, DSP libraries, operating
systems, and block diagram design tools.
QUAD-SHARC DEVELOPMENT BOARD
The BlackTip-MCM, AD14060 development board with
software is available from Bittware Research Systems, Inc. This
board has one AD14060 BITSI interface, and PROM and SRAM
expansion options on an ISA card. It is supported by Bittware’s
SHARC software development package. To contact Bittware,
call 1-800-848-0436.
OTHER PACKAGE DETAILS
The AD14060/AD14060L contains 16 on-module 0.018 µF
bypass capacitors. It is recommended that, in the target system,
at least four additional capacitors of 0.018 µF value be placed
around the module, one near each of the four corners.
The top surface (lid) of the AD14060/AD14060L is electrically
connected to GND on the industrial and military grade parts.
TARGET BOARD CONNECTOR FOR EMULATOR
PROBE
The ADSP-2106x emulator uses the IEEE 1149.1 JTAG test
access port of the ADSP-2106x to monitor and control the
target board processor during emulation. The emulator probe
requires that the AD14060/AD14060L’s CLKIN (optional), TMS,
TCK, TRST, TDI, TDO, EMU, and GND signals be made
accessible on the target system via a 14-pin connector (pin strip
header) similar to Figure 26. The emulator probe plugs directly
into this connector for chip-on-board emulation. You must add
this connector to your target board design, if you intend to use
the ADSP-2106x emulator. The length of the traces between the
connector and the AD14060/AD14060L’s JTAG pins should be
as short as possible.
Rev. B | Page 40 of 48
AD14060/AD14060L
1
Table 24. JTAG Signals
2
Signal
TMS
TCK
EMU
GND
3
4
5
6
7
8
9
10
CLKIN (OPTIONAL)
KEY (NO PIN)
BTMS
BTCK
9
BTRST
11
TMS
TRST
TCK
TDI
TDO
CLKIN
EMU
TRST
12
TDI
BTDI
______________________________________
1
TRST is driven low until the emulator probe is turned on by the emulator
software (after the invocation command).
14
TDO
TOP VIEW
00667-008
13
GND
Figure 26. Target Board Connector for ADSP-2106x Emulator
(Jumpers in Place)
The 14-pin, 2-row pin-strip header is keyed at the Pin 3 location; Pin 3 must be removed from the header. The pins must be
0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1 inch × 0.1 inch. Pin strip headers are available
from vendors such as 3M, McKenzie, and Samtec.
The BTMS, BTCK, BTRST, and BTDI signals are provided so
that the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the other pins, as shown in
Figure 26. If you are not going to use the test access port for
board testing, tie BTRST to GND and tie or pull up BTCK to
VDD. The TRST pin must be asserted after power-up (through
BTRST on the connector) or held low for proper operation of
the AD14060/AD14060L. None of the Bxxx pins (Pins 5, 7, 9,
11) are connected on the emulator probe.
The JTAG signals are terminated on the emulator probe as
listed in Table 24.
Figure 27 shows JTAG scan path connections for the
multiprocessor system.
Termination
Driven through 22 Ω resistor (16 µA to 3.2 µA driver).
Driven at 10 MHz through 22 Ω resistor (16 µA to 3.2 µA
driver).
Driven by open-drain driver1 (pulled up by on-chip
20 kΩ resistor).
Driven by 16 µA to 3.2 µA driver.
One TTL load, no termination.
One TTL load, no termination (optional signal).
4.7 kΩ pull-up resistor, one TTL load (open-drain
output from ADSP-2106x).
Connecting CLKIN to Pin 4 of the emulator header is optional.
The emulator uses CLKIN only when directed to perform
operations such as starting, stopping, and single-stepping
multiple ADSP-2106xs in a synchronous manner. If these
operations do not need to occur synchronously on the multiple
processors, tie Pin 4 of the emulator header to ground.
If synchronous multiprocessor operations are needed and
CLKIN is connected, clock skew between the AD14060/
AD14060L and the CLKIN pin on the emulator header must be
minimal. If the skew is too large, synchronous operations might
be off by one cycle between processors. For synchronous multiprocessor operation, TCK, TMS, CLKIN, and EMU should be
treated as critical signals in terms of skew, and should be laid
out as short as possible on the board.
If TCK, TMS, and CLKIN are driving a large number of
ADSP-2106x’s (more than eight) in the system, treat them as a
clock tree using multiple drivers to minimize skew. (See the
ADSP-2106x User’s Manual for details).
If synchronous multiprocessor operations are not needed
(CLKIN is not connected), use appropriate parallel termination
on TCK and TMS. Note that TDI, TDO, EMU, and TRST are
not critical signals in terms of skew.
Rev. B | Page 41 of 48
AD14060/AD14060L
SHARC_C
SHARC_D
JTAG DEVICE
ADSP-2106x
(OPTIONAL)
OTHER JTAG
CONTROLLER
#n
TDO
TCK
TMS
TDI
TRST
TCK
TDO
TMS
TDI
TRST
EMU
TCK
TDO
TMS
TDI
TRST
EMU
TCK
TDO
TMS
TDI
TRST
EMU
TCK
TDO
TMS
TDI
TRST
EMU
TDO
TMS
EMULATOR
JTAG
CONNECTOR
TDI
TCK
TDI
TRST
SHARC_B
EMU
SHARC_A
TCK
TMS
EMU
TRST
00667-009
TDO
CLKIN
OPTIONAL
Figure 27. JTAG Scan Path Connections for the AD14060/AD14060L
1
1
TDO
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
5kΩ
5kΩ
SYSTEM
CLKIN
EMU
1OPEN-DRAIN
DRIVER OR EQUIVALENT, THAT IS:
00667-010
TDI
EMU
TCK
TMS
TRST
TDO
CLKIN
TDI
Figure 28. JTAG Clock Tree for Multiple ADSP-2106x Systems
OUTPUT DRIVE CURRENTS
POWER DISSIPATION
Figure 29 shows typical I-V characteristics for the output
drivers of the ADSP-2106x. The curves represent the current
drive capability of the output drivers as a function of output
voltage.
Total power dissipation has two components, one due to
internal circuitry and one due to the switching of external
output drivers. Internal power dissipation is dependent on the
instruction execution sequence and the data operands involved.
Internal power dissipation is calculated as follows:
120
100
60
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on the
following:
40
20
0
–20
–40
–60
–80
LOW LEVEL DRIVE
(N DEVICE)
–100
–120
•
Number of output pins that switch during each cycle (O)
•
Maximum frequency at which they can switch (f)
•
Load capacitance (C)
•
Voltage swing (VDD)
–140
–160
0
1
2
3
SOURCE VOLTAGE (V)
4
5
00667-029
SOURCE CURRENT (mA)
PINT = IDDIN × VDD
HIGH LEVEL DRIVE
(P DEVICE)
80
and is calculated by
Figure 29. ADSP-2106x Typical Drive Currents (VDD = 5 V)
PEXT = O × C × VDD2 × f
Rev. B | Page 42 of 48
AD14060/AD14060L
The load capacitance should include the processor’s package
capacitance (CIN). The switching frequency includes driving the
load high and then back low. Address and data pins can drive
high and low at a maximum rate of 1/(2 tCK). The write strobe
can switch every cycle at a frequency of 1/tCK. Select pins switch
at 1/(2 tCK), but selects can switch on each cycle.
The output disable time, tDIS, is the difference between tMEASURED
and tDECAY, as shown in Figure 30. The time tMEASURED is the
interval from when the reference signal switches to when the
output voltage decays ΔV from the measured output high or
output low voltage. tDECAY is calculated with test loads CL and IL,
and with ΔV equal to 0.5 V.
Example
Output Enable Time
Estimate PEXT with the following assumptions: a system with
one bank of external data memory RAM (32-bit);
four 128k × 8 RAM chips are used, each with a load of 10 pF;
external data memory writes occur every other cycle; a rate of
1/(4 tCK) with 50% of the pins switching; and an instruction
cycle rate is 40 MHz (tCK = 25 ns) and VDD = 5.0 V.
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time, tENA, is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the output enable/disable diagram (Figure 30). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
The PEXT equation is calculated for each class of pins that can
drive, as shown in Table 25.A typical power consumption can
now be calculated for these conditions by adding a typical
internal power dissipation:
PTOTAL = PEXT + (IDDIN2 × 5.0 V)
Note that the conditions causing a worst-case PEXT are different
from those causing a worst-case PINT. Maximum PINT cannot
occur while 100% of the output pins are switching from all 1s to
all 0s. It is uncommon for an application to have 100% or even
50% of the outputs switching simultaneously.
TEST CONDITIONS
To determine the data output hold time in a particular system,
first calculate tDECAY using the previous equation. Choose ΔV to
be the difference between the ADSP-2106x’s output voltage and
the input threshold for the device requiring the hold time. A
typical ΔV is 0.4 V. CL is the total bus capacitance per data line,
and IL is the total leakage or three-state current per data line.
The hold time is tDECAY plus the minimum disable time (tHDWD
for the write cycle).
REFERENCE
SIGNAL
Output pins are considered to be disabled when they stop
driving, go into a high impedance state, and start to decay from
their output high or low voltage. The time for the voltage on the
bus to decay by ΔV is dependent on the capacitive load, CL, and
the load current, IL. This decay time can be approximated by the
following equation:
tMEASURED
tDIS
tENA
VOH (MEASURED)
VOL (MEASURED)
VOH (MEASURED) – ∆V
2.0V
VOL (MEASURED) + ∆V
1.0V
VOL (MEASURED)
tDECAY
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
CL ∆ V
VOH (MEASURED)
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V
IL
Figure 30. Output Enable/Disable
Table 25. PEXT Calculations
Pin Type
Address
MSO
WR
Data
ADRCLK
Number of Pins
15
1
1
32
1
% Switching
50
0
–
50
–
×C
× 55 pF
× 55 pF
× 55 pF
× 25 pF
× 15 pF
PEXT (5 V) = 0.476 W.
PEXT (3.3 V) = 0.207 W.
Rev. B | Page 43 of 48
×f
× 20 MHz
× 20 MHz
× 40 MHz
× 20 MHz
× 40 MHz
× VDD2
× 25 V
× 25 V
× 25 V
× 25 V
× 25 V
= PEXT
= 0.206 W
= 0.00 W
= 0.055 W
= 0.200 W
= 0.015 W
00667-030
Output Disable Time
t DECAY =
System Hold Time Calculation Example
AD14060/AD14060L
3.5
Capacitive Loading
3.0
RISE AND FALL TIMES (ns)
(0.8V – 2.0V)
2.9
2.5
RISE TIME
2.0
1.6
1.5
FALL TIME
1.0
0.6
0.5
0
IOL
0
20
40
60
80
100 120 140
LOAD CAPACITANCE (pF)
160
180
200
00667-034
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 31). The delay and hold specifications given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figure 33 and
Figure 34 show how output rise time varies with capacitance.
Figure 35 graphically shows how output delays and holds vary
with load capacitance. (Note that this graph or derating does
not apply to output disable delays; see the Output Disable Time
section.) The graphs in Figure 33, Figure 34, and Figure 35
might not be linear outside the ranges shown.
Figure 34. Typical Output Rise Time (0.8 V to 2.0 V)
vs. Load Capacitance (VDD = 5 V)
TO OUTPUT
PIN
1.5V
5.0
50pF
00667-031
OUTPUT DELAY OR HOLD (ns)
4.5
INPUT OR
OUTPUT
1.5V
00667-032
Figure 31. Equivalent Device Loading for AC Measurement
(Includes All Fixtures)
1.5V
3.0
2.0
1.0
NOMINAL
Figure 32. Voltage Reference Levels for AC Measurements
(except Output Enable/Disable)
–0.7
–1.0
25
50
75
100
125
150
LOAD CAPACITANCE (pF)
175
200
00667-035
IOH
4.0
16.0
Figure 35. Typical Output Delay or Hold vs. Load Capacitance
at Maximum Case Temperature (VDD = 5 V)
14.7
14.0
RISE TIME
16
10.0
6.0
4.0
3.7
2.0
1.1
0
0
20
40
60
80
100 120 140
LOAD CAPACITANCE (pF)
160
180
200
Figure 33. Typical Output Rise Time (10% to 90% VDD)
vs. Load Capacitance (VDD = 5 V)
Y = 0.0796X + 1.17
12
10
RISE TIME
8
Y = 0.0467X + 0.55
6
4
FALL TIME
2
0
0
20
40
60
80
100 120 140
LOAD CAPACITANCE (pF)
160
180
Figure 36. Typical Output Rise Time (10% to 90% VDD)
vs. Load Capacitance (VDD = 3.3 V)
Rev. B | Page 44 of 48
200
00667-036
7.4
FALL TIME
RISE AND FALL TIMES (ns)
(10% – 90%)
14
8.0
00667-033
RISE AND FALL TIMES (ns)
(0.5V – 4.5V, 10% – 90%)
18
12.0
AD14060/AD14060L
9
Trim/form can be accomplished with a universal trim/form,
a customer-designed trim/form, or with the Analog Devices
developed tooling described as follows.
8
RISE AND FALL TIMES (ns)
(0.8V – 2.0V)
7
6
A trim/form tool specific to the AD14060/AD14060L has been
developed and is available for use by all parties at
Y = 0.0391X + 0.36
5
4
Tintronics Industries
2122-A Metro Circle
Huntsville, AL 35801
256-650-0220
Contact Person: Tom Rice
Y = 0.0305X + 0.24
RISE TIME
3
FALL TIME
2
0
0
20
40
60
80
100 120 140
LOAD CAPACITANCE (pF)
160
180
200
00667-037
1
Figure 37. Typical Output Rise Time (0.8 V to 2.0 V)
vs. Load Capacitance (VDD = 3.3 V)
The package outline and dimensions resulting from this tool are
shown in Figure 39. (Alternatively, the package can be
trimmed/formed for cavity-down placement.)
5.0
OUTPUT DELAY OR HOLD (ns)
4.5
0.170
(4.318)
4.0
2.110 (53.59)
Y = 0.0329X – 1.65
2.210 ± 0.010 (56.134 ± 0.254)
3.0
2.0
1.0
0.016 MIN
–0.7
–1.0
25
50
75
100
125
150
LOAD CAPACITANCE (pF)
175
200
00667-038
NOMINAL
Figure 38. Typical Output Delay or Hold vs. Load Capacitance
at Maximum Case Temperature (VDD = 3.3 V)
0° TO 8°
0 TO 10 MILS
Socket Information
DETAIL A
Standard sockets and carriers are available for the
AD14060/AD14060L, if needed. Socket part number
IC53-3084-262 and carrier part number ICC-308-1 are
available from Yamaichi Electronics.
Figure 39. Package and Lead Profile
Dimensions shown in inches and (millimeters)
Trim and Form
The AD14060/AD14060L is shipped as shown in Figure 43 with
untrimmed and unformed leads and with the nonconductive tie
bar in place. This avoids disturbance of lead spacing and
coplanarity prior to assembly. Optimally, the leads should be
trimmed, formed, and solder-dipped just prior to placement on
the board.
Rev. B | Page 45 of 48
00667-039
ASSEMBLY RECOMMENDATIONS
AD14060/AD14060L
PCB LAYOUT GUIDELINES
Thermal Characteristics
The drawing in Figure 40 assumes that the trim/form tooling
described previously is used. These recommendations are
provided for user convenience and are PCB layout guidelines
only, based on standard practice. PCB pad footprint geometries
and placement are illustrated.
The AD14060/AD14060L is packaged in a 308-lead ceramic
quad flatpack (CQFP). The package is optimized for thermal
conduction through the core (base of the package) down to the
mounting surface. The AD14060/AD14060L is specified for a
case temperature (TCASE). Design of the mounting surface and
attachment material should be such that TCASE is not exceeded.
2.260 (57.404) 4 PLACES
2.060 (52.324) 4 PLACES
1.9000 (48.26) 4 PLACES
θJC = 0.36°C/W
Thermal Cross-Section
The following data, together with the detailed mechanical
drawings in Figure 43, allows the designer to construct simple
thermal models for further analysis within targeted systems.
The top layer of the package, where the die are mounted, is a
metal VDD layer. The approximate metal area coverage from the
metal planes and routing layers is estimated in Table 27. The
layers are shown in Figure 41.
0.015
(0.381)
THIS IS A PC BOARD COMPONENT FOOTPRINT,
NOT THE PACKAGE OUTLINE.
0.025
(0.635)
Table 26. Thermal Conductivity
0.025 (0.635) MIN
0.025 (0.635) MIN
Thermal Conductivity (W/cm°C)
0.18
0.14
1.78
0.03
1.45
Table 27. Metal Coverage per Layer
Layer
VDD
SIG2
SIG3
GND
SIG4
SIG5
BASE
Figure 40. PC Board Component Footprint
Dimensions shown in inches and (millimeters)
KOVAR LID
0.015 MILS
00667-040
Material
Ceramic
Kovar™
Tungsten
Thermoplastic
Silicon
% Metal (1 Mil Thick)
88
16
14
91
15
13
95
KOVAR SEAL RING
HEIGHT = 50 MILS
SURFACE
SILICON DIE
19 MILS
CERAMIC LAYER 28 MILS
THERMOPLASTIC
THICKNESS 5 MILS
SIG2
SIG3
GND
SIG4
SIG5
CERAMIC LAYER 10 MILS
CERAMIC LAYER 4 MILS
CERAMIC LAYER 10 MILS
CERAMIC LAYER 4 MILS
BASE
Figure 41. Co-Fired Packaged Profile
Rev. B | Page 46 of 48
00667-041
CERAMIC LAYER 6 MILS
CERAMIC LAYER 6 MILS
CERAMIC LAYER 10 MILS
CERAMIC LAYER 4 MILS
CERAMIC LAYER 10 MILS
VDD
AD14060/AD14060L
MECHANICAL CHARACTERISTICS
Lid Deflection Analysis
Table 28. External Pressure Reduction
Δ Pressure
Deflection
12 psi
15 psi
10.0 mil
11.9 mil
0.670
4X
Mechanical Model
0.653
4X
0.302
2.050 SQ.
The following data, together with the detailed mechanical
drawings in Figure 43, allows the designer to construct simple
mechanical models for further analysis within targeted systems.
0.616
0.633
Table 29. Mechanical Properties
Material
Ceramic
Kovar
Tungsten
Thermoplastic
Silicon
Modulas of Elasticity
26 × 103 kg/mm2
14.1 × 103 kg/mm2
35 × 103 kg/mm2
279 kg/mm2
11 × 103 kg/mm2
0.260
0.250
0.345
1.890 ± 0.005
1.810 ± 0.005
ADDITIONAL INFORMATION
0.040 ± 0.002
This data sheet provides a general overview of the AD14060/
AD14060L architecture and functionality. For detailed
information on the ADSP-2106x SHARC and the ADSP-21000
Family core architecture and instruction set, refer to the
ADSP-2106x SHARC User’s Manual.
Rev. B | Page 47 of 48
0.012 REF
4X
Figure 42. Internal Package Dimensions
Dimensions shown in inches
00667-042
1.780 ± 0.018
AD14060/AD14060L
OUTLINE DIMENSIONS
3.050 (77.47) MAX
3.01 (76.46)
3.00 (76.20)
2.99 (75.95)
2.745 (69.72)
2.730 (69.34)
2.715 (68.96)
0.350 (8.89)
0.340 (8.64)
0.330 (8.38)
2.062 (52.38)
2.050 (52.07)
2.038 (51.77)
4×
0.015 (0.381) × 45°
3 PLACES
231
155
232
154
0.010 (0.254)
0.008 (0.203)
0.006 (0.152)
2.330 (59.18)
2.300 (58.42)
2.270 (57.66)
TOP VIEW
0.025 (0.635)
BSC
308
78
1
77
0.040 (1.016) × 45°
0.101 (2.566)
0.092 (2.337)
0.083 (2.108)
0.007 (0.165)
0.005 (0.127)
0.004 (0.102)
1.895 (48.13)
1.890 (48.01)
1.885 (47.88)
0.035 (0.889)
MAX
0.160 (4.064)
MAX
Figure 43. 308-Lead Ceramic Quad Flatpack (CQFP)
(QS-308)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model
AD14060BF-4
AD14060LBF-4
Temperature
Range
−40°C to +100°C
−40°C to +100°C
SMD
N/A
N/A
Instruction
Rate
40 MHz
40 MHz
Operating
Voltage
5V
3.3 V
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00667–0–12/04(B)
Rev. B | Page 48 of 48
Package Description
308-Lead Ceramic Quad Flatpack (CQFP)
308-Lead Ceramic Quad Flatpack (CQFP)
Package
Option
QS-308
QS-308