AD AD8226CRMZ Wide supply range, rail-to-rail output instrumentation amplifier Datasheet

FEATURES
PIN CONFIGURATION
Gain set with 1 external resistor
Gain range: 1 to 1000
Input voltage goes to ground
Input overdrive protection
Very wide power supply range
Dual supply: ±1.3 V to ±18 V
Single supply: 2.6 V to 36 V
Bandwidth (G = 1): 800 kHz
CMRR (G = 1): 78 dB minimum
Input noise: 22 nV/rt(Hz)
Typical supply current: 350 µA
SOIC-8 and MSOP-8 packages
AD8226
–IN
1
8
+VS
RG
2
7
VOUT
RG
3
6
REF
+IN
4
5
–VS
TOP VIEW
(Not to Scale)
07036-001
Preliminary Technical Data
Wide Supply Range, Rail-to-Rail
Output Instrumentation Amplifier
AD8226
Figure 1.
APPLICATIONS
Industrial process controls
Bridge amplifiers
Medical instrumentation
Portable data acquisition
Multichannel systems
GENERAL DESCRIPTION
The AD8226 is a low cost instrumentation amplifier that requires
only one external resistor to set any gain between 1 and 1000.
The AD8226 is designed to work with a very wide range of
voltages. It can operate on supplies ranging from ±1.2 V to
±18 V (2.4 V to 36 V single supply). The AD8226 comes with
rail-to-rail output and a wide input range that includes the
ability to go slightly below the negative supply. In addition, the
AD8226 inputs can withstand voltages beyond the rail.
The AD8226 is perfect for multichannel, space-constrained
applications. Being a low power and low cost amplifier allows
multiple channels to be used.
Table 1. Instrumentation Amplifiers by Category
General
Purpose
AD82201
AD8221
AD8222
AD82241
AD8228
1
Zero
Drift
AD82311
AD8290
AD82931
AD85531
AD85561
AD85571
Military
Grade
AD620
AD621
AD524
AD526
AD624
Low
Power
AD6271
AD6231
AD82261
High Speed
PGA
AD8250
AD8251
AD8253
Rail-to-rail output.
The AD8226 has three grades. The A grade is the lower cost
version and is specified for temperatures from −40°C to +85°C.
The B grade is the higher performance version and is specified
from −40°C to +85°C. The C grade version is the higher
temperature version and is specified from −40°C to +105°C. All
models are operational from −40°C to +125°C; behavior at
these temperatures is shown in the typical performance curves.
The AD8226 is available in MSOP and SOIC packages.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
AD8226
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Architecture ...................................................................................9
Applications ....................................................................................... 1
Gain Selection ................................................................................9
Pin Configuration ............................................................................. 1
Input Protection ............................................................................9
General Description ......................................................................... 1
Reference Terminal .................................................................... 10
Specifications..................................................................................... 3
Input Voltage Range ................................................................... 10
Absolute Maximum Ratings ............................................................ 7
Layout .......................................................................................... 10
Thermal Resistance ...................................................................... 7
Input Bias Current Return Path ............................................... 11
ESD Caution .................................................................................. 7
Radio Frequency Interference (RFI) ........................................ 11
Pin Configuration and Function Descriptions ............................. 8
Outline Dimensions ....................................................................... 12
Theory of Operation ........................................................................ 9
Ordering Guide .......................................................................... 13
Rev. PrA | Page 2 of 16
Preliminary Technical Data
AD8226
SPECIFICATIONS
+VS = +15 V, −VS = −15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, unless otherwise noted.
Table 2.
Parameter
COMMON-MODE REJECTION RATIO
(CMRR)
CMRR DC to 60 Hz
G=1
G = 10
G = 100
G = 1000
NOISE
Voltage Noise, 1 kHz
Input Voltage Noise, eNI
Output Voltage Noise, eNO
RTI
G=1
G = 10
G = 100 to 1000
Current Noise
VOLTAGE OFFSET
Input Offset, VOSI
Over Temperature
Average temperature coefficient
Output Offset, VOSO
Over Temperature
Average temperature coefficient
Offset RTI vs. Supply (PSR)
G=1
G = 10
G = 100
G = 1000
INPUT CURRENT
Input Bias Current
Over Temperature
Average temperature coefficient
Input Offset Current
Over Temperature
Average temperature coefficient
REFERENCE INPUT
RIN
IIN
Voltage Range
Reference Gain to Output
Reference Gain Error
Conditions
Min
A, C Grade
Typ
Max
Min
B Grade
Typ
Max
Unit
VCM = –10 V to +10 V
76
90
105
105
86
100
105
105
dB
dB
dB
dB
Total Noise:
eN = √eNI2 + (eNO/G2)
VIN+, VIN−, VREF = 0
22
120
22
120
nV/√Hz
nV/√Hz
3
0.8
0.6
100
3
3
0.8
0.6
100
3
µV p-p
µV p-p
µV p-p
fA/√Hz
pA p-p
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 0.1 Hz to 10 Hz
Total offset voltage :
VOS = VOSI + (VOSO/G)
VS = ±5 V to ±15 V
TA = TMIN to TMAX
TA = TMIN to TMAX
VS = ±5 V to ±15 V
TA = TMIN to TMAX
TA = TMIN to TMAX
VS = ±5 V to ±15 V
2
500
200
µV
µV
1500
750
µV
mV
µV/°C
15
80
100
105
105
TA = TMIN to TMAX
TA = TMIN to TMAX
10
5
2
90
105
105
105
20
30
40
10
5
100
dB
dB
dB
dB
20
2
5
5
5
100
7
100
7
−VS
+VS
1
0.01
Rev. PrA | Page 3 of 16
30
40
100
3
5
TA = TMIN to TMAX
TA = TMIN to TMAX
7
−VS
+VS
1
0.01
nA
nA
pA/°C
nA
nA
pA/°C
kΩ
µA
V
V/V
%
AD8226
Parameter
DYNAMIC RESPONSE
Small Signal –3 dB Bandwidth
G=1
G = 10
G = 100
G =1000
Settling Time 0.01%
G=1
G = 10
G = 100
G = 1000
Slew Rate
GAIN
Gain Range
Gain Error
G=1
G = 10
G = 100
G = 1000
Gain Nonlinearity
G=1
G = 100
G = 1000
G = 1-100
Gain vs. Temperature
G=1
G > 11
INPUT
Input Impedance
Differential
Common Mode
Input Operating Voltage Range2
Input Overvoltage Range
OUTPUT
Output Swing
Over Temperature
Output Swing
Over Temperature
Short-Circuit Current
POWER SUPPLY
Operating Range
Quiescent Current
Over Temperature
TEMPERATURE RANGE
Specified Performance: TMIN to TMAX
Operational
Preliminary Technical Data
Conditions
Min
A, C Grade
Typ
Max
Min
B Grade
Typ
Max
Unit
1000
150
15
1.5
1000
150
15
1.5
kHz
kHz
kHz
kHz
22
22
50
600
0.5
1
22
22
50
600
0.5
1
µs
µs
µs
µs
V/µs
V/µs
10 V step
G=1
G = 5 to 100
G = 1 + (49.4kΩ/RG)
1
1000
1
1000
V/V
0.02
0.1
0.1
0.1
%
%
%
%
VOUT ±10 V
0.07
0.3
0.3
0.3
VOUT = –10 V to +10 V
RL = 10 kΩ
RL = 10 kΩ
RL = 10 kΩ
RL = 2kΩ
ppm
ppm
ppm
ppm
TA = TMIN to TMAX
TA = TMIN to TMAX
VS = ± 1.35 V to 36 V
2
10
–50
2
2||2
2||2
TA = 25°C
TA = –40°C
TA = 105°C
TA = TMIN to TMAX
VS = ± 1.35 V to 36 V
RL = 10 kΩ to ground
TA = TMIN to TMAX
RL = 100 kΩ to ground
TA = TMIN to TMAX
ppm/°C
ppm/°C
2||2
2||2
−VS − 0.1
−VS − 0.15
−VS − 0.05
+VS −40
+VS − 0.7
+VS − 0.9
+VS − 0.6
−VS +40
−VS − 0.1
−VS − 0.15
−VS − 0.05
+VS −40
+VS − 0.7
+VS − 0.9
+VS − 0.6
−VS +40
GΩ||pF
GΩ||pF
V
V
V
V
−VS + 0.2
−VS + 0.3
−VS + 0.1
−VS + 0.1
+VS − 0.2
+VS − 0.3
+VS − 0.1
+VS − 0.1
−VS + 0.2
−VS + 0.3
−VS + 0.1
−VS + 0.1
−VS + 0.2
+VS − 0.3
−VS + 0.1
−VS + 0.1
13
V
V
V
V
mA
±18
400
±1.3
±18
400
V
µA
µA
+85
+105
+125
−40
+85
°C
−40
+125
°C
13
Dual supply operation
5
–50
±1.3
350
350
TA = TMIN to TMAX
A and B grades
C grade
–40
–40
–40
1
Does not include the effects of external resistor RG
Input voltage range of the AD8226 input stage. Input range depends on common mode voltage, differential voltage, gain, and reference voltage. See the Input
Voltage Range section in the Theory of Operation for more information.
2
Rev. PrA | Page 4 of 16
Preliminary Technical Data
AD8226
+VS = 2.7 V, –VS = 0 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, unless otherwise noted.
Table 3.
Parameter
COMMON-MODE REJECTION RATIO
(CMRR)
CMRR DC to 60 Hz
G=1
G = 10
G = 100
G = 1000
NOISE
Voltage Noise, 1 kHz
Input Voltage Noise, eNI
Output Voltage Noise, eNO
RTI
G=1
G = 10
G = 100 to 1000
Current Noise
VOLTAGE OFFSET
Input Offset, VOSI
Over Temperature
Average TC
Output Offset, VOSO
Over Temperature
Average TC
Offset RTI vs. Supply (PSR)
G=1
G = 10
G = 100
G = 1000
INPUT CURRENT
Input Bias Current
Over Temperature
Average TC
Input Offset Current
Over Temperature
Average TC
REFERENCE INPUT
RIN
IIN
Voltage Range
Reference Gain to Output
Reference Gain Error
DYNAMIC RESPONSE
Small Signal –3 dB Bandwidth
G=1
G = 10
G = 100
G =1000
Conditions
Min
A,C Grade
Typ
Max
Min
B Grade
Typ
Max
Unit
VCM = 0 V to 1.7 V
76
90
105
105
86
100
105
105
dB
dB
dB
dB
Total Noise:
eN = √eNI2 + (eNO/G2)
VIN+, VIN−, VREF= 0
22
120
22
120
nV/√Hz
nV/√Hz
3
0.8
0.6
100
3
3
0.8
0.6
100
3
µV p-p
µV p-p
µV p-p
fA/√Hz
pA p-p
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 0.1 Hz to 10 Hz
Total offset voltage :
VOS = VOSI + (VOSO/G)
VS = 0 V to 1.7 V
TA = TMIN to TMAX
TA = TMIN to TMAX
VS = 0 V to 1.7 V
TA = TMIN to TMAX
TA = TMIN to TMAX
VS = 0 V to 1.7 V
300
0.1
4
1200
0.1
2
750
2
15
2
7
80
100
105
105
TA = TMIN to TMAX
TA = TMIN to TMAX
10
5
150
90
105
105
105
20
30
40
10
5
100
dB
dB
dB
dB
20
2
5
5
5
100
7
100
7
nA
nA
pA/°C
nA
nA
pA/°C
1
0.01
1
0.01
kΩ
µA
V
V/V
%
1000
150
15
1.5
1000
150
15
1.5
kHz
kHz
kHz
kHz
−VS
Rev. PrA | Page 5 of 16
30
40
100
3
5
TA = TMIN to TMAX
TA = TMIN to TMAX
µV
µV
µV/°C
µV
mV
µV/°C
+VS
−VS
+VS
AD8226
Parameter
Settling Time 0.01%
G=1
G=10
G = 100
G = 1000
Slew Rate
GAIN
Gain Range
Gain Error
G=1
G = 10
G = 100
G = 1000
Gain Nonlinearity
G=1
G = 100
G = 1000
G = 1-100
Gain vs. Temperature
G=1
G > 11
INPUT
Input Impedance
Differential
Common Mode
Input Operating Voltage Range2
Input Overvoltage Range
OUTPUT
Output Swing
Over Temperature
Output Swing
Over Temperature
Short-Circuit Current
POWER SUPPLY
Operating Range
Quiescent Current
Over Temperature
TEMPERATURE RANGE
Specified Performance: TMIN to TMAX
Operational
Preliminary Technical Data
Conditions
2 V step
Min
A,C Grade
Typ
Max
Min
22
22
50
600
0.5
1
G=1
G = 5 to 100
G = 1 + (49.4 kΩ/RG)
1
B Grade
Typ
Max
22
22
50
600
0.5
1
1000
1
Unit
µs
µs
µs
µs
V/µs
V/µs
1000
V/V
0.02
0.1
0.1
0.1
%
%
%
%
VOUT = 0 V to 1.7 V
0.07
0.3
0.3
0.3
VOUT = 0 V to 1.7 V
RL = 10 kΩ
RL = 10 kΩ
RL = 10 kΩ
RL = 2 kΩ
ppm
ppm
ppm
ppm
TA = TMIN to TMAX
TA = TMIN to TMAX
−VS = 0V; +VS = 2.7 V to 36 V
2
10
−50
2
2||2
2||2
TA = 25°C
TA = –40°C
TA = 105°C
TA = TMIN to TMAX
−VS = 0V; +VS = 2.7 V to 36 V
RL = 10 kΩ to opposite supply
TA = TMIN to TMAX
RL = 100 kΩ to opposite supply
TA = TMIN to TMAX
2||2
2||2
GΩ||pF
GΩ||pF
V
V
V
+VS − 0.7
+VS − 0.9
+VS − 0.6
−VS +40
− 0.1
− 0.15
− 0.05
+VS −40
+VS − 0.7
+VS − 0.9
+VS − 0.6
−VS +40
0.2
0.3
0.1
0.1
+VS − 0.2
+VS − 0.3
+VS − 0.1
+VS − 0.1
0.2
0.3
0.1
0.1
−VS + 0.2
+VS − 0.3
−VS + 0.1
−VS + 0.1
V
V
V
V
mA
36
350
V
µA
µA
–40
+85
°C
–40
+125
°C
13
2.6
36
300
2.6
350
300
TA = TMIN to TMAX
A and B grades
C grade
ppm/°C
ppm/°C
− 0.1
− 0.15
− 0.05
+VS −40
13
Single supply operation
5
–50
–40
–40
–40
1
+85
+105
+125
Does not include the effects of external resistor RG
Input voltage range of the AD8226 input stage. Input range depends on common mode voltage, differential voltage, gain, and reference voltage. See the Input
Voltage Range section in the Theory of Operation for more information.
2
Rev. PrA | Page 6 of 16
Preliminary Technical Data
AD8226
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Parameter
Supply Voltage
Output Short-Circuit Current
Maximum Voltage at −IN or +IN
Minimum Voltage at −IN or +IN
REF Voltage
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range1
Maximum Junction Temperature
ESD
Human Body Model
Charge Device Model
1
θJA is specified for a device in free air.
Rating
±18 V
Indefinite
−Vs + 40V
+Vs − 40V
±Vs
±40V
−65°C to +150°C
−40°C to +125°C
140°C
Table 5.
Package
8-Lead MSOP, 4-Layer JEDEC Board
8-Lead SOIC, 4-Layer JEDEC Board
ESD CAUTION
2 kV
1 kV
Temperature range for specified performance is either −40°C to +85°C or
−40°C to +105°C, depending on grade.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. PrA | Page 7 of 16
θJA
135
121
Unit
°C/W
°C/W
AD8226
Preliminary Technical Data
AD8226
–IN
1
8
+VS
RG
2
7
VOUT
RG
3
6
REF
+IN
4
5
–VS
TOP VIEW
(Not to Scale)
07036-002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
2, 3
4
5
6
7
8
Mnemonic
−IN
RG
+IN
−VS
REF
VOUT
+VS
Description
Negative Input.
Gain Setting Pins. Place gain resistor between these two pins.
Positive Input.
Negative Supply.
Reference. Must be driven by low impedance.
Output.
Positive Supply.
Rev. PrA | Page 8 of 16
Preliminary Technical Data
AD8226
THEORY OF OPERATION
+VS
+VS
RG
NODE 4
–VS
R1 –VS
2.47kΩ
R3
50kΩ
R2
2.47kΩ
+VS
R4
50kΩ
NODE 2
Q1
+IN
–VS
RB
+VS
A1
A2
UB
OUT
A3
NODE 1
+VS
Q2
+VS
R5
50kΩ
–VS
R6
50kΩ
REF
–IN
RB
–VS
–VS
DIFFERENCE
AMPLIFIER STAGE
GAIN STAGE
07036-003
NODE 3
Figure 3. Simplified Schematic
ARCHITECTURE
GAIN SELECTION
The AD8226 is based on the classic three op amp topology. This
topology has two stages: a preamplifier to provide differential
amplification, followed by a difference amplifier to remove the
common-mode voltage. Figure 3 shows a simplified schematic of
the AD8226.
Placing a resistor across the RG terminals sets the gain of the
AD8226, which can be calculated by referring to Table 7 or by
using the following gain equation:
The first stage works as follows: in order to maintain a constant
voltage across the Bias Resistor RB, Amplifier A1 must keep
Node 3 a constant diode drop above the positive input voltage.
Similarly, Amplifier A2 keeps Node 4 at a constant diode drop
above the negative input voltage. Therefore a replica of the
differential input voltage is placed across the gain setting
resistor, RG. The current that flows across this resistance must
also flow through the R1 and R2 resistors, creating a gained
differential signal between the A2 and A1 outputs. Note that, in
addition to a gained differential signal, the original commonmode signal, shifted a diode drop down, is also still present.
The second stage is a difference amplifier, composed of A3 and
four 50 kΩ resistors. The purpose of this stage is to remove the
common-mode signal from the amplified differential signal.
Because the input amplifiers employ a current feedback
architecture, the gain-bandwidth product of the AD8226
increases with gain, resulting in a system that does not suffer
from the expected bandwidth loss of voltage feedback
architectures at higher gains.
The transfer function of the AD8226 is
VOUT = G(VIN+ − VIN−) + VREF
where
G =1+
49.4 kΩ
RG
RG =
49.4 kΩ
G −1
Table 7. Gains Achieved Using 1% Resistors
1% Standard Table Value of RG (Ω)
49.9 k
12.4 k
5.49 k
2.61 k
1.00 k
499
249
100
49.9
Calculated Gain
1.990
4.984
9.998
19.93
50.40
100.0
199.4
495.0
991.0
The AD8226 defaults to G = 1 when no gain resistor is used.
The tolerance and gain drift of the RG resistor should be added
to the AD8226’s specifications to determine the total gain
accuracy of the system. When the gain resistor is not used,
gain error and gain drift are minimal.
INPUT PROTECTION
The input terminals of the AD8226 have input protection that
allows the input voltage to go beyond the rails without
damaging the part. Maximum voltage is –Vs+40 V and
minimum voltage is +Vs-40 V. For example: with ±15 V
supplies, the part can withstand input voltages of ±25 V; with a
5 V single supply, maximum input voltage is 40 V and
minimum input voltage is 35 V.
Rev. PrA | Page 9 of 16
AD8226
Preliminary Technical Data
REFERENCE TERMINAL
For the best performance, source impedance to the REF
terminal should be kept below 2 Ω. As shown in Figure 3, the
reference terminal, REF, is at one end of a 50 kΩ resistor.
Additional impedance at the REF terminal adds to this 50 kΩ
resistor and results in amplification of the signal connected to
the positive input. The amplification from the additional RREF
can be computed by 2(50 kΩ + RREF)/100 kΩ + RREF.
The common-mode input range shifts upwards with temperature. At cold temperatures, the part requires an extra 200 mV
of headroom from the positive supply, and operation near the
negative supply has more margin. Conversely, hot temperatures
require less headroom from the positive supply, but are the worstcase conditions for input voltages near the negative supply.
LAYOUT
To ensure optimum performance of the AD8226 at the PCB
level, care must be taken in the design of the board layout.
The AD8226 pins are arranged in a logical manner to aid in
this task.
Only the positive signal path is amplified; the negative path
is unaffected. This uneven amplification degrades CMRR.
INCORRECT
< + VS − 1.6 V
CORRECT
–IN 1
8
+VS
RG 2
7
VOUT
RG 3
6
REF
+IN
5
–VS
4
AD8226
TOP VIEW
(Not to Scale)
AD8226
REF
AD8226
Figure 5. Pinout Diagram
REF
V
Common-Mode Rejection Ratio over Frequency
V
+
–
07036-004
OP1177
Figure 4. Driving the Reference Pin
INPUT VOLTAGE RANGE
The three op amp architecture of the AD8226 applies gain in
the first stage before removing common-mode voltage in the
difference amplifier stage. In addition, the input transistors in
the first stage shift the common mode voltage up one diode
drop (about 650 mV.) Therefore, internal nodes between the
first and second stages (nodes 1 and 2 in Figure 3) experience a
combination of gained signal, common-mode signal, and
650 mV. This combined signal can be limited by the voltage
supplies even when the individual input and output signals are
not. Figure XX through Figure XX show the allowable
common-mode input voltage ranges for various output voltages
and supply voltages.
The following formulas can also be used to understand how the
reference voltage (VREF), common mode input voltage (VCM),
and differential input voltage (VDIFF) interact. These two
formulas, along with the input range specifications in Table 1
and Table 3, set the boundaries where the part operates with
best performance.
− V S − 0. 4 V <
07036-005
The output voltage of the AD8226 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal needs to be offset to a precise midsupply level. For
example, a voltage source can be tied to the REF pin to levelshift the output so that the AD8226 can drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +VS or −VS by more than 0.3 V.
(VDIFF )(GAIN )
+ VCM + VREF
2
2
Poor layout can cause some of the common-mode signals to be
converted to differential signals before reaching the in-amp.
Such conversions occur when one input path has a frequency
response that is different from the other. To keep CMRR across
frequency high, input source impedance and capacitance of each
path should be closely matched. Additional source resistance in
the input path (for example, for input protection) should be placed
close to the in-amp inputs, which minimizes their interaction
with parasitic capacitance from the PCB traces.
Parasitic capacitance at the gain setting pins can also affect
CMRR over frequency. If the board design has a component
at the gain setting pins (for example, a switch or jumper), the
part should be chosen so that the parasitic capacitance is as
small as possible.
Power Supplies
A stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect
performance.
A 0.1 µF capacitor should be placed as close as possible to each
supply pin. As shown in Figure 6, a 10 µF tantalum capacitor
can be used farther away from the part. In most cases, it can be
shared by other precision integrated circuits.
(VDIFF )(GAIN )
+ VCM < + VS − 0.9 V
2
Rev. PrA | Page 10 of 16
Preliminary Technical Data
AD8226
RADIO FREQUENCY INTERFERENCE (RFI)
+VS
RF rectification is often a problem when amplifiers are used in
applications having strong RF signals. The disturbance can appear
as a small dc offset voltage. High frequency signals can be filtered
with a low-pass RC network placed at the input of the instrumentation amplifier, as shown in Figure 8. The filter limits the
input signal bandwidth, according to the following relationship:
10µF
0.1µF
+IN
VOUT
AD8226
LOAD
REF
–IN
0.1µF
10µF
–VS
07036-006
FilterFrequencyDIFF =
FilterFrequencyCM =
Figure 6. Supply Decoupling, REF, and Output Referred to Local Ground
1
2πR(2CD + CC )
1
2πRCC
where CD ≥ 10 CC.
References
+VS
The output voltage of the AD8226 is developed with respect to
the potential on the reference terminal. Care should be taken to
tie REF to the appropriate local ground.
0.1µF
10µF
CC
1nF
INPUT BIAS CURRENT RETURN PATH
R
+IN
4.02kΩ
The input bias current of the AD8226 must have a return path
to ground. When the source, such as a thermocouple, cannot
provide a return current path, one should be created, as shown
in Figure 7.
CD
10nF
RG
VOUT
AD8226
R
REF
4.02kΩ
–IN
CC
1nF
CORRECT
10µF
0.1µF
+VS
+VS
–VS
07036-008
INCORRECT
Figure 8. RFI Suppression
CD affects the difference signal, and CC affects the common-mode
signal. Values of R and CC should be chosen to minimize RFI.
Mismatch between the R × CC at the positive input and the R × CC
at the negative input degrades the CMRR of the AD8226. By using
a value of CD one magnitude larger than CC, the effect of the
mismatch is reduced, and performance is improved.
AD8226
AD8226
REF
REF
–VS
–VS
TRANSFORMER
TRANSFORMER
+VS
+VS
AD8226
AD8226
REF
REF
10MΩ
–VS
–VS
THERMOCOUPLE
THERMOCOUPLE
+VS
+VS
C
C
R
1
fHIGH-PASS = 2πRC
AD8226
C
REF
AD8226
C
REF
–VS
–VS
CAPACITIVELY COUPLED
CAPACITIVELY COUPLED
07036-007
R
Figure 7. Creating an IBIAS Path
Rev. PrA | Page 11 of 16
AD8226
Preliminary Technical Data
OUTLINE DIMENSIONS
3.20
3.00
2.80
5.15
4.90
4.65
5
8
3.20
3.00
2.80
1
4
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.15
0.00
0.38
0.22
COPLANARITY
0.10
0.80
0.60
0.40
8°
0°
0.23
0.08
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 9. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-A A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 10. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. PrA | Page 12 of 16
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
Preliminary Technical Data
AD8226
ORDERING GUIDE
Model
AD8226ARMZ1
AD8226ARMZ-RL1
AD8226ARMZ-R71
AD8226ARZ1
AD8226ARZ-RL1
AD8226ARZ-R71
AD8226BRMZ1
AD8226BRMZ-RL1
AD8226BRMZ-R71
AD8226BRZ1
AD8226BRZ-RL1
AD8226ARZ-R71
AD8226CRMZ1
AD8226CRMZ-RL1
AD8226CRMZ-R71
AD8226CRZ1
AD8226CRZ-RL1
AD8226CRZ-R71
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
Package Description
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
Z = RoHS Compliant Part.
Rev. PrA | Page 13 of 16
PackageOption
RM-8
RM-8
RM-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
R-8
R-8
R-8
Branding
Y16
Y16
Y16
Y1M
Y1M
Y1M
Y1Y
Y1Y
Y1Y
AD8226
Preliminary Technical Data
NOTES
Rev. PrA | Page 14 of 16
Preliminary Technical Data
AD8226
NOTES
Rev. PrA | Page 15 of 16
AD8226
Preliminary Technical Data
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR07036-0-10/08(PrA)
Rev. PrA | Page 16 of 16