256M DDR2 -AS4C16M16D2
Revision History
AS4ϭϲDϭϲϮ - ϴϰ-ball FBGA PACKAGE
Revision
Rev 1.0
Details
Preliminary datasheet
Date
DĂLJ201ϱ
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- 1/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
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16M x 16 bit DDRII Synchronous DRAM (SDRAM)
Advanced (Rev. 1.0, Ma\/201)
Features
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- 2/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
Overview
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- 3/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
Table . Speed Grade Information
6SHHG*UDGH
Clock Frequency
CAS Latency
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tRCD (ns)
tRP (ns)
Table . Ordering Information
Part Number
2UJ
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- 4/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
Figure 1. Ball Assignment (FBGA Top View)
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VDD
- 5/66 -
VDD
VSS
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
Figure 2. Block Diagram
CK
CK#
DLL
CLOCK
BUFFER
COMMAND
DECODER
A10/AP
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MODE
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4M x 16
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Row
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CS#
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Row
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CKE
- 6/66 -
4M x 16
CELL ARRAY
(BANK #3)
Column Decoder
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
Figure 3. State Diagram
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- 7/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
Ball Descriptions
Table 3. Ball Descriptions
Symbol
Type
Description
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Data Input Mask: ,QSXWGDWDLVPDVNHGZKHQ'0LVVDPSOHG+,*+GXULQJDZULWHF\FOH
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6XSSO\ Power Supply:9±9
- 8/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
966
6XSSO\ Ground
9''/
6XSSO\ DLL Power Supply:9±9
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6XSSO\ DLL Ground
9''4
6XSSO\ DQ Power: 9±9
9664
6XSSO\ DQ Ground
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6XSSO\ Reference Voltage for Inputs: 9''4
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Confidential
No Connect:7KHVHSLQVVKRXOGEHOHIWXQFRQQHFWHG
- 9/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
Operation Mode
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Table 4. Truth Table (Note (1), (2))
Command
State
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Confidential
- 10/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
Functional Description
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Confidential
- 11/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
! Mode Register Set (MRS)
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Table 5. Mode Register Bitmap
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Confidential
- 12/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
! Extended Mode Register Set (EMRS)
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Table 6. Extended Mode Register EMR (1) Bitmap
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Confidential
- 13/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
EMR(2)
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Table 7. Extended Mode Register EMR (2) Bitmap
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Confidential
- 14/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
EMR(3)
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Table 8. Extended Mode Register EMR (3) Bitmap
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- 15/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
! Off-chip drive (OCD) impedance adjustment
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Figure 4. OCD impedance adjustment sequence
Before entering OCD impedance adjustment, all MR should be programmed and
ODT should be carefully controlled depending on system environment
Start
EMRS:OCD calibration mode exit
EMRS:Drive(1)
DQ &DQS HIGH;DQS# LOW
Test
EMRS:Drive(0)
DQ &DQS LOW;DQS# HIGH
ALL OK
ALL OK
Test
EMRS:OCD calibration mode exit
EMRS:OCD calibration mode exit
EMRS:Enter Adjust Mode
EMRS:Enter Adjust Mode
BL=4 code input to all DQs
Inc, Dec, or NOP
BL=4 code input to all DQs
Inc, Dec, or NOP
EMRS:OCD calibration mode exit
EMRS:OCD calibration mode exit
EMRS:OCD calibration mode exit
End
Confidential
- 16/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
Extended mode register for OCD impedance adjustment
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Table 9. OCD drive mode program
A9
A8
A7
operation
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Table 10. OCD adjust mode program
4bit burst code inputs to all DQs
DT0
DT1
DT2
DT3
2WKHU&RPELQDWLRQV
Confidential
Pull-up driver strength
123
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123
123
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,QFUHDVHE\VWHS
'HFUHDVHE\VWHS
- 17/66 -
Operation
Pull-down driver strength
123
123
123
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5HVHUYHG
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
! ODT (On Die Termination)
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Figure 5. Functional representation of ODT
9''4
9''4
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Table 11. ODT DC Electrical Characteristics
Parameter/Condition
Symbol
Min
Nom
Max
Unit Note
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Confidential
- 18/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
! Bank activate command
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! Read and Write access modes
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Confidential
- 19/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
Table 12. Burst Definition, Addressing Sequence of Sequential and Interleave Mode
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6WDUW$GGUHVV
$
$
$
;
;
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! Burst read command
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WKHULVLQJHGJHRIWKHFORFN7KHDGGUHVVLQSXWVGHWHUPLQHWKHVWDUWLQJFROXPQDGGUHVVIRUWKHEXUVW7KHGHOD\
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! Burst write operation
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Confidential
- 20/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
! Write data mask
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7KUHHDGGUHVVELWV$%$DQG%$DUHXVHGWRGHILQHZKLFKEDQNWRSUHFKDUJHZKHQWKHFRPPDQGLVLVVXHG
Table 13. Bank Selection for Precharge by address bits
A10
BA1
BA0
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Confidential
- 21/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
! Burst read with auto precharge
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Table 14. Precharge &Auto Precharge Clariification
Minimum Delay between ÒFrom
Unit Notes
CommandÓ to ÒTo CommandÓ
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From Command
Confidential
To Command
- 22/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
! Refresh command
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! Self refresh operation
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³GRQ¶WFDUH´)RUSURSHU6HOI5HIUHVKRSHUDWLRQDOOSRZHUVXSSO\SLQV 9''9''49''/DQG95() PXVWEHDWYDOLG
OHYHOV7KH'5$0LQLWLDWHVDPLQLPXPRIRQHUHIUHVKFRPPDQGLQWHUQDOO\ZLWKLQW&.(SHULRGRQFHLWHQWHUV6HOI
5HIUHVKPRGH7KHFORFNLVLQWHUQDOO\GLVDEOHGGXULQJ6HOI5HIUHVK2SHUDWLRQWRVDYHSRZHU7KHPLQLPXPWLPH
WKDW WKH ''5 6'5$0 PXVW UHPDLQ LQ 6HOI 5HIUHVK PRGH LV W&.( 7KH XVHU PD\ FKDQJH WKH H[WHUQDO FORFN
IUHTXHQF\RUKDOWWKHH[WHUQDOFORFNRQHFORFNDIWHU6HOI5HIUHVKHQWU\LVUHJLVWHUHGKRZHYHUWKHFORFNPXVWEH
UHVWDUWHGDQGVWDEOHEHIRUHWKHGHYLFHFDQH[LW6HOI5HIUHVKRSHUDWLRQ
7KHSURFHGXUHIRUH[LWLQJ6HOI5HIUHVKUHTXLUHVDVHTXHQFHRIFRPPDQGV)LUVWWKHFORFNPXVWEHVWDEOHSULRU
WR&.(JRLQJEDFN+,*+2QFH6HOI5HIUHVK([LWLVUHJLVWHUHGDGHOD\RIDWOHDVWW;615PXVWEHVDWLVILHGEHIRUH
D YDOLG FRPPDQG FDQ EH LVVXHG WR WKH GHYLFH WR DOORZ IRU DQ\ LQWHUQDO UHIUHVK LQ SURJUHVV &.( PXVW UHPDLQ
+,*+ IRU WKH HQWLUH 6HOI 5HIUHVK H[LW SHULRG W;65' IRU SURSHU RSHUDWLRQ H[FHSW IRU 6HOI 5HIUHVK UHHQWU\ 8SRQ
H[LWIURP6HOI5HIUHVKWKH''56'5$0FDQEHSXWEDFNLQWR6HOI5HIUHVKPRGHDIWHUZDLWLQJDWOHDVWW;615
SHULRG DQG LVVXLQJ RQH UHIUHVK FRPPDQG UHIUHVK SHULRG RI W5)& 123 RU GHVHOHFW FRPPDQGV PXVW EH
UHJLVWHUHG RQ HDFK SRVLWLYH FORFN HGJH GXULQJ WKH 6HOI 5HIUHVK H[LW LQWHUYDO W;615 2'7 VKRXOG EH WXUQHG RII
GXULQJW;65'
7KH XVH RI 6HOI 5HIUHVK PRGH LQWURGXFHV WKH SRVVLELOLW\ WKDW DQ LQWHUQDOO\ WLPHG UHIUHVK HYHQW FDQ EH PLVVHG
ZKHQ&.(LVUDLVHGIRUH[LWIURP6HOI5HIUHVKPRGH8SRQH[LWIURP6HOI5HIUHVKWKH''56'5$0UHTXLUHVD
PLQLPXPRIRQHH[WUDDXWRUHIUHVKFRPPDQGEHIRUHLWLVSXWEDFNLQWR6HOI5HIUHVKPRGH
Confidential
- 23/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
! Power-Down
3RZHUGRZQLVV\QFKURQRXVO\HQWHUHGZKHQ&.(LVUHJLVWHUHG/2:DORQJZLWK123RU'HVHOHFWFRPPDQG1R
UHDGRUZULWHRSHUDWLRQPD\EHLQSURJUHVVZKHQ&.(JRHV/2:7KHVHRSHUDWLRQVDUHDQ\RIWKHIROORZLQJ
UHDGEXUVWRUZULWHEXUVWDQGUHFRYHU\&.(LVDOORZHGWRJR/2:ZKLOHDQ\RIRWKHURSHUDWLRQVVXFKDVURZ
DFWLYDWLRQ SUHFKDUJH RU DXWRSUHFKDUJH PRGH UHJLVWHU RU H[WHQGHG PRGH UHJLVWHU FRPPDQG WLPH RU
DXWRUHIUHVKLVLQSURJUHVV
7KH'//VKRXOGEHLQDORFNHGVWDWHZKHQSRZHUGRZQLVHQWHUHG2WKHUZLVH'//VKRXOGEHUHVHWDIWHUH[LWLQJ
SRZHUGRZQPRGHIRUSURSHUUHDGRSHUDWLRQ
,I SRZHUGRZQ RFFXUV ZKHQ DOO EDQNV DUH SUHFKDUJHG WKLV PRGH LV UHIHUUHG WR DV 3UHFKDUJH 3RZHUGRZQ LI
SRZHUGRZQRFFXUVZKHQWKHUHLVDURZDFWLYHLQDQ\EDQNWKLVPRGHLVUHIHUUHGWRDV$FWLYH3RZHUGRZQ)RU
$FWLYH3RZHUGRZQWZRGLIIHUHQWSRZHUVDYLQJPRGHVFDQEHVHOHFWHGZLWKLQWKH056UHJLVWHUDGGUHVVELW$
:KHQ$LVVHWWR³/2:´WKLVPRGHLVUHIHUUHGDV³VWDQGDUGDFWLYHSRZHUGRZQPRGH´DQGDIDVWSRZHUGRZQ
H[LWWLPLQJGHILQHGE\WKHW;$5'WLPLQJSDUDPHWHUFDQEHXVHG:KHQ$LVVHWWR³+,*+´WKLVPRGHLVUHIHUUHG
DVDSRZHUVDYLQJ³/2:SRZHUDFWLYHSRZHUGRZQPRGH´7KLVPRGHWDNHVORQJHUWRH[LWIURPWKHSRZHUGRZQ
PRGH DQG WKH W;$5'6 WLPLQJ SDUDPHWHU KDV WR EH VDWLVILHG (QWHULQJ SRZHUGRZQ GHDFWLYDWHV WKH LQSXW DQG
RXWSXW EXIIHUV H[FOXGLQJ &. &. 2'7 DQG &.( $OVR WKH '// LV GLVDEOHG XSRQ HQWHULQJ SUHFKDUJH SRZHU
GRZQRUVORZH[LWDFWLYHSRZHUGRZQEXWWKH'//LVNHSWHQDEOHGGXULQJIDVWH[LWDFWLYHSRZHUGRZQ,QSRZHU
GRZQPRGH&.(/2:DQGDVWDEOHFORFNVLJQDOPXVWEHPDLQWDLQHGDWWKHLQSXWVRIWKH''56'5$0DQG
DOORWKHULQSXWVLJQDOVDUH³'RQ¶W&DUH´3RZHUGRZQGXUDWLRQLVOLPLWHGE\WLPHVW5(),RIWKHGHYLFH
7KH SRZHUGRZQ VWDWH LV V\QFKURQRXVO\ H[LWHG ZKHQ &.( LV UHJLVWHUHG +,*+ DORQJ ZLWK D 123 RU 'HVHOHFW
FRPPDQG $YDOLGH[HFXWDEOHFRPPDQGFDQEHDSSOLHGZLWKSRZHUGRZQH[LWODWHQF\W;3W;$5'RUW;$5'6DIWHU
&.(JRHV+,*+3RZHUGRZQH[LWODWHQFLHVDUHGHILQHGLQWKH$&VSHFWDEOHRIWKLVGDWDVKHHW
! Asynchronous CKE LOW Event
'5$0 UHTXLUHV &.( WR EH PDLQWDLQHG ³+,*+´ IRU DOO YDOLG RSHUDWLRQV DV GHILQHG LQ WKLV GDWDVKHHW ,I &.(
DV\QFKURQRXVO\GURSV³/2:´GXULQJDQ\YDOLGRSHUDWLRQ'5$0LVQRWJXDUDQWHHGWRSUHVHUYHWKHFRQWHQWVRI
DUUD\,IWKLVHYHQWRFFXUVPHPRU\FRQWUROOHUPXVWVDWLVI\'5$0WLPLQJVSHFLILFDWLRQW'HOD\EHIRUHWXUQLQJRII
WKHFORFNV6WDEOHFORFNVPXVWH[LVWDWWKHLQSXWRI'5$0EHIRUH&.(LVUDLVHG³+,*+´DJDLQ'5$0PXVWEH
IXOO\UHLQLWLDOL]HG'5$0LVUHDG\IRUQRUPDORSHUDWLRQDIWHUWKHLQLWLDOL]DWLRQVHTXHQFH
! Input clock frequency change during precharge power down
''5 6'5$0 LQSXW FORFN IUHTXHQF\ FDQ EH FKDQJHG XQGHU IROORZLQJ FRQGLWLRQ ''5 6'5$0 LV LQ
SUHFKDUJHGSRZHUGRZQPRGH2'7PXVWEHWXUQHGRIIDQG&.(PXVWEHDWORJLF/2:OHYHO$PLQLPXPRI
FORFNVPXVWEHZDLWHGDIWHU&.(JRHV/2:EHIRUHFORFNIUHTXHQF\PD\FKDQJH6'5$0LQSXWFORFNIUHTXHQF\
LVDOORZHGWRFKDQJHRQO\ZLWKLQPLQLPXPDQGPD[LPXPRSHUDWLQJIUHTXHQF\VSHFLILHGIRUWKHSDUWLFXODUVSHHG
JUDGH 'XULQJ LQSXW FORFN IUHTXHQF\ FKDQJH 2'7 DQG &.( PXVW EH KHOG DW VWDEOH /2: OHYHOV 2QFH LQSXW
FORFNIUHTXHQF\LVFKDQJHGVWDEOHQHZFORFNVPXVWEHSURYLGHGWR'5$0EHIRUHSUHFKDUJHSRZHUGRZQPD\
EH H[LWHG DQG '// PXVW EH 5(6(7 YLD (056 DIWHU SUHFKDUJH SRZHU GRZQ H[LW 'HSHQGLQJ RQ QHZ FORFN
IUHTXHQF\DQDGGLWLRQDO056FRPPDQGPD\QHHGWREHLVVXHGWRDSSURSULDWHO\VHWWKH:5&/HWF'XULQJ'//
UHORFN SHULRG 2'7 PXVW UHPDLQ RII $IWHU WKH '// ORFN WLPH WKH '5$0 LV UHDG\ WR RSHUDWH ZLWK QHZ FORFN
IUHTXHQF\
! No operation command
7KH1R2SHUDWLRQ&RPPDQGVKRXOGEHXVHGLQFDVHVZKHQWKH''56'5$0LVLQDQLGOHRUDZDLWVWDWH7KH
SXUSRVHRIWKH1R2SHUDWLRQ&RPPDQG 123 LVWRSUHYHQWWKH''56'5$0IURPUHJLVWHULQJDQ\XQZDQWHG
FRPPDQGVEHWZHHQRSHUDWLRQV$1R2SHUDWLRQ&RPPDQGLVUHJLVWHUHGZKHQ&6LV/2:ZLWK5$6&$6
DQG :( KHOG +,*+ DW WKH ULVLQJ HGJH RI WKH FORFN $ 1R 2SHUDWLRQ &RPPDQG ZLOO QRW WHUPLQDWH D SUHYLRXV
RSHUDWLRQWKDWLVVWLOOH[HFXWLQJVXFKDVDEXUVWUHDGRUZULWHF\FOH
! Deselect command
7KH'HVHOHFW&RPPDQGSHUIRUPVWKHVDPHIXQFWLRQDVD1R2SHUDWLRQ&RPPDQG'HVHOHFW&RPPDQGRFFXUV
ZKHQ&6LVEURXJKW+,*+DWWKHULVLQJHGJHRIWKHFORFNWKH5$6&$6DQG:(VLJQDOVEHFRPHGRQ¶W
FDUHV
Confidential
- 24/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
Table 15. Absolute Maximum DC Ratings
Symbol
Parameter
Values
Unit Note
9''
9ROWDJHRQ9''SLQUHODWLYHWR9VV
a
9
9''4
9ROWDJHRQ9''4SLQUHODWLYHWR9VV
a
9
9''/
9ROWDJHRQ9''/SLQUHODWLYHWR9VV
a
9
9,19287
9ROWDJHRQDQ\SLQUHODWLYHWR9VV
a
9
767*
6WRUDJHWHPSHUDWXUH
a
& NOTE1: 6WUHVVJUHDWHUWKDQWKRVHOLVWHGXQGHU³$EVROXWH0D[LPXP5DWLQJV´PD\FDXVHSHUPDQHQWGDPDJHWRWKH
GHYLFHV7KLVLVDVWUHVVUDWLQJRQO\DQGIXQFWLRQDORSHUDWLRQRIWKHGHYLFHDWWKHVHRUDQ\RWKHUFRQGLWLRQV
DERYHWKRVHLQGLFDWHGLQWKHRSHUDWLRQDOVHFWLRQVRIWKLVVSHFLILFDWLRQLVQRWLPSOLHG([SRVXUHWRDEVROXWH
PD[LPXPUDWLQJFRQGLWLRQVIRUH[WHQGHGSHULRGVPD\DIIHFWUHOLDELOLW\
NOTE2:6WRUDJHWHPSHUDWXUHLVWKHFDVHWHPSHUDWXUHRQWKHFHQWHUWRSVLGHRIWKH'5$0
NOTE3::KHQ9''DQG9''4DQG9''/DUHOHVVWKDQP99UHIPD\EHHTXDOWRRUOHVVWKDQP9
NOTE4:9ROWDJHRQDQ\LQSXWRU,2PD\QRWH[FHHGYROWDJHRQ9''4
Table 16. Operating Temperature Condition
Symbol
723(5
Parameter
Values
&RPPHUFLDOWHPSHUDWXUH
Unit Note
&
a
,QGXVWULDOWHPSHUDWXUH
a
& NOTE1:2SHUDWLQJWHPSHUDWXUHLVWKHFDVHVXUIDFHWHPSHUDWXUHRQFHQWHUWRSRIWKH'5$0
NOTE2: 7KH RSHUDWLQJ WHPSHUDWXUH UDQJH LV WKH WHPSHUDWXUH ZKHUH DOO '5$0 VSHFLILFDWLRQ ZLOO EH VXSSRUWHG
2XWVLGHRIWKLVWHPSHUDWXUHUDQJHHYHQLILWLVVWLOOZLWKLQWKHOLPLWRIVWUHVVFRQGLWLRQVRPHGHYLDWLRQRQ
SRUWLRQ RI RSHUDWLQJ VSHFLILFDWLRQ PD\ EH UHTXLUHG'XULQJ RSHUDWLRQ WKH '5$0 FDVH WHPSHUDWXUH PXVW
EH PDLQWDLQHG EHWZHHQ & XQGHU DOO RWKHU VSHFLILFDWLRQ SDUDPHWHU 6XSSRUWLQJ & ZLWK IXOO
-('(&$& '&VSHFLILFDWLRQVDQGEHLQJDEOHWRH[WHQGWR&ZLWKGRXEOLQJDXWRUHIUHVKFRPPDQGV
LQIUHTXHQF\WRDPVSHULRG W5(), XV 6XSSRUWLQJKLJKHUWHPSHUDWXUH6HOI5HIUHVKHQWU\YLD
WKHFRQWURORI(065 ELW$
Table 17. Recommended DC Operating Conditions (SSTL_1.8)
Symbol
Parameter
Min.
Typ.
Max.
Unit Note
9''
3RZHUVXSSO\YROWDJH
9
9''/
3RZHUVXSSO\YROWDJHIRU'//
9
9''4
3RZHUVXSSO\YROWDJHIRU,2%XIIHU
9
95()
,QSXWUHIHUHQFHYROWDJH
[9''4
[9''4
[9''4
P9
977
7HUPLQDWLRQYROWDJH
95()
95()
95()
9
NOTE1:7KHUHLVQRVSHFLILFGHYLFH9''VXSSO\YROWDJHUHTXLUHPHQWIRU667/BFRPSOLDQFH+RZHYHUXQGHUDOO
FRQGLWLRQV9''4PXVWEHOHVVWKDQRUHTXDOWR9''
NOTE2:7KHYDOXHRI95()PD\EHVHOHFWHGE\WKHXVHUWRSURYLGHRSWLPXPQRLVHPDUJLQLQWKHV\VWHP7\SLFDOO\
WKH YDOXH RI 95() LV H[SHFWHG WR EH DERXW [ 9''4 RI WKH WUDQVPLWWLQJ GHYLFH DQG 95() LV H[SHFWHG WR
WUDFNYDULDWLRQVLQ9''4
NOTE3: 3HDNWRSHDNDFQRLVHRQ95()PD\QRWH[FHHG95() GF NOTE4:977RIWUDQVPLWWLQJGHYLFHPXVWWUDFN95()RIUHFHLYLQJGHYLFH
NOTE5: 9''4 WUDFNV ZLWK 9'' 9''/ WUDFNV ZLWK 9'' $& SDUDPHWHUV DUH PHDVXUHG ZLWK 9'' 9''4 DQG 9''/ WLHG
WRJHWKHU
Confidential
- 25/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
Table 18. Input logic level
Symbol
-25/3
Parameter
Unit Note
Min.
Max.
95()
9''4
9
95()
9
9,+ GF '&,QSXWORJLF+LJK9ROWDJH
9,/ GF '&,QSXW/RZ9ROWDJH
9,+ DF $&,QSXW+LJK9ROWDJH
95()
9
9,/ DF $&,QSXW/RZ9ROWDJH
96649SHDN
95()±
9
9,' DF $&'LIIHUHQWLDO9ROWDJH
9''4
9
9''49SHDN
[
[9''4
9
9''4
NOTE1:5HIHUWR2YHUVKRRWXQGHUVKRRWVSHFLILFDWLRQVIRU9SHDNYDOXHPD[LPXPSHDNDPSOLWXGHDOORZHGIRU
RYHUVKRRWDQGXQGHUVKRRW
9,; DF $&'LIIHUHQWLDOFURVVSRLQW9ROWDJH
Table 19. AC Input test conditions
Symbol
95() Parameter
Values
,QSXWUHIHUHQFHYROWDJH
96:,1* PD[ ,QSXWVLJQDOPD[LPXPSHDNWRSHDNVZLQJ
Unit Note
[9''4
9
9
6OHZ5DWH ,QSXWVLJQDOPLQLPXPVOHZUDWH
9QV NOTE1:,QSXWZDYHIRUPWLPLQJLVUHIHUHQFHGWRWKHLQSXWVLJQDOFURVVLQJWKURXJKWKH9 ,+,/ DF OHYHODSSOLHGWRWKH
GHYLFHXQGHUWHVW
NOTE2:7KHLQSXWVLJQDOPLQLPXPVOHZUDWHLVWREHPDLQWDLQHGRYHUWKHUDQJHIURP95()WR9,+ DF PLQIRUULVLQJ
HGJHVDQGWKHUDQJHIURP95()WR9,/ DF PD[IRUIDOOLQJHGJHV
NOTE3:$&WLPLQJVDUHUHIHUHQFHGZLWKLQSXWZDYHIRUPVVZLWFKLQJIURP9,/ DF WR9,+ DF RQWKHSRVLWLYH
WUDQVLWLRQVDQG9,+ DF WR9,/ DF RQWKHQHJDWLYHWUDQVLWLRQV
Table 20. Differential AC output parameters
Symbol
Values
Parameter
Min.
Unit Note
Max.
9R[ DF $&'LIIHUHQWLDO&URVV3RLQW9ROWDJH
[9''4
[9''4
9
NOTE1:7KHW\SLFDOYDOXHRI92; DF LVH[SHFWHGWREHDERXW[9''4RIWKHWUDQVPLWWLQJGHYLFHDQG92; DF LV
H[SHFWHGWRWUDFNYDULDWLRQVLQ9''492; DF LQGLFDWHVWKHYROWDJHDWZKLFKGLIIHUHQWLDORXWSXWVLJQDOVPXVW
FURVV
Table 21. AC overshoot/undershoot specification for address and control pins
(A0-A12, BA0-BA1, CS#, RAS#, CAS#, WE#, CKE, ODT)
Parameter
-25
-3
Unit
9
0D[LPXPSHDNDPSOLWXGHDOORZHGIRUXQGHUVKRRWDUHD
9
0D[LPXPRYHUVKRRWDUHDDERYH9''
9QV
0D[LPXPXQGHUVKRRWDUHDEHORZ966
9QV
0D[LPXPSHDNDPSOLWXGHDOORZHGIRURYHUVKRRWDUHD
Confidential
- 26/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
Table 22. AC overshoot/undershoot specification for clock, data, strobe, and mask pins
(DQ, UDQS, LDQS, UDQS#, LDQS#, DM, CK, CK#)
Parameter
-25
-3
Unit
0D[LPXPSHDNDPSOLWXGHDOORZHGIRURYHUVKRRWDUHD
9
0D[LPXPSHDNDPSOLWXGHDOORZHGIRUXQGHUVKRRWDUHD
9
0D[LPXPRYHUVKRRWDUHDDERYH9''
9QV
0D[LPXPXQGHUVKRRWDUHDEHORZ966
9QV
Table 23. Output AC test conditions
Symbol
Parameter
Values
9275
2XWSXWWLPLQJPHDVXUHPHQWUHIHUHQFHOHYHO
NOTE1:7KH9''4RIWKHGHYLFHXQGHUWHVWLVUHIHUHQFHG
Unit Note
[9''4
9
Table 24. Output DC current drive
Symbol
Parameter
Values
,2+ GF 2XWSXWPLQLPXPVRXUFH'&FXUUHQW
Unit Note
P$ ,2/ GF 2XWSXWPLQLPXPVLQN'&FXUUHQW
P$ NOTE1: 9''4 99287 P9 92879''4 ,2+PXVWEHOHVVWKDQȍIRUYDOXHVRI9287EHWZHHQ9''4
DQG9''4P9
NOTE2:9''4 99287 P99287,2/ PXVWEHOHVVWKDQȍIRUYDOXHVRI9287 EHWZHHQ9DQGP9
NOTE3:7KHGFYDOXHRI95()DSSOLHGWRWKHUHFHLYLQJGHYLFHLVVHWWR977
NOTE4:7KHYDOXHVRI,2+ GF DQG,2/ GF DUHEDVHGRQWKHFRQGLWLRQVJLYHQLQ1RWHVDQG7KH\DUHXVHGWRWHVW
GHYLFHGULYHFXUUHQWFDSDELOLW\WRHQVXUH9,+PLQSOXVDQRLVHPDUJLQDQG9,/PD[PLQXVDQRLVHPDUJLQ
DUHGHOLYHUHGWRDQ667/BUHFHLYHU7KHDFWXDOFXUUHQWYDOXHVDUHGHULYHGE\VKLIWLQJWKHGHVLUHGGULYHU
RSHUDWLQJSRLQW VHH-('(&VWDQGDUG6HFWLRQRI-(6'$ DORQJDȍORDGOLQHWRGHILQHD
FRQYHQLHQWGULYHUFXUUHQWIRUPHDVXUHPHQW
Table 25. Capacitance (VDD = 1.8V, f = 1MHz, TOPER = 25 ¡C)
Symbol
Values
Parameter
Min.
Max.
Unit
&,1
,QSXW&DSDFLWDQFHDOORWKHULQSXWRQO\SLQV
S)
&&.
,QSXW&DSDFLWDQFH &.&. S)
&,2
,QSXW2XWSXW&DSDFLWDQFH'0'4'46'46
S)
'&,1
'HOWD,QSXW&DSDFLWDQFH&RPPDQGDQG$GGUHVV
S)
'&&.
'HOWD,QSXW&DSDFLWDQFH&.&.
S)
'&,2
'HOWD,QSXW2XWSXW&DSDFLWDQFH'0'4'46'46
S)
NOTE:7KHVHSDUDPHWHUVDUHSHULRGLFDOO\VDPSOHGDQGDUHQRWWHVWHG
Confidential
- 27/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
Table 26. IDD specification parameters and test conditions (VDD = 1.8V ± 0.1V, TOPER = -40~95 ¡C)
Symbol
-25
Max.
-3
Max.
Unit
,''
P$
,''
P$
,''3
P$
,''4
P$
,''1
P$
P$
P$
,''1
P$
,'':
P$
Operating burst read current:
$OO EDQNV RSHQ FRQWLQXRXV EXUVW UHDGV ,287 P$ %/ &/ &/
PLQ $/ W&. W&. PLQ W5$6 W5$6 PD[ W53 W53 PLQ &.( LV ,''5
+,*+ &6 LV +,*+ EHWZHHQ YDOLG FRPPDQGV $GGUHVV EXV LQSXWV DUH
6:,7&+,1*'DWDEXVLQSXWVDUH6:,7&+,1*
P$
P$
P$
P$
Parameter & Test Condition
Operating one bank active-precharge current:
W&. W&. PLQ W5& W5& PLQ W5$6 W5$6 PLQ &.(LV+,*+&6LV
+,*+EHWZHHQYDOLGFRPPDQGV$GGUHVVEXVLQSXWVDUH6:,7&+,1*
'DWDEXVLQSXWVDUH6:,7&+,1*
Operating one bank active-read-precharge current:
,287 P$%/ &/ &/ PLQ $/ W&. W&. PLQ W5& W5& PLQ W5$6 W5$6 PLQ W5&' W5&' PLQ &.(LV+,*+&6LV+,*+EHWZHHQ
YDOLGFRPPDQGV$GGUHVVEXVLQSXWVDUHVZLWFKLQJ'DWDSDWWHUQLVVDPH
DV,'':
Precharge power-down current:
$OOEDQNVLGOHW&. W&. PLQ &.(LV/2:2WKHUFRQWURODQGDGGUHVVEXV
LQSXWVDUH67$%/('DWDEXVLQSXWVDUH)/2$7,1*
Precharge quiet standby current:
$OOEDQNVLGOHW&. W&. PLQ &.(LV+,*+&6LV+,*+2WKHUFRQWURO
DQGDGGUHVVEXVLQSXWVDUH67$%/('DWDEXVLQSXWVDUH)/2$7,1*
Precharge standby current:
$OOEDQNVLGOHW&. W&. PLQ &.(LV+,*+&6LV+,*+2WKHUFRQWURO
DQG DGGUHVV EXV LQSXWV DUH 6:,7&+,1* 'DWD EXV LQSXWV DUH
6:,7&+,1*
Active power-down current:
056 $ $OOEDQNVRSHQW&. W&. PLQ &.(LV/2:2WKHUFRQWURO
DQGDGGUHVVEXVLQSXWVDUH67$%/('DWDEXVLQSXWVDUH
056 $ )/2$7,1*
Active standby current:
$OOEDQNVRSHQW&. W&. PLQ W5$6 W5$6 PD[ W53 W53 PLQ &.(LV
+,*+&6LV+,*+EHWZHHQYDOLGFRPPDQGV2WKHUFRQWURODQGDGGUHVV
EXVLQSXWVDUH6:,7&+,1*'DWDEXVLQSXWVDUH6:,7&+,1*
Operating burst write current:
$OOEDQNVRSHQFRQWLQXRXVEXUVWZULWHV%/ &/ &/ PLQ $/ W&. W&. PLQ W5$6 W5$6 PD[ W53 W53 PLQ &.( LV +,*+ &6 LV
+,*+EHWZHHQYDOLGFRPPDQGV$GGUHVVEXVLQSXWVDUHVZLWFKLQJ'DWD
EXVLQSXWVDUHVZLWFKLQJ
,''3
Burst refresh current:
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Confidential
- 28/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
Table 27. Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 1.8V ± 0.1V, TOPER = -40~95 ¡C)
Symbol
W&.
-25
Parameter
&ORFNF\FOHWLPH
-3
Min.
Max.
Min.
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- 29/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
W$21'
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- 30/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
General notes, which may apply for all AC parameters:
NOTE 1: DDR2 SDRAM AC timing reference load
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D 2XWSXWVOHZUDWHIRUIDOOLQJDQGULVLQJHGJHVLVPHDVXUHGEHWZHHQ977P9DQG977P9IRUVLQJOH
HQGHGVLJQDOV)RUGLIIHUHQWLDOVLJQDOV HJ'46±'46 RXWSXWVOHZUDWHLVPHDVXUHGEHWZHHQ'46±
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PHDVXUHGIURP&.±&. P9WR&.&. P9 P9WRP9IRUIDOOLQJHGJHV F 9,'LVWKHPDJQLWXGHRIWKHGLIIHUHQFHEHWZHHQWKHLQSXWYROWDJHRQ&.DQGWKHLQSXWYROWDJHRQ&.RU
EHWZHHQ'46DQG'46IRUGLIIHUHQWLDOVWUREH
NOTE 3: DDR2 SDRAM output slew rate test load
2XWSXWVOHZUDWHLVFKDUDFWHUL]HGXQGHUWKHWHVWFRQGLWLRQVDVEHOORZ
Figure 6.1 Slew rate test load
9''4
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Confidential
- 31/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
NOTE 4: Differential data strobe
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Confidential
- 32/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
Specific notes for dedicated AC parameters
NOTE 1:8VHU FDQ FKRRVH ZKLFK DFWLYH SRZHU GRZQ H[LW WLPLQJ WR XVH YLD 056 ELW W;$5' LV H[SHFWHG WR EH
XVHGIRUIDVWDFWLYHSRZHUGRZQH[LWWLPLQJW;$5'6LVH[SHFWHGWREHXVHGIRUVORZDFWLYHSRZHUGRZQH[LW
WLPLQJZKHUHDORZHUSRZHUYDOXHLVGHILQHGE\HDFKYHQGRUGDWDVKHHW
NOTE 2: $/ $GGLWLYH/DWHQF\
NOTE 3:7KLVLVDPLQLPXPUHTXLUHPHQW0LQLPXPUHDGWRSUHFKDUJHWLPLQJLV$/%/SURYLGHGWKDWWKHW573DQG
W5$6 PLQ KDYHEHHQVDWLVILHG
NOTE 4:$PLQLPXPRIWZRFORFNV W&. LVUHTXLUHGLUUHVSHFWLYHRIRSHUDWLQJIUHTXHQF\
NOTE 5:7LPLQJVDUHVSHFLILHGZLWKFRPPDQGDGGUHVVLQSXWVOHZUDWHRI9QV
NOTE 6:7LPLQJVDUHVSHFLILHGZLWK'4V'0DQG'46¶V LQVLQJOHHQGHGPRGH LQSXWVOHZUDWHRI9QV
NOTE 7:7LPLQJV DUH VSHFLILHG ZLWK &.&. GLIIHUHQWLDO VOHZ UDWH RI 9QV 7LPLQJV DUH JXDUDQWHHG IRU '46
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Table 28. DDR2-667/800 tDS/tDH derating with differential data strobe
tDS,
tDH derating values for DDR2-667, DDR2-800 (All units in ÔpsÕ; the note applies to the entire table)
DQS,DQS# Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
DQ
Sle
w
Rate
V/ns
Confidential
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.8 V/ns
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
- 33/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
NOTE 9:W,6DQGW,+ LQSXWVHWXSDQGKROG GHUDWLQJ
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Table 29. Derating values for DDR2-667, DDR2-800
tIS and
Command/
Address Slew rate
(V/ns)
tIH Derating Values for DDR2-667, DDR2-800
CK,CK# Differential Slew Rate
2.0 V/ns
1.5 V/ns
1.0 V/ns
W,6
W,+
W,6
W,+
W,6
W,+
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SV
SV
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NOTE 11: 0,1 W&/ W&+ UHIHUV WR WKH VPDOOHU RI WKH DFWXDO FORFN /2: WLPH DQG WKH DFWXDO FORFN +,*+ WLPH DV
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NOTE 16: 2'7WXUQRQWLPHPLQLVZKHQWKHGHYLFHOHDYHVKLJKLPSHGDQFHDQG2'7UHVLVWDQFHEHJLQVWRWXUQRQ
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Confidential
- 34/66 -
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
NOTE 17: 2'7 WXUQ RII WLPH PLQ LV ZKHQ WKH GHYLFH VWDUWV WR WXUQ RII 2'7 UHVLVWDQFH 2'7 WXUQ RII WLPH PD[ LV
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NOTE 20: ,QSXWZDYHIRUPWLPLQJW'6ZLWKGLIIHUHQWLDOGDWDVWUREHHQDEOHG05>ELW@ LVUHIHUHQFHGIURPWKHLQSXW
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WKHPRGHUHJLVWHUVHW
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256M DDR2 -AS4C16M16D2
Table 30. Input clock jitter spec parameter
Parameter
Symbol
&ORFNSHULRGMLWWHU
W-,7 SHU -3
Min.
SV
SV
SV
SV
SV
SV
&XPXODWLYHHUURUDFURVVF\FOHV W(55 SHU SV
&XPXODWLYHHUURUDFURVVF\FOHV W(55 SHU &XPXODWLYH HUURU DFURVV Q F\FOHV
W(55 SHU Q LQFOXVLYH
&XPXODWLYH HUURU DFURVV Q F\FOHV
W(55 SHU Q LQFOXVLYH
SV
SV
SV
'XW\F\FOHMLWWHU
SV
W-,7 GXW\ Max.
Unit Note
Max.
&ORFN SHULRG MLWWHU GXULQJ '//
W-,7 SHUOFN ORFNLQJSHULRG
&\FOHWRF\FOHFORFNSHULRGMLWWHU W-,7 FF &\FOH WR F\FOH FORFN SHULRG MLWWHU
W-,7 FFOFN GXULQJ'//ORFNLQJSHULRG
&XPXODWLYHHUURUDFURVVF\FOHV W(55 SHU &XPXODWLYHHUURUDFURVVF\FOHV W(55 SHU Min.
-25
Definitions:
W&. DYJ W&. DYJ LVFDOFXODWHGDVWKHDYHUDJHFORFNSHULRGDFURVVDQ\FRQVHFXWLYHF\FOHZLQGRZ
!
"
N
W &. (avg ) = #' W &. $ 1
M
% j =
where N=200
&
W&+ DYJ DQGW&/ DYJ W&+ DYJ LVGHILQHGDVWKHDYHUDJH+,*+SXOVHZLGWKDVFDOFXODWHGDFURVVDQ\FRQVHFXWLYH+,*+SXOVHV
!
N
"
W &+ (avg ) = $( W &+ % (N # W &. (avg ))
M
& j =
where N=200
'
W&/ DYJ LVGHILQHGDVWKHDYHUDJH/2:SXOVHZLGWKDVFDOFXODWHGDFURVVDQ\FRQVHFXWLYH/2:SXOVHV
!
N
"
W &/ (avg ) = $( W &/ % (N # W &. (avg ))
& j =
M
where N=200
'
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ZKHUH
W-,7 &+ ^W&+LW&+ DYJ ZKHUHL WR`
W-,7 &/ ^W&/LW&/ DYJ ZKHUHL WR`
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W-,7 SHU GHILQHVWKHVLQJOHSHULRGMLWWHUZKHQWKH'//LVDOUHDG\ORFNHG
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256M DDR2 -AS4C16M16D2
W-,7
W-,7
W-,7
W-,7
W-,7
W-,7
FF W-,7 FFOFN FF LVGHILQHGDVWKHGLIIHUHQFHLQFORFNSHULRGEHWZHHQWZRFRQVHFXWLYHFORFNF\FOHV
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FF DQGW-,7 FFOFN DUHQRWJXDUDQWHHGWKURXJKILQDOSURGXFWLRQWHVWLQJ
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#
=
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(
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)
W (55
W &. M &( ! N $ W &. (avg )
' j =
(
)
!Q IRU W (55 ( per )
"
IRU W (55 ( per )
"Q "
Q IRU W (55 ( per )
where "#
IRU W (55 ( per )
"Q "
" $ Q $ IRU W (55 ( % per )
" $ Q $ IRU
W (55 ( % per )
&
NOTE 34: 7KHVH SDUDPHWHUV DUH VSHFLILHG SHU WKHLU DYHUDJH YDOXHV KRZHYHU LW LV XQGHUVWRRG WKDW WKH IROORZLQJ
UHODWLRQVKLS EHWZHHQ WKH DYHUDJH WLPLQJ DQG WKH DEVROXWH LQVWDQWDQHRXV WLPLQJ KROGV DW DOO WLPHV 0LQ
DQG PD[RI63(&YDOXHVDUHWREHXVHGIRUFDOFXODWLRQVLQWKHWDEOHEHORZ Table 31. Absolute clock period average values
Parameter
Symbol
Min.
Max.
Unit
W&.
W&. DYJ PLQW-,7 SHU PLQ W&. DYJ PD[W-,7 SHU PD[ SV
$EVROXWHFORFNSHULRG
DEV W&+
W&+ DYJ PLQ W&. DYJ PLQ W&+ DYJ PD[ W&. DYJ PD[ SV
$EVROXWHFORFN+,*+SXOVHZLGWK
DEV W-,7 GXW\ PLQ
W-,7 GXW\ PD[
W&/
W&/ DYJ PLQ W&. DYJ PLQ W&/ DYJ PD[ W&. DYJ PD[ SV
$EVROXWHFORFN/2:SXOVHZLGWK
DEV W-,7 GXW\ PLQ
W-,7 GXW\ PD[
NOTE 35: W+3LVWKHPLQLPXPRIWKHDEVROXWHKDOISHULRGRIWKHDFWXDOLQSXWFORFNW+3LVDQLQSXWSDUDPHWHUEXWQRW
DQLQSXWVSHFLILFDWLRQSDUDPHWHU,WLVXVHGLQFRQMXQFWLRQZLWKW4+6WRGHULYHWKH'5$0RXWSXWWLPLQJW4+
7KHYDOXHWREHXVHGIRUW4+FDOFXODWLRQLVGHWHUPLQHGE\WKHIROORZLQJHTXDWLRQ
W+3 0LQ W&+ DEV W&/ DEV ZKHUH
W&+ DEV LVWKHPLQLPXPRIWKHDFWXDOLQVWDQWDQHRXVFORFN+,*+WLPH
W&/ DEV LVWKHPLQLPXPRIWKHDFWXDOLQVWDQWDQHRXVFORFN/2:WLPH
NOTE 36: W4+6DFFRXQWVIRU
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QH[WWUDQVLWLRQERWKRIZKLFKDUHLQGHSHQGHQWRIHDFKRWKHUGXHWRGDWDSLQVNHZRXWSXWSDWWHUQ
HIIHFWVDQGSFKDQQHOWRQFKDQQHOYDULDWLRQRIWKHRXWSXWGULYHUV
NOTE 37: W4+ W+3±W4+6ZKHUHW+3LVWKHPLQLPXPRIWKHDEVROXWHKDOISHULRGRIWKHDFWXDOLQSXWFORFNDQGW4+6LV
WKHVSHFLILFDWLRQYDOXHXQGHUWKHPD[FROXPQ^7KHOHVVKDOISXOVHZLGWKGLVWRUWLRQSUHVHQWWKHODUJHUWKH
W4+YDOXHLVDQGWKHODUJHUWKHYDOLGGDWDH\HZLOOEH`
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256M DDR2 -AS4C16M16D2
NOTE 39: :KHQ WKH GHYLFH LV RSHUDWHG ZLWK LQSXW FORFN MLWWHU WKLV SDUDPHWHU QHHGV WR EH GHUDWHG E\ WKH DFWXDO
W-,7 SHU RIWKHLQSXWFORFN RXWSXWGHUDWLQJVDUHUHODWLYHWRWKH6'5$0LQSXWFORFN NOTE 40: :KHQ WKH GHYLFH LV RSHUDWHG ZLWK LQSXW FORFN MLWWHU WKLV SDUDPHWHU QHHGV WR EH GHUDWHG E\ WKH DFWXDO
W-,7 GXW\ RIWKHLQSXWFORFN RXWSXWGHUDWLQJVDUHUHODWLYHWRWKH6'5$0LQSXWFORFN NOTE 41: :KHQ WKH GHYLFH LV RSHUDWHG ZLWK LQSXW FORFN MLWWHU WKLV SDUDPHWHU QHHGV WR EH GHUDWHG E\ ^ W-,7 GXW\ PD[ W(55 SHU PD[ ` DQG ^ W-,7 GXW\ PLQ W(55 SHU PLQ ` RI WKH DFWXDO LQSXW FORFN
RXWSXWGHUDWLQJVDUHUHODWLYHWRWKH6'5$0LQSXWFORFN NOTE 42: )RUW$2)'RI''5WKHFORFNRIW&.LQWKH[W&.DVVXPHVDW&+ DYJ DYHUDJHLQSXWFORFN
+,*+SXOVHZLGWKRIUHODWLYHWRW&. DYJ W$2)PLQDQGW$2)PD[VKRXOGHDFKEHGHUDWHGE\WKHVDPH
DPRXQWDVWKHDFWXDODPRXQWRIW&+ DYJ RIIVHWSUHVHQWDWWKH'5$0LQSXWZLWKUHVSHFWWR
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256M DDR2 -AS4C16M16D2
Timing Waveforms
Figure 7. Initialization sequence after power-up
W&+ W&/
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NOTE 1: To guarantee ODT off, VREF must be valid and a LOW level must be applied to the ODT pin.
Figure 8. OCD drive mode
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W2,7
NOTE : Drive mode, both Drive(1) and Drive(0), is used for controllers to measure DDR2 SDRAM Driver
impedance.In this mode, all outputs are driven out tOIT after "enter drive mode" command and all output
drivers are turned-off tOIT after "OCD calibration mode exit" command.
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256M DDR2 -AS4C16M16D2
Figure 9. OCD adjust mode
2&'FDOLEUDWLRQPRGHH[LW
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123
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9,+ DF
'4BLQ
123
9,+ GF
'7
'7
'7
'7
9,/ GF
'0
NOTE 1: For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1tCK and tDS /tDH should be met as shown in the figure.
NOTE 2: For input data pattern for adjustment, DT0-DT3 is a fixed order and is not affected by burst type
(i.e., sequential or interleave)
Figure 10. ODT update delay timing-tMOD
&0'
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123
123
123
123
123
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2'7
W,6
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NOTE 1: To prevent any impedance glitch on the channel, the following conditions must be met:
- tAOFD must be met before issuing the EMRS command.
- ODT must remain LOW for the entire duration of tMOD window, until tMOD, max is met.
then the ODT is ready for normal operation with the new setting, and the ODT signal may be raised again to turned
on the ODT.
NOTE 2: EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal).
NOTE 3: "setting" in this diagram is the Register and I/O setting, not what is measured from outside.
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256M DDR2 -AS4C16M16D2
Figure 11. ODT update delay timing-tMOD, as measured from outside
&.
&.
&0'
(056
123
123
2'7
123
123
W,6
W$2)'
5WW
123
W$21'
W02'PD[
1HZVHWWLQJ
2OGVHWWLQJ
NOTE 1: EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal).
NOTE 2: "setting" in this diagram is measured from outside.
Figure 12. ODT timing for active standby mode
7
7
7
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7
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7
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Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
Figure 13. ODT timing for power-down mode
7
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W,6
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W,6
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Figure 14. ODT timing mode switch at entering power-down mode
7
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Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
Figure 15. ODT timing mode switch at exit power-down mode
7
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Figure 16. Bank activate command cycle ( tRCD=3, AL=2, tRP=3, tRRD=2, tCCD=2)
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256M DDR2 -AS4C16M16D2
Figure 17.1. Posted CAS# operation: AL=2
Read followed by a write to the same bank
&.
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Figure 17.2. Posted CAS# operation: AL=0
Read followed by a write to the same bank
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256M DDR2 -AS4C16M16D2
Figure 18. Data output (read) timing
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Figure 19.1. Burst read operation: RL=5 (AL=2, CL=3, BL=4)
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Figure 19.2. Burst read operation: RL=3 (AL=0 and CL=3, BL=8)
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Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
Figure 20. Burst read followed by burst write: RL=5, WL= (RL-1) =4, BL=4
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NOTE : The minimum time from the burst read command to the burst write command is defined by a read-to-writeturn-around-time, which is 4 clocks in case of BL = 4 operation, 6 clocks in case of BL = 8 operation.
Figure 21. Seamless burst read operation: RL=5, AL=2, CL=3, BL=4
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NOTE : The seamless burst read operation is supported by enabling a read command at every other clock for BL =
4 operation, and every 4 clock for BL =8 operation. This operation is allowed regardless of same or different banks
as long as the banks are activated.
Confidential
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256M DDR2 -AS4C16M16D2
Figure 22. Read burst interrupt timing: (CL=3, AL=0, RL=3, BL=8)
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NOTE 1: Read burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
NOTE 2: Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write
command or Precharge command is prohibited.
NOTE 3: Read burst interrupt must occur exactly two clocks after previous Read command. Any other Read burst
interrupt timings are prohibited.
NOTE 4: Read burst interruption is allowed to any bank inside DRAM.
NOTE 5: Read burst with Auto Precharge enabled is not allowed to interrupt.
NOTE 6: Read burst interruption is allowed by another Read with Auto Precharge command.
NOTE 7: All command timings are referenced to burst length set in the mode register. They are not referenced to
actual burst. For example, Minimum Read to Precharge timing is AL+BL/2 where BL is the burst length set in the
mode register and not the actual burst (which is shorter because of interrupt).
Figure 23. Data input (write) timing
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Figure 24.1. Burst write operation: RL=5 (AL=2, CL=3), WL=4, BL=4
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Figure 25. Burst write followed by burst read:
RL=5 (AL=2, CL=3, WL=4, tWTR=2, BL=4)
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NOTE : The minimum number of clock from the burst write command to the burst read command is [CL-1 + BL/2 + tWTR].
This tWTR is not a write recovery time (tWR) but the time required to transfer the 4 bit write data from the input buffer into
sense amplifiers in the array. tWTR is defined in the timing parameter table of this standard.
Figure 26. Seamless burst write operation RL=5, WL=4, BL=4
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BL= 4 operation, every four clocks for BL = 8 operation. This operation is allowed regardless of same or
different banks as long as the banks are activated.
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256M DDR2 -AS4C16M16D2
Figure 27. Write burst interrupt timing: (CL=3, AL=0, RL=3, WL=2, BL=8)
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NOTE 1: Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
NOTE 2: Write burst of 8 can only be interrupted by another Write command. Write burst interruption by Read command or
Precharge command is prohibited.
NOTE 3: Write burst interrupt must occur exactly two clocks after previous Write command. Any other Write burst interrupt
timings are prohibited.
NOTE 4: Write burst interruption is allowed to any bank inside DRAM.
NOTE 5: Write burst with Auto Precharge enabled is not allowed to interrupt.
NOTE 6: Write burst interruption is allowed by another Write with Auto Precharge command.
NOTE 7: All command timings are referenced to burst length set in the mode register. They are not referenced to actual
burst. For example, minimum Write to Precharge timing is WL + BL/2 + tWR where tWR starts with the rising clock after the
uninterrupted burst end and not from the end of actual burst end.
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256M DDR2 -AS4C16M16D2
Figure 28. Write data mask
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Rev.1.0
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Figure 29.1. Burst read operation followed by precharge:
(RL=4, AL=1, CL=3, BL=4, tRTP 2 clocks)
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Figure 29.3. Burst read operation followed by precharge:
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Figure 29.5. Burst read operation followed by precharge:
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Figure 30.1. Burst write operation followed by precharge: WL= (RL-1) =3
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Figure 30.2. Burst write followed by precharge: WL= (RL-1) =4
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Figure 31.2. Burst read operation with auto precharge:
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bank (tRC Limit): RL=5(AL=2, CL=3, internal tRCD=3, BL=4,tRTP2 clocks)
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Figure 31.4. Burst read operation with auto precharge followed by an activation to the same
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Figure 32.2. Burst write with auto-precharge (WR+tRP): WL=4, WR=2, BL=4, tRP=3
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Figure 34. Self refresh operation
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Figure 35. Basic power down entry and exit timing diagram
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Figure 36.2.CKE intensive environment
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Figure 37. Read to power-down entry
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Figure 38. Read with autoprecharge to power-down entry
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Figure 40. Write with autoprecharge to power-down entry
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Figure 42. Active command to power-down entry
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256M DDR2 -AS4C16M16D2
Figure 45. Asynchronous CKE LOW event
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Figure 46. Clock frequency change in precharge power down mode
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Confidential
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- 64/66 -
W,+
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Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
Figure 47. 84-Ball TFBGA Package Outline Drawing Information
PIN A1 INDEX
Top View
Bottom View
Side View
DETAIL : "A"
Symbol
$
$
'
(
'
(
)
H
E
Confidential
Dimension in inch
Min
Nom
Max
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Dimension in mm
Min
Nom
Max
Rev.1.0
May 2015
256M DDR2 -AS4C16M16D2
PART NUMBERING SYSTEM
AS4C
DRAM
6MD
6M=6Mx
D=''5
B
=00MHz
B = FBGA
C/I
C=Commercial
(0¡ C5¡ C)
I=Industrial
(-40¡ C95¡ C)
N
Indicates Pb and
Halogen Free
Alliance Memory, Inc.
511 Taylor Way,
San Carlos, CA 94070
Tel: 650-610-6800
Fax: 650-620-9211
www.alliancememory.com
Copyright © Alliance Memory
All Rights Reserved
© Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time
without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right
to change or correct this data at any time, without notice. If the product described herein is under development,
significant changes to these specifications are possible. The information in this product data sheet is intended to be
general descriptive information for potential customers and users, and is not intended to operate as, or provide, any
guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of
the application or use of any product described herein, and disclaims any express or implied warranties related to the
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merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms
and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively
according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a
license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of
Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting
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Confidential
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Rev.1.0
May 2015