NSC COP888CL-XXX/N General description Datasheet

COP688CL/COP684CL, COP888CL/COP884CL,
COP988CL/COP984CL 8-Bit Microcontroller
Y
General Description
The COP888 family of microcontrollers uses an 8-bit single
chip core architecture fabricated with National Semiconductor’s M2CMOSTM process technology. The COP888CL is a
member of this expandable 8-bit core processor family of
microcontrollers.
(Continued)
Y
Y
Y
Y
Two 16-bit timers, each with two 16-bit registers
supporting:
Ð Processor Independent PWM mode
Ð External Event counter mode
Ð Input Capture mode
4 kbytes of on-chip ROM
128 bytes of on-chip RAM
Additional Peripheral Features
Y
Y
Y
Y
Idle Timer
Multi-input Wake Up (MIWU) with optional interrupts (8)
WATCHDOGTM and Clock Monitor logic
MICROWIRE/PLUSTM serial I/O
I/O Features
Y
Y
Y
Y
CPU/Instruction Set Feature
Y
Key Features
Y
Y
Y
1 ms instruction cycle time
Ten multi-source vectored interrupts servicing
Ð External Interrupt with selectable edge
Ð Idle Timer T0
Ð Timers (Each with 2 interrupts)
Ð MICROWIRE/PLUS
Ð Multi-Input Wake Up
Ð Software Trap
Ð Default VIS (default interrupt)
Versatile and easy to use instruction set
8-bit Stack Pointer (SP)Ðstack in RAM
Two 8-bit Register Indirect Data Memory Pointers (B, X)
Fully Static CMOS
Y
Y
Memory mapped I/O
Software selectable I/O options (TRI-STATEÉ Output,
Push-Pull Output, Weak Pull-Up Input, High Impedance
Input)
High current outputs
Schmitt trigger inputs on port G
Packages:
Ð 44 PLCC with 40 I/O pins
Ð 40 DIP with 36 I/O pins
Ð 28 DIP with 24 I/O pins
Ð 28 SO with 24 I/O pins
Y
Low current drain (typically k 1 mA)
Single supply operation: 2.5V to 6.0V
Temperature ranges: 0§ C to a 70§ C, b40§ C to a 85§ C,
b 55§ C to a 125§ C
Development Support
Y
Y
Emulation and OTP devices
Real time emulation and full program debug offered by
MetaLink Development System
Block Diagram
TL/DD/9766 – 1
FIGURE 1. Block Diagram
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
MICROWIRE/PLUSTM , M2CMOSTM , COPSTM microcontrollers, WATCHDOGTM and MICROWIRETM are trademarks of National Semiconductor Corporation.
iceMASTERTM is a trademark of MetaLink Corporation.
C1996 National Semiconductor Corporation
TL/DD/9766
RRD-B30M96/Printed in U. S. A.
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COP688CL/COP684CL, COP888CL/COP884CL,
COP988CL/COP984CL 8-Bit Microcontroller
September 1996
General Description (Continued)
sourced wakeup/interrupt capability. This multi-sourced interrupt capability may also be used independent of the
HALT or IDLE modes. Each I/O pin has software selectable
configurations. The device operates over a voltage range of
2.5V to 6V. High throughput is achieved with an efficient,
regular instruction set operating at a maximum of 1 ms per
instruction rate.
It is a fully static part, fabricated using double-metal silicon
gate microCMOS technology. Features include an 8-bit
memory mapped architecture, MICROWIRE/PLUS serial
I/O, two 16-bit timer/counters supporting three modes
(Processor Independent PWM generation, External Event
counter, and Input Capture mode capabilities), and two power savings modes (HALT and IDLE), both with a multi-
Connection Diagrams
Dual-In-Line Package
Plastic Chip Carrier
TL/DD/9766–2
Top View
Order Number COP688CL-XXX/V, COP888CL-XXX/V,
COP988CL-XXX/V or COP988CLH-XXX/V
See NS Plastic Chip Package Number V44A
TL/DD/9766 – 4
Top View
Order Number COP688CL-XXX/N, COP888CL-XXX/N,
COP988CL-XXX/N or COP988CLH-XXX/N
See NS Molded Package Number N40A
Dual-In-Line Package
Order Number COP688CL-XXX/N, COP884CL-XXX/N,
COP984CL-XXX/N or COP984CLH-XXX/N
See NS Molded Package Number N28B
Order Number COP684CL-XXX/WM,
COP884CL-XXX/WM, COP984CL-XXX/WM,
or COP984CLHXXX/WM
See NS Surface Mount Package Number M28B
TL/DD/9766–5
Top View
FIGURE 2. Connection Diagrams
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2
Connection Diagrams (Continued)
Pinouts for 28-, 40- and 44-Pin Packages
Port
Type
Alt. Fun
Alt. Fun
28-Pin
Pack.
40-Pin
Pack.
44-Pin
Pack.
11
12
13
14
15
16
17
18
17
18
19
20
21
22
23
24
17
18
19
20
25
26
27
28
25
26
27
28
1
2
3
4
35
36
37
38
3
4
5
6
39
40
41
42
3
4
5
6
L0
L1
L2
L3
L4
L5
L6
L7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
G0
G1
G2
G3
G4
G5
G6
G7
I/O
WDOUT
I/O
I/O
I/O
I/O
I
I/CKO
INT
D0
D1
D2
D3
O
O
O
O
19
20
21
22
25
26
27
28
29
30
31
32
I0
I1
I2
I3
I
I
I
I
7
8
9
10
11
12
9
10
11
12
I4
I5
I6
I7
I
I
I
I
9
10
13
14
13
14
15
16
D4
D5
D6
D7
O
O
O
O
29
30
31
32
33
34
35
36
C0
C1
C2
C3
C4
C5
C6
C7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
39
40
1
2
43
44
1
2
21
22
23
24
T2A
T2B
T1B
T1A
SO
SK
SI
HALT
RESTART
Unused*
Unused*
VCC
GND
CKI
RESET
6
23
5
24
16
15
8
33
7
34
8
37
7
38
* e On the 40-pin package Pins 15 and 16 must be connected to GND.
3
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Absolute Maximum Ratings
Total Current out of GND Pin (Sink)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
Voltage at Any Pin
Total Current into VCC Pin (Source)
110 mA
Storage Temperature Range
b 65§ C to a 140§ C
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
7V
b 0.3V to VCC a 0.3V
100 mA
DC Electrical Characteristics COP98XCL: 0§ C s TA s a 70§ C unless otherwise specified
Parameter
Conditions
Operating Voltage
COP98XCL
COP98XCLH
Peak-to-Peak
Supply Current (Note 2)
CKI e 10 MHz
CKI e 4 MHz
VCC e 6V, tc e 1 ms
VCC e 4V, tc e 2.5 ms
IDLE Current
CKI e 10 MHz
Max
Units
4.0
6.0
V
V
0.1 VCC
V
12.5
2.5
mA
mA
8
5
mA
mA
3.5
mA
0.2 VCC
V
V
0.2 VCC
V
V
0.2 VCC
V
V
b1
a1
mA
b 40
b 250
mA
0.35 VCC
V
VCC e 6V, CKI e 0 MHz
VCC e 4V, CKI e 0 MHz
k 0.7
k 0.4
VCC e 6V, tc e 1 ms
Input Levels
RESET
Logic High
Logic Low
CKI (External and Crystal Osc. Modes)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
0.8 VCC
0.7 VCC
0.7 VCC
Hi-Z Input Leakage
VCC e 6V
Input Pullup Current
VCC e 6V, VIN e 0V
G and L Port Input Hysteresis
Output Current Levels
D Outputs
Source
Sink
All Others
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
Typ
2.5
4.0
Power Supply Ripple (Note 1)
HALT Current (Note 3)
Min
VCC
VCC
VCC
VCC
e
e
e
e
4V, VOH e 3.3V
2.5V, VOH e 1.8V
4V, VOL e 1V
2.5V, VOL e 0.4V
b 0.4
b 0.2
VCC
VCC
VCC
VCC
VCC
VCC
e
e
e
e
e
e
4V, VOH e 2.7V
2.5V, VOH e 1.8V
4V, VOH e 3.3V
2.5V, VOH e 1.8V
4V, VOL e 0.4V
2.5V, VOL e 0.4V
b 10
b 2.5
b 0.4
b 0.2
mA
mA
mA
mA
10
2.0
b 100
b 33
1.6
0.7
mA
mA
mA
mA
mA
mA
Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L and G0–G5 configured as
outputs and set high. The D port set to zero. The clock monitor is disabled.
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4
DC Electrical Characteristics 0§ C s TA s a 70§ C unless otherwise specified (Continued)
Parameter
TRI-STATE Leakage
Conditions
Min
VCC e 6.0V
Typ
b1
Allowable Sink/Source
Current per Pin
D Outputs (Sink)
All others
Maximum Input Current
without Latchup (Note 4)
TA e 25§ C
RAM Retention Voltage, Vr
500 ns Rise
and Fall Time (Min)
Max
Units
a1
mA
15
3
mA
mA
g 100
mA
2
V
Input Capacitance
Load Capacitance on D2
7
pF
1000
pF
AC Electrical Characteristics 0§ C s TA s a 70§ C unless otherwise specified
Parameter
Instruction Cycle Time (tc)
Crystal or Resonator
R/C Oscillator
Inputs
tSETUP
tHOLD
Output Propagation Delay (Note 5)
tPD1, tPD0
SO, SK
All Others
Conditions
Min
4V s VCC s 6V
2.5V s VCC k 4V
4V s VCC s 6V
2.5V s VCC k 4V
1
2.5
3
7.5
4V s VCC s 6V
2.5V s VCC k 4V
4V s VCC s 6V
2.5V s VCC k 4V
200
500
60
150
Typ
Max
Units
DC
DC
DC
DC
ms
ms
ms
ms
ns
ns
ns
ns
RL e 2.2k, CL e 100 pF
4V s VCC s 6V
2.5V s VCC k 4V
4V s VCC s 6V
2.5V s VCC k 4V
MICROWIRETM Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Propagation Delay (tUPD)
0.7
1.75
1
2.5
ms
ms
ms
ms
220
ns
ns
ns
20
56
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
1
1
1
1
tc
tc
tc
tc
Reset Pulse Width
1
ms
Note 4: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will
have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective
resistance to VCC is 750X (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 5: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
5
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Absolute Maximum Ratings
Total Current out of GND Pin (Sink)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
Voltage at Any Pin
Total Current into VCC Pin (Source)
Storage Temperature Range
110 mA
b 65§ C to a 140§ C
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
7V
b 0.3V to VCC a 0.3V
100 mA
DC Electrical Characteristics COP88XCL: b40§ C s TA s a 85§ C unless otherwise specified
Parameter
Conditions
Operating Voltage
Min
Power Supply Ripple (Note 1)
Peak-to-Peak
Supply Current (Note 2)
CKI e 10 MHz
CKI e 4 MHz
VCC e 6V, tc e 1 ms
VCC e 4V, tc e 2.5 ms
HALT Current (Note 3)
VCC e 6V, CKI e 0 MHz
IDLE Current
CKI e 10 MHz
VCC e 6V, tc e 1 ms
Input Levels
RESET
Logic High
Logic Low
CKI (External and Crystal Osc. Modes)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
V
0.1 VCC
V
12.5
2.5
mA
mA
10
mA
3.5
mA
0.2 VCC
V
V
0.2 VCC
V
V
0.2 VCC
V
V
b1
a1
mA
b 40
b 250
mA
0.35 VCC
V
k1
0.7 VCC
VCC e 6V
VCC e 6V, VIN e 0V
G and L Port Input Hysteresis
All Others
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage
VCC
VCC
VCC
VCC
e
e
e
e
4V, VOH e 3.3V
2.5V, VOH e 1.8V
4V, VOL e 1V
2.5V, VOL e 0.4V
b 0.4
b 0.2
VCC
VCC
VCC
VCC
VCC
VCC
e
e
e
e
e
e
4V, VOH e 2.7V
2.5V, VOH e 1.8V
4V, VOH e 3.3V
2.5V, VOH e 1.8V
4V, VOL e 0.4V
2.5V, VOL e 0.4V
b 10
b 2.5
b 0.4
b 0.2
VCC e 6.0V
Units
6
0.7 VCC
Input Pullup Current
Sink
Max
0.8 VCC
Hi-Z Input Leakage
Output Current Levels
D Outputs
Source
Typ
2.5
mA
mA
mA
mA
10
2.0
b 100
b 33
mA
mA
mA
mA
mA
mA
a2
mA
1.6
0.7
b2
Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L and G0–G5 configured as
outputs and set high. The D port set to zero. The clock monitor is disabled.
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6
DC Electrical Characteristics b40§ C s TA s a 85§ C unless otherwise specified (Continued)
Parameter
Conditions
Min
Typ
Allowable Sink/Source
Current per Pin
D Outputs (Sink)
All others
Maximum Input Current
without Latchup (Note 4)
TA e 25§ C
RAM Retention Voltage, Vr
500 ns Rise
and Fall Time (Min)
Max
Units
15
3
mA
mA
g 100
mA
2
V
Input Capacitance
Load Capacitance on D2
7
pF
1000
pF
AC Electrical Characteristics b40§ C s TA s a 85§ C unless otherwise specified
Parameter
Instruction Cycle Time (tc)
Crystal or Resonator
R/C Oscillator
Inputs
tSETUP
tHOLD
Output Propagation Delay (Note 5)
tPD1, tPD0
SO, SK
All Others
Conditions
Min
4V s VCC s 6V
2.5V s VCC k 4V
4V s VCC s 6V
2.5V s VCC k 4V
1
2.5
3
7.5
4V s VCC s 6V
2.5V s VCC k 4V
4V s VCC s 6V
2.5V s VCC k 4V
200
500
60
150
Typ
Max
Units
DC
DC
DC
DC
ms
ms
ms
ms
ns
ns
ns
ns
RL e 2.2k, CL e 100 pF
4V s VCC s 6V
2.5V s VCC k 4V
4V s VCC s 6V
2.5V s VCC k 4V
MICROWIRE Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Propagation Delay (tUPD)
0.7
1.75
1
2.5
ms
ms
ms
ms
220
ns
ns
ns
20
56
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
1
1
1
1
tc
tc
tc
tc
Reset Pulse Width
1
ms
Note 4: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will
have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective
resistance to VCC is 750X (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 5: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
7
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Electrical Specifications
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
DC ELECTRICAL SPECIFICATIONS
COP688CL Absolute Specifications
Supply Voltage (VCC)
Voltage at Any Pin
Total Current into VCC Pin (Source)
Total Current out of GND Pin (Sink)
Storage Temperature Range
7V
b 0.3V to VCC a 0.3V
90 mA
100 mA
b 65§ C to a 150§ C
DC Electrical Characteristics COP68XCL: b55§ C s TA s a 125§ C unless otherwise specified
Parameter
Conditions
Operating Voltage
Min
Power Supply Ripple (Note 1)
Peak-to-Peak
Supply Current (Note 2)
CKI e 10 MHz
CKI e 4 MHz
VCC e 5.5V, tc e 1 ms
VCC e 5.5V, tc e 2.5 ms
HALT Current (Note 3)
VCC e 5.5V, CKI e 0 MHz
IDLE Current
CKI e 10 MHz
CKI e 4 MHz
VCC e 5.5V, tc e 1 ms
VCC e 5.5V, tc e 2.5 ms
Input Levels
RESET
Logic High
Logic Low
CKI (External and Crystal Osc. Modes)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Max
V
0.1 VCC
V
12.5
5.5
mA
mA
30
mA
3.5
2.5
mA
mA
0.2 VCC
V
V
0.2 VCC
V
V
0.2 VCC
V
V
k 10
0.7 VCC
0.7 VCC
VCC e 5.5V
Input Pullup Current
VCC e 5.5V, VIN e 0V
b5
a5
mA
b 35
b 400
mA
0.35 VCC
V
G and L Port Input Hysteresis
VCC e 4.5V, VOH e 3.8V
VCC e 4.5V, VOL e 1.0V
b 0.4
VCC
VCC
VCC
VCC
b 9.0
b 0.4
e
e
e
e
4.5V, VOH e 3.8V
4.5V, VOH e 3.8V
4.5V, VOL e 0.4V
5.5V
Units
5.5
0.8 VCC
Hi-Z Input Leakage
Output Current Levels
D Outputs
Source
Sink
All Others
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage
Typ
4.5
mA
mA
9
b 140
1.4
b 5.0
a 5.0
mA
mA
mA
mA
Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L and G0–G5 configured as
outputs and set high. The D port set to zero. The clock monitor is disabled.
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8
DC Electrical Characteristics b55§ C s TA s a 25§ C unless otherwise specified (Continued)
Parameter
Conditions
Min
Typ
Allowable Sink/Source
Current per Pin
D Outputs (Sink)
All others
Maximum Input Current
without Latchup (Note 4)
RAM Retention Voltage, Vr
500 ns Rise
and Fall Time (Min)
Max
Units
12
2.5
mA
mA
150
mA
2.0
V
Input Capacitance
Load Capacitance on D2
7
pF
1000
pF
Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L and G ports in the TRISTATE mode and tied to ground, all outputs low and tied to ground. The Clock Monitor and the comparators are disabled.
AC Specifications for COP688CL
AC Electrical Characteristics b55§ C s TA s a 125§ C unless otherwise specified
Parameter
Conditions
Min
Max
Units
1
DC
ms
3
DC
ms
Instruction Cycle Time (tc)
Crystal, Resonator, or
External Oscillator
R/C Oscillator (div-by 10)
VCC t 4.5V
VCC t 4.5V
Inputs
tSETUP
tHOLD
VCC t 4.5V
VCC t 4.5V
200
60
Output Propagation Delay (Note 5)
tPD1, tPD0
SO, SK
All Others
Typ
ns
ns
RL e 2.2k, CL e 100 pF
VCC t 4.5V
VCC t 4.5V
MICROWIRE Setup Time (tUWS)
MICROWIRE Hold Time(tUWH)
MICROWIRE Output Propagation Delay (tUPD)
0.7
1
ms
ms
220
ns
ns
ns
20
56
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
1
1
1
1
tc
tc
tc
tc
Reset Pulse Width
1
ms
Note 4: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will
have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective
resistance to VCC is 750X (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 5: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
9
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Typical Performance Characteristics (b40§ C s TA s a 85§ C)
HaltÐIDD
IdleÐIDD (Crystal Clock Option)
TL/DD/9766–27
TL/DD/9766 – 28
DynamicÐIDD vs VCC
(Crystal Clock Option)
Port L/C/G Weak Pull-Up
Source Current
TL/DD/9766–29
TL/DD/9766 – 30
Port L/C/G Push-Pull Source Current
Port L/C/G Push-Pull Sink Current
TL/DD/9766–31
TL/DD/9766 – 32
Port D Source Current
Port D Sink Current
TL/DD/9766–33
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TL/DD/9766 – 34
10
AC Electrical Characteristics
PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers
on the inputs.
(Continued)
Port L supports Multi-Input Wakeup (MIWU) on all eight
pins. L4 and L5 are used for the timer input functions T2A
and T2B.
Port L has the following alternate features:
L0
MIWU
L1
MIWU
L2
MIWU
L3
MIWU
L4
MIWU or T2A
L5
MIWU or T2B
L6
MIWU
L7
MIWU
Port G is an 8-bit port with 5 I/O pins (G0, G2 – G5), an input
pin (G6), and two dedicated output pins (G1 and G7). Pins
G0 and G2 – G6 all have Schmitt Triggers on their inputs. Pin
G1 serves as the dedicated WDOUT WATCHDOG output,
while pin G7 is either input or output depending on the oscillator mask option selected. With the crystal oscillator option
selected, G7 serves as the dedicated output pin for the CKO
clock output. With the single-pin R/C oscillator mask option
selected, G7 serves as a general purpose input pin, but is
also used to bring the device out of HALT mode with a low
to high transition. There are two registers associated with
the G Port, a data register and a configuration register.
Therefore, each of the 5 I/O bits (G0, G2 – G5) can be individually configured under software control.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin or general purpose input (R/C clock configuration), the associated bits in the data and configuration
registers for G6 and G7 are used for special purpose functions as outlined below. Reading the G6 and G7 data bits
will return zeros.
Note that the chip will be placed in the HALT mode by writing a ‘‘1’’ to bit 7 of the Port G Data Register. Similarly the
chip will be placed in the IDLE mode by writing a ‘‘1’’ to bit 6
of the Port G Data Register.
Writing a ‘‘1’’ to bit 6 of the Port G Configuration Register
enables the MICROWIRE/PLUS to operate with the alternate phase of the SK clock. The G7 configuration bit, if set
high, enables the clock start up delay after HALT when the
R/C clock configuration is used.
TL/DD/9766 – 26
FIGURE 2. MICROWIRE/PLUS Timing
Pin Descriptions
VCC and GND are the power supply pins.
CKI is the clock input. This can come from an R/C generated oscillator, or a crystal oscillator (in conjunction with
CKO). See Oscillator Description section.
RESET is the master reset input. See Reset Description
section.
The device contains three bidirectional 8-bit I/O ports (C, G
and L), where each individual bit may be independently configured as an input (Schmitt trigger inputs on ports G and L),
output or TRI-STATE under program control. Three data
memory address locations are allocated for each of these I/
O ports. Each I/O port has two associated 8-bit memory
mapped registers, the CONFIGURATION register and the
output DATA register. A memory mapped address is also
reserved for the input pins of each I/O port. (See the memory map for the various addresses associated with the I/O
ports.) Figure 3 shows the I/O port configurations. The
DATA and CONFIGURATION registers allow for each port
bit to be individually configured under software control as
shown below:
CONFIGURATION
Register
DATA
Register
0
0
0
1
1
1
0
1
Port Set-Up
Hi-Z Input
(TRI-STATE Output)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output
Config Reg.
Data Reg.
G7
CLKDLY
HALT
G6
Alternate SK
IDLE
Port G has the following alternate features:
G0
INTR (External Interrupt Input)
G2
T1B (Timer T1 Capture Input)
G3
T1A (Timer T1 I/O)
G4
SO (MICROWIRETM Serial Data Output)
G5
SK (MICROWIRE Serial Clock)
G6
SI (MICROWIRE Serial Data Input)
TL/DD/9766 – 6
FIGURE 3. I/O Port Configurations
11
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tables for the LAID instruction, jump vectors for the JID instruction, and interrupt vectors for the VIS instruction). The
program memory is addressed by the 15-bit program counter (PC). All interrupts vector to program memory location
0FF Hex.
Pin Descriptions (Continued)
Port G has the following dedicated functions:
G1
WDOUT WATCHDOG and/or Clock Monitor
dedicated output
G7
CKO Oscillator dedicated output or general
purpose input
Port C is an 8-bit I/O port. The 40-pin device does not have
a full complement of Port C pins. The unavailable pins are
not terminated. A read operation for these unterminated
pins will return unpredictable values.
Port I is an 8-bit Hi-Z input port. The 40-pin device does not
have a full complement of Port I pins. Pins 15 and 16 on this
package must be connected to GND.
The 28-pin device has four I pins (I0, I1, I4, I5). The user
should pay attention when reading port I to the fact that I4
and I5 are in bit positions 4 and 5 rather than 2 and 3.
The unavailable pins (I4–I7) are not terminated i.e., they are
floating. A read operation for these unterminated pins will
return unpredictable values. The user must ensure that the
software takes into account by either masking or restricting
the accesses to bit operations. The unterminated port I pins
will draw power only when addressed.
Port D is an 8-bit output port that is preset high when RESET goes low. The user can tie two or more D port outputs
(except D2) together in order to get a higher drive.
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data
and Pin), the control registers, the MICROWIRE/PLUS SIO
shift register, and the various registers, and counters associated with the timers (with the exception of the IDLE timer).
Data memory is addressed directly by the instruction or indirectly by the B, X and SP pointers.
The device has 128 bytes of RAM. Sixteen bytes of RAM
are mapped as ‘‘registers’’ at addresses 0F0 to 0FF Hex.
These registers can be loaded immediately, and also decremented and tested with the DRSZ (decrement register and
skip if zero) instruction. The memory pointer registers X, SP,
and B are memory mapped into this space at address locations 0FC to 0FE Hex respectively, with the other registers
(other than reserved register 0FF) being available for general usage.
The instruction set permits any bit in memory to be set,
reset or tested. All I/O and registers (except A and PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. The accumulator (A) bits can also be directly and individually tested.
Note: Care must be exercised with the D2 pin operation. At RESET, the
external loads on this pin must ensure that the output voltages stay
above 0.8 VCC to prevent the chip from entering special modes. Also
keep the external loading on D2 to less than 1000 pF.
Note: RAM contents are undefined upon power-up.
Reset
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for Ports L, G, and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is
dedicated as the WATCHDOG and/or Clock Monitor error
output pin. Port D is initialized high with RESET. The PC,
PSW, CNTRL, ICNTRL, and T2CNTRL control registers are
cleared. The Multi-Input Wakeup registers WKEN, WKEDG,
and WKPND are cleared. The Stack Pointer, SP, is initialized to 06F Hex.
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, and with both
the WATCHDOG service window bits set and the Clock
Monitor bit set. The WATCHDOG and Clock Monitor detector circuits are inhibited during reset. The WATCHDOG service window bits are initialized to the maximum WATCHDOG
service window of 64k tc clock cycles. The Clock Monitor bit
is initialized high, and will cause a Clock Monitor error following reset if the clock has not reached the minimum specified frequency at the termination of reset. A Clock Monitor
error will cause an active low error output on pin G1. This
error output will continue until 16 – 32 tc clock cycles following the clock frequency reaching the minimum specified value, at which time the G1 output will enter the TRI-STATE
mode.
The external RC network shown in Figure 4 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes.
Functional Description
The architecture of the device is modified Harvard architecture. With the Harvard architecture, the control store program memory (ROM) is separated from the data store memory (RAM). Both ROM and RAM have their own separate
addressing space with separate address buses. The architecture, though based on Harvard architecture, permits
transfer of data from ROM to RAM.
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or
shift operation in one instruction (tc) cycle time.
There are five CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM address 06F with reset.
All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC).
PROGRAM MEMORY
Program memory consists of 4096 bytes of ROM. These
bytes may hold program instructions or constant data (data
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12
Reset (Continued)
TABLE A. Crystal Oscillator Configuration, TA e 25§ C
R1
(kX)
R2
(MX)
C1
(pF)
C2
(pF)
CKI Freq
(MHz)
Conditions
0
0
0
1
1
1
30
30
200
30 – 36
30 – 36
100 – 150
10
4
0.455
VCC e 5V
VCC e 5.0V
VCC e 5V
TABLE B. RC Oscillator Configuration, TA e 25§ C
TL/DD/9766 – 7
RC l 5 c Power Supply Rise Time
FIGURE 4. Recommended Reset Circuit
Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input frequency is divided down by 10 to produce the instruction
cycle clock (1/tc).
Figure 5 shows the Crystal and R/C diagrams.
R
(kX)
C
(pF)
CKI Freq
(MHz)
Instr. Cycle
(ms)
Conditions
3.3
5.6
6.8
82
100
100
2.2 to 2.7
1.1 to 1.3
0.9 to 1.1
3.7 to 4.6
7.4 to 9.0
8.8 to 10.8
VCC e 5V
VCC e 5V
VCC e 5V
Note: 3k s R s 200k, 50 pF s C s 200 pF
Control Registers
CNTRL Register (Address XÊ 00EE)
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
SL1 & SL0 Select the MICROWIRE/PLUS clock divide
by (00 e 2, 01 e 4, 1x e 8)
IEDG
External interrupt edge polarity select
(0 e Rising edge, 1 e Falling edge)
MSEL
Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively
CRYSTAL OSCILLATOR
CKI and CKO can be connected to make a closed loop
crystal (or resonator) controlled oscillator.
Table A shows the component values required for various
standard crystal values.
R/C OSCILLATOR
By selecting CKI as a single pin oscillator input, a single pin
R/C oscillator circuit can be connected to it. CKO is available as a general purpose input, and/or HALT restart pin.
Table B shows the variation in the oscillator frequencies as
functions of the component (R and C) values.
TL/DD/9766 – 9
TL/DD/9766–8
FIGURE 5. Crystal and R/C Oscillator Diagrams
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Control Registers (Continued)
T1C0
T1C1
T1C2
T1C3
Timer T1 Start/Stop control in timer
modes 1 and 2
Timer T1 Underflow Interrupt Pending Flag in
timer mode 3
Timer T1 mode control bit
Timer T1 mode control bit
Timer T1 mode control bit
T1C3 T1C2 T1C1 T1C0 MSEL IEDG
Bit 7
SL1
mWEN
T0EN
T0PND
LPEN
SL0
Bit 7
PSW Register (Address XÊ 00EF)
The PSW register contains the following select bits:
GIE
Global interrupt enable (enables interrupts)
EXEN
Enable external interrupt
BUSY
MICROWIRE/PLUS busy shifting flag
EXPND External interrupt pending
T1ENA Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
in mode 1, T1 Underflow in Mode 2, T1A capture edge in mode 3)
C
Carry Flag
HC
Half Carry Flag
HC
C T1PNDA T1ENA EXPND BUSY EXEN GIE
Bit 0
Bit 0
T2CNTRL Register (Address XÊ 00C6)
The T2CNTRL register contains the following bits:
T2ENB Timer T2 Interrupt Enable for T2B Input capture
edge
T2PNDB Timer T2 Interrupt Pending Flag for T2B capture edge
T2ENA Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge
T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA
in mode 1, T2 Underflow in mode 2, T2A capture edge in mode 3)
T2C0
Timer T2 Start/Stop control in timer modes 1
and 2 Timer T2 Underflow Interrupt Pending
Flag in timer mode 3
T2C1
Timer T2 mode control bit
T2C2
Timer T2 mode control bit
T2C3
Timer T2 mode control bit
The Half-Carry bit is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and RC (Reset
Carry) instructions will respectively set or clear both the carry flags. In addition to the SC and RC instructions, ADC,
SUBC, RRC and RLC instructions affect the carry and Half
Carry flags.
T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB
Bit 7
Bit 0
Timers
The device contains a very versatile set of timers (T0, T1,
T2). All timers and associated autoreload/capture registers
power up containing random data.
ICNTRL Register (Address XÊ 00E8)
The ICNTRL register contains the following bits:
T1ENB Timer T1 Interrupt Enable for T1B Input capture
edge
T1PNDB Timer T1 Interrupt Pending Flag for T1B capture edge
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Timer T0 Interrupt Enable (Bit 12 toggle)
Timer T0 Interrupt pending
L Port Interrupt Enable (Multi-Input Wakeup/Interrupt)
Bit 7 could be used as a flag
Unused LPEN T0PND T0EN mWPND mWEN T1PNDB T1ENB
Bit 0
Bit 7
Enable MICROWIRE/PLUS interrupt
mWPND MICROWIRE/PLUS interrupt pending
Figure 6 shows a block diagram for the timers.
14
Timers (Continued)
TL/DD/9766 – 11
FIGURE 6. Timers
block, while the pin TxB is an input to the timer block. The
powerful and flexible timer block allows the device to easily
perform all timer functions with minimal software overhead.
The timer block has three operating modes: Processor Independent PWM mode, External Event Counter mode, and
Input Capture mode.
The control bits TxC3, TxC2, and TxC1 allow selection of
the different modes of operation.
TIMER T0 (IDLE TIMER)
The device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer T0, which is a
16-bit timer. The Timer T0 runs continuously at the fixed
rate of the instruction cycle clock, tc. The user cannot read
or write to the IDLE Timer T0, which is a count down timer.
The Timer T0 supports the following functions:
Exit out of the Idle Mode (See Idle Mode description)
WATCHDOG logic (See WATCHDOG description)
Start up delay out of the HALT mode
The IDLE Timer T0 can generate an interrupt when the thirteenth bit toggles. This toggle is latched into the T0PND
pending flag, and will occur every 4 ms at the maximum
clock frequency (tc e 1 ms). A control flag T0EN allows the
interrupt from the thirteenth bit of Timer T0 to be enabled or
disabled. Setting T0EN will enable the interrupt, while resetting it will disable the interrupt.
Mode 1. Processor Independent PWM Mode
As the name suggests, this mode allows the device to generate a PWM signal with very minimal user intervention.
The user only has to define the parameters of the PWM
signal (ON time and OFF time). Once begun, the timer block
will continuously generate the PWM signal completely independent of the microcontroller. The user software services
the timer block only when the PWM parameters require updating.
In this mode the timer Tx counts down at a fixed rate of tc.
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, RxA and RxB. The very
first underflow of the timer causes the timer to reload from
the register RxA. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register RxB.
The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the
timer for PWM mode operation.
TIMER T1 AND TIMER T2
The device has a set of two powerful timer/counter blocks,
T1 and T2. The associated features and functioning of a
timer block are described by referring to the timer block Tx.
Since the two timer blocks, T1 and T2, are identical, all comments are equally applicable to either timer block.
Each timer block consists of a 16-bit timer, Tx, and two
supporting 16-bit autoreload/capture registers, RxA and
RxB. Each timer block has two pins associated with it, TxA
and TxB. The pin TxA supports I/O required by the timer
Figure 7 shows a block diagram of the timer in PWM mode.
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Timers (Continued)
TL/DD/9766 – 13
FIGURE 7. Timer in PWM Mode
The underflows can be programmed to toggle the TxA output pin. The underflows can also be programmed to generate interrupts.
Underflows from the timer are alternately latched into two
pending flags, TxPNDA and TxPNDB. The user must reset
these pending flags under software control. Two control enable flags, TxENA and TxENB, allow the interrupts from the
timer underflow to be enabled or disabled. Setting the timer
enable flag TxENA will cause an interrupt when a timer underflow causes the RxA register to be reloaded into the timer. Setting the timer enable flag TxENB will cause an interrupt when a timer underflow causes the RxB register to be
reloaded into the timer. Resetting the timer enable flags will
disable the associated interrupts.
Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of interrupting once
per PWM period on either the rising or falling edge of the
PWM output. Alternatively, the user may choose to interrupt
on both edges of the PWM output.
Mode 2. External Event Counter Mode
This mode is quite similar to the processor independent
PWM mode described above. The main difference is that
the timer, Tx, is clocked by the input signal from the TxA pin.
The Tx timer control bits, TxC3, TxC2 and TxC1 allow the
timer to be clocked either on a positive or negative edge
from the TxA pin. Underflows from the timer are latched into
the TxPNDA pending flag. Setting the TxENA control flag
will cause an interrupt when the timer underflows.
In this mode the input pin TxB can be used as an independent positive edge sensitive interrupt input if the TxENB
control flag is set. The occurrence of a positive edge on the
TxB input pin is latched into the TxPNDB flag.
Figure 8 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the TxA pin is
being used as the counter input clock.
TL/DD/9766 – 14
FIGURE 8. Timer in External Event Counter Mode
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16
Timers (Continued)
flow interrupt pending flag in the Input Capture mode). Consequently, the TxC0 control bit should be reset when entering the Input Capture mode. The timer underflow interrupt is
enabled with the TxENA control flag. When a TxA interrupt
occurs in the Input Capture mode, the user must check both
the TxPNDA and TxC0 pending flags in order to determine
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.
Mode 3. Input Capture Mode
The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the
input capture mode.
In this mode, the timer Tx is constantly running at the fixed
tc rate. The two registers, RxA and RxB, act as capture
registers. Each register acts in conjunction with a pin. The
register RxA acts in conjunction with the TxA pin and the
register RxB acts in conjunction with the TxB pin.
The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin. Control bits,
TxC3, TxC2 and TxC1, allow the trigger events to be specified either as a positive or a negative edge. The trigger condition for each input pin can be specified independently.
The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag TxENA allows the interrupt on TxA to be either enabled or disabled. Setting the TxENA flag enables interrupts to be generated when the selected trigger condition occurs on the
TxA pin. Similarly, the flag TxENB controls the interrupts
from the TxB pin.
Underflows from the timer can also be programmed to generate interrupts. Underflows are latched into the timer TxC0
pending flag (the TxC0 control bit serves as the timer under-
Figure 9 shows a block diagram of the timer in Input Capture
mode.
TIMER CONTROL FLAGS
The timers T1 and T2 have indentical control structures.
The control bits and their functions are summarized below.
TxC0
Timer Start/Stop control in Modes 1 and 2
(Processor Independent PWM and External
Event Counter), where 1 e Start, 0 e Stop
Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture)
TxPNDA Timer Interrupt Pending Flag
TxPNDB Timer Interrupt Pending Flag
TxENA Timer Interrupt Enable Flag
TxENB Timer Interrupt Enable Flag
1 e Timer Interrupt Enabled
0 e Timer Interrupt Disabled
TxC3
Timer mode control
TxC2
Timer mode control
TxC1
Timer mode control
TL/DD/9766 – 15
FIGURE 9. Timer in Input Capture Mode
17
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Timers (Continued)
The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:
Interrupt A
Source
Interrupt B
Source
Timer
Counts On
MODE 2 (External
Event Counter)
Timer
Underflow
Pos. TxB
Edge
TxA
Pos. Edge
1
MODE 2 (External
Event Counter)
Timer
Underflow
Pos. TxB
Edge
TxA
Neg. Edge
0
1
MODE 1 (PWM)
TxA Toggle
Autoreload
RA
Autoreload
RB
tc
1
0
0
MODE 1 (PWM)
No TxA Toggle
Autoreload
RA
Autoreload
RB
tc
0
1
0
MODE 3 (Capture)
Captures:
TxA Pos. Edge
TxB Pos. Edge
Pos. TxA
Edge or
Timer
Underflow
Pos. TxB
Edge
tc
1
1
0
MODE 3 (Capture)
Captures:
TxA Pos. Edge
TxB Neg. Edge
Pos. TxA
Edge or
Timer
Underflow
Neg. TxB
Edge
tc
0
1
1
MODE 3 (Capture)
Captures:
TxA Neg. Edge
TxB Pos. Edge
Neg. TxB
Edge or
Timer
Underflow
Pos. TxB
Edge
tc
1
1
1
MODE 3 (Capture)
Captures:
TxA Neg. Edge
TxB Neg. Edge
Neg. TxA
Edge or
Timer
Underflow
Neg. TxB
Edge
tc
TxC3
TxC2
TxC1
Timer Mode
0
0
0
0
0
1
Power Save Modes
with the Multi-Input Wakeup feature on the L port. The second method is with a low to high transition on the CKO (G7)
pin. This method precludes the use of the crystal clock configuration (since CKO becomes a dedicated output), and so
may be used with an RC clock configuration. The third
method of exiting the HALT mode is by pulling the RESET
pin low.
Since a crystal or ceramic resonator may be selected as the
oscillator, the Wakeup signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full amplitude and frequency stability. The IDLE timer is used to generate a fixed delay to ensure that the oscillator has indeed
stabilized before allowing instruction execution. In this case,
upon detecting a valid Wakeup signal, only the oscillator
circuitry is enabled. The IDLE timer is loaded with a value of
256 and is clocked with the tc instruction cycle clock. The tc
clock is derived by dividing the oscillator clock down by a
factor of 10. The Schmitt trigger following the CKI inverter
on the chip ensures that the IDLE timer is clocked only
when the oscillator has a sufficiently large amplitude to
meet the Schmitt trigger specifications. This Schmitt trigger
is not part of the oscillator closed loop. The startup timeout
from the IDLE timer enables the clock signals to be routed
to the rest of the chip.
The device offers the user two power save modes of operation: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board oscillator circuitry and timer T0 are active but all other microcontroller activities are stopped. In either mode, all on-board
RAM, registers, I/O states, and timers (with the exception of
T0) are unaltered.
HALT MODE
The device is placed in the HALT mode by writing a ‘‘1’’ to
the HALT flag (G7 data bit). All microcontroller activities,
including the clock, timers, are stopped. The WATCHDOG
logic is disabled during the HALT mode. However, the clock
monitor circuitry, if enabled, remains active and will cause
the WATCHDOG output pin (WDOUT) to go low. If the
HALT mode is used and the user does not want to activate
the WDOUT pin, the Clock Monitor should be disabled after
the device comes out of reset (resetting the Clock Monitor
control bit with the first write to the WDSVR register). In the
HALT mode, the power requirements of the device are minimal and the applied voltage (VCC) may be decreased to Vr
(Vr e 2.0V) without altering the state of the machine.
The device supports three different ways of exiting the
HALT mode. The first method of exiting the HALT mode is
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18
Power Save Modes (Continued)
As with the HALT mode, the device can be returned to normal operation with a reset, or with a Multi-Input Wake-up
from the L Port. Alternately, the microcontroller resumes
normal operation from the IDLE mode when the thirteenth
bit (representing 4.096 ms at internal clock frequency of
1 MHz, tc e 1 ms) of the IDLE Timer toggles.
This toggle condition of the thirteenth bit of the IDLE Timer
T0 is latched into the T0PND pending flag.
The user has the option of being interrupted with a transition
on the thirteenth bit of the IDLE Timer T0. The interrupt can
be enabled or disabled via the T0EN control bit. Setting the
T0EN flag enables the interrupt and vice versa.
The user can enter the IDLE mode with the Timer T0 interrupt enabled. In this case, when the T0PND bit gets set, the
device will first execute the Timer T0 interrupt service routine and then return to the instruction following the ‘‘Enter
Idle Mode’’ instruction.
Alternatively, the user can enter the IDLE mode with the
IDLE Timer T0 interrupt disabled. In this case, the device
will resume normal operation with the instruction immediately following the ‘‘Enter IDLE Mode’’ instruction.
If an RC clock option is being used, the fixed delay is introduced optionally. A control bit, CLKDLY, mapped as configuration bit G7, controls whether the delay is to be introduced or not. The delay is included if CLKDLY is set, and
excluded if CLKDLY is reset. The CLKDLY bit is cleared on
reset.
The device has two mask options associated with the HALT
mode. The first mask option enables the HALT mode feature, while the second mask option disables the HALT
mode. With the HALT mode enable mask option, the device
will enter and exit the HALT mode as described above. With
the HALT disable mask option, the device cannot be placed
in the HALT mode (writing a ‘‘1’’ to the HALT flag will have
no effect).
The WATCHDOG detector circuit is inhibited during the
HALT mode. However, the clock monitor circuit, if enabled,
remains active during HALT mode in order to ensure a clock
monitor error if the device inadvertently enters the HALT
mode as a result of a runaway program or power glitch.
IDLE MODE
The device is placed in the IDLE mode by writing a ‘‘1’’ to
the IDLE flag (G6 data bit). In this mode, all activity, except
the associated on-board oscillator circuitry, the WATCHDOG logic, the clock monitor and the IDLE Timer T0, is
stopped.
Note: It is necessary to program two NOP instructions following both the
set HALT mode and set IDLE mode instructions. These NOP instructions are necessary to allow clock resynchronization following the
HALT or IDLE modes.
19
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Multi-Input Wakeup
The Multi-Input Wakeup feature is used to return (wakeup)
the device from either the HALT or IDLE modes. Alternately
Multi-Input Wakeup/Interrupt feature may also be used to
generate up to 8 edge selectable external interrupts.
RBIT 5, WKEN
SBIT 5, WKEDG
RBIT 5, WKPND
SBIT 5, WKEN
If the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wakeup/Interrupt, a safety procedure should also be followed to avoid inherited
pseudo wakeup conditions. After the selected L port bits
have been changed from output to input but before the associated WKEN bits are enabled, the associated edge select bits in WKEDG should be set or reset for the desired
edge selects, followed by the associated WKPND bits being
cleared.
This same procedure should be used following reset, since
the L port inputs are left floating as a result of reset.
The occurrence of the selected trigger condition for Multi-Input Wakeup is latched into a pending register called
WKPND. The respective bits of the WKPND register will be
set on the occurrence of the selected trigger edge on the
corresponding Port L pin. The user has the responsibility of
clearing these pending flags. Since WKPND is a pending
register for the occurrence of selected wakeup conditions,
the device will not enter the HALT mode if any Wakeup bit is
both enabled and pending. Consequently, the user has the
responsibility of clearing the pending flags before attempting to enter the HALT mode.
The WKEN, WKPND and WKEDG are all read/write registers, and are cleared at reset.
Figure 10 shows the Multi-Input Wakeup logic.
The Multi-Input Wakeup feature utilizes the L Port. The user
selects which particular L port bit (or combination of L Port
bits) will cause the device to exit the HALT or IDLE modes.
The selection is done through the Reg: WKEN. The Reg:
WKEN is an 8-bit read/write register, which contains a control bit for every L port bit. Setting a particular WKEN bit
enables a Wakeup from the associated L port pin.
The user can select whether the trigger condition on the
selected L Port pin is going to be either a positive edge (low
to high transition) or a negative edge (high to low transition).
This selection is made via the Reg: WKEDG, which is an 8bit control register with a bit assigned to each L Port pin.
Setting the control bit will select the trigger condition to be a
negative edge on that particular L Port pin. Resetting the bit
selects the trigger condition to be a positive edge. Changing
an edge select entails several steps in order to avoid a
pseudo Wakeup condition as a result of the edge change.
First, the associated WKEN bit should be reset, followed by
the edge select change in WKEDG. Next, the associated
WKPND bit should be cleared, followed by the associated
WKEN bit being re-enabled.
An example may serve to clarify this procedure. Suppose
we wish to change the edge select from positive (low going
high) to negative (high going low) for L Port bit 5, where bit 5
has previously been enabled for an input interrupt. The program would be as follows:
PORT L INTERRUPTS
Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all vectored into
the same service subroutine.
The interrupt from Port L shares logic with the wake up circuitry. The register WKEN allows interrupts from Port L to
TL/DD/9766 – 16
FIGURE 10. Multi-Input Wake Up Logic
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20
Multi-Input Wakeup (Continued)
amplitude to meet the Schmitt trigger specifications. This
Schmitt trigger is not part of the oscillator closed loop. The
startup timeout from the IDLE timer enables the clock signals to be routed to the rest of the chip. If the RC clock
option is used, the fixed delay is under software control. A
control flag, CLKDLY, in the G7 configuration bit allows the
clock start up delay to be optionally inserted. Setting
CLKDLY flag high will cause clock start up delay to be inserted and resetting it will exclude the clock start up delay.
The CLKDLY flag is cleared during reset, so the clock start
up delay is not present following reset with the RC clock
options.
be individually enabled or disabled. The register WKEDG
specifies the trigger condition to be either a positive or a
negative edge. Finally, the register WKPND latches in the
pending trigger conditions.
The GIE (Global Interrupt Enable) bit enables the interrupt
function.
A control flag, LPEN, functions as a global interrupt enable
for Port L interrupts. Setting the LPEN flag will enable interrupts and vice versa. A separate global pending flag is not
needed since the register WKPND is adequate.
Since Port L is also used for waking the device out of the
HALT or IDLE modes, the user can elect to exit the HALT or
IDLE modes either with or without the interrupt enabled. If
he elects to disable the interrupt, then the device will restart
execution from the instruction immediately following the instruction that placed the microcontroller in the HALT or
IDLE modes. In the other case, the device will first execute
the interrupt service routine and then revert to normal operation.
The Wakeup signal will not start the chip running immediately since crystal oscillators or ceramic resonators have a finite start up time. The IDLE Timer (T0) generates a fixed
delay to ensure that the oscillator has indeed stabilized before allowing the device to execute instructions. In this case,
upon detecting a valid Wakeup signal, only the oscillator
circuitry and the IDLE Timer T0 are enabled. The IDLE Timer is loaded with a value of 256 and is clocked from the tc
instruction cycle clock. The tc clock is derived by dividing
down the oscillator clock by a factor of 10. A Schmitt trigger
following the CKI on-chip inverter ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large
Arbitration
Ranking
Interrupts
The device supports a vectored interrupt scheme. It supports a total of ten interrupt sources. The following table
lists all the possible interrupt sources, their arbitration ranking and the memory locations reserved for the interrupt vector for each source.
Two bytes of program memory space are reserved for each
interrupt source. All interrupt sources except the software
interrupt are maskable. Each of the maskable interrupts
have an Enable bit and a Pending bit. A maskable interrupt
is active if its associated enable and pending bits are set. If
GIE e 1 and an interrupt is active, then the processor will
be interrupted as soon as it is ready to start executing an
instruction except if the above conditions happen during the
Software Trap service routine. This exception is described
in the Software Trap sub-section.
The interruption process is accomplished with the INTR instruction (opcode 00), which is jammed inside the Instruc-
Source
(1) Highest
Description
Vector
Address
Hi-Low Byte
Software
INTR Instruction
0yFE – 0yFF
Reserved
for Future Use
0yFC – 0yFD
(2)
External
Pin G0 Edge
0yFA – 0yFB
(3)
Timer T0
Underflow
0yF8 – 0yF9
(4)
Timer T1
T1A/Underflow
0yF6 – 0yF7
(5)
Timer T1
T1B
0yF4 – 0yF5
(6)
MICROWIRE/PLUS
BUSY Goes Low
0yF2 – 0yF3
Reserved
for Future Use
0yF0 – 0yF1
Reserved
for UART
0yEE – 0yEF
Reserved
for UART
0yEC – 0yED
(7)
Timer T2
T2A/Underflow
0yEA – 0yEB
(8)
Timer T2
T2B
0yE8 – 0yE9
Reserved
for Future Use
0yE6 – 0yE7
Reserved
for Future Use
0yE4 – 0yE5
(9)
Port L/Wakeup
Port L Edge
0yE2 – 0yE3
(10) Lowest
Default
VIS Instr. Execution
without Any Interrupts
0yE0 – 0yE1
y is VIS page, y
i
0.
21
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Interrupts (Continued)
The addresses of the different interrupt service routines,
called vectors, are chosen by the user and stored in ROM in
a table starting at 01E0 (assuming that VIS is located between 00FF and 01DF). The vectors are 15-bit wide and
therefore occupy 2 ROM locations.
VIS and the vector table must be located in the same 256byte block (0y00 to 0yFF) except if VIS is located at the last
address of a block. In this case, the table must be in the
next block. The vector table cannot be inserted in the first
256-byte block.
The vector of the maskable interrupt with the lowest rank is
located at 0yE0 (Hi-Order byte) and 0yE1 (Lo-Order byte)
and so forth in increasing rank number. The vector of the
maskable interrupt with the highest rank is located at 0yFA
(Hi-Order byte) and 0yFB (Lo-Order byte).
The Software Trap has the highest rank and its vector is
located at 0yFE and 0yFF.
If, by accident, a VIS gets executed and no interrupt is active, then the PC (Program Counter) will branch to a vector
located at 0yE0 – 0yE1.
tion Register and replaces the opcode about to be executed. The following steps are performed for every interrupt:
1. The GIE (Global Interrupt Enable) bit is reset.
2. The address of the instruction about to be executed is
pushed into the stack.
3. The PC (Program Counter) branches to address 00FF.
This procedure takes 7 tc cycles to execute.
At this time, since GIE e 0, other maskable interrupts are
disabled. The user is now free to do whatever context
switching is required by saving the context of the machine in
the stack with PUSH instructions. The user would then program a VIS (Vector Interrupt Select) instruction in order to
branch to the interrupt service routine of the highest priority
interrupt enabled and pending at the time of the VIS. Note
that this is not necessarily the interrupt that caused the
branch to address location 00FF Hex prior to the context
switching.
Thus, if an interrupt with a higher rank than the one which
caused the interruption becomes active before the decision
of which interrupt to service is made by the VIS, then the
interrupt with the higher rank will override any lower ones
and will be acknowledged. The lower priority interrupt(s) are
still pending, however, and will cause another interrupt immediately following the completion of the interrupt service
routine associated with the higher priority interrupt just serviced. This lower priority interrupt will occur immediately following the RETI (Return from Interrupt) instruction at the
end of the interrupt service routine just completed.
Inside the interrupt service routine, the associated pending
bit has to be cleared by software. The RETI (Return from
Interrupt) instruction at the end of the interrupt service routine will set the GIE (Global Interrupt Enable) bit, allowing
the processor to be interrupted again if another interrupt is
active and pending.
The VIS instruction looks at all the active interrupts at the
time it is executed and performs an indirect jump to the
beginning of the service routine of the one with the highest
rank.
WARNING
A Default VIS interrupt handle routine must be present. As a
minimum, this handler should confirm that the GIE bit is
cleared (this indicates that the interrupt sequence has been
taken), take care of any required housekeeping, restore
context and return. Some sort of Warm Restart procedure
should be implemented. These events can occur without
any error on the part of the system designer or programmer.
Note: There is always the possibility of an interrupt occurring during an instruction which is attempting to reset the
GIE bit or any other interrupt enable bit. If this occurs when
a single cycle instruction is being used to reset the interrupt
enable bit, the interrupt enable bit will be reset but an interrupt may still occur. This is because interrupt processing is
started at the same time as the interrupt bit is being reset.
To avoid this scenario, the user should always use a two,
three, or four cycle instruction to reset interrupt enable bits.
Figure 11 shows the Interrupt block diagram.
TL/DD/9766 – 18
FIGURE 11. Interrupt Block Diagram
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22
TABLE II. WATCHDOG Service Window Select
Interrupts (Continued)
SOFTWARE TRAP
The Software Trap (ST) is a special kind of non-maskable
interrupt which occurs when the INTR instruction (used to
acknowledge interrupts) is fetched from ROM and placed
inside the instruction register. This may happen when the
PC is pointing beyond the available ROM address space or
when the stack is over-popped.
When an ST occurs, the user can re-initialize the stack
pointer and do a recovery procedure (similar to reset, but
not necessarily containing all of the same initialization procedures) before restarting.
The occurrence of an ST is latched into the ST pending bit.
The GIE bit is not affected and the ST pending bit (not
accessible by the user) is used to inhibit other interrupts
and to direct the program to the ST service routine with the
VIS instruction. The RPND instruction is used to clear the
software interrupt pending bit. This pending bit is also
cleared on reset.
The ST has the highest rank among all interrupts.
Nothing (except another ST) can interrupt an ST being
serviced.
X
0
1
1
0
0
Y
6
5
4
3
2
1
0
2k-8k tc Cycles
2k-16k tc Cycles
2k-32k tc Cycles
2k-64k tc Cycles
The WATCHDOG and Clock Monitor are disabled during
reset. The device comes out of reset with the WATCHDOG
armed, the WATCHDOG Window Select bits (bits 6, 7 of the
WDSVR Register) set, and the Clock Monitor bit (bit 0 of the
WDSVR Register) enabled. Thus, a Clock Monitor error will
occur after coming out of reset, if the instruction cycle clock
frequency has not reached a minimum specified value, including the case where the oscillator fails to start.
The WDSVR register can be written to only once after reset
and the key data (bits 5 through 1 of the WDSVR Register)
must match to be a valid write. This write to the WDSVR
register involves two irrevocable choices: (i) the selection of
the WATCHDOG service window (ii) enabling or disabling of
the Clock Monitor. Hence, the first write to WDSVR Register
involves selecting or deselecting the Clock Monitor, select
the WATCHDOG service window and match the WATCHDOG key data. Subsequent writes to the WDSVR register
will compare the value being written by the user to the
WATCHDOG service window value and the key data (bits 7
through 1) in the WDSVR Register. Table III shows the sequence of events that can occur.
The user must service the WATCHDOG at least once before the upper limit of the serivce window expires. The
WATCHDOG may not be serviced more than once in every
lower limit of the service window. The user may service the
WATCHDOG as many times as wished in the time period
between the lower and upper limits of the service window.
The first write to the WDSVR Register is also counted as a
WATCHDOG service.
The WATCHDOG has an output pin associated with it. This
is the WDOUT pin, on pin 1 of the port G. WDOUT is active
low. The WDOUT pin is in the high impedance state in the
inactive state. Upon triggering the WATCHDOG, the logic
will pull the WDOUT (G1) pin low for an additional
16 tc –32 tc cycles after the signal level on WDOUT pin goes
below the lower Schmitt trigger threshold. After this delay,
the device will stop forcing the WDOUT output low.
The WATCHDOG service window will restart when the
WDOUT pin goes high It is recommended that the user tie
the WDOUT pin back to VCC through a resistor in order to
pull WDOUT high.
A WATCHDOG service while the WDOUT signal is active
will be ignored. The state of the WDOUT pin is not guaranteed on reset, but if it powers up low then the WATCHDOG
will time out and WDOUT will enter high impedance state.
Clock
Monitor
7
0
1
0
1
WATCHDOG Operation
TABLE I. WATCHDOG Service Register (WDSVR)
X
0
0
1
1
Service Window
(Lower-Upper Limits)
The Clock Monitor aboard the device can be selected or
deselected under program control. The Clock Monitor is
guaranteed not to reject the clock if the instruction cycle
clock (1/tc) is greater or equal to 10 kHz. This equates to a
clock input rate on CKI of greater or equal to 100 kHz.
The device contains a WATCHDOG and clock monitor. The
WATCHDOG is designed to detect the user program getting
stuck in infinite loops resulting in loss of program control or
‘‘runaway’’ programs. The Clock Monitor is used to detect
the absence of a clock or a very slow clock below a specified rate on the CKI pin.
The WATCHDOG consists of two independent logic blocks:
WD UPPER and WD LOWER. WD UPPER establishes the
upper limit on the service window and WD LOWER defines
the lower limit of the service window.
Servicing the WATCHDOG consists of writing a specific value to a WATCHDOG Service Register named WDSVR
which is memory mapped in the RAM. This value is composed of three fields, consisting of a 2-bit Window Select, a
5-bit Key Data field, and the 1-bit Clock Monitor Select field.
Table I shows the WDSVR register.
The lower limit of the service window is fixed at 2048 instruction cycles. Bits 7 and 6 of the WDSVR register allow
the user to pick an upper limit of the service window.
Table II shows the four possible combinations of lower and
upper limits for the WATCHDOG service window. This flexibility in choosing the WATCHDOG service window prevents
any undue burden on the user software.
Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the
5-bit Key Data field. The key data is fixed at 01100. Bit 0 of
the WDSVR Register is the Clock Monitor Select bit.
Key Data
WDSVR
Bit 6
Clock Monitor
WATCHDOG
Window
Select
WDSVR
Bit 7
23
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WATCHDOG Operation (Continued)
TABLE III. WATCHDOG Service Actions
Key
Data
Window
Data
Clock
Monitor
Action
Valid Service: Restart Service Window
Match
Match
Match
Don’t Care
Mismatch
Don’t Care
Error: Generate WATCHDOG Output
Mismatch
Don’t Care
Don’t Care
Error: Generate WATCHDOG Output
Don’t Care
Don’t Care
Mismatch
Error: Generate WATCHDOG Output
TABLE IV. MICROWIRE/PLUS
Master Mode Clock Select
SL1
SL0
SK
0
0
1
0
1
x
2 c tc
4 c tc
8 c tc
Where tc is the instruction cycle clock
# With the single-pin R/C oscillator mask option selected
The Clock Monitor forces the G1 pin low upon detecting a
clock frequency error. The Clock Monitor error will continue
until the clock frequency has reached the minimum specified value, after which the G1 output will enter the high impedance TRI-STATE mode following 16 tc – 32 tc clock cycles. The Clock Monitor generates a continual Clock Monitor error if the oscillator fails to start, or fails to reach the
minimum specified frequency. The specification for the
Clock Monitor is as follows:
1/tc l 10 kHzÐNo clock rejection.
and the CLKDLY bit reset, the WATCHDOG service window will resume following HALT mode from where it left
off before entering the HALT mode.
# With the crystal oscillator mask option selected, or with
the single-pin R/C oscillator mask option selected and
the CLKDLY bit set, the WATCHDOG service window will
be set to its selected value from WDSVR following HALT.
Consequently, the WATCHDOG should not be serviced
for at least 2048 instruction cycles following HALT, but
must be serviced within the selected window to avoid a
WATCHDOG error.
1/tc k 10 HzÐGuaranteed clock rejection.
WATCHDOG AND CLOCK MONITOR SUMMARY
The following salient points regarding the WATCHDOG and
Clock Monitor should be noted:
# The IDLE timer T0 is not initialized with reset.
# The user can sync in to the IDLE counter cycle with an
IDLE counter (T0) interrupt or by monitoring the T0PND
flag. The T0PND flag is set whenever the thirteenth bit of
the IDLE counter toggles (every 4096 instruction cycles).
The user is responsible for resetting the T0PND flag.
# Both WATCHDOG and Clock Monitor detector circuits
are inhibited during reset.
# Following reset, the WATCHDOG and Clock Monitor are
both enabled, with the WATCHDOG having the maximum service window selected.
# A hardware WATCHDOG service occurs just as the de-
able/disable option can only be changed once, during
the initial WATCHDOG service following reset.
vice exits the IDLE mode. Consequently, the Watchdog
should not be serviced for at least 2048 instruction cycles following IDLE, but must be serviced within the selected window to avoid a WATCHDOG error.
# The initial WATCHDOG service must match the key data
# Following reset, the initial WATCHDOG service (where
value in the WATCHDOG Service register WDSVR in order to avoid a WATCHDOG error.
the service window and the Clock Monitor enable/disable must be selected) may be programmed anywhere
within the maximum service window (65,536 instruction
cycles) initialized by RESET. Note that this initial
WATCHDOG service may be programmed within the initial 2048 instruction cycles without causing a WATCHDOG error.
# The WATCHDOG service window and Clock Monitor en-
# Subsequent WATCHDOG services must match all three
data fields in WDSVR in order to avoid WATCHDOG errors.
# The correct key data value cannot be read from the
WATCHDOG Service register WDSVR. Any attempt to
read this key data value of 01100 from WDSVR will read
as key data value of all 0’s.
Detection of Illegal Conditions
The device can detect various illegal conditions resulting
from coding errors, transient noise, power supply voltage
drops, runaway programs, etc.
Reading of undefined ROM gets zeros. The opcode for software interrupt is zero. If the program fetches instructions
from undefined ROM, this will force a software interrupt,
thus signaling that an illegal condition has occurred.
# The WATCHDOG detector circuit is inhibited during both
the HALT and IDLE modes.
# The Clock Monitor detector circuit is active during both
the HALT and IDLE modes. Consequently, the device
inadvertently entering the HALT mode will be detected
as a Clock Monitor error (provided that the Clock Monitor
enable option has been selected by the program).
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24
Detection of Illegal
Conditions (Continued)
master mode, the SK clock rate is selected by the two bits,
SL0 and SL1, in the CNTRL register. Table IV details the
different clock rates that may be selected.
The subroutine stack grows down for each call (jump to
subroutine), interrupt, or PUSH, and grows up for each return or POP. The stack pointer is initialized to RAM location
06F Hex during reset. Consequently, if there are more returns than calls, the stack pointer will point to addresses
070 and 071 Hex (which are undefined RAM). Undefined
RAM from addresses 070 to 07F Hex is read as all 1’s,
which in turn will cause the program to return to address
7FFF Hex. This is an undefined ROM location and the instruction fetched (all 0’s) from this location will generate a
software interrupt signaling an illegal condition.
Thus, the chip can detect the following illegal conditions:
a. Executing from undefined ROM
b. Over ‘‘POP’’ing the stack by having more returns than
calls.
When the software interrupt occurs, the user can re-initialize
the stack pointer and do a recovery procedure before restarting (this recovery program is probably similar to that
following reset, but might not contain the same program
initialization procedures). The recovery program should reset the software interrupt pending bit using the RPND instruction.
MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have
been shifted. The device may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave. Figure 13 shows
how two COP888CL microcontrollers and several peripherals may be interconnected using the MICROWIRE/PLUS
arrangements.
Warning:
The SIO register should only be loaded when the SK clock
is low. Loading the SIO register while the SK clock is high
will result in undefined data in the SIO register. The SK
clock is normally low when not shifting.
Setting the BUSY flag when the input SK clock is high in the
MICROWIRE/PLUS slave mode may cause the current SK
clock for the SIO shift register to be narrow. For safety, the
BUSY flag should only be set when the input SK clock is
low.
MICROWIRE/PLUS Master Mode Operation
In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIRE
Master always initiates all data exchanges. The MSEL bit in
the CNTRL register must be set to enable the SO and SK
functions onto the G Port. The SO and SK pins must also be
selected as outputs by setting appropriate bits in the Port G
configuration register. Table V summarizes the bit settings
required for Master mode of operation.
MICROWIRE/PLUS
MICROWIRE/PLUS is a serial synchronous communications interface. The MICROWIRE/PLUS capability enables
the device to interface with any of National Semiconductor’s
MICROWIRE peripherals (i.e. A/D converters, display drivers, E2PROMs etc.) and with other microcontrollers which
support the MICROWIRE interface. It consists of an 8-bit
serial shift register (SIO) with serial data input (SI), serial
data output (SO) and serial shift clock (SK). Figure 12
shows a block diagram of the MICROWIRE logic.
The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIRE/
PLUS arrangement with the internal clock source is called
the Master mode of operation. Similarly, operating the MICROWIRE arrangement with an external shift clock is called
the Slave mode of operation.
MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and
resetting the appropriate bit in the Port G configuration register. Table V summarizes the settings required to enter the
Slave mode of operation.
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by
the Master will be shifted properly. After eight clock pulses
the BUSY flag will be cleared and the sequence may be
repeated.
Alternate SK Phase Operation
The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register.
In both the modes the SK is normally low. In the normal
mode data is shifted in on the rising edge of the SK clock
and the data is shifted out on the falling edge of the SK
clock. The SIO register is shifted on each falling edge of the
SK clock. In the alternate SK phase operation, data is shifted in on the falling edge of the SK clock and shifted out on
the rising edge of the SK clock.
TL/DD/9766 – 20
FIGURE 12. MICROWIRE/PLUS Block Diagram
The CNTRL register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,
the MSEL bit in the CNTRL register is set to one. In the
25
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MICROWIRE/PLUS (Continued)
TL/DD/9766 – 21
FIGURE 13. MICROWIRE/PLUS Application
A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Resetting SKSEL
causes the MICROWIRE/PLUS logic to be clocked from the
normal SK signal. Setting the SKSEL flag selects the alternate SK clock. The SKSEL is mapped into the G6 configuration bit. The SKSEL flag will power up in the reset condition,
selecting the normal SK signal.
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TABLE V
This table assumes that the control flag MSEL is set.
26
G4
(SO)
Config.
Bit
G5
(SK)
Config.
Bit
G4
Fun.
G5
Fun.
Operation
1
1
SO
Int.
SK
MICROWIRE/PLUS
Master
0
1
TRISTATE
Int.
SK
MICROWIRE/PLUS
Master
1
0
SO
Ext.
SK
MICROWIRE/PLUS
Slave
0
0
TRISTATE
Ext.
SK
MICROWIRE/PLUS
Slave
Memory Map
Addressing Modes
All RAM, ports and registers (except A and PC) are mapped
into data memory address space
The device has ten addressing modes, six for operand addressing and four for transfer of control.
Address
00 to 6F
OPERAND ADDRESSING MODES
Register Indirect
This is the ‘‘normal’’ addressing mode. The operand is the
data memory addressed by the B pointer or X pointer.
Register Indirect (with auto post increment or
decrement of pointer)
This addressing mode is used with the LD and X instructions. The operand is the data memory addressed by the B
pointer or X pointer. This is a register indirect mode that
automatically post increments or decrements the B or X register after executing the instruction.
Direct
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
Immediate
The instruction contains an 8-bit immediate field as the operand.
Short Immediate
This addressing mode is used with the Load B Immediate
instruction. The instruction contains a 4-bit immediate field
as the operand.
Indirect
This addressing mode is used with the LAID instruction. The
contents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.
Contents
On-Chip RAM bytes
70 to BF
Unused RAM Address Space
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD to CF
Timer T2 Lower Byte
Timer T2 Upper Byte
Timer T2 Autoload Register T2RA Lower Byte
Timer T2 Autoload Register T2RA Upper Byte
Timer T2 Autoload Register T2RB Lower Byte
Timer T2 Autoload Register T2RB Upper Byte
Timer T2 Control Register
WATCHDOG Service Register (Reg:WDSVR)
MIWU Edge Select Register (Reg:WKEDG)
MIWU Enable Register (Reg:WKEN)
MIWU Pending Register (Reg:WKPND)
Reserved
Reserved
Reserved
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD to DF
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
Port D Data Register
Reserved for Port D
E0 to E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
Reserved
Timer T1 Autoload Register T1RB Lower Byte
Timer T1 Autoload Register T1RB Upper Byte
ICNTRL Register
MICROWIRE Shift Register
Timer T1 Lower Byte
Timer T1 Upper Byte
Timer T1 Autoload Register T1RA Lower Byte
Timer T1 Autoload Register T1RA Upper Byte
CNTRL Control Register
PSW Register
F0 to FB
FC
FD
FE
FF
On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
Reserved
TRANSFER OF CONTROL ADDRESSING MODES
Relative
This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new
program location. JP has a range from b31 to a 32 to allow
a 1-byte relative jump (JP a 1 is implemented by a NOP
instruction). There are no ‘‘pages’’ when using JP, since all
15 bits of PC are used.
Absolute
This mode is used with the JMP and JSR instructions, with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any location in the current 4k program memory segment.
Absolute Long
This mode is used with the JMPL and JSRL instructions,
with the instruction field of 15 bits replacing the entire 15
bits of the program counter (PC). This allows jumping to any
location in the current 4k program memory space.
Indirect
This mode is used with the JID instruction. The contents of
the accumulator are used as a partial address (lower 8 bits
of PC) for accessing a location in the program memory. The
contents of this program memory location serve as a partial
address (lower 8 bits of PC) for the jump to the next instruction.
Reading memory locations 70-7F Hex will return all ones. Reading other
unused memory locations will return undefined data.
Note: The VIS is a special case of the Indirect Transfer of Control addressing mode, where the double byte vector associated with the interrupt
is transferred from adjacent addresses in the program memory into
the program counter (PC) in order to jump to the associated interrupt
service routine.
27
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Instruction Set
Register and Symbol Definition
Registers
A
B
X
SP
PC
PU
PL
C
HC
GIE
VU
VL
Symbols
[B]
8-Bit Accumulator Register
8-Bit Address Register
8-Bit Address Register
8-Bit Stack Pointer Register
15-Bit Program Counter Register
Upper 7 Bits of PC
Lower 8 Bits of PC
1 Bit of PSW Register for Carry
1 Bit of PSW Register for Half Carry
1 Bit of PSW Register for Global
Interrupt Enable
Interrupt Vector Upper Byte
Interrupt Vector Lower Byte
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[X]
MD
Mem
Meml
Imm
Reg
Bit
w
Ý
28
Memory Indirectly Addressed by B
Register
Memory Indirectly Addressed by X
Register
Direct Addressed Memory
Direct Addressed Memory or [B]
Direct Addressed Memory or [B] or
Immediate Data
8-Bit Immediate Data
Register Memory: Addresses F0 to FF
(Includes B, X and SP)
Bit Number (0 to 7)
Loaded with
Exchanged with
Instruction Set (Continued)
INSTRUCTION SET
ADD
ADC
A,Meml
A,Meml
ADD
ADD with Carry
SUBC
A,Meml
Subtract with Carry
AND
ANDSZ
OR
XOR
IFEQ
IFEQ
IFNE
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
RPND
A,Meml
A,Imm
A,Meml
A,Meml
MD,Imm
A,Meml
A,Meml
A,Meml
Logical AND
Logical AND Immed., Skip if Zero
Logical OR
Logical EXclusive OR
IF EQual
IF EQual
IF Not Equal
IF Greater Than
If B Not Equal
Decrement Reg., Skip if Zero
Set BIT
Reset BIT
IF BIT
Reset PeNDing Flag
A w A a Meml
A w A a Meml a C, C w Carry
HC w Half Carry
A w A b MemI a C, C w Carry
HC w Half Carry
A w A and Meml
Skip next if (A and Imm) e 0
A w A or Meml
A w A xor Meml
Compare MD and Imm, Do next if MD e Imm
Compare A and Meml, Do next if A e Meml
Compare A and Meml, Do next if A i Meml
Compare A and Meml, Do next if A l Meml
Do next if lower 4 bits of B i Imm
Reg w Regb 1, Skip if Reg e 0
1 to bit, Mem (bit e 0 to 7 immediate)
0 to bit, Mem
If bit in A or Mem is true do next instruction
Reset Software Interrupt Pending Flag
Ý
Reg
Ý,Mem
Ý,Mem
Ý,Mem
X
X
LD
LD
LD
LD
LD
A,Mem
A,[X]
A,Meml
A,[X]
B,Imm
Mem,Imm
Reg,Imm
EXchange A with Memory
EXchange A with Memory [X]
LoaD A with Memory
LoaD A with Memory [X]
LoaD B with Immed.
LoaD Memory Immed
LoaD Register Memory Immed.
A Ý Mem
A Ý [X]
A w Meml
A w [X]
B w Imm
Mem w Imm
Reg w Imm
X
X
LD
LD
LD
A, [B g ]
A, [X g ]
A, [B g ]
A, [X g ]
[B g ],Imm
EXchange A with Memory [B]
EXchange A with Memory [X]
LoaD A with Memory [B]
LoaD A with Memory [X]
LoaD Memory [B] Immed.
A Ý [B], (B w B g 1)
A Ý [X], (X w g 1)
A w [B], (B w B g 1)
A w [X], (X w X g 1)
[B] w Imm, (B w g 1)
CLR
INC
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
RC
IFC
IFNC
POP
PUSH
A
A
A
CLeaR A
INCrement A
DECrementA
Load A InDirect from ROM
Decimal CORrect A
Rotate A Right thru C
Rotate A Left thru C
SWAP nibbles of A
Set C
Reset C
IF C
IF Not C
POP the stack into A
PUSH A onto the stack
Aw0
AwA a 1
AwA b 1
A w ROM (PU,A)
A w BCD correction of A (follows ADC, SUBC)
C Ý A7 Ý . . . Ý A0 Ý C
C w A7 w . . . w A0 w C
A7 . . . A4 Ý A3 . . . A0
C w 1, HC w 1
C w 0, HC w 0
IF C is true, do next instruction
If C is not true, do next instruction
SP w SP a 1, A w [SP]
[SP] w A, SP w SP b 1
Vector to Interrupt Service Routine
Jump absolute Long
Jump absolute
Jump relative short
Jump SubRoutine Long
Jump SubRoutine
Jump InDirect
RETurn from subroutine
RETurn and SKip
RETurn from Interrupt
Generate an Interrupt
No OPeration
PU w [VU], PL w [VL]
PC w ii (ii e 15 bits, 0 to 32k)
PC9 . . . 0 w i (i e 12 bits)
PC w PC a r (r is b31 to a 32, except 1)
[SP] w PL, [SPb1] w PU,SPb2, PC w ii
[SP] w PL, [SPb1] w PU,SPb2, PC9 . . . 0 w i
PL w ROM (PU,A)
SP a 2, PL w [SP], PU w [SPb1]
SP a 2, PL w [SP],PU w [SPb1]
SP a 2, PL w [SP],PU w [SPb1],GIE w 1
[SP] w PL, [SPb1] w PU, SPb2, PC w 0FF
PC w PC a 1
VIS
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
A
A
A
A
A
A
Addr.
Addr.
Disp.
Addr.
Addr
29
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Instruction Execution Time
Most instructions are single byte (with immediate addressing mode instructions taking two bytes).
Most single byte instructions take one cycle time to execute.
Skipped instructions require x number of cycles to be
skipped, where x equals the number of bytes in the skipped
instruction opcode.
See the BYTES and CYCLES per INSTRUCTION table for
details.
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles
for each instruction in the format of byte/cycle.
Instructions Using A & C
CLRA
INCA
DECA
LAID
DCOR
RRCA
RLCA
SWAPA
SC
RC
IFC
IFNC
PUSHA
POPA
ANDSZ
Arithmetic and Logic Instructions
[B]
Direct
ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFNE
IFGT
IFBNE
DRSZ
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
SBIT
RBIT
IFBIT
1/1
1/1
1/1
RPND
1/1
Immed.
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/3
2/2
Transfer of Control
Instructions
JMPL
JMP
JP
JSRL
JSR
JID
VIS
RET
RETSK
RETI
INTR
NOP
1/3
3/4
3/4
3/4
Memory Transfer Instructions
Register
Indirect
X A,*
LD A,*
LD B, Imm
LD B, Imm
LD Mem, Imm
LD Reg, Imm
IFEQ MD, Imm
[B]
[X]
1/1
1/1
1/3
1/3
2/2
Direct Immed.
2/3
2/3
2/2
1/1
2/2
3/3
2/3
3/3
[B a , Bb]
[X a , Xb]
1/2
1/2
1/3
1/3
(IF B k 16)
(IF B l 15)
2/2
* e l Memory location addressed by B or X or directly.
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Register Indirect
Auto Incr. & Decr.
30
3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/5
1/7
1/1
Opcode Table
Upper Nibble Along X-Axis
Lower Nibble Along Y-Axis
F
E
D
C
JP b15
JP b31
LD 0F0, Ý i
DRSZ 0F0
RRCA
B
RC
ADC A,Ýi
ADC A,[B]
0
JP b14
JP b30
LD 0F1, Ý i
DRSZ 0F1
*
SC
SUBC A, Ýi
SUB A,[B]
1
JP b13
JP b29
LD 0F2, Ý i
DRSZ 0F2
X A, [X a ]
X A,[B a ]
IFEQ A,Ýi
IFEQ A,[B]
2
JP b12
JP b28
LD 0F3, Ý i
DRSZ 0F3
X A, [Xb]
X A,[Bb]
IFGT A,Ýi
IFGT A,[B]
3
JP b11
JP b27
LD 0F4, Ý i
DRSZ 0F4
VIS
LAID
ADD A,Ýi
ADD A,[B]
4
JP b10
JP b26
LD 0F5, Ý i
DRSZ 0F5
RPND
JID
AND A,Ýi
AND A,[B]
5
JP b9
JP b25
LD 0F6, Ý i
DRSZ 0F6
X A,[X]
X A,[B]
XOR A,Ýi
XOR A,[B]
6
JP b8
JP b24
LD 0F7, Ý i
DRSZ 0F7
*
*
OR A,Ýi
OR A,[B]
7
JP b7
JP b23
LD 0F8, Ý i
DRSZ 0F8
NOP
RLCA
LD A,Ýi
IFC
8
JP b6
JP b22
LD 0F9, Ý i
DRSZ 0F9
IFNE
A,[B]
IFEQ
Md,Ýi
IFNE
A,Ýi
IFNC
9
JP b5
JP b21
LD 0FA, Ý i
DRSZ 0FA
LD A,[X a ]
LD A,[B a ]
LD [B a ],Ýi
INCA
A
JP b4
JP b20
LD 0FB, Ý i
DRSZ 0FB
LD A,[Xb]
LD A,[Bb]
LD [Bb],Ýi
DECA
B
JP b3
JP b19
LD 0FC, Ý i
DRSZ 0FC
LD Md,Ýi
JMPL
X A,Md
POPA
C
JP b2
JP b18
LD 0FD, Ý i
DRSZ 0FD
DIR
JSRL
LD A,Md
RETSK
D
JP b1
JP b17
LD 0FE, Ý i
DRSZ 0FE
LD A,[X]
LD A,[B]
LD [B],Ýi
RET
E
JP b0
JP b16
LD 0FF, Ý i
DRSZ 0FF
*
*
LD B,Ýi
RETI
F
31
A
9
8
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Opcode Table (Continued)
Upper Nibble Along X-Axis
Lower Nibble Along Y-Axis
7
6
5
3
2
1
IFBIT
0,[B]
ANDSZ
A, Ýi
LD B,Ý0F
IFBNE 0
4
JSR
x000 – x0FF
JMP
x000 – x0FF
JP a 17
INTR
0
IFBIT
1,[B]
*
LD B,Ý0E
IFBNE 1
JSR
x100 – x1FF
JMP
x100 – x1FF
JP a 18
JP a 2
1
IFBIT
2,[B]
*
LD B,Ý0D
IFBNE 2
JSR
x200 – x2FF
JMP
x200 – x2FF
JP a 19
JP a 3
2
IFBIT
3,[B]
*
LD B,Ý0C
IFBNE 3
JSR
x300 – x3FF
JMP
x300 – x3FF
JP a 20
JP a 4
3
IFBIT
4,[B]
CLRA
LD B,Ý0B
IFBNE 4
JSR
x400 – x4FF
JMP
x400 – x4FF
JP a 21
JP a 5
4
IFBIT
5,[B]
SWAPA
LD B,Ý0A
IFBNE 5
JSR
x500 – x5FF
JMP
x500 – x5FF
JP a 22
JP a 6
5
IFBIT
6,[B]
DCORA
LD B,Ý09
IFBNE 6
JSR
x600 – x6FF
JMP
x600 – x6FF
JP a 23
JP a 7
6
IFBIT
7,[B]
PUSHA
LD B,Ý08
IFBNE 7
JSR
x700 – x7FF
JMP
x700 – x7FF
JP a 24
JP a 8
7
SBIT
0,[B]
RBIT
0,[B]
LD B,Ý07
IFBNE 8
JSR
x800 – x8FF
JMP
x800 – x8FF
JP a 25
JP a 9
8
SBIT
1,[B]
RBIT
1,[B]
LD B,Ý06
IFBNE 9
JSR
x900 – x9FF
JMP
x900 – x9FF
JP a 26
JP a 10
9
SBIT
2,[B]
RBIT
2,[B]
LD B,Ý05
IFBNE 0A
JSR
xA00 – xAFF
JMP
xA00 – xAFF
JP a 27
JP a 11
A
SBIT
3,[B]
RBIT
3,[B]
LD B,Ý04
IFBNE 0B
JSR
xB00 – xBFF
JMP
xB00 – xBFF
JP a 28
JP a 12
B
SBIT
4,[B]
RBIT
4,[B]
LD B,Ý03
IFBNE 0C
JSR
xC00 – xCFF
JMP
xC00 – xCFF
JP a 29
JP a 13
C
SBIT
5,[B]
RBIT
5,[B]
LD B,Ý02
IFBNE 0D
JSR
xD00 – xDFF
JMP
xD00 – xDFF
JP a 30
JP a 14
D
SBIT
6,[B]
RBIT
6,[B]
LD B,Ý01
IFBNE 0E
JSR
xE00 – xEFF
JMP
xE00 – xEFF
JP a 31
JP a 15
E
SBIT
7,[B]
RBIT
7,[B]
LD B,Ý00
IFBNE 0F
JSR
xF00 – xFFF
JMP
xF00 – xFFF
JP a 32
JP a 16
F
Where,
i is the immediate data
Md is a directly addressed memory location
* is an unused opcode
Note: The opcode 60 Hex is also the opcode for IFBIT Ýi,A
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32
0
Mask Options
Development Support
The mask programmable options are shown below. The options are programmed at the same time as the ROM pattern
submission.
SUMMARY
# iceMASTERTM : IM-COP8/400ÐFull feature in-circuit emulation for all COP8 products. A full set of COP8 Basic
and Feature Family device and package specific probes
are available.
OPTION 1: CLOCK CONFIGURATION
4 1
Crystal Oscillator (CKI/10)
G7 (CKO) is clock generator
output to crystal/resonator
CKI is the clock input
4 2
Single-pin RC controlled
oscillator (CKI/10)
G7 is available as a HALT
restart and/or general purpose
input
# COP8 Debug Module: Moderate cost in-circuit emulation
and development programming unit.
# COP8
Evaluation and Programming Unit: EPUCOP888GGÐlow cost in-circuit simulation and development programming unit.
# Assembler: COP8-DEV-IBMA. A DOS installable cross
development Assembler, Linker, Librarian and Utility
Software Development Tool Kit.
# C Compiler: COP8C. A DOS installable cross develop-
OPTION 2: HALT
4 1
Enable HALT mode
4 2
Disable HALT mode
ment Software Tool kit.
# OPT/EPROM Programmer Support: Covering needs
from engineering prototype, pilot production to full production environments.
OPTION 3: BONDING
4 1
44-Pin PCC
4 2
40-Pin DIP
4 3
N.A.
4 4
28-Pin DIP
4 5
28-Pin SO
33
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Development Support (Continued)
# Single base unit and debugger software reconfigurable to
IceMASTER (IM) IN-CIRCUIT EMULATION
The iceMASTER IM-COP8/400 is a full feature, PC based,
in-circuit emulation tool developed and marketed by MetaLink Corporation to support the whole COP8 family of products. National is a resale vendor for these products.
See Figure 19 for configuration.
support the entire COP8 family; only the probe personality needs to change. Debugger software is processor customized, and reconfigured from a master model file.
# Processor specific symbolic display of registers and bit
level assignments, configured from master model file.
# Halt/Idle mode notification.
# On-line HELP customized to specific processor using
The iceMASTER IM-COP8/400 with its device specific
COP8 Probe provides a rich feature set for developing, testing and maintaining product:
master model file.
# Includes a copy of COP8-DEV-IBMA assembler and link-
# Real-time in-circuit emulation; full 2.4V–5.5V operation
er SDK.
range, full DC-10 MHz clock. Chip options are programmable or jumper selectable.
IM Order Information
# Direct connection to application board by package com-
Base Unit
patible socket or surface mount assembly.
# Full 32 kbyte of loadable programming space that overlays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated on
the probe as necessary.
IM-COP8/400-1
iceMASTER Base Unit,
110V Power Supply
IM-COP8/400-2
iceMASTER Base Unit,
220V Power Supply
# Full 4k frame synchronous trace memory. Address, iniceMASTER Probe
struction, and 8 unspecified, circuit connectable trace
lines. Display can be HLL source (e.g., C source), assembly or mixed.
MHW-884CL28DWPC
# A full 64k hardware configurable break, trace on, trace
off control, and pass count increment events.
# Tool set integrated interactive symbolic debuggerÐsup-
28 DIP
MHW-888CL40DWPC
40 DIP
MHW-888CL44PWPC
44 PLCC
Adapter for SO package
ports both assembler (COFF) and C Compiler (.COD)
linked object formats.
MHW-SO -SOIC28
28 SO
# Real time performance profiling analysis; selectable
bucket definition.
# Watch windows, content updated automatically at each
execution break.
# Instruction by instruction memory/register changes displayed on source window when in single step operation.
TL/DD/9766 – 35
FIGURE 19. COP8 iceMASTER Environment
http://www.national.com
34
Development Support (Continued)
# Debugger software is processed customized, and recon-
IceMASTER DEBUG MODULE (DM)
The iceMASTER IM-COP8/400 is a PC based, combination
in-circuit emulation tool and COP8 based OPT/EPROM programming tool developed and marketed by MetaLink Corporation to support the whole COP8 family of products. National is a resale vendor for these products.
See Figure 20 for configuration.
figured from a master model file.
# Processor specific symbolic display of registers and bit
level assignments, configured from master model file.
# Halt/Idle mode notification.
# Programming menu supports full product line of programmable OTP and EPROM COP8 products. Program data
is taken directly from the overlay RAM.
The iceMASTER Debug Module is a moderate cost development tool. It has the capability of in-circuit emulation for a
specific COP8 microcontroller and in addition serves as a
programming tool for COP8 OTP and EPROM product families. Summary of features is as follows:
# Programming of 44PLCC and 68PLCC parts requires external programming adapters.
# Includes wallmount power supply.
# On-board VPP generator from 5V input or connection to
# Real-time in-circuit emulation; full operating voltage
external supply supported. Requires VPP level adjustment per the family programming specification (correct
level is provided on an on-screen pop-down display).
range operation, full DC-10 MHz clock.
# All processor I/O pins can be cabled to an application
development board with package compatible cable to
socket and surface mount assembly.
# ON-Line HELP customized to specific processor using
# Full 32 kbyte of loadable programming space that over-
# Includes a copy of COP8-DEV-IBMA assembler and link-
master model file.
lays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated on
the probe as necessary.
er SDK.
DM Order Information
# 100 frames of synchronous trace memory. The display
Debug Module Unit
can be HLL source (C source), assembly or mixed. The
most recent history prior to a break is available in the
trace memory.
COP8-DM/888CF
Cable Adapters
# Configured break points; uses INTR instruction which is
DM-COP8/28D
modestly intrusive.
# SoftwareÐonly supported features are selectable.
# Tool set integrated interactive symbolic debugger - supports both assembler (COFF) and C Compiler (.COD)
SDK linked object formats.
28 DIP
DM-COP8/40D
40 DIP
DM-COP8/44P
44 PLCC
Adapter for SO package
MHW-SO -SOIC28
# Instruction by instruction memory/register changes dis-
28 SO
played when in single step operation.
TL/DD/9766 – 36
FIGURE 20. COP8-DM Environment
35
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Development Support (Continued)
COP8 ASSEMBLER/LINKER SOFTWARE
DEVELOPMENT TOOL KIT
COP8 C COMPILER
A C Compiler is developed and marketed by Byte Craft Limited. The COP8C compiler is a fully integrated development
tool specifically designed to support the compact embedded configuration of the COP8 family of products.
Features are summarized as follows:
National Semiconductor offers a relocateable COP8 macro
cross assembler, linker, librarian and utility software development tool kit. Features are summarized as follows:
# Basic and Feature Family instruction set by ‘‘device’’
type
#
#
#
#
#
#
#
# ANSI C with some restrictions and extensions that optimize development for the COP8 embedded application.
Nested macro capability.
Extensive set of assembler directives.
Supported on PC/DOS platform.
Generates National standard COFF output files.
# BITS data type extension. Register declaration Ýpragma
with direct bit level definitions.
# C language support for interrupt routines.
# Expert system, rule based code geration and optimiza-
Integrated Linker and Librarian.
Integrated utilities to generate ROM code file outputs.
DUMPCOFF utility.
This product is integrated as a part of MetaLink tools as a
development kit, fully supported by the MetaLink debugger.
It may be ordered separately or it is bundled with the MetaLink products at no additional cost.
Order Information
tion.
# Performs consistency checks against the architectural
definitions of the target COP8 device.
# Generates program memory code.
# Supports linking of compiled object or COP8 assembled
object formats.
# Global optimization of linked code.
# Symbolic debug load format fully source level supported
Assembler SDK:
COP8-DEV-IBMA
by the MetaLink debugger.
Assembler SDK on installable 3.5×
PC/DOS Floppy Disk Drive format.
Periodic upgrades and most recent
version is available on National’s
BBS and Internet.
Approved List
Manufacturer
North
America
Europe
Asia
BP
Microsystems
(800) 225-2102
(713) 688-4600
Fax: (713) 688-0920
a 49-8152-4183
a 49-8856-932616
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36
Development Support (Continued)
DIAL-A-HELPER via FTP
SINGLE CHIP OTP/EMULATOR SUPPORT
The COP8 family is supported by single chip OTP emulators. For detailed information refer to the emulator specific
datasheet and the emulator selection table below:
ftp nscmicro.nsc.com
user:
password:
OTP Emulator Ordering Information
Device Number
Clock
Option
Package
COP87L84CLN-XE
Crystal
28 DIP
COP884CL
COP87L84CLM-XE
Crystal
28 SO
COP884CL
COP87L88CLN-XE
Crystal
40 DIP
COP888CL
COP87L88CLV-XE
Crystal
44 PLCC
COP888CL
anonymous
username @ yourhost.site.domain
DIAL-A-HELPER via a WorldWide Web Browser
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Emulates
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Deutsch
AVAILABLE LITERATURE
For more information, please see the COP8 Basic Family
User’s Manual, Literature Number 620895, COP8 Feature
Family User’s Manual, Literature Number 620897 and National’s Family of 8-bit Microcontrollers COP8 Selection
Guide, Literature Number 630009.
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DIAL-A-HELPER SERVICE
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The Dial-A-Helper system provides access to an automated
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DIAL-A-HELPER BBS via a Standard Modem
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( a 49) 0-8141-351332
Baud:
Set-Up:
Operation:
14.4k
Length:
Parity:
Stop Bit:
24 Hours,
8-Bit
None
1
7 Days
37
http://www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted
28-Lead Small Outline Package (M)
Order Number COP684CL-XXX/WM, COP884CL-XXX/WM, COP984CL-XXX/WM or COP984CLH-XXX/WM
NS Package Number M28B
http://www.national.com
38
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
Order Number COP684CL-XXX/N, COP884CL-XXX/N, COP984CL-XXX/N or COP984CLH-XXX/N
NS Package Number N28B
Molded Dual-In-Line Package (N)
Order Number COP688CL-XXX/N, COP888CL-XXX/N, COP988CL-XXX/N or COP988CLH-XXX/N
NS Package Number N40A
39
http://www.national.com
COP688CL/COP684CL, COP888CL/COP884CL,
COP988CL/COP984CL 8-Bit Microcontroller
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Plastic Leaded Chip Carrier (V)
Order Number COP688CL-XXX/V, COP888CL-XXX/V, COP988CL-XXX/V, COP988CLH-XXX/V
NS Package Number V44A
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