TI BQ24316DSG Overvoltage and overcurrent protection ic and li charger front-end protection ic Datasheet

bq24314
bq24316
www.ti.com
SLUS763C – JULY 2007 – REVISED OCTOBER 2007
OVERVOLTAGE AND OVERCURRENT PROTECTION IC AND
Li+ CHARGER FRONT-END PROTECTION IC
•
FEATURES
1
• Provides Protection for Three Variables:
– Input Overvoltage, with Rapid Response in
< 1 μs
– User-Programmable Overcurrent with
Current Limiting
– Battery Overvoltage
• 30V Maximum Input Voltage
• Supports up to 1.5A Input Current
• Robust Against False Triggering Due to
Current Transients
• Thermal Shutdown
• Enable Input
• Status Indication – Fault Condition
2
Available in Space-Saving Small 8 Lead 2×2
SON and 12 Lead 4x3 SON Packages
APPLICATIONS
•
•
•
•
•
Mobile Phones and Smart Phones
PDAs
MP3 Players
Low-Power Handheld Devices
Bluetooth Headsets
DESCRIPTION
The bq24314 and bq24316 are highly integrated circuits designed to provide protection to Li-ion batteries from
failures of the charging circuit. The IC continuously monitors the input voltage, the input current, and the battery
voltage. In case of an input overvoltage condition, the IC immediately removes power from the charging circuit by
turning off an internal switch. In the case of an overcurrent condition, it limits the system current at the threshold
value, and if the overcurrent persists, switches the pass element OFF after a blanking period. Additionally, the IC
also monitors its own die temperature and switches off if it becomes too hot. The input overcurrent threshold is
user-programmable.
The IC can be controlled by a processor and also provides status information about fault conditions to the host.
APPLICATION SCHEMATIC
AC Adapter
1 IN
VDC
OUT 8
1 mF
1 mF
GND
bq24080
Charger IC
bq24316DSG
SYSTEM
VBAT 6
VSS
ILIM
FAULT 4
2
7
CE 5
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
bq24314
bq24316
www.ti.com
SLUS763C – JULY 2007 – REVISED OCTOBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
DEVICE (2)
OVP THRESHOLD
PACKAGE
MARKING
bq24314DSG
5.85 V
2mm x 2mm SON CBV
bq24314DSJ
5.85 V
4mm x 3mm SON CBX
bq24316DSG
6.80 V
2mm x 2mm SON CBW
bq24316DSJ
6.80 V
4mm x 3mm SON BZC
(1)
(2)
For the most current package and ordering information, see the
Package Option Addendum at the end of this document, or see the
TI website at www.ti.com.
To order a 3000 pcs reel add R to the part number, or to order a 250
pcs reel add T to the part number.
PACKAGE DISSIPATION RATINGS
PART NO.
PACKAGE
RθJC
RθJA
BQ24314DSG
BQ24316DSG
2×2 SON
5°C/W
75°C/W
BQ24314DSJ
BQ24316DSJ
4×3 SON
5°C/W
40°C/W
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Input voltage
PIN
VALUE
UNIT
IN (with respect to VSS)
–0.3 to 30
OUT (with respect to VSS)
–0.3 to 12
ILIM, FAULT, CE, VBAT (with respect to VSS)
–0.3 to 7
V
Input current
IN
2.0
Output current
OUT
2.0
A
Output sink current
FAULT
15
mA
Junction temperature, TJ
–40 to 150
°C
Storage temperature, TSTG
–65 to 150
°C
300
°C
Lead temperature (soldering, 10 seconds)
(1)
A
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
3.3
26
V
Input current, IN pin
1.5
A
Output current, OUT pin
1.5
A
15.0
90.0
kΩ
0
125
°C
VIN
Input voltage range
IIN
IOUT
RILIM
OCP Programming resistor
TJ
Junction temperature
2
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UNIT
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): bq24314 bq24316
bq24314
bq24316
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SLUS763C – JULY 2007 – REVISED OCTOBER 2007
ELECTRICAL CHARACTERISTICS
over junction temperature range 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
IN
VUVLO
Under-voltage lock-out, input
power detected threshold
CE = Low, VIN increasing from 0V to 3V
2.6
2.7
2.8
V
VHYS-UVLO
Hysteresis on UVLO
CE = Low, VIN decreasing from 3V to 0V
200
260
300
mV
TDGL(PGOOD)
Deglitch time, input power
detected status
CE = Low. Time measured from VIN 0V → 5V 1μs rise-time,
to output turning ON
IDD
Operating current
CE = Low, No load on OUT pin,
VIN = 5V, RILIM = 25kΩ
ISTDBY
Standby current
CE = High, VIN = 5.0V
8
ms
400
600
μA
65
95
μA
170
280
mV
5.71
5.85
6.00
V
6.60
6.80
7.00
V
1
μs
110
mV
INPUT TO OUTPUT CHARACTERISTICS
VDO
Drop-out voltage IN to OUT
CE = Low, VIN = 5V, IOUT = 1A
INPUT OVERVOLTAGE PROTECTION
VOVP
Input overvoltage
protection
threshold
bq24314
tPD(OVP)
Input OV propagation delay (1)
CE = Low
VHYS-OVP
Hysteresis on OVP
CE = Low, VIN decreasing from 7.5V to 5V
tON(OVP)
Recovery time from input
overvoltage condition
CE = Low, Time measured from
VIN 7.5V → 5V, 1μs fall-time
bq24316
CE = Low, VIN increasing from 5V to 7.5V
25
60
8
ms
INPUT OVERCURRENT PROTECTION
IOCP
Input overcurrent protection
threshold range
IOCP
Input overcurrent protection
threshold
tBLANK(OCP)
Blanking time, input overcurrent
detected
tREC(OCP)
Recovery time from input
overcurrent condition
300
CE = Low, RILIM = 25kΩ
1500
mA
930 1000 1070
mA
176
μs
64
ms
BATTERY OVERVOLTAGE PROTECTION
BVOVP
Battery overvoltage protection
threshold
CE = Low, VIN > 4.4V
4.30
4.35
4.4
V
VHYS-BOVP
Hysteresis on BVOVP
CE = Low, VIN > 4.4V
200
275
320
mV
IVBAT
TDGL(BOVP)
Input bias current
on VBAT pin
DSG
Package
VBAT = 4.4V, TJ = 25°C
10
DSJ
Package
VBAT = 4.4V, TJ = 85°C
10
nA
Deglitch time, battery overvoltage CE = Low, VIN > 4.4V. Time measured from VVBAT rising from
detected
4.1V to 4.4V to FAULT going low.
μs
176
THERMAL PROTECTION
TJ(OFF)
Thermal shutdown temperature
TJ(OFF-HYS)
Thermal shutdown hysteresis
140
150
°C
°C
20
LOGIC LEVELS ON CE
VIL
Low-level input voltage
0
VIH
High-level input voltage
1.4
0.4
V
IIL
Low-level input current
VCE = 0V
1
μA
IIH
High-level input current
VCE = 1.8V
15
μA
V
LOGIC LEVELS ON FAULT
VOL
Output low voltage
ISINK = 5mA
0.2
V
IHI-Z
Leakage current, FAULT pin HI-Z VFAULT = 5V
10
μA
(1)
Not tested in production. Specified by design.
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SLUS763C – JULY 2007 – REVISED OCTOBER 2007
Q1
IN
Charge Pump,
Bandgap,
Bias Gen
OUT
VBG
ISNS
ILIM
ILIMREF
Current limiting
loop
OFF
OCP comparator
ILIMREF - Δ
t BLANK(OCP)
ISNS
FAULT
VIN
VBG
COUNTERS,
CONTROL,
AND STATUS
OVP
VIN
CE
VBG
t DGL(PGOOD)
UVLO
VBAT
THERMAL
SHUTDOW
VBG
t DGL(BOVP)
VSS
Figure 1. Simplified Block Diagram
4
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SLUS763C – JULY 2007 – REVISED OCTOBER 2007
TERMINAL FUNCTIONS
TERMINAL
NAME
I/O
DESCRIPTION
DSJ
DSG
1, 2
1
I
Input power, connect to external DC supply. Connect external 1μF ceramic capacitor (minimum) to
VSS. For the 12 pin (DSJ-suffix) device, ensure that pins 1 and 2 are connected together on the
PCB at the device.
OUT
10, 11
8
O
Output terminal to the charging system. Connect external 1μF ceramic capacitor (minimum) to VSS.
VBAT
8
6
I
Battery voltage sense input. Connect to pack positive terminal through a resistor.
9
7
I/O
Input overcurrent threshold programming. Connect a resistor to VSS to set the overcurrent
threshold.
CE
7
5
I
Chip enable input. Active low. When CE = High, the input FET is off. Internally pulled down.
FAULT
4
4
O
Open-drain output, device status. FAULT = Low indicates that the input FET Q1 has been turned off
due to input overvoltage, input overcurrent, battery overvoltage, or thermal shutdown.
VSS
3
2
–
Ground terminal
NC
5, 6, 12
3
IN
ILIM
Thermal
PAD
These pins may have internal circuits used for test purposes. Do not make any external connections
at these pins for normal operation.
–
There is an internal electrical connection between the exposed thermal pad and the VSS pin of the
device. The thermal pad must be connected to the same potential as the VSS pin on the printed
circuit board. Do not use the thermal pad as the primary ground input for the device. The VSS pin
must be connected to ground at all times.
IN 1
8
7
VSS 2
NC 3
IN 1
12 NC
IN 2
11
OUT
10
OUT
OUT
ILIM
VSS 3
bq24314DSG
bq24316DSG
6
bq24314DSJ
bq24316DSJ
VBAT
FAULT 4
FAULT 4
5
CE
9 ILIM
NC 5
8 VBAT
NC 6
7 CE
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SLUS763C – JULY 2007 – REVISED OCTOBER 2007
TYPICAL OPERATING PERFORMANCE
Test conditions (unless otherwise noted) for typical operating performance: VIN = 5 V, CIN = 1 μF, COUT = 1 μF,
RILIM = 25 kΩ, RBAT = 100 kΩ, TA = 25°C, VPU = 3.3V (see Figure 23 for the Typical Application Circuit)
VIN
VIN
VOUT
VOUT
IOUT
FAULT
Figure 2. Normal Power-On Showing Soft-Start,
ROUT = 6.6Ω
Figure 3. OVP at Power-On, VIN = 0V to 9V, tr = 50μs
VIN
VIN
Max VOUT = 6.84 V
Max VOUT = 6.76 V
VOUT
VOUT
FAULT
FAULT
Figure 4. bq24316 OVP Response for Input Step, VIN = 5V
to 12V, tr = 1μs
Figure 5. bq24316 OVP Response for Input Step, VIN = 5V
to 12V, tr = 20μs
VIN
VIN
Max VOUT = 6.84 V
Max VOUT = 6.76 V
VOUT
VOUT
FAULT
FAULT
Figure 6. bq24314 OVP Response for Input Step, VIN = 5V
to 12V, tr = 1μs
6
Figure 7. bq24314 OVP Response for Input Step, VIN = 5V
to 12V, tr = 20μs
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SLUS763C – JULY 2007 – REVISED OCTOBER 2007
TYPICAL OPERATING PERFORMANCE (continued)
VIN
VIN
VOUT
IOUT
IOUT
VOUT
FAULT
FAULT
Figure 8. Recovery from OVP, VIN = 7.5V to 5V, tf = 400μs
Figure 9. OCP, Powering Up into a Short Circuit on OUT
Pin, OCP Counter Counts to 15 Before Switching OFF the
Device
VIN
VIN
VOUT
IOUT
IOUT
VOUT
FAULT
FAULT
Figure 10. OCP, Zoom-in on the First Cycle of Figure 9
Figure 11. OCP, ROUT Switches from 6.6Ω to 3.3Ω, Shows
Current Limiting and Soft-Stop
VOUT
VVBAT
Begin
soft-stop
VOUT
VVBAT
tDGL(BAT-OVP)
= 220 ms
FAULT
FAULT
Figure 12. BAT-OVP, VVBAT Steps from 4.2V to 4.4V,
Shows tDGL(BAT-OVP) and Soft-Stop
Figure 13. BAT-OVP, VVBAT Cycles Between 4.1V and 4.4V,
Shows BAT-OVP Counter
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SLUS763C – JULY 2007 – REVISED OCTOBER 2007
TYPICAL OPERATING PERFORMANCE (continued)
UNDERVOLTAGE LOCKOUT
vs
FREE-AIR TEMPERATURE
DROPOUT VOLTAGE (IN to OUT)
vs
FREE-AIR TEMPERATURE
280
2.75
260
2.7
VIN Increasing
240
VIN = 4 V
220
VDO @ 1A - mV
VUVLO, VHYS-UVLO - V
2.65
2.6
2.55
200
VIN = 5 V
180
160
2.5
140
VIN Decreasing
2.45
2.4
-50
120
100
-30
-10
10
30
50
70
Temperature - °C
90
110
0
130
50
100
150
Temperature - °C
Figure 14.
Figure 15.
OVERVOLTAGE THRESHOLD PROTECTION (bq24316)
vs
FREE-AIR TEMPERATURE
OVERVOLTAGE THRESHOLD PROTECTION (bq24314)
vs
FREE-AIR TEMPERATURE
5.88
6.82
6.8
5.86
6.78
VOVP, VHYS-OVP - V
VOVP, VHYS-OVP - V
VIN Increasing
6.76
6.74
5.84
VIN Increasing
5.82
VIN Decreasing
5.8
6.72
6.7
-50
VIN Decreasing
-30
-10
10
30
50
70
Temperature - °C
90
110
5.78
-50
130
-30
-10
10
30
50
70
90
110
130
Temperature - °C
Figure 16.
Figure 17.
INPUT OVERCURRENT PROTECTION
vs
ILIM RESISTANCE
INPUT OVERCURRENT PROTECTION
vs
FREE-AIR TEMPERATURE
985
1600
984
1400
983
1200
982
IOCP - mA
IOCP - mA
1000
800
981
980
979
600
978
400
977
200
0
0
976
10
20
30
40
50
60
RILIM - kW
70
80
90
100
975
-50
-30
Figure 18.
8
-10
10
30
50
70
Temperature - °C
90
110
130
Figure 19.
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SLUS763C – JULY 2007 – REVISED OCTOBER 2007
TYPICAL OPERATING PERFORMANCE (continued)
BATTERY OVERVOLTAGE PROTECTION
vs
FREE-AIR TEMPERATURE
LEAKAGE CURRENT (VBAT Pin)
vs
FREE-AIR TEMPERATURE
4.4
2.5
4.35
BVOVP (VVBAT Increasing)
2
1.5
4.25
IVBAT - nA
BVOVP - V
4.3
4.2
1
4.15
0.5
4.1
4.05
-50
Bat-OVP Recovery (VVBAT Decreasing)
-30
-10
10
30
50
70
Temperature - °C
90
110
0
-50
130
-30
-10
10
Figure 20.
30
50
70
Temperature - °C
90
110
130
Figure 21.
SUPPLY CURRENT (bq24314)
vs
INPUT VOLTAGE
900
800
IDD (CE = Low)
IDD, ISTDBY - mA
700
600
500
400
300
200
ISTDBY (CE = High)
100
0
0
5
10
15
20
25
30
35
VIN - V
Figure 22.
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SLUS763C – JULY 2007 – REVISED OCTOBER 2007
TYPICAL APPLICATION CIRCUIT
VOVP = 6.8V, IOCP = 1000mA, BVOVP = 4.35V (Terminal numbers shown are for the 2×2 DSG package)
AC Adapter
VDC
1
IN
OUT 8
CIN
GND
COUT
1 mF
1 mF
bq24080
Charger IC
bq24316DSG
RBAT
SYSTEM
VBAT 6
100 kW
VPU
RPU
47 kW
47 kW
FAULT 4
RFAULT
ILIM
VSS
47 kW
7
2
CE 5
Host
Controller
RCE
RILM
25 kW
Figure 23.
DETAILED FUNCTIONAL DESCRIPTION
The bq24314 and bq24316 are highly integrated circuits designed to provide protection to Li-ion batteries from
failures of the charging circuit. The IC continuously monitors the input voltage, the input current and the battery
voltage. In case of an input overvoltage condition, the IC immediately removes power from the charging circuit by
turning off an internal switch. In the case of an overcurrent condition, it limits the system current at the threshold
value, and if the overcurrent persists, switches the pass element OFF after a blanking period. If the battery
voltage rises to an unsafe level, the IC disconnects power from the charging circuit until the battery voltage
returns to an acceptable value. Additionally, the IC also monitors its own die temperature and switches off if it
becomes too hot. The input overcurrent threshold is user-programmable. The IC can be controlled by a
processor, and also provides status information about fault conditions to the host.
POWER DOWN
The device remains in power down mode when the input voltage at the IN pin is below the undervoltage
threshold VUVLO. The FET Q1 connected between IN and OUT pins is off, and the status output, FAULT, is set to
Hi-Z.
POWER-ON RESET
The device resets when the input voltage at the IN pin exceeds the UVLO threshold. All internal counters and
other circuit blocks are reset. The IC then waits for duration tDGL(PGOOD) for the input voltage to stabilize. If, after
tDGL(PGOOD), the input voltage and battery voltage are safe, FET Q1 is turned ON. The IC has a soft-start feature
to control the inrush current. The soft-start minimizes the ringing at the input (the ringing occurs because the
parasitic inductance of the adapter cable and the input bypass capacitor form a resonant circuit). Figure 2 shows
the power-up behavior of the device. Because of the deglitch time at power-on, if the input voltage rises rapidly to
beyond the OVP threshold, the device will not switch on at all, instead it will go into protection mode and indicate
a fault on the FAULT pin, as shown in Figure 3.
10
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SLUS763C – JULY 2007 – REVISED OCTOBER 2007
OPERATION
The device continuously monitors the input voltage, the input current, and the battery voltage as described in
detail in the following sections.
Input Overvoltage Protection
If the input voltage rises above VOVP, the internal FET Q1 is turned off, removing power from the circuit. As
shown in Figure 4 to Figure 7, the response is very rapid, with the FET turning off in less than a microsecond.
The FAULT pin is driven low. When the input voltage returns below VOVP – VHYS-OVP (but is still above VUVLO), the
FET Q1 is turned on again after a deglitch time of tON(OVP) to ensure that the input supply has stabilized. Figure 8
shows the recovery from input OVP.
Input Overcurrent Protection
The overcurrent threshold is programmed by a resistor RILIM connected from the ILIM pin to VSS. Figure 18
shows the OCP threshold as a function of RILIM, and may be approximated by the following equation:
IOCP = 25 ÷ RILIM (current in A, resistance in kΩ)
If the load current tries to exceed the IOCP threshold, the device limits the current for a blanking duration of
tBLANK(OCP). If the load current returns to less than IOCP before tBLANK(OCP) times out, the device continues to
operate. However, if the overcurrent situation persists for tBLANK(OCP), the FET Q1 is turned off for a duration of
tREC(OCP), and the FAULT pin is driven low. The FET is then turned on again after tREC(OCP) and the current is
monitored all over again. Each time an OCP fault occurs, an internal counter is incremented. If 15 OCP faults
occur in one charge cycle, the FET is turned off permanently. The counter is cleared either by removing and
re-applying input power, or by disabling and re-enabling the device with the CE pin. Figure 9 to Figure 11 show
what happens in an overcurrent fault.
To prevent the input voltage from spiking up due to the inductance of the input cable, Q1 is turned off slowly,
resulting in a “soft-stop”, as shown in Figure 11.
Battery Overvoltage Protection
The battery overvoltage threshold BVOVP is internally set to 4.35V. If the battery voltage exceeds the BVOVP
threshold, the FET Q1 is turned off, and the FAULT pin is driven low. The FET is turned back on once the battery
voltage drops to BVOVP – VHYS-BOVP (see Figure 12 and Figure 13). Each time a battery overvoltage fault occurs,
an internal counter is incremented. If 15 such faults occur in one charge cycle, the FET is turned off permanently.
The counter is cleared either by removing and re-applying input power, or by disabling and re-enabling the
device with the CE pin. In the case of a battery overvoltage fault, Q1 is switched OFF gradually (see Figure 12).
Thermal Protection
If the junction temperature of the device exceeds TJ(OFF), the FET Q1 is turned off, and the FAULT pin is driven
low. The FET is turned back on when the junction temperature falls below TJ(OFF) – TJ(OFF-HYS).
Enable Function
The IC has an enable pin which can be used to enable or disable the device. When the CE pin is driven high, the
internal FET is turned off. When the CE pin is low, the FET is turned on if other conditions are safe. The OCP
counter and the Bat-OVP counter are both reset when the device is disabled and re-enabled. The CE pin has an
internal pulldown resistor and can be left floating. Note that the FAULT pin functionality is also disabled when the
CE pin is high.
Fault Indication
The FAULT pin is an active-low open-drain output. It is in a high-impedance state when operating conditions are
safe, or when the device is disabled by setting CE high. With CE low, the FAULT pin goes low whenever any of
these events occurs:
• Input overvoltage
• Input overcurrent
• Battery overvoltage
• IC Overtemperature
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Power Down
All IC functions OFF
FAULT = HiZ
V(IN) > V(UVLO) ?
Any State
if V(IN) < V (UVLO),
go to Power Down
No
Any State
if CE = Hi,
go to Reset
Yes
Reset
Timers reset
Counters reset
FAULT = HiZ
FET off
No
CE = Low ?
V(IN) < V(OVP) ?
No
Turn off FET
FAULT = Low
No
CE = Hi ?
Yes
Go to Reset
Yes
No
I < IOCP ?
No
Turn off FET
FAULT = Low
Incr OCP counter
Wait tREC(OCP)
count <15 ?
Yes
No
CE = Hi ?
Yes
Go to Reset
No
Turn off FET
FAULT = Low
VBAT < BATOVP ?
No Incr BAT counter
count <15 ?
Yes
TJ < TJ(OFF) ?
No
Turn off FET
FAULT = Low
Yes
Turn on FET
FAULT = HiZ
Figure 24. Flow Diagram
12
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APPLICATION INFORMATION (WITH REFERENCE TO FIGURE 23)
Selection of RBAT
It is strongly recommended that the battery not be tied directly to the VBAT pin of the device, as under some
failure modes of the IC, the voltage at the IN pin may appear on the VBAT pin. This voltage can be as high as
30V, and applying 30V to the battery in case of the failure of the bq2431x can be hazardous. Connecting the
VBAT pin through RBAT prevents a large current from flowing into the battery in case of a failure of the IC. In the
interests of safety, RBAT should have a very high value. The problem with a large RBAT is that the voltage drop
across this resistor because of the VBAT bias current IVBAT causes an error in the BVOVP threshold. This error is
over and above the tolerance on the nominal 4.35V BVOVP threshold.
Choosing RBAT in the range 100kΩ to 470kΩ is a good compromise. In the case of an IC failure, with RBAT equal
to 100kΩ, the maximum current flowing into the battery would be (30V – 3V) ÷ 100kΩ = 246μA, which is low
enough to be absorbed by the bias currents of the system components. RBAT equal to 100kΩ would result in a
worst-case voltage drop of RBAT × IVBAT = 1mV. This is negligible to compared to the internal tolerance of 50mV
on BVOVP threshold.
If the Bat-OVP function is not required, the VBAT pin should be connected to VSS.
Selection of RCE, RFAULT, and RPU
The CE pin can be used to enable and disable the IC. If host control is not required, the CE pin can be tied to
ground or left un-connected, permanently enabling the device.
In applications where external control is required, the CE pin can be controlled by a host processor. As in the
case of the VBAT pin (see above), the CE pin should be connected to the host GPIO pin through as large a
resistor as possible. The limitation on the resistor value is that the minimum VOH of the host GPIO pin less the
drop across the resistor should be greater than VIH of the bq2431× CE pin. The drop across the resistor is given
by RCE × IIH.
The FAULT pin is an open-drain output that goes low during OV, OC, battery-OV, and OT events. If the
application does not require monitoring of the FAULT pin, it can be left unconnected. But if the FAULT pin has to
be monitored, it should be pulled high externally through RPU, and connected to the host through RFAULT. RFAULT
prevents damage to the host controller if the bq2431x fails (see above). The resistors should be of high value, in
practice values between 22kΩ and 100kΩ should be sufficient.
Selection of Input and Output Bypass Capacitors
The input capacitor CIN in Figure 23 is for decoupling, and serves an important purpose. Whenever there is a
step change downwards in the system load current, the inductance of the input cable causes the input voltage to
spike up. CIN prevents the input voltage from overshooting to dangerous levels. It is strongly recommended that a
ceramic capacitor of at least 1μF be used at the input of the device. It should be located in close proximity to the
IN pin.
COUT in Figure 23 is also important: If a very fast (< 1μs rise time) overvoltage transient occurs at the input, the
current that charges COUT causes the device’s current-limiting loop to kick in, reducing the gate-drive to FET Q1.
This results in improved performance for input overvoltage protection. COUT should also be a ceramic capacitor of
at least 1μF, located close to the OUT pin. COUT also serves as the input decoupling capacitor for the charging
circuit downstream of the protection IC.
Powering Accessories
In some applications, the equipment that the protection IC resides in may be required to provide power to an
accessory (e.g. a cellphone may power a headset or an external memory card) through the same connector pins
that are used by the adapter for charging. Figure 25 and Figure 26 illustrate typical charging and
accessory-powering scenarios:
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Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): bq24314 bq24316
13
bq24314
bq24316
www.ti.com
SLUS763C – JULY 2007 – REVISED OCTOBER 2007
Accessory
power supply
IN
AC Adapter
OUT
Charger
bq24316
e.g.
cellphone
DIS
EN
Battery
pack
to rest of
system
Figure 25. Charging - The Red Arrows Show the Direction of Current Flow
IN
OUT
Charger
bq24316
e.g.
cellphone
EN
Accessory
power supply
DIS
Battery
pack
to rest of
system
Figure 26. Powering an Accessory - The Red Arrows Show the Direction of Current Flow
In the second case, when power is being delivered to an accessory, the bq24314/bq24316 device is required to
support current flow from the OUT pin to the IN pin.
If VOUT > VUVLO + 0.7V, FET Q1 is turned on, and the reverse current does not flow through the diode but through
Q1. Q1 will then remain ON as long as VOUT > VUVLO – VHYS-UVLO + RDSON*IACCESSORY. Within this voltage range,
the reverse current capability is the same as the forward capability, 1.5A. It should be noted that there is no
overcurrent protection in this direction.
IN
Q1
OUT
VOUT
Charge Pump,
Bandgap,
Bias Gen
Figure 27.
14
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Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): bq24314 bq24316
bq24314
bq24316
www.ti.com
SLUS763C – JULY 2007 – REVISED OCTOBER 2007
PCB Layout Guidelines:
•
•
•
This device is a protection device, and is meant to protect down-stream circuitry from hazardous voltages.
Potentially, high voltages may be applied to this IC. It has to be ensured that the edge-to-edge clearances of
PCB traces satisfy the design rules for high voltages.
The device uses SON packages with a PowerPAD™. For good thermal performance, the PowerPAD should
be thermally coupled with the PCB ground plane. In most applications, this will require a copper pad directly
under the IC. This copper pad should be connected to the ground plane with an array of thermal vias.
CIN and COUT should be located close to the IC. Other components like RILIM and RBAT should also be located
close to the IC.
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Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): bq24314 bq24316
15
bq24314
bq24316
www.ti.com
SLUS763C – JULY 2007 – REVISED OCTOBER 2007
Revision History
Changes from Revision B (September 2007) to Revision C .......................................................................................... Page
•
•
16
Changed bq24314DSJ marking from preview to CBX .......................................................................................................... 2
Changed bq24316DSJ marking from preview to BZC........................................................................................................... 2
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Product Folder Link(s): bq24314 bq24316
PACKAGE OPTION ADDENDUM
www.ti.com
7-Nov-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
BQ24314DSGR
ACTIVE
SON
DSG
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24314DSGT
ACTIVE
SON
DSG
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24314DSJR
ACTIVE
SON
DSJ
12
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24314DSJT
ACTIVE
SON
DSJ
12
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24316DSGR
ACTIVE
SON
DSG
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24316DSGRG4
ACTIVE
SON
DSG
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24316DSGT
ACTIVE
SON
DSG
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24316DSGTG4
ACTIVE
SON
DSG
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Nov-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ24314DSGR
DSG
8
SITE 48
179
8
2.2
2.2
1.2
4
8
Q2
BQ24314DSJR
DSJ
12
SITE 41
330
12
3.3
4.3
1.1
8
12
Q1
BQ24314DSJT
DSJ
12
SITE 41
180
12
3.3
4.3
1.1
8
12
Q1
BQ24316DSGR
DSG
8
SITE 48
179
8
2.2
2.2
1.2
4
8
Q2
BQ24316DSGT
DSG
8
SITE 48
179
8
2.2
2.2
1.2
4
8
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Nov-2007
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
BQ24314DSGR
BQ24314DSJR
DSG
8
SITE 48
195.0
200.0
45.0
DSJ
12
SITE 41
346.0
346.0
29.0
BQ24314DSJT
DSJ
12
SITE 41
190.0
212.7
31.75
BQ24316DSGR
DSG
8
SITE 48
195.0
200.0
45.0
BQ24316DSGT
DSG
8
SITE 48
195.0
200.0
45.0
Pack Materials-Page 2
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