Sample & Buy Product Folder Support & Community Tools & Software Technical Documents DAC80004, DAC70004, DAC60004 SLASED6B – APRIL 2016 – REVISED JUNE 2016 DACx0004, Quad 16-,14-,12-Bit, 1 LSB INL, Buffered, Voltage-Output Digital-to-Analog Converters 1 Features 3 Description • • • • • • • • • • The DAC80004/70004/60004 (DACx0004) are highly accurate, low-power, voltage-output, quad-channel, 16-, 14-, 12-bit digital-to-analog converters (DACs) respectively. The DACx0004 devices are ensured monotonic by design and offer excellent linearity of less than 1 LSB (Max). The reference input of the DAC is buffered internally using a dedicated reference buffer. 1 True 16-Bit Performance: 1 LSB INL/DNL (Max) Ultra Low Glitch Energy: 1 nV-s Wide Power-Supply Range: 2.7 V to 5.5 V Output Buffer with Rail-to-Rail Operation Current Consumption: 1 mA/Channel 50-MHz, 4- or 3-Wire SPI Compatible Interface SDO Pin for Readback and Daisy Chain Power-On Reset to Zero or Mid Scale Temperature Range: –40°C to +125°C Multiple Packages: – Tiny 14-Pin VSON – 14-Pin TSSOP 2 Applications • • • • The DACx0004 devices incorporate a power-on-reset circuit that ensures the DAC output powers up at zero scale or mid scale depending on status of the POR pin and remains in this state until a valid code is written to the device. These devices consume very low current of 1 mA/channel making them ideal for portable, battery-operated equipment. These devices also contain a power-down feature that reduces current consumption to typically 3 µA at 5 V. The DACx0004 devices use a versatile 4- or 3-wire serial interface that operates at clock rates up to 50 MHz. The DACx0004 devices also include a SDO pin to daisy chain multiple devices. The interface is compatible with standard SPI™, QSPI™, Microwire, and digital signal processor (DSP) interfaces. The DACx0004 devices are offered in easy-to-assemble 14-pin TSSOP packages or an ultra small 14-pin VSON package and are fully specified over the extended industrial temperature range of –40°C to 125°C. Portable Instrumentation PLC Analog Output Module (4-20 mA) Closed-Loop Servo Control Data Acquisition Systems Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DACx0004 VSON (14) 3.00 mm x 4.00 mm DACx0004 TSSOP (14) 5.00 mm x 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. DACx0004 Block Diagram VDD Linearity Error vs Digital Input Code 1.00 REFIN 0.75 DAC Buffer DAC Register DAC 0.50 BUF VOUTA Channel A VOUTB VOUTC VOUTD Channel B Channel C Channel D INL Error (LSB) SCLK SDIN SYNC SDO CLR LDAC POR Interface Logic REF BUF 0.25 0.00 -0.25 -0.50 Channel A Channel B Channel C Channel D -0.75 Power Down Logic Power On Reset Resistive Network DACx0004 -1.00 0 GND 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code D001 Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DAC80004, DAC70004, DAC60004 SLASED6B – APRIL 2016 – REVISED JUNE 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 8 1 1 1 2 3 3 4 Absolute Maximum Ratings ...................................... 4 ESD Ratings ............................................................ 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 4 Electrical Characteristics........................................... 5 DACx0004 Timing Requirements ............................. 8 Typical Characteristics ............................................ 10 Detailed Description ............................................ 18 8.1 Overview ................................................................. 18 8.2 Functional Block Diagram ....................................... 18 8.3 Feature Description................................................. 19 8.4 Device Functional Modes........................................ 20 9 Application and Implementation ........................ 26 9.1 Application Information............................................ 26 9.2 Typical Application - Digitally Controlled Asymmetric Bipolar Output .......................................................... 26 10 Power Supply Recommendations ..................... 28 11 Layout................................................................... 29 11.1 Layout Guidelines ................................................. 29 11.2 Layout Example .................................................... 29 12 Device and Documentation Support ................. 30 12.1 12.2 12.3 12.4 12.5 12.6 Receiving Notification of Documentation Updates Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 30 30 30 30 30 30 13 Mechanical, Packaging, and Orderable Information ........................................................... 31 4 Revision History Changes from Revision A (June 2016) to Revision B • Page Added DAC80004IPW Device Marking Addendum to Mechanical, Packaging, and Orderable Information ...................... 31 Changes from Original (April 2016) to Revision A • 2 Page Changed from Product Preview to Production Data .............................................................................................................. 1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 DAC80004, DAC70004, DAC60004 www.ti.com SLASED6B – APRIL 2016 – REVISED JUNE 2016 5 Device Comparison Table DEVICE RESOLUTION DAC80004 16 DAC70004 14 DAC60004 12 6 Pin Configuration and Functions 14-Pin VSON DMD Package Top View 14-Pin TSSOP PW Package Top View LDAC 1 14 SCLK SYNC 2 13 SDIN VDD 3 12 GND VOUTA 4 11 VOUTB VOUTC 5 10 VOUTD POR 6 9 CLR REFIN 7 8 SDO Thermal Pad LDAC 1 14 SCLK SYNC 2 13 SDIN VDD 3 12 GND VOUTA 4 11 VOUTB VOUTD Thermal Pad VOUTC 5 10 POR 6 9 CLR REFIN 7 8 SDO Pin Functions PIN NAME NUMBER I/O DESCRIPTION CLR 9 Digital Input GND 12 Power Clear DAC pin, falling edge sensitive LDAC 1 Digital Input Load DAC pin, active low POR 6 Digital Input Power-on-reset configuration, Connecting the POR pin to GND powers up all four DACs to zero scale. Connecting this pin to VDD powers up all four DACs to midscale. REFIN 7 Analog Input Voltage reference input for all channels SCLK 14 Digital Input Serial interface shift clock SDIN 13 Digital Input Serial interface digital input SDO 8 Digital Output SYNC 2 Digital Input VDD 3 Power VOUTA 4 Analog Output DAC A output VOUTB 11 Analog Output DAC B output VOUTC 5 Analog Output DAC C output VOUTD 10 Analog Output DAC D output Ground Serial interface digital output for readback and daisy chaining Serial interface synchronization, active low Positive power supply (2.7 V to 5.5 V) Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback 3 DAC80004, DAC70004, DAC60004 SLASED6B – APRIL 2016 – REVISED JUNE 2016 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Voltage, VDD to GND –0.3 7 V Voltage, digital input or output to GND –0.3 VDD + 0.3 V Voltage, analog input (REFIN) or output (VOUTx) to GND –0.3 VDD + 0.3 V Input current to any pin except supply pins –10 10 mA 150 °C 150 °C Maximum junction temperature Storage temperature range, Tstg (1) -60 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN Voltage, VDD to GND Voltage, analog input (REFIN) or output (VOUTx) to GND NOM MAX UNIT 2.7 5.5 V 2.7 V ≤ VDD ≤ 4.5 V 2.2 VDD – 0.2 V 4.5 V ≤ VDD ≤ 5.5 V 2.2 VDD V -40 125 °C Ambient Operating Temperature, TA 7.4 Thermal Information DACx0004 THERMAL METRIC (1) DMD (VSON) PW (TSSOP) 14 PINS 14 PINS UNIT RθJA Junction-to-ambient thermal resistance 39.6 99.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 27.3 23.4 °C/W RθJB Junction-to-board thermal resistance 9.0 42.8 °C/W ψJT Junction-to-top characterization parameter 0.3 0.9 °C/W ψJB Junction-to-board characterization parameter 8.9 42.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6.5 N/A °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 DAC80004, DAC70004, DAC60004 www.ti.com SLASED6B – APRIL 2016 – REVISED JUNE 2016 7.5 Electrical Characteristics All minimum/maximum specifications at TA = -40°C to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.5 V ≤ REFIN (1) ≤ VDD, Rload = 5 kΩ to GND, Cload = 200 pF to GND (unless otherwise noted), Digital inputs held at 0 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE (2) Resolution DAC80004 16 DAC70004 14 DAC60004 12 Bits Relative accuracy (3) INL DNL Differential nonlinearity (3) TUE Total unadjusted error (3) ZCE Zero code error ZCE-TC ±1 LSB Ensured monotonic ±1 LSB TA = +20°C to +40°C 1.5 TA = –40°C to +125°C Zero code error TC TA = –40°C to +125°C, Code 0d into DAC ±0.2 TA = +25°C, Code 0d into DAC ±0.1 TA = –40°C to +125°C Offset error (3) OE-TC Offset error drift ±0.2 TA = +25°C ±0.2 Full-scale error (4) µV/°C ±1.8 ±4 TA = +20°C to +40°C, Code 65535d into DAC FSE mV ±1.2 TA = –40°C to +125°C TA = –40°C to +125°C ±2 ±5 TA = +20°C to +40°C OE mV 2 µV/°C ±0.05 TA = –40°C to +125°C, Code 65535d into DAC ±0.01 TA = +25°C ±0.01 TA = –40°C to +125°C ±2 TA = –40°C to +125°C ±0.005 TA = +25°C ±0.005 mV ±0.07 %FSR %FSR ppm FSR/°C FSE-TC Full-scale error drift (4) GE Gain error (3) GE-TC Gain drift TA = –40°C to +125°C ±2 ppm FSR/°C Output voltage drift vs.Time TA = +25°C, Vout = ¾ of full scale, 1900 hr 20 ppm FSR Load Regulation TA = +25°C, Vout =Mid Scale 0.003 % DC Power supply rejection ratio (4) TA = +25°C, Vout = full scale –92 dB PSRR (1) (2) (3) (4) ±0.05 %FSR 200 mV headroom is required between REFIN and VDD when 2.7 V ≤ VDD ≤ 4.5 V. Output unloaded End point fit between codes Code 512 to Code 65,024 - DAC80004, Code 128 to Code 16,256 - DAC70004, Code 32 to Code 4064 DAC60004, Output unloaded. With 100 mV headroom between DAC output and VDD. Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback 5 DAC80004, DAC70004, DAC60004 SLASED6B – APRIL 2016 – REVISED JUNE 2016 www.ti.com Electrical Characteristics (continued) All minimum/maximum specifications at TA = -40°C to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.5 V ≤ REFIN(1) ≤ VDD, Rload = 5 kΩ to GND, Cload = 200 pF to GND (unless otherwise noted), Digital inputs held at 0 V PARAMETER TEST CONDITIONS MIN TYP MAX 5.8 8 UNIT DYNAMIC PERFORMANCE ¼ to ¾ scale and ¾ to ¼ scale settling to ±1 LSB, RL = 5 kΩ, Cload = 200 pF to GND Output voltage settling time Slew rate Power-up time 1.5 (5) µs V/µs 100 µs Power-on glitch energy Supply slew rate <5 V/msec 8 mV Power-off glitch energy DAC in power down mode (1 kΩGND), Supply slew rate <5 V/msec 7 mV 0.1 Hz to 10 Hz Output noise 5 100 kHz BW Output noise density µVpp 100 Measured at 1 kHz 60 Measured at 10 kHz 55 µVRMS nV/√Hz THD Total harmonic distortion REFIN = 3 V ± 0.2 Vpp, Frequency = 10 kHz, DAC at mid scale, specified by design –80 dB PSRR AC power supply rejection ratio 200 mV 50 Hz and 60 Hz sine wave superimposed on power supply voltage (AC analysis) -90 dB Code change glitch impulse 1 LSB change around major carry, Software LDAC mode 1 Channel-to-channel AC (analog) crosstalk Full-scale swing on adjacent channel, Hardware LDAC mode 1 1 Channel-to-channel DC crosstalk Full-scale swing on adjacent channels, Measured channel at zero scale Full-scale swing on all channel, Measured channel at zero scale 1 nV-s nV-s LSB Digital crosstalk DAC code mid scale, Adjacent input buffer change from 0000h to FFFFh or vice versa 0.2 nV-S Reference feedthrough REFIN = 3 V ± 0.86 Vpp, Frequency = 100 Hz to 100 kHz, DAC at zero scale –85 dB Digital feedthrough At SCLK = 1 MHz, DAC output static at mid scale 0.2 nV-s OUTPUT CHARACTERISTICS Voltage range Headroom RL 0 Output loaded 5 kΩ, DAC code FFFFh Output loaded 0.5 kΩ, DAC code FFFFh Resistive load CL Capacitive load RO DC output impedance 10 %FSR 0.5 kΩ 1 RL = 5 kΩ 2 nF Normal mode 0.5 Ω Power down with 100 kΩ network 100 kΩ Power down with 1 kΩ network 6 V V RL = ∞ Short circuit current (5) VDD 0.1 1 kΩ 36 mA Time to exit power-down mode into normal mode. Measured from 32nd falling edge SCLK to 90% of DAC final value, Characterized at mid scale. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 DAC80004, DAC70004, DAC60004 www.ti.com SLASED6B – APRIL 2016 – REVISED JUNE 2016 Electrical Characteristics (continued) All minimum/maximum specifications at TA = -40°C to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.5 V ≤ REFIN(1) ≤ VDD, Rload = 5 kΩ to GND, Cload = 200 pF to GND (unless otherwise noted), Digital inputs held at 0 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOLTAGE REFERENCE INPUT Reference input range 2.7 V ≤ VDD ≤ 4.5 V 2.2 VDD – 0.2 4.5 V ≤ VDD ≤ 5.5 V 2.2 VDD Reference input current MBW 450 V µA Reference input impedance 15 Reference input capacitance 10 pF 340 kHz Multiplying bandwidth kΩ DIGITAL INPUTS VIH High-level input voltage VIL Low-level input voltage 2.3 Input leakage V 0 < VDIGITAL INPUT < VDD Pin capacitance 0.7 V ±1 µA 4 pF DIGITAL OUTPUTS VOH High-level output voltage IOH = 2 mA VOL Low-level output voltage IOL = 2 mA VDD – 1 V 0.7 Pin capacitance 7 V pF POWER SUPPLY REQUIREMENTS VDD IVDD Supply voltage 2.7 Supply current V TA = –40°C to +125°C, Normal mode 4 5.5 mA TA = –40°C to +125°C, Power-down mode 3 7 µA TA = –40°C to +125°C, Normal mode Power dissipation 5.5 20 mW TEMPERATURE RANGE TA Specified performance –40 Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 125 Submit Documentation Feedback °C 7 DAC80004, DAC70004, DAC60004 SLASED6B – APRIL 2016 – REVISED JUNE 2016 www.ti.com 7.6 DACx0004 Timing Requirements At TA = -40°C to +125°C, Trise = Tfall = 1 nV/sec (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2, SDO pin loaded with 10 pF 4.5 V ≤ VDD ≤ 5.5 V MIN TYP 2.7 V ≤ VDD ≤ 4.5 V MAX MIN TYP MAX UNIT SERIAL WRITE and READ tc SCLK cycle time 20 40 ns tw1 SCLK high pulse duration 10 20 ns tw2 SCLK low pulse duration 10 20 ns tsu SYNC to SCLK falling edge setup time 15 30 ns tsu1 Data setup time 5 10 ns th1 Data hold time 5 10 ns td1 SCLK falling edge to SYNC rising edge delay time 5 10 ns tw3 Minimum SYNC high pulse duration (1) 25 35 ns td2 SYNC rising edge to SCLK fall ignore delay time 15 20 ns tw4 LDAC pulse duration low 20 30 ns td3 SCLK falling edge to LDAC rising edge delay time 10 20 ns tw5 CLR minimum pulse duration low 10 20 ns td4 SCLK falling edge to LDAC falling edge delay time 10 20 ns tv SCLK rising edge to SDO valid time td5 SCLK falling edge to SYNC rising edge delay time 5 10 ns td6 SYNC rising edge to SCLK rising edge delay time 5 10 ns td7 SYNC rising edge to LDAC or CLR falling edge delay time 20 40 ns t19 CLR pulse activation time 20 20 ns t20 Successive DAC Update (1) 18 18 2.4 2.4 ns µs Does not include output settling tiime td2 tc SCLK 1 tw3 2 32 tw2 tsu tw1 td1 SYNC tsu1 SDIN th1 t19 DB31 DB0 td3 LDAC2 td4 tw4 LDAC1 tw5 CLR t19 VOUTX (1) Asynchronous LDAC update (2) Synchronous LDAC update Figure 1. Stand-Alone Timing 8 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 DAC80004, DAC70004, DAC60004 www.ti.com SLASED6B – APRIL 2016 – REVISED JUNE 2016 td6 SCLK 1 2 32 33 34 64 td5 SYNC Input Word for DAC-N SDIN DB31 DB0 X SDO DB31 Input Word for DAC-N-1 DB0 DB31 Input Word for DAC-N DB0 tv td7 LDAC1 td7 CLR (1) Asynchronous LDAC update Figure 2. Daisy-Chain Timing Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback 9 DAC80004, DAC70004, DAC60004 SLASED6B – APRIL 2016 – REVISED JUNE 2016 www.ti.com 7.7 Typical Characteristics 1.00 1.00 0.75 0.75 0.50 0.50 DNL Error (LSB) INL Error (LSB) At TA = 25°C, VDD = 5.5 V, REFIN = 5.45 V, DAC outputs unloaded, unless otherwise noted. 0.25 0.00 -0.25 -0.50 Channel A Channel B Channel C Channel D -1.00 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code D001 0 Figure 3. Linearity Error vs Digital Input Code 1.00 0.75 0.75 0.50 0.50 0.25 0.00 -0.25 -0.50 0.25 0.00 -0.25 -0.50 Channel A Channel B Channel C Channel D -0.75 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code D001 Figure 4. Differential Linearity Error vs Digital Input Code 1.00 DNL Error (LSB) INL Error (LSB) -0.25 -0.75 -1.00 Channel A Channel B Channel C Channel D -0.75 -1.00 -1.00 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code D001 DAC load 5 kΩ//200 pF 0 Figure 6. Differential Linearity Error vs Digital Input Code 2.0 1.5 1.5 1.0 0.5 0.0 -0.5 Channel A Channel B Channel C Channel D -1.5 -2.0 Total Unadjusted Error (mV) 2.0 -1.0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code D001 DAC load 5 kΩ//200 pF Figure 5. Linearity Error vs Digital Input Code Total Unadjusted Error (mV) 0.00 -0.50 Channel A Channel B Channel C Channel D -0.75 0.25 1.0 0.5 0.0 -0.5 -1.0 Channel A Channel B Channel C Channel D -1.5 -2.0 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code D001 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code D001 DAC load 5 kΩ//200 pF Figure 7. Total Unadjusted Error vs Digital Input Code 10 Submit Documentation Feedback Figure 8. Total Unadjusted Error vs Digital Input Code Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 DAC80004, DAC70004, DAC60004 www.ti.com SLASED6B – APRIL 2016 – REVISED JUNE 2016 Typical Characteristics (continued) 1.00 1.00 0.75 0.75 DNL Error Max-Min (LSB) INL Error Max-Min (LSB) At TA = 25°C, VDD = 5.5 V, REFIN = 5.45 V, DAC outputs unloaded, unless otherwise noted. 0.50 0.25 0.00 -0.25 -0.50 Ch-A Max Ch-B Max Ch-C Max -0.75 -1.00 -40 -25 -10 5 Ch-D Max Ch-A Min Ch-B Min 20 35 50 65 Temperature (oC) Ch-C Min Ch-D Min 80 95 0.50 0.25 0.00 -0.25 -0.50 -0.75 -1.00 -40 110 125 -10 5 Ch-A DNL Min Ch-B DNL Min Ch-C DNL Min Ch-D DNL Min 20 35 50 65 Temperature (oC) 80 95 110 125 D001 DAC load 5 kΩ//200 pF Figure 9. Linearity Error (Max-Min) vs Temperature Figure 10. Differential Linearity Error (Max-Min) vs Temperature 2.00 1.8 1.5 1.50 1.2 1.00 0.9 Offset Error (mV) Total Unadjusted Error Max/Min (mV) -25 D001 DAC load 5 kΩ//200 pF 0.50 0.00 -0.50 -1.00 Ch-A TUE Max Ch-B TUE Max Ch-C TUE Max Ch-D TUE Max -1.50 -2.00 -40 Ch-A DNL Max Ch-B DNL Max Ch-C DNL Max Ch-D DNL Max -25 -10 5 80 95 0.3 0.0 -0.3 -0.6 -0.9 Ch-A TUE Min Ch-B TUE Min Ch-C TUE Min Ch-D TUE Min 20 35 50 65 Temperature (oC) 0.6 Channel A (5 k://200 pF) Channel B (5 k://200 pF) Channel C (5 k://200 pF) Channel D (5 k://200 pF) -1.2 -1.5 -1.8 -40 110 125 -25 -10 5 D001 20 35 50 65 Temperature (oC) 80 95 110 125 D001 DAC load 5 kΩ//200 pF Figure 11. Total Unadjusted Error Max/Min vs Temperature Figure 12. Offset Error vs Temperature 0.05 0.04 Full Scale Error (%FSR) Gain Error (%FSR) 0.03 0.02 0.01 0.00 -0.01 -0.02 -0.04 -0.05 -40 Channel A (no load) Channel B (no load) Channel C (no load) Channel D (no load) Channel A (5 k://200 pF) Channel B (5 k://200 pF) Channel C (5 k://200 pF) Channel D (5 k://200 pF) -0.03 -25 -10 5 20 35 50 65 Temperature (oC) 80 95 Figure 13. Gain Error vs Temperature 110 125 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0.00 -0.01 -0.02 -0.03 -0.04 -0.05 -0.06 -0.07 -40 Channel A (5 k://200 pF) Channel B (5 k://200 pF) Channel C (5 k://200 pF) Channel D (5 k://200 pF) -25 -10 5 D001 Channel A (no load) Channel B (no load) Channel C (no load) Channel D (no load) 20 35 50 65 Temperature (oC) 80 95 110 125 D001 Figure 14. Full Scale Error vs Temperature Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback 11 DAC80004, DAC70004, DAC60004 SLASED6B – APRIL 2016 – REVISED JUNE 2016 www.ti.com Typical Characteristics (continued) 1.00 1.00 0.75 0.75 0.50 0.50 DNL Error (LSB) INL Error (LSB) At TA = 25°C, VDD = 2.7 V, REFIN = 2.5 V, DAC outputs unloaded, unless otherwise noted. 0.25 0.00 -0.25 -0.50 Channel A Channel B Channel C Channel D -1.00 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code D001 0 Figure 15. Linearity Error vs Digital Input Code 1.00 0.75 0.75 0.50 0.50 0.25 0.00 -0.25 -0.50 0.25 0.00 -0.25 -0.50 Channel A Channel B Channel C Channel D -0.75 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code D001 Figure 16. Differential Linearity Error vs Digital Input Code 1.00 DNL Error (LSB) INL Error (LSB) -0.25 -0.75 -1.00 Channel A Channel B Channel C Channel D -0.75 -1.00 -1.00 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code D001 DAC load 5 kΩ//200 pF 0 Figure 18. Differential Linearity Error vs Digital Input Code 2.0 1.5 1.5 1.0 0.5 0.0 -0.5 Channel A Channel B Channel C Channel D -1.5 -2.0 Total Unadjusted Error (mV) 2.0 -1.0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code D001 DAC load 5 kΩ//200 pF Figure 17. Linearity Error vs Digital Input Code Total Unadjusted Error (mV) 0.00 -0.50 Channel A Channel B Channel C Channel D -0.75 0.25 1.0 0.5 0.0 -0.5 -1.0 Channel A Channel B Channel C Channel D -1.5 -2.0 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code D001 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code D001 DAC load 5 kΩ//200 pF Figure 19. Total Unadjusted Error vs Digital Input Code 12 Submit Documentation Feedback Figure 20. Total Unadjusted Error vs Digital Input Code Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 DAC80004, DAC70004, DAC60004 www.ti.com SLASED6B – APRIL 2016 – REVISED JUNE 2016 Typical Characteristics (continued) At TA = 25°C, VDD = 2.7 V, REFIN = 2.5 V, DAC output unloaded, unless otherwise noted. 1.8 0.05 1.5 0.04 1.2 0.03 Gain Error (%FSR) Offset Error (mV) 0.9 0.6 0.3 0.0 -0.3 -0.6 -0.9 Channel A (5 k://200 pF) Channel B (5 k://200 pF) Channel C (5 k://200 pF) Channel D (5 k://200 pF) -1.2 -1.5 -1.8 -40 -25 -10 5 20 35 50 65 Temperature (oC) 80 95 0.02 0.01 0.00 -0.01 -0.02 -0.03 -0.04 -0.05 -40 110 125 -10 5 20 35 50 65 Temperature (oC) 80 95 110 125 D001 Figure 22. Gain Error vs Temperature 1.00 Channel A (no load) Channel B (no load) Channel C (no load) Channel D (no load) Channel A (5 k://200 pF) Channel B (5 k://200 pF) Channel C (5 k://200 pF) Channel D (5 k://200 pF) Ch-A Max Ch-B Max Ch-C Max 0.75 INL Error Max-Min (LSB) Full Scale Error (%FSR) -25 D001 Figure 21. Offset Error vs Temperature 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0.00 -0.01 -0.02 -0.03 -0.04 -0.05 -0.06 -0.07 -40 Channel A (no load) Channel B (no load) Channel C (no load) Channel D (no load) Channel A (5 k://200 pF) Channel B (5 k://200 pF) Channel C (5 k://200 pF) Channel D (5 k://200 pF) Ch-D Max Ch-A Min Ch-B Min Ch-C Min Ch-D Min 0.50 0.25 0.00 -0.25 -0.50 -0.75 -25 -10 5 20 35 50 65 Temperature (oC) 80 95 -1.00 2.7 110 125 3.1 3.5 D001 3.9 4.3 VDD (V) 4.7 5.1 5.5 D001 DAC load 5 kΩ//200 pF Figure 23. Full Scale Error vs Temperature Figure 24. Linearity Error (Max-Min) vs Power Supply Voltage 1.00 1.8 1.5 1.2 0.50 0.9 Offset Error (mV) DNL Error Max-Min (LSB) 0.75 0.25 0.00 -0.25 -0.50 Ch-A DNL Max Ch-B DNL Max Ch-C DNL Max Ch-D DNL Max -0.75 -1.00 2.7 3.1 3.5 3.9 VDD (V) 4.7 0.3 0.0 -0.3 -0.6 -0.9 Ch-A DNL Min Ch-B DNL Min Ch-C DNL Min Ch-D DNL Min 4.3 0.6 Channel A (5 k://200 pF) Channel B (5 k://200 pF) Channel C (5 k://200 pF) Channel D (5 k://200 pF) -1.2 -1.5 5 -1.8 2.7 3.1 3.5 D001 3.9 4.3 VDD (V) 4.7 5.1 5.5 D001 DAC load 5 kΩ//200 pF Figure 25. Differential Linearity Error (Max-Min) vs Power Supply Voltage Figure 26. Offset Error vs Power Supply Voltage Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback 13 DAC80004, DAC70004, DAC60004 SLASED6B – APRIL 2016 – REVISED JUNE 2016 www.ti.com Typical Characteristics (continued) 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0.00 -0.01 -0.02 -0.03 -0.04 -0.05 -0.06 -0.07 2.7 Channel A (5 k://200 pF) Channel B (5 k://200 pF) Channel C (5 k://200 pF) Channel D (5 k://200 pF) 3.1 3.5 3.9 4.3 VDD (V) 4.7 5.1 Full Scale Error (%FSR) Gain Error (%FSR) At TA = 25°C, VDD = 5.5 V, REFIN = 2.5 V, DAC output load = 5 kΩ||200 pF, unless otherwise noted. 5.5 0.75 0.75 DNL Error Max-Min (LSB) 1.00 0.50 0.25 0.00 -0.25 -0.50 -0.75 -1.00 2.5 2.9 3.3 Ch-D Max Ch-A Min Ch-B Min 3.7 4.1 REFIN (V) 4.5 Ch-C Min Ch-D Min 4.9 3.9 4.3 VDD (V) 4.7 5.1 5.5 D001 0.25 0.00 -0.25 -0.50 Ch-A DNL Max Ch-B DNL Max Ch-C DNL Max Ch-D DNL Max -0.75 -1.00 2.5 5.3 2.9 3.3 D001 3.7 4.1 REFIN (V) Ch-A DNL Min Ch-B DNL Min Ch-C DNL Min Ch-D DNL Min 4.5 4.9 5.3 D001 Figure 30. Differential Linearity Error (Max-Min) vs Reference Voltage 0.05 0.07 Full Scale Error Max (%FSR) 0.04 Gain Error Max (%FSR) 3.5 0.50 Figure 29. Linearity Error (Max-Min) vs Reference Voltage 0.03 0.02 0.01 0.00 -0.01 -0.02 Ch-A GE Max Ch-B GE Max Ch-C GE Max Ch-D GE Max -0.03 -0.04 -0.05 2.0 0.05 0.03 0.01 -0.01 -0.03 Ch-A FSE Max Ch-B FSE Max Ch-C FSE Max Ch-D FSE Max -0.05 -0.07 2.5 3.0 3.5 4.0 REFIN (V) 4.5 5.0 5.5 Submit Documentation Feedback 2 2.5 3 D001 Figure 31. Gain Error (Max) vs Reference Voltage 14 3.1 Figure 28. Full Scale Error vs Power Supply Voltage 1.00 Ch-A Max Ch-B Max Ch-C Max Channel A (5 k://200 pF) Channel B (5 k://200 pF) Channel C (5 k://200 pF) Channel D (5 k://200 pF) D001 Figure 27. Gain Error vs Power Supply Voltage INL Error Max-Min (LSB) 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0.00 -0.01 -0.02 -0.03 -0.04 -0.05 -0.06 -0.07 2.7 3.5 4 REFIN (V) 4.5 5 5.5 D001 Figure 32. Full Scale Error (Max) vs Reference Voltage Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 DAC80004, DAC70004, DAC60004 www.ti.com SLASED6B – APRIL 2016 – REVISED JUNE 2016 Typical Characteristics (continued) 5.5 5.5 5.0 5.0 4.5 4.5 Power Supply Current (mA) Power Supply Current (mA) At TA = 25°C, VDD = 5.5 V, REFIN = 5.45 V, DAC outputs unloaded, All channels active, unless otherwise noted. 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.0 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code D001 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code D001 VDD = 2.7 V, REFIN = 2.5 V Figure 34. Power Supply Current vs Digital Input Code 5.5 5.0 5.0 4.5 4.5 Power Supply Current (mA) Power Supply Current (mA) Figure 33. Power Supply Current vs Digital Input Code 5.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 3.5 3.0 2.5 2.0 1.5 Unit #1 Unit #2 Unit #3 Unit #4 1.0 0.5 0.0 -40 -25 -10 5 20 35 50 65 Temperature (oC) 80 95 0.0 2.7 110 125 Figure 35. Power Supply Current vs Temperature 2.7 2.4 4.5 DAC Output (V) 3.0 2.5 2.0 1.5 Ch-A Ch-B Ch-C Ch-D DAC Code - Zero Scale 0.5 -16 -12 -8 4.7 5.1 5.5 D001 2.1 DAC Code - Full Scale 3.5 0.0 -20 3.9 4.3 VDD (V) Figure 36. Power Supply Current vs Power Supply Voltage 5.0 1.0 3.5 REFIN = 2.5 V, DAC code = mid-scale code 5.5 4.0 3.1 D001 DAC code = mid-scale code DAC Output (V) 4.0 -4 0 4 Load Current (mA) 8 12 16 1.8 DAC Code - Full Scale 1.5 1.2 0.9 0.6 Ch-A Ch-B Ch-C Ch-D DAC Code - Zero Scale 0.3 20 0.0 -20 -16 -12 -8 D001 -4 0 4 Load Current (mA) 8 12 16 20 D001 VDD = 2.7 V, REFIN = 2.5 V Figure 37. DAC Output Voltage vs Load Current Figure 38. DAC Output Voltage vs Load Current Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback 15 DAC80004, DAC70004, DAC60004 SLASED6B – APRIL 2016 – REVISED JUNE 2016 www.ti.com Typical Characteristics (continued) At TA = 25°C, VDD = 5.5 V, REFIN = 5.45 V, DAC output load = 5 kΩ||200 pF, unless otherwise noted. 7 2.49960 Ch-A Ch-B 6 2.49950 5 2.49945 IVDD (mA) DAC Output Voltage (V) 2.49955 Ch-C Ch-D 2.49940 2.49935 4 3 2 2.49930 1 2.49925 2.49920 2.7 3.1 3.5 3.9 4.3 4.7 Power Supply Voltage (V) 5.1 5.5 3.1 3.5 3.9 4.3 4.7 Digital Input Pins Logic Level (V) 5.5 D001 Figure 40. Power Supply Current vs Digital Input Pins Logic Level 5 0.020 0 0.015 5 0 LDAC Feedthrough 0.010 5.1 DAC unloaded, All channels to mid-scale Figure 39. DAC Output Voltage vs Power Supply Voltage 0.015 2.7 D001 REFIN = 2.5 V, All channels active with full-scale code, DAC unloaded 0.020 0 2.3 LDAC Feedthrough Glitch Impulse (1nV-sec) -5 0.010 -5 Glitch Impulse (1nV-sec) 0.005 -10 0.005 -10 0.000 -15 0.000 -15 -0.005 -20 -0.005 -20 -0.010 -25 -0.010 -25 -0.015 -30 VOUT (5 mV/div) LDAC Trigger (5 V/div) -35 2E-6 3E-6 4E-6 5E-6 Time (0.5 msec/div) D001 -0.015 -30 VOUT (5 mV/div) LDAC Trigger (5 V/div) -35 2E-6 3E-6 4E-6 5E-6 Time (0.5 msec/div) D001 -0.020 0 1E-6 DAC code transition from 8000h to 7FFFh Figure 41. Glitch Impulse, Falling Edge, 1LSB Step -0.020 0 1E-6 DAC code transition from 7FFFh to 8000h Figure 42. Glitch Impulse, Rising Edge, 1LSB Step LDAC Trigger (5 V/div) LDAC Trigger (5 V/div) Large Signal VOUT (2 V/div) Large Signal VOUT (2 V/div) Settling Band (±1 LSB) Small Signal VOUT (160 µV/div = 2 LSB) Time (2 µsec/div) From code 512d to 65024d, Typical channel shown Figure 43. Full-Scale Settling Time, Rising Edge 16 Small Signal VOUT (160 µV/div = 2 LSB) Settling Band (±1 LSB) Submit Documentation Feedback Time (2 µsec/div) From code 65024d to 512d, Typical channel shown Figure 44. Full-Scale Settling Time, Falling Edge Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 DAC80004, DAC70004, DAC60004 www.ti.com SLASED6B – APRIL 2016 – REVISED JUNE 2016 Typical Characteristics (continued) At TA = 25°C, VDD = 5.5 V, REFIN = 5.45 V, DAC output load = 5 kΩ||200 pF, unless otherwise noted. Ch-A (20 mV/div) Ch-B (20 mV/div) Ch-C (20 mV/div) Ch-D (20 mV/div) VDD (5 V/div) Ch-A (1 mV/div) Ch-B (1 mV/div) Ch-C (1 mV/div) Ch-D (1 mV/div) VDD (5 V/div) Time (0.2 ms/div) Time (2 ms/div) D001 D001 DAC unloaded DAC in power down mode (1 kΩ-GND) Figure 45. Power-On Glitch, Reset to Zero Scale Figure 46. Power-Off Glitch, Reset to Zero Scale 0 -10 SCLK (5 V/div) -20 VOUT PSRR (dB) Clock Feedthrough Impulse VOUT (2 mV/div) -30 -40 -50 -60 -70 -80 -90 -100 10 Time (0.5 µsec/div) DAC unloaded, DAC code mid-scale, Typical channel shown 100 1000 10000 Frequency (Hz) 100000 1000000 D001 VDD = 5.0 + 1 VPP (Sinusoid), REFIN = 2.5 V, DAC code fullscale, Typical channel shown Figure 47. Clock Feedthrough, 1MHz Midscale Figure 48. DAC Output AC PSRR vs VDD 450.0 DAC Code = 32768 DAC Code = 512 DAC Code = 65024 350.0 = 4 µVPP VNOISE (1 µV/div) Voltage Noise (nV/—Hz) 400.0 300.0 250.0 200.0 150.0 100.0 50.0 0.0 100 1000 10000 Frequency (Hz) 100000 DAC unloaded, DAC code mid-scale, Typical channel shown D001 DAC unloaded, Typical channel shown Figure 49. DAC Output Noise Density vs Frequency Figure 50. DAC Output Noise, 0.1 Hz to 10 Hz Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback 17 DAC80004, DAC70004, DAC60004 SLASED6B – APRIL 2016 – REVISED JUNE 2016 www.ti.com 8 Detailed Description 8.1 Overview The DAC80004, DAC70004, and DAC60004 are quad-channel, 16-bit, voltage-output DACs with internal reference buffers and output buffers. Each channel consists of an R-2R ladder configuration with the 4 MSBs segmented, followed by an operational amplifier, as shown in Figure 51. The DACx0004 devices have a constant impedance (30 kΩ typical), buffered reference input. The output of the reference buffers drives the R-2R ladders. With the production trim process these devices have excellent dc accuracy and ac performance. R R VOUT Buffer 2R 2R 2R S0 REFIN 2R 2R 2R S11 S1 S12 2R S13 S15 Buffer Figure 51. DACx0004 Architecture The input coding to the DACx0004 is straight binary, so the ideal output voltage is given by Equation 1: æD ö VOUT = ç IN ÷ x REFIN è 2N ø (1) Where: N = resolution in bits; either 16 (DAC80004), 14 (DAC70004) or 12 (DAC60004) DIN = decimal equivalent of the binary code that is loaded to the DAC register. DIN ranges from 0 to 2N –1 REFIN = DAC reference voltage 8.2 Functional Block Diagram VDD REFIN SCLK SDIN SYNC SDO CLR LDAC POR Interface Logic REF BUF DAC Buffer DAC Register DAC VOUTA BUF Channel A VOUTB VOUTC VOUTD Channel B Channel C Channel D Power Down Logic Power On Reset Resistive Network DACx0004 GND Copyright © 2016, Texas Instruments Incorporated 18 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 DAC80004, DAC70004, DAC60004 www.ti.com SLASED6B – APRIL 2016 – REVISED JUNE 2016 8.3 Feature Description 8.3.1 Output Amplifier The DACx0004 output buffer amplifier is capable of generating near rail-to-rail voltages on its output, giving a maximum output range of 0 V to REFIN. It is capable of driving a load of 5 kΩ in parallel with 2 nF to GND. The typical slew rate of this amplifier while driving no load is 1.5 V/µs, with a full-scale settling time of 8 µs to 1 LSB of the final value as shown in Figure 43 and Figure 44. The current consumption of the amplifier (unloaded) is 1 mA/channel (typical). The DACx0004 output amplifier also implements a short circuit current limiting circuit. The default value of short circuit limit is 40 mA, however this can be reduced to 30 mA using dedicated bits (1 per channel) via SPI command 1010 (see Table 2). 8.3.2 Reference Buffer The DACx0004 requires an external reference to operate. The reference input pin has the following input range: 2.2 V to (VDD – 0.2) for 2.7 V ≤ VDD ≤ 4.5 V 2.2 V to VDD for 4.5 V ≤ VDD ≤ 5.5 V The DACx0004 contains a dedicated reference buffer for each DAC channel. The REFIN pin drives the input of these buffers. The integrated reference buffers offers constant impedance of 30 kΩ (typical) at the REFIN pin. This simplifies the external reference drive circuit for the device. 8.3.3 Power-On Reset The DACx0004 contain a power-on-reset circuit that controls the output voltage during power up. The power-on reset is useful in applications where it is important to know the state of the output of each DAC while the device is in the process of powering up. At power up all DAC registers are filled with power-on reset code (see Table 1). 8.3.3.1 POR Pin Feature The DAC power-on reset code for all of the channels depends on the state of the POR pin at power up (see Pin Configuration and Functions). Each DAC channel remains that way until a valid load command is written to it. All device registers are reset at power up as shown in Table 1. Table 1. DACx0004 Power-On Reset Values DACx0004 - POWER-ON RESET VALUE REGISTER NAME TSSOP-/VSON-14 DAC latches (per channel) If POR pin = '0' then Zero Scale else Mid scale DAC buffers (per channel) If POR pin= '0' then Zero Scale else Mid scale Power down (per channel) 00 – Normal mode Clear mode 00 – Clear to Zero Ignore LDAC (per channel) 0000 – Do not ignore Daisy chain 0 – Daisy chain disabled, DAC update at 32nd SCLK falling edge Short circuit limit (per channel) 0000 – all DACs 40 mA 8.3.3.2 Internal Power-On Reset (IPOR) Levels When the device powers up, an IPOR circuit sets the device in default mode as shown in Table 1. The IPOR circuit requires specific VDD levels, as indicated in Figure 52, to ensure discharging of internal capacitors and to reset the device on power up. In order to ensure a power-on reset, VDD must be below 0.7 V for at least 1 ms. When VDD drops below 2.4 V but remains above 0.7 V (shown as the undefined region), the device may or may not reset under all specified temperature and power supply conditions. In this case, In this case a power-down reset is recommended. When VDD remains above 2.4 V, a power-on reset does not occur. Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback 19 DAC80004, DAC70004, DAC60004 SLASED6B – APRIL 2016 – REVISED JUNE 2016 www.ti.com VDD (V) 5.5 V No Power-On Reset Specified Supply Voltage Range 2.7 V 2.4 V Undefined 0.7 V Power-On Reset 0.0 V Figure 52. Relevant Voltage Levels for IPOR Circuit 8.4 Device Functional Modes 8.4.1 Serial Interface The DACx0004 devices have a 4-wire serial interface: SYNC, SCLK, SDIN, and SDO (see Pin Configuration and Functions). The serial interface (3-wire and 4-wire) is compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs and it operates up to 50 MHz. See the Write Mode Stand-Alone Timing and Write Mode Daisy-Chain Timing diagrams (see Figure 1 and Figure 2) for examples of typical write and read sequences. The input shift register is 32 bits wide. 8.4.1.1 Stand-Alone Mode The serial clock SCLK can be a continuous or a gated clock. The first falling edge of SYNC starts the operation cycle. When SYNC is high, the SCLK and SDIN signals are blocked and the SDO pin (TSSOP-14 and VSON-14 packages) is in a Hi-Z state. The device internal registers are updated from the shift register on the 32nd falling edge of SCLK. 8.4.1.1.1 SYNC Interrupt – Stand-Alone Mode For stand-alone operation, the SYNC line stays low for at least 32 falling edges of SCLK and the addressed DAC register updates on the 32nd SCLK falling edge. However, if SYNC is brought high before the 32nd SCLK falling edge, it acts as an interrupt to the write sequence; the shift register resets and the write sequence is discarded. Neither an update of the data buffer contents, DAC register contents, nor a change in the operating mode occurs (as shown in Figure 53). SCLK 1 2 32 32 SYNC SDIN DB31 DB0 Invalid/Interrupted Write Sequence nd Output/Mode Does Not Update on 32 SCLK Falling Edge DB31 DB0 Valid Write Sequence nd Output/Mode Update on 32 SCLK Falling Edge Figure 53. SYNC Interrupt – Stand Alone Operation 20 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 DAC80004, DAC70004, DAC60004 www.ti.com SLASED6B – APRIL 2016 – REVISED JUNE 2016 Device Functional Modes (continued) 8.4.1.1.2 Read-Back Mode The READ command is used to start read-back operation. However, before read-back operation can be initiated, the SDO pin must be enabled by setting the DSDO bit to '1'; this bit is disabled by default. Read-back operation is then started by executing a READ command (R/W bit = '1', see Table 3). Bits C3 to C0 select the register to be read. The remaining data in the command are don’t care bits. During the next SPI operation, the data appearing on the SDO output are from the previously addressed register. For a read of a single register, a NOP (No Operation) command (1110) can be used to clock out the data from the selected register on SDO. Multiple registers can be read if multiple READ commands are issued (see Figure 54). SCLK 1 2 32 1 2 32 SYNC Read Command SDIN DB31 NOP Command DB0 DB31 DB0 Readback Data SDO DB31 X DB0 tv Figure 54. Read-Back Operation 8.4.1.2 Daisy-Chain Mode For systems that contain more than one device, the SDO pin can be used to daisy-chain multiple devices together (see Figure 55). Daisy-chain operation can be useful in system diagnostics and in reducing the number of serial interface lines. The daisy-chain feature can be enabled by writing a logic '1' to the DSDO bit (see Table 3); the SDO pin is set to HIZ when the DSDO bit is set to 0. The first falling edge of SYNC starts the operating cycle. SCLK is continuously applied to the SPI shift register when SYNC is low. If more than 32 clock pulses are applied, the data ripples out of the shift register and appear on the SDO line. The data bits are clocked out on the rising edge of SCLK and are valid on the falling edge. By connecting the SDO pin of the first device to the SDI input of the next device in the chain, a multiple-device interface is constructed (see Figure 2). Each device in the system requires 32 clock pulses. Therefore, the total number of clock cycles must equal 32 × N, where N is the total number of DACx0004s in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This action latches the data from the SPI shift registers to the device internal registers for each device in the daisy-chain and prevents any further data from being clocked in. The serial clock can be a continuous or a gated clock. Note that a continuous SCLK source can only be used if SYNC is held low for the correct number of clock cycles. For gated clock mode, a burst clock containing the exact number of clock cycles must be used and SYNC must be taken high after the final clock in order to latch the data. C DACx0004 SDIN SDO B DACx0004 SDIN SDO A DACx0004 SDIN SCLK SCLK SCLK SYNC SYNC SYNC SDO Figure 55. DACx0004 in Daisy Chain Mode 8.4.1.2.1 SYNC Interrupt – Daisy-Chain Mode For daisy-chain operation, the SYNC line stays low for at least 32 × N SCLK cycles, where N is the number of DACx0004s in the daisy chain. If SYNC is brought high before a multiple 32 SCLKs, it acts as an interrupt to the write sequence; the shift register resets and the write sequence is discarded. Neither an update of the data buffer contents, DAC register contents, nor a change in the operating mode occurs (see Figure 56). Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback 21 DAC80004, DAC70004, DAC60004 SLASED6B – APRIL 2016 – REVISED JUNE 2016 www.ti.com Device Functional Modes (continued) SCLK 1 2 32XN 32XN SYNC SDIN Invalid/Interrupted Write Sequence Output/Mode Does Not Update on the Rising SYNC Valid Write Sequence Output/Mode Does Update on the Rising SYNC Figure 56. SYNC Interrupt – Daisy-Chain Operation 8.4.2 SPI Shift Register The SPI shift register is 32 bits wide, as shown in Table 2. The shift register command mapping is shown in Table 3. The DACx0004 accepts DAC code in straight binary format. Note that, the DAC data is left alligned from MSB (D19) to LSB (D4 - 16 bits, D6 - 14 bits, D8 - 12 bits). Table 2. DACx0004 SPI Shift Register Format D31 D30 D29 D28 Don't Cares R/W D27-D24 D23-D20 D19-D04 D03-D00 Command Bits Channel Address Bits 16/14/12-Bit DAC Data left alligned/Power Down Bits/Device Ready bit Mode Bits Table 3. DAC Commands D31 - D28 D23 - D20 D19 - D16 D15 - D12 D11 - D08 D07 - D04 D03 - D00 X W/R 0 0 D27 - D24 0 0 Channel Address DAC Data DAC Data DAC Data DAC Data X Write to buffer n Commands X W 0 0 0 1 Channel Address X X X X X Update DAC n DAC Data DAC Data DAC Data DAC Data X Write to buffer n and update all DACs (Software LDAC) DAC Data DAC Data X Write to buffer and update DAC n X W 0 0 1 0 Channel Address X W 0 0 1 1 Channel Address DAC Data DAC Data X W/R 0 1 0 0 X X X Ch-D Ch-C Ch-B Ch-A Power up/down DAC n X W/R 0 1 0 1 X X X X X X X CM1 CM0 Clear mode register X W/R 0 1 1 0 X X X X X Ch-D Ch-C Ch-B Ch-A LDAC register X W 0 1 1 1 X X X X X X PD1 PD0 X X Ch-B Ch-A X W/R 1 0 0 0 X X X X X X X 1 0 0 1 X X X X X X W/R 1 0 1 0 X X X X X X W 1 0 1 1 X X X X X X Software clear X X 1 1 0 0 X X X X X X Reserved X R 1 1 0 1 X X X X X Status register X W 1 1 1 0 X X X X X X No operation (NOP) X X 1 1 1 1 X X X X X X Reserved X X Software reset DSD 0 X Ch-D Ch-C DRDY Disable SDO register Reserved Short circuit limit register Table 4. Channel Address Bits CHANNEL ADDRESS BITS 22 DESCRIPTION D23 D22 D21 D20 0 0 0 0 Select channel A 0 0 0 1 Select channel B 0 0 1 0 Select channel C 0 0 1 1 Select channel D 1 1 1 1 Select all channel Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 DAC80004, DAC70004, DAC60004 www.ti.com SLASED6B – APRIL 2016 – REVISED JUNE 2016 8.4.3 DAC Power-Down Modes The DACx0004 use four modes of operation. These modes are accessed by setting command bits D28 – D24 and power-down register bits D09 and D08. The command bits must be set to 0100 (see Table 3). Once the command bits are set correctly, the four different power-down modes are software programmable by setting bits D09 and D08 in the shift register. Table 5 shows how to control the operating mode with data bits PD1 (D09), PD0 (D08). Table 5. Power-Down Bits POWER DOWN BITS DESCRIPTION D09 D08 0 0 Normal operation/power up selected channel(s) (Default) 0 1 Power down selected channel(s) 1 kΩ-GND 1 0 Power down selected channel(s) 100 kΩ-GND 1 1 Power down selected channel(s) Hi-Z It is possible to write to the DAC register/buffer of the DAC channel that is powered down. When the DAC channel is then powered up, it powers up to this new value. The advantage of the available power-down modes is that the output impedance of the device is known while it is in power-down mode. As described in Table 5, there are three different power-down options. VOUTX can be connected internally to GND through a 1 kΩ resistor, a 100 kΩ resistor, or open-circuited (Hi-Z). The DAC powerdown circuitry is shown in Figure 57. R2R Ladder Amplifier Power-Down Circuitry VOUTX Resistor Network Figure 57. DACx0004 Power Down 8.4.4 CLR Pin Functionality and Software CLEAR Mode The CLR pin is an asynchronous input pin to the DAC. When activated, this falling edge sensitive pin clears the DAC buffers and the DAC latches to zero, mid, full or user programmed code depending on the clear mode register (see Table 6). The default setting for clear operation is clear to 0 V. The device exits clear mode on the 32nd falling edge of the next write to the device. If the CLR pin receives a falling edge signal during a write sequence in normal operation, the clear mode is activated and changes the input and DAC registers immediately. Additionally, all DAC registers can also be cleared via SPI command 1011. Note that the clear mode bits determine the clear code for all the DACs upon clear operation. 8.4.4.1 DAC Clear Mode Registers The DACx0004 implement four different clear modes. These modes are accessed by setting command bits D28 – D24 and clear mode register bits D01 and D00. The command bits must be set to 0101 (see Table 3). Based on the value of clear mode register (see Table 6), all of the DAC and the buffers are cleared to zero, mid, or full-scale code, when the CLR pin sees a falling edge or after a software clear command is issued. The user defined clear scale can be set by writing 16-/14-/12- data to 1001 to bits D28 – D24. Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback 23 DAC80004, DAC70004, DAC60004 SLASED6B – APRIL 2016 – REVISED JUNE 2016 www.ti.com Table 6. Clear Mode Bits CLEAR MODE BITS DESCRIPTION D01 D00 0 0 All DACs clear to zero scale (default) 0 1 All DACs clear to mid scale 1 0 All DACs clear to full scale 8.4.5 LDAC Pin Functionality The DACx0004 devices offer both a software and hardware simultaneous update and control function. The DAC double-buffered architecture has been designed so that new data can be entered for each DAC without disturbing the analog outputs. Data updates can be performed either in synchronous or in asynchronous mode. In asynchronous mode, the LDAC pin is used as an active low signal for simultaneous DAC updates. Multiple single-channel writes can be done in order to set different channel buffers to desired values and then pulse the LDAC pin low to simultaneously update the DAC output registers. Data buffers of all channels must be loaded with desired data before an LDAC low pulse. After a LDAC low pulse, all DACs are simultaneously updated with the last contents of the corresponding data buffers. If the content of a data buffer is not changed, the corresponding DAC output remains unchanged after the LDAC pin is pulsed low. In synchronous mode, data are updated with the falling edge of the 32nd SCLK cycle, which follows a falling edge of SYNC. For such synchronous updates, the LDAC pin is not required, and it must be connected to GND permanently or asserted and held low before sending commands to the device. 8.4.5.1 Software LDAC Mode Registers Alternatively, all DAC outputs can be updated simultaneously using the built-in software function of LDAC. The LDAC register offers additional flexibility and control by allowing the selection of which DAC channel(s) should be updated simultaneously when the LDAC pin is being brought low. The LDAC register is loaded with a 4-bit word (D03 and D00) using command bits D28 – D24 (see Table 3). The default value for each bit, and therefore for each DAC channel, is zero. If the LDAC register bit is set to 1, it overrides the LDAC pin (the LDAC pin is internally tied low for that particular DAC channel), and this DAC channel updates synchronously after the falling edge of the 32nd SCLK cycle. However, if the LDAC register bit is set to 0, the DAC channel is controlled by the LDAC pin. See Table 7 for more information. Table 7. LDAC Register LDAC REGISTER BITS (D03 – D00) DAC UPDATE 0 Determined by LDAC pin (Default) 1 DAC channel ignores LDAC pin, DAC updates on 32nd falling edge of SCLK, DAC channels see LDAC as 0 8.4.6 Software Reset Mode The DACx0004 implements a software reset feature. The software reset function uses command bits D28 – D24 (see Table 3). Table 1 shows the reset values for different registers. 24 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 DAC80004, DAC70004, DAC60004 www.ti.com SLASED6B – APRIL 2016 – REVISED JUNE 2016 8.4.7 Output Short Circuit Limit Register The DACx0004 output amplifier has a default short circuit limit of 40 mA. However, this limit can be reduced to 30 mA by using command 1010 on bits D28 – D24 and selecting channel(s) (D03 – D00). Please note that DACx0004 has a dedicated bit per channel, this allows the user to set different short circuit limit for different DAC output channels. Table 8. Short Circuit Limit Register SHORT CIRCUIT LIMIT REGISTER BITS (D03 – D00) DAC SHORT CIRCUIT LIMIT 0 DAC output short circuit limit = 40 mA (Default) 1 DAC output short circuit limit = 30 mA 8.4.8 Status Register The DACx0004 implements a read-only status register (see Table 3). This register can be read by using command 1101 on bits D28 – D24, followed by a NOP command. Logic ‘1’ on bit D04 indicates that the device is ready to be used. This feature is useful to check if the device is ready to accept commands after power up. Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback 25 DAC80004, DAC70004, DAC60004 SLASED6B – APRIL 2016 – REVISED JUNE 2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.2 Typical Application - Digitally Controlled Asymmetric Bipolar Output VOUTA DACNEG RNEG RFB OPA277 DACx0004 RPOS VOUTB DACPOS + VOUT RA Figure 58. Asymmetric Bipolar Output Block Diagram 9.2.1 Design Requirements This design requires two channels of the DACx0004 to generate a bipolar output. The design is very flexible and allows for many different configurations. Typically, one channel is used to finely control the output, while the other is used to offset the output. The direction of the offset depends on which channel is used as an offset. DACPOS provides a positive offset and DACNEG has a negative offset. 9.2.2 Detailed Design Procedure The output of each DAC can be modified via the digital interface and the gain of each output can be modified independently by changing the external resistors. In order for the gain of each offset to be independent, Equation 2 must be true. æ 1 1 1 ö + RA = ç ÷ è RFB RNEG RPOS ø -1 (2) The output voltage range, VOUT, is adjusted according to Equation 3. Keep in mind that Equation 3 is only true when Equation 2 is true. R R VOUT = DACPOS ´ FB - DACNEG ´ FB RPOS RNEG (3) Each DAC outputs a voltage from 0 to REFIN. As an example, if DACPOS gain is 1, DACNEG gain is 2 and RFB = 2 kΩ, then RPOS = 2 kΩ, RNEG = 1 kΩ and RA = 1 kΩ. With the correct digital implementation it gives the output an effective output range of ±15 V, with discrete 16-bit steps. 26 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 DAC80004, DAC70004, DAC60004 www.ti.com SLASED6B – APRIL 2016 – REVISED JUNE 2016 Typical Application - Digitally Controlled Asymmetric Bipolar Output (continued) 9.2.3 Application Curve Figure 59 displays two different modes of operation. Mode 1 gains the output of DACNeg by a factor of 2 and maintains DACPOS at unity gain. Mode 2 reverses the gains of each stage to invert the system. These are just two examples of the types of outputs that can be achieved using this configuration. 15 Mode 1 Mode 2 Output Voltage (V) 10 5 0 -5 -10 512 11264 22016 32768 43520 Fine DAC Input Code 54272 65024 D001 Figure 59. Output Voltage vs Fine DAC Input Code Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback 27 DAC80004, DAC70004, DAC60004 SLASED6B – APRIL 2016 – REVISED JUNE 2016 www.ti.com 10 Power Supply Recommendations The DACx0004 can operate within the specified supply voltage range of 2.7 V to 5.5 V. The power applied to VDD should be well-regulated and have low-noise. Switching power supplies and DC-DC converters often have high frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high frequency spikes. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. A 1 µF to 10 µF capacitor and 0.1 µF bypass capacitor is recommended in order to further minimize noise from the power supply. The current consumption on the VDD pin, the short-circuit current limit, and the load current for the device are listed in the Electrical Characteristics. The power supply must meet the aforementioned current requirements. 28 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 DAC80004, DAC70004, DAC60004 www.ti.com SLASED6B – APRIL 2016 – REVISED JUNE 2016 11 Layout 11.1 Layout Guidelines A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. As a general rule it is important to keep digital traces as far away from analog traces when possible. The DACx0004 is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to keep digital noise from appearing at the output. Due to the single ground pin of the DACx0004, all return currents, including digital and analog return currents for the DAC, must flow through a single point. Ideally, GND must be connected directly to an analog ground plane. This plane must be separate from the ground connection for the digital components until they were connected at the power-entry point of the system. As with the GND connection, VDD should be connected to a 5 V power-supply plane or trace that is separate from the connection for digital logic until they are connected at the power-entry point. It is recommended to have an additional 1 μF to 10 μF capacitor and 0.1 μF bypass capacitor. In some situations, additional bypassing may be required, such as a 100 μF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all designed to essentially low-pass filter the 5 V supply, removing the high-frequency noise. In general it is always a good idea to maintain the digital signals away from analog signals. 11.2 Layout Example Figure 60. Layout Diagram Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback 29 DAC80004, DAC70004, DAC60004 SLASED6B – APRIL 2016 – REVISED JUNE 2016 www.ti.com 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 9. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY DAC60004 Click here Click here Click here Click here Click here DAC70004 Click here Click here Click here Click here Click here DAC80004 Click here Click here Click here Click here Click here 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. SPI, QSPI are trademarks of Motorola. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 30 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 DAC80004, DAC70004, DAC60004 www.ti.com SLASED6B – APRIL 2016 – REVISED JUNE 2016 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. DAC80004IPW Device Marking Addendum: Note that both DA80004 and XDC84 are valid Device Markings for the DAC80004IPW Orderable Device Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback 31 PACKAGE OPTION ADDENDUM www.ti.com 19-Jun-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DAC60004IDMDR ACTIVE VSON DMD 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 DA60004 DAC60004IDMDT ACTIVE VSON DMD 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 DA60004 DAC60004IPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 DA60004 DAC60004IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 DA60004 DAC70004IDMDR ACTIVE VSON DMD 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 DA70004 DAC70004IDMDT ACTIVE VSON DMD 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 DA70004 DAC70004IPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 DA70004 DAC70004IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 DA70004 DAC80004IDMDR ACTIVE VSON DMD 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 DA80004 DAC80004IDMDT ACTIVE VSON DMD 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 DA80004 DAC80004IPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 DA80004 DAC80004IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 DA80004 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 19-Jun-2016 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jun-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DAC60004IDMDT VSON SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DMD 14 250 180.0 12.4 3.3 4.3 1.1 8.0 12.0 Q1 DAC60004IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 DAC70004IDMDT VSON DMD 14 250 180.0 12.4 3.3 4.3 1.1 8.0 12.0 Q1 DAC70004IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 DAC80004IDMDT VSON DMD 14 250 180.0 12.4 3.3 4.3 1.1 8.0 12.0 Q1 DAC80004IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jun-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC60004IDMDT VSON DMD DAC60004IPWR TSSOP PW 14 250 195.0 200.0 45.0 14 2000 367.0 367.0 35.0 DAC70004IDMDT VSON DMD DAC70004IPWR TSSOP PW 14 250 195.0 200.0 45.0 14 2000 367.0 367.0 DAC80004IDMDT VSON 35.0 DMD 14 250 195.0 200.0 45.0 DAC80004IPWR TSSOP PW 14 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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