TI1 BQ4285LS Enhanced rtc with nvram control Datasheet

bq4285E/L
Enhanced RTC With NVRAM Control
Features
➤ BCD or binary format for clock
and calendar data
General Description
➤ Direct clock/calendar replacement for IBM® AT-compatible
computers and other applications
➤ Calendar in day of the week, day
of the month, months, and years,
with automatic leap-year adjustment
The CMOS bq4285E/L is a low-power
microprocessor peripheral providing a
time-of-day clock and 100-year calendar with alarm features and battery
operation. Other features include
three maskable interrupt sources,
square wave output, and 114 bytes of
general nonvolatile storage.
➤ 114 bytes of general nonvolatile
storage
➤ Enhanced features include:
-
System wake-up capability—
alarm interrupt output active
in battery-backup mode
➤ Time of day in seconds, minutes,
and hours
-
12- or 24-hour format
Optional daylight saving
adjustment
-
2.7–3.6V operation (bq4285L);
4.5–5.5V operation (bq4285E)
➤ Programmable square wave output
-
32kHz output for power
management
➤ Three individually maskable interrupt event flags:
➤ Automatic backup and writeprotect control to external SRAM
-
Periodic rates from 122µs to
500ms
➤ Functionally compatible with the
DS1285
-
Time-of-day alarm once per
second to once per day
➤ Less than 0.5 µA load under battery operation
-
End-of-clock update cycle
➤ 24-pin plastic DIP or SOIC
A 32.768kHz output is available for
sustaining power-management activities. Wake-up capability is provided by
an alarm interrupt, which is active in
battery-backup mode.
The bq4285E/L write-protects the
clock, calendar, and storage registers
during power failure. A backup battery then maintains data and operates the clock and calendar.
The bq4285E/L is a fully compatible
re a l - ti me cl o ck f o r IB M ATcompatible computers and other applications. The only external components are a 32.768kHz crystal and a
backup battery.
T h e b q 4 2 8 5 E / L i n te g ra te s a
battery-backup controller to make a
➤ 14 bytes for clock/calendar and
control
Pin Names
Pin Connections
AD0–AD7
VOUT
X1
X2
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
VSS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
SQW
CEOUT
CEIN
BC
INT
RST
DS
VSS
R/W
AS
CS
24-Pin DIP or SOIC
28-Pin PLCC: No Longer Available
PN428501.eps
SLUS006A - MAY 1994 - REVISED MAY 2004
1
MOT
Multiplexed address/data
input/output
Bus type select input
CS
AS
DS
R/W
INT
RST
SQW
BC
X1–X2
NC
CEIN
CEOUT
VOUT
VCC
Chip select input
Address strobe input
Data strobe input
Read/write input
Interrupt request output
Reset input
Square wave output
3V backup cell input
Crystal inputs
No connect
RAM chip enable input
RAM chip enable output
Supply output
+5V supply
bq4285E/L
Block Diagram
standard CMOS SRAM nonvolatile during power-fail
conditions. During power-fail, the bq4285E/L automatically write-protects the external SRAM and provides a V CC output sourced from the clock backup
battery.
The setting should not be changed during
system operation. MOT is internally pulled
low by a 20KΩ resistor. For the DIP and
SOIC packages, this pin is internally connected to VSS, enabling the bus timing for
the Intel architecture.
Pin Descriptions
AD0–AD7
CS
Multiplexed address/data input/
output
CS should be driven low and held stable
during the data-transfer phase of a bus cycle accessing the bq4285E/L.
The bq4285E/L bus cycle consists of two
phases: the address phase and the datatransfer phase. The address phase precedes
the data-transfer phase. During the address phase, an address placed on AD0–AD7
is latched into the bq4285E/L on the falling
edge of the AS signal. During the datatransfer phase of the bus cycle, the AD0–AD7
pins serve as a bidirectional data bus.
MOT
Chip select input
Table 1. Bus Setup
Bus
Type
MOT
DS
R/W
AS
Level Equivalent Equivalent Equivalent
Connect to VSS for normal operation
Intel
2
VSS
RD,
MEMR, or
I/OR
WR,
MEMW, or ALE
I/OW
bq4285E/L
AS
Reset may be disabled by connecting RST to
VCC. This allows the control bits to retain their
states through power-down/power-up cycles.
Address strobe input
AS serves to demultiplex the address/data
bus. The falling edge of AS latches the address on AD0–AD7. This demultiplexing process is independent of the CS signal.
DS
SQW
Data strobe input
With MOT = VSS, the DS input is provided a signal similar to RD, MEMR, or I/OR in an
Intel-based system. The falling edge on DS
is used to enable the outputs during a read
cycle.
BC
R/W
Read/write input
A 32.768kHz output is enabled by setting
the SQWE bit in register B to 1 and the
32KE bit in register C to 1 after setting
OSC2–OSC0 in register A to 011 (binary).
3V backup cell input
Upon power-up, a voltage within the VBC
range must be present on the BC pin for
the oscillator to start up.
Crystal inputs
The X1–X2 inputs are provided for an external 32.768Khz quartz crystal, Daiwa
DT-26 or equivalent, with 6pF load capacitance. A trimming capacitor may be necessary for extremely precise time-base generation.
Interrupt request output
CEIN
INT is an open-drain output. This allows
INT to be valid in battery-backup mode for
the alarm interrupt. To use this feature,
INT must be connected to a power supply
other than VCC. INT is asserted low when
any event flag is set and the corresponding
event enable bit is also set. INT becomes
high-impedance whenever register C is read
(see the Control/Status Registers section).
RST
SQW may output a programmable frequency square-wave signal during normal
(VCC valid) system operation. Any one of
the 13 specific frequencies may be selected
through register A. This pin is held low
when the square-wave enable bit (SQWE)
in register B is 0 (see the Control/Status
Registers section).
BC should be connected to a 3V backup cell
for RTC operation and storage register nonvolatility in the absence of power. When VCC
slews down past VBC (3V typical), the integral control circuitry switches the power
source to BC. When VCC returns above VBC,
the power source is switched to VCC.
With MOT = VSS, R/W is provided a signal similar to WR, MEMW, or I/OW in an Intelbased system. The rising edge on R/W
latches data into the bq4285E/L.
X1–X2
INT
Square-wave output
External RAM chip enable input,
active low
CEIN should be driven low to enable the
controlled external RAM. CEIN is internally
pulled up with a 50KΩ resistor.
CEOUT
External RAM chip enable output,
active low
When power is valid, CEOUT reflects CEIN.
Reset input
VOUT
The bq4285E/L is reset when RST is pulled
low. When reset, INT becomes highimpedance, and the bq4285E/L is not accessible. Table 4 in the Control/Status Registers
section lists the register bits that are cleared
by a reset.
Supply output
VOUT provides the higher of VCC or VBC,
switched internally, to supply external RAM.
3
VCC
Positive power supply
VSS
Ground
bq4285E/L
Functional Description
update period (see Figure 2). The alarm flag bit may
also be set during the update cycle.
Address Map
The bq4285E/L copies the local register updates into the
user buffer accessed by the host processor. When a 1 is
written to the update transfer inhibit bit (UTI) in register B, the user copy of the clock and calendar bytes remains unchanged, while the local copy of the same bytes
continues to be updated every second.
The bq4285E/L provides 14 bytes of clock and control/status registers and 114 bytes of general nonvolatile
storage. Figure 1 illustrates the address map for the
bq4285L.
The update-in-progress bit (UIP) in register A is set
tBUC time before the beginning of an update cycle (see
Figure 2). This bit is cleared and the update-complete
flag (UF) is set at the end of the update cycle.
Update Period
The update period for the bq4285E/L is one second. The
bq4285E/L updates the contents of the clock and calendar locations during the update cycle at the end of each
Figure 1. Address Map
Figure 2. Update Period Timing and UIP
4
bq4285E/L
Programming the RTC
2.
Write new values to all the time, alarm, and
calendar locations.
The time-of-day, alarm, and calendar bytes can be written
in either the BCD or binary format (see Table 2).
3.
Clear the UTI bit to allow update transfers.
On the next update cycle, the RTC updates all 10 bytes
in the selected format.
These steps may be followed to program the time, alarm,
and calendar:
1.
Square-Wave Output
Modify the contents of register B:
a.
Write a 1 to the UTI bit to prevent transfers between RTC bytes and user buffer.
b.
Write the appropriate value to the data format (DF) bit to select BCD or binary format
for all time, alarm, and calendar bytes.
c.
Write the appropriate value to the hour
format (HF) bit.
The bq4285E/L divides the 32.768kHz oscillator frequency to produce the 1 Hz update frequency for the
clock and calendar. Thirteen taps from the frequency divider are fed to a 16:1 multiplexer circuit. The output of
this mux is fed to the SQW output and periodic interrupt generation circuitry. The four least-significant bits
of register A, RS0–RS3, select among the 13 taps (see
Table 3). The square-wave output is enabled by writing
a 1 to the square-wave enable bit (SQWE) in register B.
A 32.768kHz output may be selected by setting
OSC2–OSC0 in register A to 011 while SQWE = 1 and
32KE = 1.
Table 2. Time, Alarm, and Calendar Formats
Range
Address
RTC Bytes
Decimal
Binary
Binary-Coded
Decimal
0
Seconds
0–59
00H–3BH
00H–59H
1
Seconds alarm
0–59
00H–3BH
00H–59H
2
Minutes
0–59
00H–3BH
00H–59H
3
Minutes alarm
0–59
00H–3BH
00H–59H
Hours, 12-hour format
1–12
01H–OCH AM;
81H–8CH PM
01H–12H AM;
81H–92H PM
Hours, 24-hour format
0–23
00H–17H
00H–23H
Hours alarm, 12-hour format
1–12
01H–OCH AM;
81H–8CH PM
01H–12H AM;
81H–92H PM
Hours alarm, 24-hour format
0–23
00H–17H
00H–23H
6
Day of week (1=Sunday)
1–7
01H–07H
01H–07H
7
Day of month
1–31
01H–1FH
01H–31H
8
Month
1–12
01H–0CH
01H–12H
9
Year
0–99
00H–63H
00H–99H
4
5
5
bq4285E/L
Interrupts
Two methods can be used to process bq4285E/L interrupt events:
The bq4285E/L allows three individually selected interrupt events to generate an interrupt request. These
three interrupt events are:
n
n
n
n
The periodic interrupt, programmable to occur once
every 122 µs to 500 ms.
n
The alarm interrupt, programmable to occur once per
second to once per day, is active in battery-backup
mode, providing a “wake-up” feature.
Enable interrupt events and use the interrupt request
output to invoke an interrupt service routine.
Do not enable the interrupts and use a polling routine
to periodically check the status of the flag bits.
The individual interrupt sources are described in detail
in the following sections.
Periodic Interrupt
The update-ended interrupt, which occurs at the end
of each update cycle.
The mux output used to drive the SQW output also
drives the interrupt-generation circuitry. If the periodic
interrupt event is enabled by writing a 1 to the periodic
interrupt enable bit (PIE) in register C, an interrupt request is generated once every 122µs to 500ms. The period between interrupts is selected by the same bits in
register A that select the square wave frequency (see Table 3). Setting OSC2–OSC0 in register A to 011 does
not affect the periodic interrupt timing.
Each of the three interrupt events is enabled by an individual interrupt-enable bit in register B. When an event
occurs, its event flag bit in register C is set. If the corresponding event enable bit is also set, then an interrupt
request is generated. The interrupt request flag bit
(INTF) of register C is set with every interrupt request.
Reading register C clears all flag bits, including INTF,
and makes INT high-impedance.
Table 3. Square-Wave Frequency/Periodic Interrupt Rate
Register A Bits
Square Wave
OSC2
OSC1
OSC0
RS3
RS2
RS1
RS0
Frequency
0
1
0
0
0
0
0
None
0
1
0
0
0
0
1
256
Hz
3.90625
ms
0
1
0
0
0
1
0
128
Hz
7.8125
ms
0
1
0
0
0
1
1
8.192
kHz
122.070
µs
0
1
0
0
1
0
0
4.096
kHz
244.141
µs
0
1
0
0
1
0
1
2.048
kHz
488.281
µs
0
1
0
0
1
1
0
1.024
kHz
976.5625
0
1
0
0
1
1
1
512
Hz
1.95315
ms
0
1
0
1
0
0
0
256
Hz
3.90625
ms
0
1
0
1
0
0
1
128
Hz
7.8125
ms
0
1
0
1
0
1
0
64
Hz
15.625
ms
0
1
0
1
0
1
1
32
Hz
31.25
ms
0
1
0
1
1
0
0
16
Hz
62.5
0
1
0
1
1
0
1
8
Hz
125
ms
0
1
0
1
1
1
0
4
Hz
250
ms
0
1
0
1
1
1
1
2
Hz
500
ms
0
1
1
X
X
X
X
kHz
same as above defined
by RS3–RS0
6
32.768
Units
Periodic Interrupt
Period
Units
None
µs
ms
bq4285E/L
Accessing RTC bytes
Alarm Interrupt
The alarm interrupt request is valid in battery-backup
mode, providing a “wake-up” capability. During each update cycle, the RTC compares the hours, minutes, and
seconds bytes with the three corresponding alarm bytes.
If a match of all bytes is found, the alarm interrupt
event flag bit, AF in register C, is set to 1. If the alarm
event is enabled, an interrupt request is generated.
Time and calendar bytes read during an update cycle
may be in error. Three methods to access the time and
calendar bytes without ambiguity are:
n
An alarm byte may be removed from the comparison by
setting it to a “don’t care” state. An alarm byte is set to a
“don’t care” state by writing a 1 to each of its two mostsignificant bits. A “don’t care” state may be used to select
the frequency of alarm interrupt events as follows:
n
n
n
n
n
n
If none of the three alarm bytes is “don’t care,” the
frequency is once per day, when hours, minutes, and
seconds match.
If only the hour alarm byte is “don’t care,” the
frequency is once per hour, when minutes and
seconds match.
Enable the update interrupt event to generate
interrupt requests at the end of the update cycle.
The interrupt handler has a maximum of 999ms to
access the clock bytes before the next update cycle
begins (see Figure 3).
Poll the update-in-progress bit (UIP) in register A. If
UIP = 0, the polling routine has a minimum of tBUC
time to access the clock bytes (see Figure 3).
Use the periodic interrupt event to generate
interrupt requests every tPI time, such that UIP = 1
always occurs between the periodic interrupts. The
interrupt handler will have a minimum of tPI/2 +
tBUC time to access the clock bytes (see Figure 3).
Oscillator Control
If only the hour and minute alarm bytes are “don’t care,”
the frequency is once per minute, when seconds match.
When power is first applied to the bq4285E/L and VCC is
above VPFD, the internal oscillator and frequency divider
are turned on by writing a 010 pattern to bits 4 through 6
of register A. A pattern of 011 behaves as 010 but additionally transforms register C into a read/write register.
This allows the 32.768kHz output on the square wave pin
to be turned on. A pattern of 11X turns the oscillator on,
but keeps the frequency divider disabled. Any other pattern to these bits keeps the oscillator off.
If the hour, minute, and second alarm bytes are
“don’t care,” the frequency is once per second.
Update Cycle Interrupt
The update cycle ended flag bit (UF) in register C is set to
a 1 at the end of an update cycle. If the update interrupt
enable bit (UIE) of register B is 1, and the update transfer
inhibit bit (UTI) in register B is 0, then an interrupt request is generated at the end of each update cycle.
Figure 3. Update-Ended/Periodic Interrupt Relationship
7
bq4285E/L
not terminated within time tWPT (30µs maximum), the
chip enable output is unconditionally driven high,
write-protecting the controlled SRAM.
Power-Down/Power-Up Cycle
The bq4285E/L power-up/power-down cycles are different. The bq4285L continuously monitors VCC for out-oftolerance. During a power failure, when VCC falls below
VPFD (2.53V typical), the bq4285L write-protects the clock
and storage registers. The power source is switched to BC
when VCC is less than VPFD and BC is greater than VPFD,
or when VCC is less than VBC and VBC is less than VPFD.
RTC operation and storage data are sustained by a valid
backup energy source. When VCC is above VPFD, the power
source is VCC. Write-protection continues for tCSR time after VCC rises above VPFD.
As the supply continues to fall past VPFD, an internal
switching device forces VOUT to the external backup energy
source. CEOUT is held high by the VOUT energy source.
During power-up, VOUT is switched back to the main
supply as VCC rises above the backup cell input voltage
sourcing VOUT. If VPFD < VBC on the bq4285L, the
switch to the main supply occurs at VPFD. CEOUT is held
inactive for time tCER (200ms maximum) after the power
supply has reached VPFD, independent of the CEIN input, to allow for processor stabilization.
The bq4285E continuously monitors V CC for out-oftolerance. During a power failure, when VCC falls below
VPFD (4.17V typical), the bq4285E write-protects the clock
and storage registers. When VCC is below VBC (3V typical),
the power source is switched to BC. RTC operation and
storage data are sustained by a valid backup energy source.
When VCC is above VBC, the power source is VCC. Writeprotection continues for tCSR time after VCC rises above
VPFD.
During power-valid operation, the CEIN input is passed
through to the CEOUT output with a propagation delay
of less than 10ns.
Figure 4 shows the hardware hookup for the external RAM.
A primary backup energy source input is provided on
the bq4285E/L. The BC input accepts a 3V primary battery, typically some type of lithium chemistry. To prevent battery drain when there is no valid data to retain,
VOUT and CEOUT are internally isolated from BC by the
initial connection of a battery. Following the first application of VCC above VPFD, this isolation is broken, and
the backup cell provides power to VOUT and CEOUT for
the external SRAM.
An external CMOS static RAM is battery-backed using
the V O U T and chip enable output pins from the
bq4285E/L. As the voltage input VCC slows down during
a power failure, the chip enable output, CEOUT, is forced
inactive independent of the chip enable input CEIN.
This activity unconditionally write-protects the external
SRAM as VCC falls below VPFD. If a memory access is in
process to the external SRAM during power-fail detection, that memory cycle continues to completion before
the memory is write-protected. If the memory cycle is
Figure 4. External RAM Hookup to the bq4285E/L RTC
8
bq4285E/L
The four control/status registers of the bq4285E/L are
accessible regardless of the status of the update cycle
(see Table 4).
vider. A pattern of 011 behaves as 010 but additionally
transforms register C into a read/write register. This allows the 32.768kHz output on the square wave pin to be
turned on. A pattern of 11X turns the oscillator on, but
keeps the frequency divider disabled. When 010 is written, the RTC begins its first update after 500ms.
Register A
UIP - Update Cycle Status
Control/Status Registers
7
UIP
6
OS2
Register A Bits
5
4
3
2
OS1 OS0 RS3 RS2
1
RS1
7
UIP
0
RS0
Register A programs:
n
n
5
-
4
-
3
-
2
-
1
-
0
-
This read-only bit is set prior to the update cycle. When
UIP equals 1, an RTC update cycle may be in progress.
UIP is cleared at the end of each update cycle. This bit
is also cleared when the update transfer inhibit (UTI)
bit in register B is 1.
The frequency of the square-wave and the periodic
event rate.
Oscillator operation.
Register A provides:
n
6
-
Register B
Status of the update cycle.
RS0–RS3 - Frequency Select
7
-
6
-
5
-
4
-
3
RS3
2
RS2
1
RS1
7
UTI
0
RS0
6
PIE
5
AIE
Register B Bits
4
3
2
UIE SQWE DF
1
HF
0
DSE
Register B enables:
These bits select one of the 13 frequencies for the SQW output and the periodic interrupt rate, as shown in Table 3.
n
Update cycle transfer operation
n
Square-wave output
n
Interrupt events
n
Daylight saving adjustment
OS0–OS2 - Oscillator Control
7
-
6
OS2
5
OS1
4
OS0
3
-
2
-
1
-
0
-
Register B selects:
n
These three bits control the state of the oscillator and divider stages. A pattern of 010 enables RTC operation by
turning on the oscillator and enabling the frequency di-
Clock and calendar data formats
All bits of register B are read/write.
Table 4. Control/Status Registers
Reg.
7 (MSB)
6
5
4
3
2
Yes1
UIP
na OS2 na OS1 na OS0 na
Yes
Yes
UTI
na
PIE
0
AIE
0
UIE
0 SQWE
0
Yes
No2 INTF
0
PF
0
AF
0
UF
0
-
0
Yes
No
na
-
0
-
0
-
0
-
0
A
0A
Yes
B
0B
C
0C
D
0D
Notes:
Bit Name and State on Reset
Loc.
(Hex) Read Write
VRT
RS3
na = not affected.
1. Except bit 7.
2. Read/write only when OSC2–OSC0 in register A is 011 (binary).
9
1
0 (LSB)
na RS2 na RS1 na
DF
na
32KE na
-
0
HF
RS0 na
na DSE na
-
0
-
0
-
0
-
0
bq4285E/L
DSE - Daylight Saving Enable
7
-
6
-
5
-
4
-
UIE - Update Cycle Interrupt Enable
3
-
2
-
1
-
0
DSE
7
-
This bit enables daylight-saving time adjustments when
written to 1:
n
n
5
-
4
-
3
-
2
-
1
HF
4
UIE
3
-
2
-
1
-
0
-
1 = Enabled
0 = Disabled
The UIE bit is automatically cleared when the UTI bit
equals 1.
On the first Sunday in April, the time springs
forward from 2:00:00 AM to 3:00:00 AM.
6
-
5
-
This bit enables an interrupt request due to an update
ended interrupt event:
On the last Sunday in October, the first time the
bq4285E/L increments past 1:59:59 AM, the time
falls back to 1:00:00 AM.
7
-
6
-
AIE - Alarm Interrupt Enable
0
-
7
-
HF - Hour Format
This bit selects the time-of-day and alarm hour format:
6
-
5
AIE
4
-
3
-
2
-
1
-
0
-
This bit enables an interrupt request due to an alarm
interrupt event:
1 = 24-hour format
1 = Enabled
0 = 12-hour format
0 = Disabled
7
-
6
-
5
-
4
-
3
-
2
DF
1
-
0
-
PIE - Periodic Interrupt Enable
7
-
DF - Data Format
This bit selects the numeric format in which the time,
alarm, and calendar bytes are represented:
1 = Binary
6
PIE
5
-
4
-
3
-
2
-
1
-
0
-
This bit enables an interrupt request due to a periodic
interrupt event:
1 = Enabled
0 = BCD
0 = Disabled
7
-
6
-
5
-
4
-
3
SQWE
2
-
1
-
0
-
UTI - Update Transfer Inhibit
7
UTI
SQWE - Square-Wave Enable
6
-
5
-
4
-
3
-
2
-
1
-
0
-
This bit enables the square-wave output:
This bit inhibits the transfer of RTC bytes to the user
buffer:
1 = Enabled
0 = Disabled and held low
1 = Inhibits transfer and clears UIE
0 = Allows transfer
10
bq4285E/L
INTF - Interrupt Request Flag
Register C
7
INTF
6
PF
5
AF
Register C Bits
4
3
2
UF
0
32KE
1
0
7
INTF
0
0
6
-
5
-
4
-
3
-
2
-
1
-
0
-
This flag is set to a 1 when any of the following is true:
Register C is the read-only event status register.
AIE = 1 and AF = 1
Bits 0–3 - Unused Bits
7
-
6
-
PIE = 1 and PF = 1
5
-
4
-
3
0
2
-
1
0
0
0
UIE = 1 and UF = 1
Reading register C clears this bit.
These bits are always set to 0.
Register D
32KE–32KHz Enable Output
7
-
6
-
5
-
4
-
3
-
2
32KE
1
-
7
VRT
0
-
6
0
5
0
Register D Bits
4
3
0
0
2
0
1
0
0
0
Register D is the read-only data integrity status register.
This bit may be set to a 1 only when the OSC2–OSC0
bits in register A are set to 011. Setting OSC2–OSC0 to
anything other than 011 clears this bit. If SQWE in register B and 32KE are set, a 32.768KHz waveform is output on the square wave pin.
Bits 0–6 - Unused Bits
7
-
UF - Update-Event Flag
7
-
6
-
5
-
6
0
5
0
4
0
3
0
2
0
1
0
0
0
3
-
2
-
1
-
0
-
These bits are always set to 0.
4
UF
3
-
2
-
1
-
0
-
VRT - Valid RAM and Time
This bit is set to a 1 at the end of the update cycle.
Reading register C clears this bit.
7
VRT
6
-
5
-
4
-
1 = Valid backup energy source
AF - Alarm Event Flag
0 = Backup energy source is depleted
7
-
6
-
5
AF
4
-
3
-
2
-
1
-
When the backup energy source is depleted (VRT = 0),
data integrity of the RTC and storage registers is not
guaranteed.
0
-
This bit is set to a 1 when an alarm event occurs. Reading register C clears this bit.
PF - Periodic Event Flag
7
-
6
PF
5
-
4
-
3
-
2
-
1
-
0
-
This bit is set to a 1 every tPI time, where tPI is the time
period selected by the settings of RS0–RS3 in register A.
Reading register C clears this bit.
11
bq4285E/L
Absolute Maximum Ratings—bq4285E
Value
Unit
VCC
Symbol
DC voltage applied on VCC relative to VSS
Parameter
-0.3 to 7.0
V
VT
DC voltage applied on any pin excluding VCC
relative to VSS
-0.3 to 7.0
V
TOPR
Operating temperature
VT ≤ VCC + 0.3
0 to +70
°C
Commercial
-40 to +85
°C
Industrial “N”
TSTG
Storage temperature
-55 to +125
°C
TBIAS
Temperature under bias
-40 to +85
°C
TSOLDER
Soldering temperature
260
°C
Note:
Conditions
For 10 seconds
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to
conditions beyond the operational limits for extended periods of time may affect device reliability.
Absolute Maximum Ratings—bq4285L
Symbol
Parameter
Value
Unit
Conditions
VCC
DC voltage applied on VCC relative to VSS
-0.3 to 6.0
V
VT
DC voltage applied on any pin excluding VCC
relative to VSS
-0.3 to 6.0
V
VT ≤ VCC + 0.3
TOPR
Operating temperature
0 to +70
°C
Commercial
TSTG
Storage temperature
-55 to +125
°C
TBIAS
Temperature under bias
-40 to +85
°C
TSOLDER
Soldering temperature
260
°C
Note:
For 10 seconds
Permanent device damage may occur if Absolute Maximum Ratings are exceeded.
Functional operation should be limited to the Recommended DC Operating Conditions detailed
in this data sheet. Exposure to conditions beyond the operational limits for extended periods of
time may affect device reliability.
12
bq4285E/L
Recommended DC Operating Conditions—bq4285E (TA = TOPR)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
VCC
Supply voltage
4.5
5.0
5.5
V
VIL
Input low voltage
-0.3
-
0.8
V
VIH
Input high voltage
2.2
-
VCC + 0.3
V
VBC
Backup cell voltage
2.5
-
4.0
V
Notes:
Typical values indicate operation at TA = 25°C.
Potentials are relative to VSS.
Recommended DC Operating Conditions—bq4285L (TA = TOPR)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
VCC
Supply voltage
2.7
3.15
3.6
V
VIL
Input low voltage
-0.3
-
0.6
V
VIH
Input high voltage
2.2
-
VCC + 0.3
V
VBC
Backup cell voltage
2.4
-
4.0
V
Notes:
Typical values indicate operation at TA = 25°C.
Potentials are relative to VSS.
Crystal Specifications—bq4285E/L (DT-26 or Equivalent)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
fO
Oscillation frequency
-
32.768
-
kHz
CL
Load capacitance
-
6
-
pF
TP
Temperature turnover point
20
25
30
°C
k
Parabolic curvature constant
-
-
-0.042
ppm/°C
Q
Quality factor
40,000
70,000
-
R1
Series resistance
-
-
45
KΩ
C0
Shunt capacitance
-
1.1
1.8
pF
C0/C1
Capacitance ratio
-
430
600
DL
Drive level
-
-
1
µW
∆f/fO
Aging (first year at 25°C)
-
1
-
ppm
13
bq4285E/L
DC Electrical Characteristics—bq4285E (TA = TOPR, VCC = 5V ± 10%)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Conditions/Notes
ILI
Input leakage current
-
-
±1
µA
VIN = VSS to VCC
ILO
Output leakage current
-
-
±1
µA
AD0–AD7, INT, and SQW
in high impedance,
VOUT = VSS to VCC
VOH
Output high voltage
2.4
-
-
V
IOH = -2.0 mA
VOL
Output low voltage
-
-
0.4
V
IOL = 4.0 mA
ICC
Operating supply current
-
7
15
mA
VSO
Supply switch-over voltage
-
VBC
-
V
ICCB
Battery operation current
-
0.3
0.5
µA
VBC = 3V, TA = 25°C, no
load on VOUT or CEOUT
ICCSB
Standby supply current
-
300
-
µA
VIN = VCC or VSS,
CS ≥ VCC - 0.2,
no load on VOUT
VPFD
Power-fail-detect voltage
4.0
4.17
4.35
V
VOUT1
VOUT voltage
VCC - 0.3V
-
-
V
VOUT2
VOUT voltage
VBC - 0.3V
ICE
Chip enable input current
Note:
-
IOUT = 100mA, VCC >VBC
IOUT = 100µA, VCC < VBC
-
100
Typical values indicate operation at TA = 25°C, VCC = 5V or VBC = 3V.
14
Min. cycle, duty = 100%,
IOH = 0mA, IOL = 0mA
µA
Internal 50K pull-up
bq4285E/L
DC Electrical Characteristics—bq4285L (TA = TOPR, VCC = 3.13V ± 0.45%)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Conditions/Notes
ILI
Input leakage current
-
-
±1
µA
VIN = VSS to VCC
ILO
Output leakage current
-
-
±1
µA
AD0–AD7, INT, and SQW
in high impedance,
VOUT = VSS to VCC
VOH
Output high voltage
2.2
-
-
V
IOH = -2.0 mA
VOL
Output low voltage
-
-
0.4
V
IOL = 4.0 mA
ICC
Operating supply current
-
5
9
mA
-
V
VBC > VPFD
Supply switch-over voltage
VPFD
-
VSO
-
VBC
-
V
VBC < VPFD
Min. cycle, duty = 100%,
IOH = 0mA, IOL = 0mA
ICCB
Battery operation current
-
0.3
0.5
µA
VBC = 3V, TA = 25°C, no
load on VOUT or CEOUT
ICCSB
Standby supply current
-
100
-
µA
VIN = VCC or VSS,
CS ≥ VCC - 0.2,
no load on VOUT
VPFD
Power-fail-detect voltage
2.4
2.53
2.65
V
VOUT1
VOUT voltage
VCC - 0.3V
-
-
V
VOUT2
VOUT voltage
VBC - 0.3V
ICE
Chip enable input current
Note:
-
IOUT = 100µA, VCC < VBC
-
Typical values indicate operation at TA = 25°C, VCC = 3V.
15
IOUT = 80mA, VCC >VBC
120
µA
Internal 30K pull-up
bq4285E/L
Capacitance—bq4285E/L (TA = 25°C, F = 1MHz, VCC = 5.0V)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Conditions
CI/O
Input/output capacitance
-
-
7
pF
VOUT = 0V
CIN
Input capacitance
-
-
5
pF
VIN = 0V
Note:
This parameter is sampled and not 100% tested. It does not include the X1 or X2 pin.
AC Test Conditions—bq4285E
Parameter
Test Conditions
Input pulse levels
0 to 3.0 V
Input rise and fall times
5 ns
Input and output timing reference levels
1.5 V (unless otherwise specified)
Output load (including scope and jig)
See Figures 5 and 6
+5V
+5V
1.15K
960
For all outputs
except INT
510
INT
50pF
130pF
OL-10
OL-11
Figure 6. Output Load B—bq4285E
Figure 5. Output Load A—bq4285E
16
bq4285E/L
AC Test Conditions—bq4285L
Parameter
Test Conditions
Input pulse levels
0 to 2.3 V
Input rise and fall times
5 ns
Input and output timing reference levels
1.2 V (unless otherwise specified)
Output load (including scope and jig)
See Figures 7 and 8
Figure 7. Output Load A—bq4285L
Figure 8. Output Load B—bq4285L
17
bq4285E/L
Read/Write Timing—bq4285E (TA = TOPR, VCC = 5V ± 10%)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
tCYC
Cycle time
160
-
-
ns
tDSL
DS low or RD/WR high time
80
-
-
ns
tDSH
DS high or RD/WR low time
55
-
-
ns
tRWH
R/W hold time
0
-
-
ns
tRWS
R/W setup time
10
-
-
ns
tCS
Chip select setup time
5
-
-
ns
tCH
Chip select hold time
0
-
-
ns
tDHR
Read data hold time
0
-
25
ns
tDHW
Write data hold time
0
-
-
ns
tAS
Address setup time
20
-
-
ns
tAH
Address hold time
5
-
-
ns
tDAS
Delay time, DS to AS rise
10
-
-
ns
tASW
Pulse width, AS high
30
-
-
ns
tASD
Delay time, AS to DS rise
(RD/WR fall)
35
-
-
ns
tOD
Output data delay time from DS
rise (RD fall)
-
-
50
ns
tDW
Write data setup time
30
-
-
ns
tBUC
Delay time before update
-
244
-
µs
tPI
Periodic interrupt time interval
-
-
-
-
tUC
Time of update cycle
-
1
-
µs
18
Notes
See Table 3
bq4285E/L
Read/Write Timing—bq4285L (TA = TOPR, VCC = 3.15V ± 0.45%)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
tCYC
Cycle time
270
-
-
ns
tDSL
DS low or RD/WR high time
135
-
-
ns
tDSH
DS high or RD/WR low time
90
-
-
ns
tRWH
R/W hold time
0
-
-
ns
tRWS
R/W setup time
15
-
-
ns
tCS
Chip select setup time
8
-
-
ns
tCH
Chip select hold time
0
-
-
ns
tDHR
Read data hold time
0
-
40
ns
tDHW
Write data hold time
0
-
-
ns
tAS
Address setup time
30
-
-
ns
tAH
Address hold time
15
-
-
ns
tDAS
Delay time, DS to AS rise
15
-
-
ns
tASW
Pulse width, AS high
50
-
-
ns
tASD
Delay time, AS to DS rise
(RD/WR fall)
55
-
-
ns
tOD
Output data delay time from DS
rise (RD fall)
-
-
100
ns
tDW
Write data setup time
50
-
-
ns
tBUC
Delay time before update
-
244
-
µs
tPI
Periodic interrupt time interval
-
-
-
-
tUC
Time of update cycle
-
1
-
µs
19
Notes
See Table 3
bq4285E/L
Motorola Bus Read/Write Timing—bq4285E/L (PLCC Package Only) Note: Package OBSOLETE
20
bq4285E/L
Intel Bus Read Timing—bq4285E/L
Intel Bus Write Timing—bq4285E/L
21
bq4285E/L
Power-Down/Power-Up Timing—bq4285E (TA = TOPR)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Conditions
tF
VCC slew from 4.5V to 0V
300
-
-
µs
tR
VCC slew from 0V to 4.5V
100
-
-
µs
tCSR
CS at VIH after power-up
20
-
200
ms
Internal write-protection
period after VCC passes VPFD
on power-up.
tWPT
Write-protect time for
external RAM
10
16
30
µs
Delay after VCC slows down
past VPFD before SRAM is
write-protected.
tCER
Chip enable recovery time
tCSR
-
tCSR
ms
Time during which external
SRAM is write-protected after
VCC passes VPFD on power-up.
tCED
Chip enable propagation
delay to external SRAM
-
7
10
ns
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing—bq4285E
22
bq4285E/L
Power-Down/Power-Up Timing—bq4285L (TA = TOPR)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Conditions
tF
VCC slew from 2.7V to 0V
300
-
-
µs
tR
VCC slew from 0V to 2.7V
100
-
-
µs
tCSR
CS at VIH after power-up
20
-
200
ms
tWPT
Write-protect time for external RAM
-
0
-
10
16
30
µs
VBC < VPFD
tCER
Chip enable recovery time
tCSR
-
tCSR
ms
Time during which external
SRAM is write-protected after
VCC passes VPFD on power-up.
tCED
Chip enable propagation
delay to external SRAM
-
9
15
ns
Internal write-protection
period after VCC passes VPFD
on power-up.
VBC > VPFD
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing—bq4285L
23
bq4285E/L
Interrupt Delay Timing—bq4285E/L (TA = TOPR)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
tRSW
Reset pulse width
5
-
-
µs
tIRR
INT release from RST
-
-
2
µs
tIRD
INT release from DS (RD)
-
-
2
µs
Interrupt Delay Timing—bq4285E/L (PLCC Package Only) Note: Package OBSOLETE
Interrupt Delay Timing—bq4285E/L
24
bq4285E/bq4285L
P: 24-Pin DIP (0.600")
24-Pin P (0.600" DIP)
Inches
Dimension
Millimeters
Min.
Max.
Min.
Max.
A
0.160
0.190
4.06
4.83
A1
0.015
0.040
0.38
1.02
B
0.015
0.022
0.38
0.56
B1
0.045
0.065
1.14
1.65
C
0.008
0.013
0.20
0.33
D
1.240
1.280
31.50
32.51
E
0.600
0.625
15.24
15.88
E1
0.530
0.570
13.46
14.48
e
0.600
0.670
15.24
17.02
G
0.090
0.110
2.29
2.79
L
0.115
0.150
2.92
3.81
S
0.070
0.090
1.78
2.29
S: 24-Pin SOIC (0.300")
24-Pin S (0.300" SOIC)
Inches
Dimension
B
e
D
E
Millimeters
Min.
Max.
Min.
Max.
A
0.095
0.105
2.41
2.67
A1
0.004
0.012
0.10
0.30
B
0.013
0.020
0.33
0.51
C
0.008
0.013
0.20
0.33
D
0.600
0.615
15.24
15.62
E
0.290
0.305
7.37
7.75
e
0.045
0.055
1.14
1.40
H
0.395
0.415
10.03
10.54
L
0.020
0.040
0.51
1.02
H
A
C
.004
A1
L
25
bq4285E/bq4285L
Data Sheet Revision History
Change
No.
Page No.
Description
Nature of Change
1
1, 25
Package option change
Last time buy for PLCC
2
1, 2, 3, 14, 15, 20,
24, 26, 27
Package option removal
PLCC Last Time Buy Complete
Note:
Change 1 = Jan. 1999 B changes from May 1994.
Change 2 = May 2004 (SLUS006A) changes from Jan. 1999 B
26
bq4285E/bq4285L
Ordering Information
bq4285E/L
Temperature:
blank = Commercial (0 to +70°C)
Package Option:
P = 24-pin plastic DIP (0.600)
S = 24-pin SOIC (0.300)
Device:
bq4285E Real-Time Clock With NVRAM Control
or
bq4285L Real-Time Clock With NVRAM Control
*Contact factory for availability.
27
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
BQ4285EP
ACTIVE
PDIP
N
24
BQ4285LP
OBSOLETE
BQ4285LS
OBSOLETE
PDIP
N
SOIC
DW
BQ4285LSTR
OBSOLETE
SOIC
DW
15
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
Pb-Free
(RoHS)
A42 SN
N / A for Pkg Type
24
TBD
Call TI
Call TI
24
TBD
Call TI
Call TI
24
TBD
Call TI
Call TI
(4)
0 to 70
4285P
-SB2
0 to 70
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
MECHANICAL DATA
MPDI008 – OCTOBER 1994
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PIN SHOWN
A
24
13
0.560 (14,22)
0.520 (13,21)
1
12
0.060 (1,52) TYP
0.200 (5,08) MAX
0.610 (15,49)
0.590 (14,99)
0.020 (0,51) MIN
Seating Plane
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.125 (3,18) MIN
0.010 (0,25) M
PINS **
0°– 15°
0.010 (0,25) NOM
24
28
32
40
48
52
A MAX
1.270
(32,26)
1.450
(36,83)
1.650
(41,91)
2.090
(53,09)
2.450
(62,23)
2.650
(67,31)
A MIN
1.230
(31,24)
1.410
(35,81)
1.610
(40,89)
2.040
(51,82)
2.390
(60,71)
2.590
(65,79)
DIM
4040053 / B 04/95
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Falls within JEDEC MS-011
Falls within JEDEC MS-015 (32 pin only)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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