EL7156 Data Sheet September 1, 2015 FN7280.4 High Performance Pin Driver Features The EL7156 high performance pin driver with three-state is suited to many ATE and level-shifting applications. The 3.5A peak drive capability makes this part an excellent choice when driving high capacitance loads. • Clocking speeds up to 40MHz The output pin OUT is connected to input pins VH or VL respectively, depending on the status of the IN pin. When the OE pin is active low, the output is placed in the three-state mode. The isolation of the output FETs from the power supplies enables VH and VL to be set independently, enabling level-shifting to be implemented. Related to the EL7155, the EL7156 adds a lower supply pin VS- and makes VL an isolated and independent input. This feature adds applications flexibility and improves switching response due to the increased enhancement of the output FETs. This pin driver has improved performance over existing pin drivers. It is specifically designed to operate at voltages down to 0V across the switch elements while maintaining good speed and ON-resistance characteristics. Available in the 8 Ld SOIC and 8 Ld PDIP packages, the EL7156 is specified for operation over the full -40°C to +85°C temperature range. • 15ns tR/tFat 2000pF CLOAD • 0.5ns rise and fall times mismatch • 0.5ns tON-tOFF prop delay mismatch • 3.5pF typical input capacitance • 3.5A peak drive • Low ON-resistance of 3.5Ω • High capacitive drive capability • Operates from 4.5V to 16.5V • Pb-free plus anneal available (RoHS compliant) Applications • ATE/burn-in testers • Level shifting • IGBT drivers • CCD drivers Pinout EL7156 (8 LD PDIP, SOIC) TOP VIEW VS+ 1 OE 2 IN 3 8 VH L O G I C 7 OUT 6 VL GND 4 5 VS- Ordering Information PART NUMBER PART MARKING TAPE & REEL PKG PKG. DWG. # EL7156CNZ (Note) (No longer available, recommended replacement: EL7156CSZ) EL7156CN Z - 8 Ld PDIP* (Pb-free) MDP0031 EL7156CSZ (Note) 7156CSZ - 8 Ld SOIC (Pb-free) MDP0027 EL7156CSZ-T7 (Note) 7156CSZ 7” 8 Ld SOIC (Pb-free) MDP0027 EL7156CSZ-T13 (Note) 7156CSZ 13” 8 Ld SOIC (Pb-free) MDP0027 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas LLC Copyright Intersil Americas LLC 2003, 2005, 2007, 2015. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL7156 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.3V, VS +0.3V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C, unless otherwise specified. DESCRIPTION CONDITION MIN TYP MAX UNIT INPUT VIH Logic ‘1’ Input Voltage IIH Logic ‘1’ Input Current VIL Logic ‘0’ Input Voltage IIL Logic ‘0’ Input Current CIN Input Capacitance 3.5 pF RIN Input Resistance 50 MΩ 2.4 VIH = VS+ V 0.1 VIL = 0V 0.1 10 µA 0.8 V 10 µA OUTPUT ROVH ON-Resistance VH to OUT IOUT = -200 mA 2.7 4.5 Ω ROVL ON-Resistance VL to OUT IOUT = +200 mA 3.5 5.5 Ω IOUT Output Leakage Current OE = 0V, OUT = VH/VL 0.1 10 µA IPK Peak Output Current (linear resistive operation) Source 3.5 A Sink 3.5 A Continuous Output Current Source/Sink IS Power Supply Current Inputs = VS+ 1.3 3 mA IVH Off Leakage at VH and VL VH, VL = 0V 4 10 µA IDC 200 mA POWER SUPPLY SWITCHING CHARACTERISTICS tR Rise Time CL = 2000pF 14.5 ns tF Fall Time CL = 2000pF 15 ns tRFΔ tR, tF Mismatch CL = 2000pF 0.5 ns td-1 Turn-Off Delay Time CL = 2000pF 9.5 ns td-2 Turn-On Delay Time CL = 2000pF 10 ns tdΔ td-1-td-2 Mismatch CL = 2000pF 0.5 ns td-3 Three-state Delay Enable 10 ns td-4 Three-state Delay Disable 10 ns 2 FN7280.4 September 1, 2015 EL7156 Electrical Specifications PARAMETER VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C, unless otherwise specified. (Continued) DESCRIPTION CONDITION MIN TYP MAX UNIT INPUT VIH Logic ‘1’ Input Voltage IIH Logic ‘1’ Input Current VIL Logic ‘0’ Input Voltage IIL Logic ‘0’ Input Current CIN Input Capacitance 3.5 pF RIN Input Resistance 50 MΩ 2.0 VIH = VS+ V 0.1 VIL = 0V 0.1 10 µA 0.8 V 10 µA OUTPUT ROVH ON-Resistance VH to OUT IOUT = -200mA 3.4 5 Ω ROVL ON-Resistance VL to OUT IOUT = +200mA 4 6 Ω IOUT Output Leakage Current OE = 0V, OUT = VH/VL 0.1 10 µA IPK Peak Output Current (linear resistive operation) Source 3.5 A Sink 3.5 A Continuous Output Current Source/Sink IS Power Supply Current Inputs = VS+ 1 2.5 mA VH Off Leakage at VH and VL VH, VL = 0V 4 10 µA IDC 200 mA POWER SUPPLY SWITCHING CHARACTERISTICS tR Rise Time CL = 2000pF 17 ns tF Fall Time CL = 2000pF 17 ns tRFΔ tR, tF Mismatch CL = 2000pF 0 ns td-1 Turn-Off Delay Time CL = 2000pF 11.5 ns td-2 Turn-On Delay Time CL = 2000pF 12 ns tdΔ td-1-td-2 Mismatch CL = 2000pF 0.5 ns td-3 Three-state Delay Enable 10 ns td-4 Three-state Delay Disable 10 ns 3 FN7280.4 September 1, 2015 EL7156 Typical Performance Curves JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD T = +25°C MAX TJ = +125°C 1.0 PDIP8 HIGH THRESHOLD θJA = 100°C/W 0.8 0.6 INPUT VOLTAGE (V) POWER DISSIPATION (W) 1.8 SOIC8 0.4 θJA = 160°C/W 1.6 HYSTERESIS 1.4 1.2 LOW THRESHOLD 0.2 0 1.0 0 25 50 75 85 100 125 150 5 10 AMBIENT TEMPERATURE (°C) FIGURE 1. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE T = +25°C 6 IOUT = 200mA, T = +25°C, VS+ = VH, VS- = VL = 0V VOUT - VL 5 1.6 1.2 FIGURE 2. INPUT THRESHOLD vs SUPPLY VOLTAGE “ON” RESISTANCE (Ω) SUPPLY CURRENT (mA) 2.0 ALL INPUTS = GND 0.8 0.4 4 VOUT - VH 3 2 1 ALL INPUTS = VS+ 0 0 10 5 5 15 7.5 10 12.5 15 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) FIGURE 4. “ON”-RESISTANCE vs SUPPLY VOLTAGE FIGURE 3. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE 30 15 SUPPLY VOLTAGE (V) CL = 2000pF, T = +25°C 20 CL = 2000pF, VS+ = 15V RISE/FALL TIME (ns) RISE/FALL TIME (ns) 18 25 tR 20 tI tF 15 tR 10 5 10 15 SUPPLY VOLTAGE (V) FIGURE 5. RISE/FALL TIME vs SUPPLY VOLTAGE 4 tF 16 14 tR 12 10 -50 0 50 100 150 TEMPERATURE (°C) FIGURE 6. RISE/FALL TIME vs TEMPERATURE FN7280.4 September 1, 2015 EL7156 Typical Performance Curves CL = 2000pF, T = +25°C 14 DELAY TIME (ns) 15 13 td-1 11 td-1 8 6 -50 15 10 td-2 10 9 5 CL = 2000pF, VS+ = 15V 12 td-2 DELAY TIME (ns) 17 (Continued) -25 0 VS+ = +15V, T = +25°C 5 50 40 tF 20 tR 0 100 1000 3 2 1 0 100 10000 1000 10000 LOAD CAPACITANCE (pF) FIGURE 9. RISE/FALL TIME vs LOAD CAPACITANCE FIGURE 10. SUPPLY CURRENT vs LOAD CAPACITANCE VS+ = VH, VS -= VL = 0V, CL = 0pF 30 12 VS+ = VH, VS- = VL = 0V, CL = 0pF 25 10 VS+ = VH = 15V VS+ = VH = 10V 8 6 20 IVH (mA) SUPPLY CURRENT (mA) 125 VS+ = VH = 15V, VS- = VL = 0V, T = +25°C, f = 20kHz LOAD CAPACITANCE (pF) 14 100 4 SUPPLY CURRENT (mA) RISE/FALL TIME (ns) 60 10 75 FIGURE 8. PROPAGATION DELAY vs TEMPERATURE FIGURE 7. PROPAGATION DELAY vs SUPPLY VOLTAGE 30 50 TEMPERATURE (°C) SUPPLY VOLTAGE (V) 70 25 VS+ = VH = 15V VS+ = VH = 10V 15 10 4 5 2 0 1M VS+ =VS V+=VH H = 5V 2M 3M 4M 6M 6M 7M 8M 9M 10M FREQUENCY (Hz) FIGURE 11. SUPPLY CURRENT vs FREQUENCY 5 0 1M VS+ =VVSH+=VH = 5V 2M 3M 4M 6M 6M 7M 8M 9M 10M FREQUENCY (Hz) FIGURE 12. VH SUPPLY CURRENT vs FREQUENCY FN7280.4 September 1, 2015 EL7156 Truth Table Operating Voltage Range OE IN OUT PIN MIN MAX 0 0 Three-state VS- to GND -5 0 0 1 Three-state VS+ to VS- 5 16.5 1 0 VH VH to VL 0 16.5 1 1 VL VS+ to VH 0 16.5 VS+ to GND 5 16.5 VL to VS- 0 16.5 Three-state Output VL VH Timing Diagram 5V INPUT 2.5V 0 INVERTED OUTPUT 90% 10% td2 td1 tF tR Standard Test Configuration VH 0.1µF VS+ VS+ 4.7µF 10kΩ 1 0.1µF 2 OE IN 3 GND 4 4.7µF 8 OUT L O G I C 7 2000pF 6 5 0.1µF VL 4.7µF EL7156 0.1µF 6 VS- 4.7µF FN7280.4 September 1, 2015 EL7156 Pin Descriptions PIN NAME FUNCTION 1 VS+ Positive Supply Voltage 2 OE Output Enable EQUIVALENT CIRCUIT VS+ INPUT VSCIRCUIT 1 3 IN Input 4 GND Ground 5 VS- Negative Supply Voltage 6 VL Lower Output Voltage 7 OUT Reference Circuit 1 Output VH VSVS+ VOUT VSVSVL CIRCUIT 2 8 VH High Output Voltage Block Diagram VH OE VS+ IN LEVEL SHIFTER GND THREESTATE CONTROL OUT VSVL 7 FN7280.4 September 1, 2015 EL7156 Applications Information Power dissipation may be calculated: Product Description PD = ( V S × I S ) + ( C VS × V S × f ) + [ ( C INT + C L ) × V OUT × f ] 2 The EL7156 is a high performance 40MHz pin driver. It contains two analog switches connecting VH and VL to OUT. Depending on the value of the IN pin, one of the two switches will be closed and the other switch open. An output enable (OE) is also supplied which opens both switches simultaneously. Due to the topology of the EL7156, both the VH and VL pins can be connected to any voltage between the VS+ and VSpins, but VH must be greater than VL in order to prevent turning on the body diode at the output stage. The EL7156 is available in both the 8 Ld SOIC and the 8 Ld PDIP packages. The relevant package should be chosen depending on the calculated power dissipation. Three-state Operation When the OE pin is low, the output is three-state (floating). The output voltage is the parasitic capacitance’s voltage. It can be any voltage between VH and VL, depending on the previous state. At three-state, the output voltage can be pushed to any voltage between VH and VL. The output voltage can’t be pushed higher than VH or lower than VL since the body diode at the output stage will turn on. Supply Voltage Range and Input Compatibility The EL7156 is designed for operation on supplies from 5V to 15V (4.5V to 16.5V maximum). “Operating Voltage Range” on page 6 shows the specifications for the relationship between the VS+, VS-, VH, VL, and GND pins. All input pins are compatible with both 3V and 5V CMOS signals. With a positive supply (VS+) of 5V, the EL7156 is also compatible with TTL inputs. Power Supply Bypassing When using the EL7156, it is very important to use adequate power supply bypassing. The high switching currents developed by the EL7156 necessitate the use of a bypass capacitor between the supplies (VS+ and VS-) and GND pins. It is recommended that a 2.2µF tantalum capacitor be used in parallel with a 0.1µF low-inductance ceramic MLC capacitor. These should be placed as close to the supply pins as possible. It is also recommended that the VH and VL pins have some level of bypassing, especially if the EL7156 is driving highly capacitive loads. Power Dissipation Calculation When switching at high speeds, or driving heavy loads, the EL7156 drive capability is limited by the rise in die temperature brought about by internal power dissipation. For reliable operation, die temperature must be kept below TJMAX (+125°C). It is necessary to calculate the power dissipation for a given application prior to selecting the package type. 8 2 (EQ. 1) where: VS is the total power supply to the EL7156 (from VS+ to GND) VOUT is the swing on the output (VH to VL) CVS is the integral capacitance due to VS+ CINT is the integral load capacitance due to VH IS is the quiescent supply current (3mA max) f is frequency TABLE 1. INTEGRAL CAPACITANCE VS+ = VH(V) CVS(pF) CINT(pF) 5 80 120 10 85 145 15 90 180 Having obtained the application’s power dissipation, a maximum package thermal coefficient may be determined, to maintain the internal die temperature below TJMAX: T JMAX – T MAX θ JA = ----------------------------------------PD (EQ. 2) where: TJMAX is the maximum junction temperature (+125°C) TMAX is the maximum operating temperature PD is the power dissipation calculated above θJA thermal resistance on junction to ambient θJA is 160°C/W for the SOIC8 package and 100°C/W for the PDIP8 package when using a standard JEDEC JESD51-3 single-layer test board. If TJMAX is greater than +125°C when calculated using Equation 2, then one of the following actions must be taken: Reduce θJA the system by designing more heat-sinking into the PCB (as compared to the standard JEDEC JESD51-3). Use the PDIP8 instead of the SOIC8 package. De-rate the application either by reducing the switching frequency, the capacitive load, or the maximum operating (ambient) temperature (TMAX). FN7280.4 September 1, 2015 EL7156 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION September 1, 2015 FN7280.4 CHANGE Updated Ordering Information Table on page 1. Added Revision History and About Intersil sections. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support 9 FN7280.4 September 1, 2015 EL7156 Plastic Dual-In-Line Packages (PDIP) E D A2 SEATING PLANE L N A PIN #1 INDEX E1 c e b A1 NOTE 5 1 eA eB 2 N/2 b2 MDP0031 PLASTIC DUAL-IN-LINE PACKAGE INCHES SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE A 0.210 0.210 0.210 0.210 0.210 MAX A1 0.015 0.015 0.015 0.015 0.015 MIN A2 0.130 0.130 0.130 0.130 0.130 ±0.005 b 0.018 0.018 0.018 0.018 0.018 ±0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 D 0.375 0.750 0.750 0.890 1.020 ±0.010 E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 E1 0.250 0.250 0.250 0.250 0.250 ±0.005 e 0.100 0.100 0.100 0.100 0.100 Basic eA 0.300 0.300 0.300 0.300 0.300 Basic eB 0.345 0.345 0.345 0.345 0.345 ±0.025 L 0.125 0.125 0.125 0.125 0.125 ±0.010 N 8 14 16 18 20 Reference NOTES 1 2 Rev. C 2/07 NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 FN7280.4 September 1, 2015 EL7156 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 11 FN7280.4 September 1, 2015