Cypress CY8CLED04-68LTXI Ez-colorâ ¢ hb led controller Datasheet

CY8CLED04
EZ-Color™ HB LED Controller
Features
■
HB LED Controller
❐ Configurable Dimmers Support up to four
Independent LED Channels
❐ 8 to 32 Bits of Resolution per Channel
❐ Dynamic Reconfiguration Enables LED Controller Plus Other
Features: CapSense, Battery Charging, and Motor Control
■
Visual Embedded Design
❐ LED-Based Drivers
• Binning Compensation
• Temperature Feedback
• Optical Feedback
• DMX512
■
■
■
PrISM Modulation Technology
❐ Reduces Radiated EMI
❐ Reduces Low Frequency Blinking
®
■ Advanced Peripherals (PSoC Blocks)
❐ Four Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• Full-duplex UART
• Multiple SPI Masters or Slaves
• Connectable to all GPI/O pins
❐ Six Rail-to-Rail Analog Psoc Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters And Comparators
❐ Complex Peripherals By Combining Blocks
❐ Capacitive Sensing Application Capability
Cypress Semiconductor Corporation
Document Number: 001-13108 Rev. *C
•
■
■
198 Champion Court
Complete Development Tools
❐ Free Development Software
• PSoC Designer™
❐ Full Featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128 KBytes Trace Memory
Programmable Pin Configurations
❐ 25 mA Sink, 10 mA Source on all GPI/O
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on all GPI/O
❐ Up to 12 Analog Inputs on GPI/O
❐ Four 30 mA Analog Outputs on GPI/O
❐ Configurable Interrupt on all GPI/O
Flexible On-Chip Memory
❐ 16K Flash Program Storage 50,000 Erase/Write Cycles
❐ 1K SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
Full Speed USB (12 Mbps)
❐ Four Uni-Directional Endpoints
❐ One Bi-Directional Control Endpoint
❐ USB 2.0 Compliant
❐ Dedicated 256 Byte Buffer
❐ No External Crystal Required
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 15, 2010
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CY8CLED04
Logic Block Diagram
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
System Bus
Port 7
Global Digital Interconnect
Analog
Drivers
Global Analog Interconnect
PSoC CORE
SRAM
1K
SROM
Flash 16K
CPU Core (M8C)
Interrupt
Controller
Sleep and
Watchdog
Clock Sources
(Includes IMO and ILO)
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref.
Digital
Block
Array
Digital
2
Decimator
Clocks MACs
Type 2
Analog
Block
Array
I2C
Internal
POR and LVD
Voltage
System Resets
Ref.
USB
Analog
Input
Muxing
SYSTEM RESOURCES
Document Number: 001-13108 Rev. *C
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Contents
EZ-Color™ Functional Overview....................................... 4
Target Applications........................................................ 4
The PSoC Core ............................................................. 4
The Digital System ........................................................ 4
The Analog System ....................................................... 5
The Analog Multiplexer System..................................... 6
Additional System Resources ....................................... 6
EZ-Color Device Characteristics ................................... 6
Getting Started.................................................................... 7
Application Notes .......................................................... 7
Development Kits .......................................................... 7
Training ......................................................................... 7
Cypros Consultants ....................................................... 7
Solutions Library............................................................ 7
Technical Support ......................................................... 7
Development Tools ............................................................ 7
PSoC Designer Software Subsystems.......................... 7
In-Circuit Emulator......................................................... 8
Document Conventions ..................................................... 8
Units of Measure ........................................................... 8
Numeric Naming............................................................ 8
Acronyms Used ............................................................. 8
Pin Information ................................................................... 9
68-Pin Part Pinout ......................................................... 9
Document Number: 001-13108 Rev. *C
Register Conventions ...................................................... 10
Abbreviations Used ..................................................... 10
Register Mapping Tables ............................................ 10
Electrical Specifications .................................................. 13
Absolute Maximum Ratings...........................................14
Operating Temperature ............................................... 14
DC Electrical Characteristics....................................... 15
AC Electrical Characteristics ....................................... 23
Packaging Information..................................................... 31
Thermal Impedance .................................................... 32
Solder Reflow Peak Temperature ............................... 32
Development Tools ..........................................................
Software ......................................................................
Evaluation Tools..........................................................
Device Programmers...................................................
Third Party Tools .........................................................
Build a PSoC Emulator into Your Board......................
Ordering Information........................................................
Key Device Features ...................................................
Ordering Code Definitions ...........................................
Document History Page ...................................................
Sales, Solutions, and Legal Information ........................
Worldwide Sales and Design Support.........................
Products ......................................................................
33
33
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Page 3 of 37
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CY8CLED04
Cypress's EZ-Color family of devices offers the ideal control
solution for high brightness LED applications requiring intelligent
dimming control. EZ-Color devices combine the power and flexibility of PSoC (Programmable System-on-Chip); with Cypress's
PrISM (precise illumination signal modulation) modulation
technology providing lighting designers a fully customizable and
integrated lighting solution platform.
The EZ-Color family supports a range of independent LED
channels from 4 channels at 32 bits of resolution each, up to 16
channels at 8 bits of resolution each. This enables lighting
designers the flexibility to choose the LED array size and color
quality. PSoC Designer software, with lighting specific drivers,
can significantly cut development time and simplify implementation of fixed color points through temperature, optical, and LED
binning compensation. EZ-Color's virtually limitless analog and
digital customization enable simple integration of features in
addition to intelligent lighting, such as CapSense, battery
charging, image stabilization, and motor control during the development process. These features, along with Cypress's
best-in-class quality and design support, make EZ-Color the
ideal choice for intelligent HB LED control applications.
Target Applications
■
LCD Backlight
■
Large Signs
■
General Lighting
■
Architectural Lighting
■
Camera/Cell Phone Flash
■
Flashlights
The PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPI/O (General Purpose I/O).
The M8C CPU core is a powerful processor with speeds up to
68 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with up to 20
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
EZ-Color GPI/Os provide connection to the CPU, digital and
analog resources of the device. Each pin’s drive mode may be
selected from eight options, allowing great flexibility in external
interfacing. Every pin can also generate a system interrupt on
high level, low level, and change from last read.
The Digital System
The Digital System is composed of four digital PSoC blocks.
Each block is an 8-bit resource that can be used alone or
combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references.
Digital peripheral configurations include:
■
PrISM (8 to 32 bit)
■
Full speed USB (12 Mbps)
■
PWMs (8 to 32 bit)
■
PWMs with Dead band (8 to 24 bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
UART 8-bit with selectable parity
■
SPI master and slave
■
I2C slave and multi-master
■
Cyclical Redundancy Checker/Generator (8 to 32 bit)
■
IrDA
■
Generators (8 to 32 bit)
The digital blocks can be connected to any GPI/O through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by EZ-Color device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in the table titled EZ-Color Device Characteristics.
Figure 1. Digital System Block Diagram
Port 7
Memory encompasses 16K of Flash for program storage, 1K of
SRAM for data storage, and up to 2K of EEPROM emulated
using the Flash. Program Flash uses four protection levels on
blocks of 64 bytes, allowing customized software IP protection.
Port 3
To System Bus
Digital Clocks
From Core
Port 0
To Analog
System
DIGITAL SYSTEM
Digital PSoC Block Array
8
8
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
GIE[7:0]
GIO[7:0]
Document Number: 001-13108 Rev. *C
Port 1
Port 2
Global Digital
Interconnect
Row Output
Configuration
The EZ-Color family incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate
to 8 percent over temperature and voltage. The 24 MHz IMO can
also be doubled to 48 MHz for use by the digital system. A low
power 32 kHz ILO (internal low speed oscillator) is provided for
the Sleep timer and WDT. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the EZ-Color
device. In USB systems, the IMO self-tunes to ± 0.25% accuracy
for USB communication.
Port 5
Port 4
Row Input
Configuration
EZ-Color™ Functional Overview
8
8
GOE[7:0]
GOO[7:0]
Page 4 of 37
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■
Analog-to-digital converters (up to 2, with 6- to 14-bit resolution,
selectable as Incremental, Delta Sigma, and SAR)
■
Filters (2 and 4 pole band-pass, low-pass, and notch)
■
Amplifiers (up to 2, with selectable gain to 48x)
■
Instrumentation amplifiers (1 with selectable gain to 93x)
■
Comparators (up to 2, with 16 selectable thresholds)
■
DACs (up to 2, with 6- to 9-bit resolution)
■
Multiplying DACs (up to 2, with 6- to 9-bit resolution)
■
High current output drivers (two with 30 mA drive as a PSoC
Core Resource)
■
1.3V reference (as a System Resource)
■
DTMF Dialer
■
Modulators
■
Correlators
■
Peak Detectors
■
Many other topologies possible
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in the figure below.
All IO
(Except Port 7)
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
AGNDIn RefIn
The Analog System is composed of six configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common EZ-Color analog functions (most
available as user modules) are listed below.
Figure 2. Analog System Block Diagram
Analog
Mux Bus
The Analog System
P2[3]
P2[6]
P2[4]
P2[1]
P2[2]
P2[0]
ACI0[1:0]
ACI1[1:0]
Array Input
Configuration
Block
Array
ACB00
ACB01
ASC10
ASD11
ASD20
ASC21
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-13108 Rev. *C
Page 5 of 37
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The Analog Multiplexer System
Additional System Resources
The Analog Mux Bus can connect to every GPI/O pin in ports 0-5.
Pins can be connected to the bus individually or in any combination. The bus also connects to the analog system for analysis
with comparators and analog-to-digital converters. It can be split
into two sections for simultaneous dual-channel processing. An
additional 8:1 analog input multiplexer provides a second path to
bring Port 0 pins to the analog array.
System Resources, provide additional capability useful to
complete systems. Additional resources include a multiplier,
decimator, low voltage detection, and power on reset. Brief statements describing the merits of each resource follow.
Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■
Track pad, finger sensing.
■
Chip-wide mux that allows analog input from up to 48 I/O pins.
■
Crosspoint connection between any I/O pin combinations.
When designing capacitive sensing applications, refer to the
latest signal-to-noise signal level requirements Application
Notes, which can be found under http://www.cypress.com >
Documentation. In general, and unless otherwise noted in the
relevant Application Notes, the minimum signal-to-noise ratio
(SNR) for CapSense applications is 5:1.
■
Full-Speed USB (12 Mbps) with 5 configurable endpoints and
256 bytes of RAM. No external components required except
two series resistors. Wider than commercial temperature USB
operation (-10°C to +85°C).
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■
Two multiply accumulates (MACs) provide fast 8-bit multipliers
with 32-bit accumulate, to assist in both general math as well
as digital filters.
■
Decimator provides a custom hardware filter for digital signal
processing apps. including creation of Delta Sigma ADCs.
■
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, multi-master are supported.
■
Low Voltage Detection (LVD) interrupts signal the application
of falling voltage levels, while the advanced POR (Power On
Reset) circuit eliminates the need for a system supervisor.
■
An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■
Versatile analog multiplexer system.
EZ-Color Device Characteristics
Depending on your EZ-Color device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4
analog blocks. The following table lists the resources available for specific EZ-Color device groups. The device covered by this data
sheet is shown in the highlighted row of the table
Digital
I/O
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
SRAM
Size
CY8CLED02
2
16
1
4
8
0
2
4
256 Bytes
4K
No
CY8CLED04
4
56
1
4
48
2
2
6
1K
16K
Yes
CY8CLED08
8
44
2
8
12
4
4
12
256 Bytes
16K
No
CY8CLED16
16
44
4
16
12
4
4
12
2K
32K
No
Document Number: 001-13108 Rev. *C
Flash
Size
PSoC Part
Number
LED
Channels
CapSense
Table 1. EZ-Color Device Characteristics
Page 6 of 37
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Getting Started
Development Tools
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
PSoC Designer is a Microsoft® Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP or Windows Vista.
For in depth information, along with detailed programming
details, see the PSoC® Programmable System-on-Chip
Technical Reference Manual.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at http://www.cypress.com/ez-color.
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party
assemblers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
PSoC Designer Software Subsystems
System-Level View
A drag-and-drop visual embedded system design environment
based on PSoC Designer. In the system level view you create a
model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state
based upon any or all other system devices. Based upon the
design, PSoC Designer automatically selects one or more PSoC
Mixed-Signal Controllers that match your system requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Training
Chip-Level View
Free PSoC technical training (on demand, webinars, and
workshops) is available online at www.cypress.com/training. The
training covers a wide variety of topics and skill levels to assist
you in your designs.
The chip-level view is a more traditional Integrated Development
Environment (IDE) based on PSoC Designer. Choose a base
device to work with and then select different onboard analog and
digital components called user modules that use the PSoC
blocks. Examples of user modules are ADCs, DACs, Amplifiers,
and Filters. Configure the user modules for your chosen
application and connect them to each other and to the proper
pins. Then generate your project. This prepopulates your project
with APIs and libraries that you can use to program your
application.
Cypros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
Solutions Library
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various application designs that include firmware and hardware design files
that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at
1-800-541-4736.
Document Number: 001-13108 Rev. *C
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share a common code
editor, builder, and common debug, emulation, and programming
tools.
Page 7 of 37
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Code Generation Tools
PSoC Designer supports multiple third party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
Document Conventions
Units of Measure
A units of measure table is located in the Electrical Specifications
section. Table 5 on page 13 lists all the abbreviations used to
measure the PSoC devices.
Numeric Naming
Hexidecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’ or ‘b’ are decimal.
Acronyms Used
The following table lists the acronyms that are used in this
document.
Acronym
Description
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.
Debugger commands allow the designer to read and program
and read and write data memory, read and write I/O registers,
read and write CPU registers, set and clear breakpoints, and
provide program run, halt, and step control. The debugger also
allows the designer to create a trace buffer of registers and
memory locations of interest.
AC
alternating current
ADC
analog-to-digital converter
API
application programming interface
CPU
central processing unit
CT
continuous time
DAC
digital-to-analog converter
DC
direct current
Online Help System
ECO
external crystal oscillator
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
EEPROM
electrically erasable programmable read-only
memory
FSR
full scale range
GPI/O
general purpose I/O
In-Circuit Emulator
GUI
graphical user interface
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices.
HBM
human body model
ICE
in-circuit emulator
ILO
internal low speed oscillator
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
IMO
internal main oscillator
I/O
input/output
IPOR
imprecise power on reset
LSb
least-significant bit
LVD
low voltage detect
MSb
most-significant bit
PC
program counter
PLL
phase-locked loop
POR
power on reset
PPOR
precision power on reset
PSoC®
Programmable System-on-Chip™
PWM
pulse width modulator
SC
switched capacitor
SRAM
static random access memory
Document Number: 001-13108 Rev. *C
Page 8 of 37
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Pin Information
68-Pin Part Pinout
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
P7[2]
P7[1]
P7[0]
P1[0]
P1[2]
P1[4]
35
36
37
38
39
40
41
42
43
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
M
M
M
M
M
M
P1[6]
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
P3[6]
44
45
46
47
48
49
NC
NC
XRES
Input
I/O
I/O
I/O
M
M
M
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
NC
NC
Vss
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
I2C SCL, M, P1[7]
I2C SDA, M, P1[5]
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
I2C Serial Clock (SCL) ISSP SCLK.
Ground connection.
Supply voltage.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
29
30
31
32
33
34
No connection.
No connection.
Ground connection.
51
50
QFN
(Top View)
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
P4[7]
P4[5]
P4[3]
P4[1]
NC
NC
Vss
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
D+
DVdd
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
P2[0], M, AI
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
NC
NC
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
P1[6], M
M, P1[3]
I2C SCL, M, P1[1]
Vss
D+
DVdd
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
I2C SDA, M, P1[0]
M, P1[2]
M, P1[4]
No. Digital Analog
1
I/O
M
2
I/O
M
3
I/O
M
4
I/O
M
5
6
7
Power
8
I/O
M
9
I/O
M
10
I/O
M
11
I/O
M
12
I/O
M
13
I/O
M
14
I/O
M
15
I/O
M
16
I/O
M
17
I/O
M
18
I/O
M
19
I/O
M
20
Power
21
USB
22
USB
23
Power
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
P2[1], M, AI
P2[3], M, AI
P2[5], M
P2[7], M
P0[1], M, AI
P0[3], M, AIO
P0[5], M, AIO
P0[7], M, AI
Vss
Vdd
P0[6], M, AI
P0[4], M, AI
P0[2], M, AI
P0[0], M, AI
P2[6], M, Ext. VREF
P2[4], M, Ext. AGND
P2[2], M, AI
This Section describes, lists, and illustrates the CY8CLED04 EZ-Color device pins and pinout configuration. The CY8CLED04 device
is available in the following package. Every port pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, and XRES are
not capable of Digital I/O.
Table 2. 68-Pin Part Pinout (QFN)[1, 2]
Type
Pin
Figure 3. 68-Pin Device
Name
Description
I2C Serial Data (SDA), ISSP SDATA.
Optional External Clock Input
(EXTCLK).
No connection.
No connection.
Active high pin reset with internal pull
down.
P4[0]
P4[2]
P4[4]
Type
Pin
No. Digital Analog
50
I/O
M
51
I/O
I,M
52
I/O
I,M
53
I/O
M
P4[6]
P2[0]
P2[2]
P2[4]
54
55
56
57
58
59
60
61
62
I/O
M
I/O
I,M
I/O
I,M
I/O
I,M
I/O
I,M
Power
Power
I/O
I,M
I/O
I/O,M
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Vss
P0[7]
P0[5]
63
64
65
I/O
I/O
I/O
I/O,M
I,M
M
P0[3]
P0[1]
P2[7]
66
67
68
I/O
I/O
I/O
M
I,M
I,M
P2[5]
P2[3]
P2[1]
Name
Description
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND) input.
External Voltage Reference (VREF) input.
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Supply voltage.
Ground connection.
Analog column mux input, integration input #1
Analog column mux input and column output,
integration input #2.
Analog column mux input and column output.
Analog column mux input.
Direct switched capacitor block input.
Direct switched capacitor block input.
LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input.
Notes
1. These are the ISSP pins, which are not High Z at POR.
2. The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
should be electrically floated and not connected to any other signal.
Document Number: 001-13108 Rev. *C
Page 9 of 37
[+] Feedback
CY8CLED04
Register Conventions
This section lists the registers of the CY8CLED04 EZ-Color device.
Abbreviations Used
The register conventions specific to this section are listed in the following table.
Convention
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Register Mapping Tables
The device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two
banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in
Bank 1.
Note In the following register mapping tables, blank fields are Reserved and should not be accessed.
Table 3. Register Map Bank 0 Table: User Space
Name
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
Addr (0,Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
PRT3DR
0C
RW
Name
PMA0_DR
PMA1_DR
PMA2_DR
PMA3_DR
PMA4_DR
PMA5_DR
PMA6_DR
PMA7_DR
USB_SOF0
USB_SOF1
USB_CR0
USBI/O_CR
0
USBI/O_CR
1
PRT3IE
PRT3GS
PRT3DM2
PRT4DR
PRT4IE
PRT4GS
PRT4DM2
PRT5DR
PRT5IE
PRT5GS
PRT5DM2
0D
RW
0E
RW
EP1_CNT1
0F
RW
EP1_CNT
10
RW
EP2_CNT1
11
RW
EP2_CNT
12
RW
EP3_CNT1
13
RW
EP3_CNT
14
RW
EP4_CNT1
15
RW
EP4_CNT
16
RW
EP0_CR
17
RW
EP0_CNT
18
EP0_DR0
19
EP0_DR1
1A
EP0_DR2
1B
EP0_DR3
PRT7DR
1C
RW
EP0_DR4
PRT7IE
1D
RW
EP0_DR5
PRT7GS
1E
RW
EP0_DR6
PRT7DM2
1F
RW
EP0_DR7
DBB00DR0
20
#
AMX_IN
DBB00DR1
21
W
AMUXCFG
DBB00DR2
22
RW
DBB00CR0
23
#
ARF_CR
DBB01DR0
24
#
CMP_CR0
Blank fields are Reserved and should not be accessed.
Document Number: 001-13108 Rev. *C
Addr (0,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
Access
RW
RW
RW
RW
RW
RW
RW
RW
R
R
RW
#
4C
RW
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
#
RW
#
RW
#
RW
#
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
Addr (0,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
Access
RW
RW
RW
RW
RW
RW
RW
RW
Name
8C
8D
8E
8F
ASD20CR0
90
ASD20CR1
91
ASD20CR2
92
ASD20CR3
93
ASC21CR0
94
ASC21CR1
95
ASC21CR2
96
ASC21CR3
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
# Access is bit specific.
Addr (0,Hex) Access
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
RW
RW
RW
RW
RW
RW
RW
RW
CUR_PP
STK_PP
IDX_PP
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK3
INT_MSK2
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
RW
RW
RW
RW
RW
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
RC
Page 10 of 37
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CY8CLED04
Table 3. Register Map Bank 0 Table: User Space (continued)
Name
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
Addr (0,Hex)
25
26
27
28
29
2A
2B
2C
Access
W
RW
#
#
W
RW
#
#
Name
ASY_CR
CMP_CR1
Access
#
RW
TMP_DR0
Addr (0,Hex)
65
66
67
68
69
6A
6B
6C
DCB03DR1
2D
W
TMP_DR1
DCB03DR2
2E
RW
DCB03CR0
2F
#
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
RW
MUL1_X
MUL1_Y
MUL1_DH
MUL1_DL
ACC1_DR1
Addr (0,Hex)
A5
A6
A7
A8
A9
AA
AB
AC
W
W
R
R
RW
6D
RW
ACC1_DR0
AD
RW
TMP_DR2
6E
RW
ACC1_DR3
AE
RW
TMP_DR3
6F
RW
ACC1_DR2
AF
RW
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
RW
RW
RW
RW
RW
RW
RW
3F
Name
7F
Access
CPU_F
DAC_D
CPU_SCR
1
CPU_SCR
0
BF
Blank fields are Reserved and should not be accessed.
Name
DEC_DL
DEC_CR0
DEC_CR1
MUL0_X
MUL0_Y
MUL0_DH
MUL0_DL
ACC0_DR
1
ACC0_DR
0
ACC0_DR
3
ACC0_DR
2
Addr (0,Hex)
E5
E6
E7
E8
E9
EA
EB
EC
Access
RC
RW
RW
W
W
R
R
RW
ED
RW
EE
RW
EF
RW
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
RL
FF
#
RW
#
# Access is bit specific.
Table 4. Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
Addr (1,Hex)
00
Access
RW
Name
PMA0_WA
Addr (1,Hex)
40
Access
RW
PRT0DM1
01
RW
PMA1_WA
41
RW
PRT0IC0
02
RW
PMA2_WA
42
RW
PRT0IC1
03
RW
PMA3_WA
43
RW
PRT1DM0
04
RW
PMA4_WA
44
RW
PRT1DM1
05
RW
PMA5_WA
45
RW
PRT1IC0
06
RW
PMA6_WA
46
RW
PRT1IC1
07
RW
PMA7_WA
47
RW
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
PRT4DM1
08
09
0A
0B
0C
0D
0E
0F
10
11
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
PMA0_RA
PMA1_RA
48
49
4A
4B
4C
4D
4E
4F
50
51
RW
RW
PRT4IC0
12
RW
PMA2_RA
52
RW
PRT4IC1
13
RW
PMA3_RA
53
RW
Blank fields are Reserved and should not be accessed.
Document Number: 001-13108 Rev. *C
Name
ASC10CR
0
ASC10CR
1
ASC10CR
2
ASC10CR
3
ASD11CR
0
ASD11CR
1
ASD11CR
2
ASD11CR
3
Addr (1,Hex) Access
80
RW
Name
USBI/O_CR2
Addr (1,Hex) Access
C0
RW
81
RW
USB_CR1
C1
#
82
RW
83
RW
84
RW
EP1_CR0
C4
#
85
RW
EP2_CR0
C5
#
86
RW
EP3_CR0
C6
#
87
RW
EP4_CR0
C7
#
RW
GDI_O_IN
GDI_E_IN
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
RW
RW
RW
GDI_O_OU
D2
RW
RW
GDI_E_OU
D3
RW
88
89
8A
8B
8C
8D
8E
8F
90
ASD20CR 91
1
ASD20CR 92
2
ASD20CR 93
3
# Access is bit specific.
Page 11 of 37
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CY8CLED04
Table 4. Register Map Bank 1 Table: Configuration Space (continued)
Name
PRT5DM0
Addr (1,Hex)
14
Access
RW
Name
PMA4_RA
Addr (1,Hex)
54
Access
RW
PRT5DM1
15
RW
PMA5_RA
55
RW
PRT5IC0
16
RW
PMA6_RA
56
RW
PRT5IC1
17
RW
PMA7_RA
57
RW
DBB01FN
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
RW
DBB01IN
25
RW
DBB01OU
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
RW
PRT7DM0
PRT7DM1
PRT7IC0
PRT7IC1
DBB00FN
DBB00IN
DBB00OU
DCB02FN
DCB02IN
DCB02OU
DCB03FN
DCB03IN
DCB03OU
RW
RW
RW
RW
RW
RW
RW
CLK_CR0
CLK_CR1
ABF_CR0
AMD_CR0
CMP_GO_E
N
CMP_GO_E
N1
AMD_CR1
ALT_CR0
RW
RW
RW
RW
RW
RW
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
Blank fields are Reserved and should not be accessed.
Document Number: 001-13108 Rev. *C
Name
ASC21CR
0
ASC21CR
1
ASC21CR
2
ASC21CR
3
Addr (1,Hex) Access
94
RW
Name
Addr (1,Hex)
D4
95
RW
D5
96
RW
D6
97
RW
D7
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
RW
RW
RW
RW
RW
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
65
RW
A5
E5
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
RW
RW
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
MUX_CR0
MUX_CR1
MUX_CR2
MUX_CR3
D8
D9
DA
DB
DC
OSC_GO_EN DD
OSC_CR4
DE
OSC_CR3
DF
OSC_CR0
E0
OSC_CR1
E1
OSC_CR2
E2
VLT_CR
E3
VLT_CMP
E4
IMO_TR
ILO_TR
BDG_TR
ECO_TR
MUX_CR4
MUX_CR5
RW
RW
RW
RW
RW
RW
RW
CPU_F
DAC_CR
CPU_SCR1
CPU_SCR0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
W
W
RW
W
RW
RW
RL
RW
#
#
# Access is bit specific.
Page 12 of 37
[+] Feedback
CY8CLED04
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8CLED04 EZ-Color device. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at
http://www.cypress.com/ez-color.
Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted. Specifications for devices running at greater than
12 MHz are valid for -40oC ≤ TA ≤ 70oC and TJ ≤ 82oC.
Figure 4. Voltage versus CPU Frequency
5.25
Vdd Voltage
lid ng
Va rati n
e io
Op Reg
4.75
3.00
93 kHz
12 MHz
24 MHz
CPU Frequency
The following table lists the units of measure that are used in this chapter.
Table 5. Units of Measure
Symbol
oC
dB
fF
Hz
KB
Kbit
kHz
kΩ
MHz
MΩ
μA
μF
μH
μs
μV
μVrms
Unit of Measure
degree Celsius
decibels
femto farad
hertz
1024 bytes
1024 bits
kilohertz
kilohm
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microvolts
microvolts root-mean-square
Document Number: 001-13108 Rev. *C
Symbol
μW
mA
ms
mV
nA
ns
nV
W
pA
pF
pp
ppm
ps
sps
s
V
Unit of Measure
microwatts
milli-ampere
milli-second
milli-volts
nanoampere
nanosecond
nanovolts
ohm
picoampere
picofarad
peak-to-peak
parts per million
picosecond
samples per second
sigma: one standard deviation
volts
Page 13 of 37
[+] Feedback
CY8CLED04
Absolute Maximum Ratings
Symbol
TSTG
Description
Storage Temperature
Min
-55
Typ
25
Max
+100
TA
Vdd
VI/O
Ambient Temperature with Power Applied
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
–
–
–
VI/O2
DC Voltage Applied to Tri-state
IMI/O
IMAI/O
Maximum Current into any Port Pin
Maximum Current into any Port Pin
Configured as Analog Driver
Electro Static Discharge Voltage
Latch-up Current
-40
-0.5
Vss 0.5
Vss 0.5
-25
-50
–
–
+85
+6.0
Vdd +
0.5
Vdd +
0.5
+50
+50
mA
mA
2000
–
–
–
–
200
V
mA
Min
-40
-10
-40
Typ
–
–
–
Max
+85
+85
+100
Units
oC
oC
oC
ESD
LU
–
Units
o
C
Notes
Higher storage temperatures will
reduce data retention time. Recommended storage temperature is
+25oC ± 25oC. Extended duration
storage temperatures above 65oC
will degrade reliability.
o
C
V
V
V
Human Body Model ESD.
Operating Temperature
Symbol
TA
TAUSB
TJ
Description
Ambient Temperature
Ambient Temperature using USB
Junction Temperature
Document Number: 001-13108 Rev. *C
Notes
The temperature rise from ambient
to junction is package specific. See
“Thermal Impedance” on page 32.
The user must limit the power
consumption to comply with this
requirement.
Page 14 of 37
[+] Feedback
CY8CLED04
DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Symbol
Description
Vdd
Supply Voltage
Min
3.0
Typ
–
Max
5.25
Units
V
IDD5
Supply Current, IMO = 24 MHz (5V)
–
14
27
mA
IDD3
Supply Current, IMO = 24 MHz (3.3V)
–
8
14
mA
ISB
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT[3]
–
3
6.5
μA
ISBH
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT at high temperature.[3]
–
4
25
μA
Notes
See DC POR and LVD specifications, Table 16 on page 21.
Conditions are Vdd = 5.0V, TA = 25
o
C, CPU = 3 MHz, SYSCLK
doubler disabled, VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 93.75
kHz, analog power = off.
Conditions are Vdd = 3.3V, TA = 25
oC, CPU = 3 MHz, SYSCLK
doubler disabled, VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 0.367
kHz, analog power = off.
Conditions are with internal slow
speed oscillator, Vdd = 3.3V, -40 oC
≤ TA ≤ 55 oC, analog power = off.
Conditions are with internal slow
speed oscillator, Vdd = 3.3V, 55 oC
< TA ≤ 85 oC, analog power = off.
DC General Purpose I/O Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 6. DC GPI/O Specifications
Symbol
Description
Pull-Up Resistor
RPU
RPD
Pull-Down Resistor
High Output Level
VOH
Min
4
4
Vdd 1.0
Typ
5.6
5.6
–
Max
8
8
–
Units
kΩ
kΩ
V
VOL
Low Output Level
–
–
0.75
V
IOH
High Level Source Current
10
–
–
mA
IOL
Low Level Sink Current
25
–
–
mA
VIL
VIH
Input Low Level
Input High Level
–
2.1
–
–
0.8
V
V
Notes
I/OH = 10 mA, Vdd = 4.75 to 5.25V
(8 total loads, 4 on even port pins
(for example, P0[2], P1[4]), 4 on
odd port pins (for example, P0[3],
P1[5])). 80 mA maximum combined
I/OH budget.
I/OL = 25 mA, Vdd = 4.75 to 5.25V
(8 total loads, 4 on even port pins
(for example, P0[2], P1[4]), 4 on
odd port pins (for example, P0[3],
P1[5])). 200 mA maximum
combined I/OL budget.
VOH = Vdd-1.0V. See the limitations of the total current in the Note
for VOH.
VOL = 0.75V. See the limitations of
the total current in the Note for VOL.
Vdd = 3.0 to 5.25.
Vdd = 3.0 to 5.25.
Note
3. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar
functions enabled.
Document Number: 001-13108 Rev. *C
Page 15 of 37
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CY8CLED04
Table 6. DC GPI/O Specifications (continued)
VH
IIL
CIN
Input Hysterisis
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
–
–
–
60
1
3.5
–
–
10
mV
nA
pF
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF
Gross tested to 1 μA.
Package and pin dependent. Temp
= 25oC.
Package and pin dependent. Temp
= 25oC.
DC Full-Speed USB Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -10°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -10°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 7. DC Full-Speed (12 Mbps) USB Specifications
Symbol
Description
USB Interface
Differential Input Sensitivity
VDI
VCM
Differential Input Common Mode Range
Single Ended Receiver Threshold
VSE
Transceiver Capacitance
CIN
II/O
High-Z State Data Line Leakage
REXT
External USB Series Resistor
Static Output High, Driven
VUOH
VUOHI
Static Output High, Idle
VUOL
Static Output Low
ZO
VCRS
USB Driver Output Impedance
D+/D- Crossover Voltage
Min
Typ
Max
Units
0.2
0.8
0.8
–
-10
23
2.8
–
–
–
–
–
–
–
–
2.5
2.0
20
10
25
3.6
V
V
V
pF
μA
W
V
2.7
–
3.6
V
–
–
0.3
V
28
1.3
–
–
44
2.0
W
V
Notes
| (D+) - (D-) |
0V < VIN < 3.3V.
In series with each USB pin.
15 kΩ ± 5% to Ground. Internal
pull-up enabled.
15 kΩ ± 5% to Ground. Internal
pull-up enabled.
15 kΩ ± 5% to Ground. Internal
pull-up enabled.
Including REXT Resistor.
DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.
Table 8. 5V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
TCVOSOA Average Input Offset Voltage Drift
Input Leakage Current (Port 0 Analog
IEBOA
Pins)
CINOA
Input Capacitance (Port 0 Analog
Pins)
Document Number: 001-13108 Rev. *C
Min
Typ
Max
Units
–
–
–
–
–
1.6
1.3
1.2
7.0
20
10
8
7.5
35.0
–
mV
mV
mV
μV/oC
pA
–
4.5
9.5
pF
Notes
Gross tested to 1 μA.
Package and pin dependent. Temp
= 25oC.
Page 16 of 37
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Table 8. 5V DC Operational Amplifier Specifications (continued)
Symbol
VCMOA
Description
Common Mode Voltage Range
Common Mode Voltage Range (high
power or high opamp bias)
GOLOA
Open Loop Gain
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
VOHIGHO High Output Voltage Swing (internal
signals)
A
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
VOLOWOA Low Output Voltage Swing (internal
signals)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
ISOA
Supply Current (including associated
AGND buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
PSRROA Supply Voltage Rejection Ratio
Min
0.0
0.5
Typ
–
–
Max
Vdd
Vdd - 0.5
Units
V
–
–
dB
Vdd - 0.2
Vdd - 0.2
Vdd - 0.5
–
–
–
–
–
–
V
V
V
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
–
–
–
–
–
–
65
400
500
800
1200
2400
4600
80
800
900
1000
1600
3200
6400
–
μA
μA
μA
μA
μA
μA
dB
Notes
The common-mode input voltage
range is measured through an
analog output buffer. The specification includes the limitations
imposed by the characteristics of
the analog output buffer.
60
60
80
Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd 1.25V) ≤ VIN ≤ Vdd.
Table 9. 3.3V DC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
High Power is 5 Volts Only
–
–
1.65
1.32
10
8
mV
mV
TCVOSOA Average Input Offset Voltage Drift
–
7.0
35.0
μV/oC
IEBOA
Input Leakage Current (Port 0 Analog
Pins)
–
20
–
pA
Gross tested to 1 μA.
CINOA
Input Capacitance (Port 0 Analog
Pins)
–
4.5
9.5
pF
Package and pin dependent. Temp
= 25oC.
VCMOA
Common Mode Voltage Range
0.2
–
Vdd - 0.2
V
The common-mode input voltage
range is measured through an
analog output buffer. The specification includes the limitations
imposed by the characteristics of
the analog output buffer.
GOLOA
Open Loop Gain
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High, Opamp Bias = Low
–
–
dB
60
60
80
VOSOA
Document Number: 001-13108 Rev. *C
Notes
Page 17 of 37
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CY8CLED04
Table 9. 3.3V DC Operational Amplifier Specifications (continued)
Symbol
Description
Min
Typ
Max
Units
VOHIGHO
High Output Voltage Swing (internal
signals)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High is 5V only
Vdd - 0.2
Vdd - 0.2
Vdd - 0.2
–
–
–
–
–
–
V
V
V
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
Supply Current (including associated
AGND buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
–
–
–
–
–
–
400
500
800
1200
2400
4600
800
900
1000
1600
3200
6400
μA
μA
μA
μA
μA
μA
Supply Voltage Rejection Ratio
65
80
–
dB
A
VOLOWOA Low Output Voltage Swing (internal
signals)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High, Opamp Bias = Low
ISOA
PSRROA
Notes
Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd 1.25V) ≤ VIN ≤ Vdd.
DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C and are for design guidance only.
Table 10. DC Low Power Comparator Specifications
Symbol
VREFLPC
ISLPC
VOSLPC
Description
Low Power Comparator (LPC)
Reference Voltage Range
LPC Supply Current
LPC Voltage Offset
Document Number: 001-13108 Rev. *C
Min
0.2
Typ
–
Max
Vdd - 1
Units
V
–
–
10
2.5
40
30
μA
mV
Notes
Page 18 of 37
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DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 11. 5V DC Analog Output Buffer Specifications
Symbol
VOSOB
TCVOSOB
VCMOB
ROUTOB
VOHIGHOB
VOLOWOB
ISOB
PSRROB
Description
Input Offset Voltage (Absolute Value)
Average Input Offset Voltage Drift
Common-Mode Input Voltage Range
Output Resistance
Power = Low
Power = High
High Output Voltage Swing (Load = 32 ohms
to Vdd/2)
Power = Low
Power = High
Low Output Voltage Swing (Load = 32 ohms
to Vdd/2)
Power = Low
Power = High
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
Supply Voltage Rejection Ratio
Min
–
–
0.5
Typ
3
+6
–
Max
12
–
Vdd - 1.0
Units
mV
μV/°C
V
–
–
0.6
0.6
–
–
W
W
–
–
–
–
V
V
0.5 x Vdd + 1.1
0.5 x Vdd + 1.1
–
–
–
–
–
–
53
1.1
2.6
64
5.1
8.8
–
mA
mA
dB
Min
–
–
0.5
Typ
3
+6
-
Max
12
–
Vdd - 1.0
Units
mV
μV/°C
V
–
–
1
1
–
–
W
W
–
–
–
–
V
V
0.5 x Vdd - 1.3
0.5 x Vdd - 1.3
Notes
V
V
(0.5 x Vdd - 1.3) ≤
VOUT ≤ (Vdd - 2.3).
Table 12. 3.3V DC Analog Output Buffer Specifications
Symbol
VOSOB
TCVOSOB
VCMOB
ROUTOB
VOHIGHOB
VOLOWOB
ISOB
PSRROB
Description
Input Offset Voltage (Absolute Value)
Average Input Offset Voltage Drift
Common-Mode Input Voltage Range
Output Resistance
Power = Low
Power = High
High Output Voltage Swing (Load = 1K ohms
to Vdd/2)
Power = Low
Power = High
Low Output Voltage Swing (Load = 1K ohms
to Vdd/2)
Power = Low
Power = High
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
Supply Voltage Rejection Ratio
Document Number: 001-13108 Rev. *C
0.5 x Vdd + 1.0
0.5 x Vdd + 1.0
–
–
–
–
–
34
0.8
2.0
64
0.5 x Vdd - 1.0
0.5 x Vdd - 1.0
2.0
4.3
–
Notes
V
V
mA
mA
dB
(0.5 x Vdd - 1.0) ≤
VOUT ≤ (0.5 x Vdd +
0.9).
Page 19 of 37
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DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 13. 5V DC Analog Reference Specifications
Symbol
BG
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Description
Min
Bandgap Voltage Reference
1.28
AGND = Vdd/2[4]
Vdd/2 - 0.04
AGND = 2 x BandGap[4]
2 x BG - 0.048
AGND = P2[4] (P2[4] = Vdd/2)[4]
P2[4] - 0.011
AGND = BandGap[4]
BG - 0.009
AGND = 1.6 x BandGap[4]
1.6 x BG - 0.022
AGND Block to Block Variation (AGND = Vdd/2)[4]
-0.034
RefHi = Vdd/2 + BandGap
Vdd/2 + BG - 0.10
RefHi = 3 x BandGap
3 x BG - 0.06
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)
2 x BG + P2[6] - 0.113
Typ
Max
Units
1.30
1.32
V
Vdd/2 - 0.01
Vdd/2 + 0.007
V
2 x BG - 0.030
2 x BG + 0.024
V
P2[4]
P2[4] + 0.011
V
BG + 0.008
BG + 0.016
V
1.6 x BG - 0.010
1.6 x BG + 0.018
V
0.000
0.034
V
Vdd/2 + BG
Vdd/2 + BG + 0.10
V
3 x BG
3 x BG + 0.06
V
2 x BG + P2[6] 2 x BG + P2[6] + 0.077
V
0.018
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
P2[4] + BG - 0.130
P2[4] + BG - 0.016
P2[4] + BG + 0.098
V
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] + P2[6] - 0.133 P2[4] + P2[6] - 0.016 P2[4] + P2[6]+ 0.100
V
RefHi = 3.2 x BandGap
3.2 x BG - 0.112
3.2 x BG
3.2 x BG + 0.076
V
RefLo = Vdd/2 – BandGap
Vdd/2 - BG - 0.04
Vdd/2 - BG + 0.024
Vdd/2 - BG + 0.04
V
RefLo = BandGap
BG - 0.06
BG
BG + 0.06
V
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
2 x BG - P2[6] - 0.084
2 x BG - P2[6] +
2 x BG - P2[6] + 0.134
V
0.025
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
P2[4] - BG - 0.056
P2[4] - BG + 0.026
P2[4] - BG + 0.107
V
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] - 0.057 P2[4] - P2[6] + 0.026 P2[4] - P2[6] + 0.110
V
Table 14. 3.3V DC Analog Reference Specifications
Symbol
BG
–
–
–
–
–
–
–
–
–
–
–
–
–
Description
Bandgap Voltage Reference
AGND = Vdd/2[5]
AGND = 2 x BandGap[5]
AGND = P2[4] (P2[4] = Vdd/2)
AGND = BandGap[5]
AGND = 1.6 x BandGap[5]
AGND Column to Column Variation
(AGND = Vdd/2)[5]
RefHi = Vdd/2 + BandGap
RefHi = 3 x BandGap
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2,
P2[6] = 0.5V)
RefHi = 3.2 x BandGap
RefLo = Vdd/2 - BandGap
Min
1.28
Vdd/2 - 0.03
P2[4] - 0.008
BG - 0.009
1.6 x BG - 0.027
-0.034
Typ
1.30
Vdd/2 - 0.01
Not Allowed
P2[4] + 0.001
BG + 0.005
1.6 x BG - 0.010
0.000
Max
1.32
Vdd/2 + 0.005
Units
V
V
P2[4] + 0.009
BG + 0.015
1.6 x BG + 0.018
0.034
V
V
V
V
Not Allowed
Not Allowed
Not Allowed
Not Allowed
P2[4] + P2[6] - 0.075 P2[4] + P2[6] - 0.009 P2[4] + P2[6] + 0.057
V
Not Allowed
Not Allowed
Notes
4. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.
5. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.
Document Number: 001-13108 Rev. *C
Page 20 of 37
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Table 14. 3.3V DC Analog Reference Specifications (continued)
Symbol
–
–
–
–
Description
RefLo = BandGap
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
Min
P2[4] - P2[6] - 0.048
Typ
Max
Not Allowed
Not Allowed
Not Allowed
P2[4]- P2[6] + 0.022 P2[4] - P2[6] + 0.092
Units
V
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 15. DC Analog PSoC Block Specifications
Symbol
RCT
CSC
Description
Resistor Unit Value (Continuous Time)
Capacitor Unit Value (Switched Capacitor)
Min
–
–
Typ
12.2
80
Max
–
–
Units
kΩ
fF
Notes
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V or 3.3V at 25°C and are
for design guidance only.
Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register.
Table 16. DC POR and LVD Specifications
Symbol
VPPOR0R
VPPOR1R
VPPOR2R
VPPOR0
VPPOR1
VPPOR2
VPH0
VPH1
VPH2
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Description
Vdd Value for PPOR Trip (positive ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
Vdd Value for PPOR Trip (negative ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
PPOR Hysteresis
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
Min
Typ
Max
Units
–
2.91
4.39
4.55
–
V
V
V
–
2.82
4.39
4.55
–
V
V
V
–
–
–
92
0
0
–
–
–
mV
mV
mV
2.86
2.96
3.07
3.92
4.39
4.55
4.63
4.72
2.92
3.02
3.13
4.00
4.48
4.64
4.73
4.81
2.98[6]
3.08
3.20
4.08
4.57
4.74[7]
4.82
4.91
V
V
V
V
V
V
V
V
V
Notes
Notes
6. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
7. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
Document Number: 001-13108 Rev. *C
Page 21 of 37
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DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 17. DC Programming Specifications
Symbol
Description
IDDP
Supply Current During Programming or
Verify
VILP
Input Low Voltage During Programming or
Verify
VIHP
Input High Voltage During Programming or
Verify
IILP
Input Current when Applying Vilp to P1[0] or
P1[1] During Programming or Verify
IIHP
Input Current when Applying Vihp to P1[0] or
P1[1] During Programming or Verify
VOLV
Output Low Voltage During Programming or
Verify
VOHV
Output High Voltage During Programming or
Verify
FlashENP Flash Endurance (per block)
Min
–
Typ
15
Max
30
Units
mA
–
–
0.8
V
2.1
–
–
V
–
–
0.2
mA
–
–
1.5
mA
–
–
Vss + 0.75
V
Vdd - 1.0
–
Vdd
V
50,000[8]
–
–
–
1,800,000
10
–
–
–
–
–
Years
Notes
Driving internal pull-down
resistor.
Driving internal pull-down
resistor.
Erase/write cycles per block.
B
FlashENT Flash Endurance (total)[9]
FlashDR Flash Data Retention
Erase/write cycles.
Notes
8. The 50,000 cycle Flash endurance per block will only be guaranteed if the Flash is operating within one voltage range. Voltage ranges are 3.0V to 3.6V and 4.75V
to 5.25V.
9. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2
blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block
ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the
temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
Document Number: 001-13108 Rev. *C
Page 22 of 37
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CY8CLED04
AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 18. AC Chip-Level Specifications
Symbol
FIMO245V
Description
Internal Main Oscillator Frequency for 24
MHz (5V)
FIMO243V
Internal Main Oscillator Frequency for 24
MHz (3.3V)
FIMOUSB5V Internal Main Oscillator Frequency with
USB (5V)
Frequency locking enabled and USB traffic
present.
FIMOUSB3V Internal Main Oscillator Frequency with
USB (3.3V)
Frequency locking enabled and USB traffic
present.
FCPU1
CPU Frequency (5V Nominal)
FCPU2
CPU Frequency (3.3V Nominal)
FBLK5
Digital PSoC Block Frequency (5V Nominal)
FBLK3
F32K1
F32K_U
DCILO
Jitter32k
Step24M
Fout48M
Digital PSoC Block Frequency (3.3V
Nominal)
Internal Low Speed Oscillator Frequency
Internal Low Speed Oscillator Untrimmed
Frequency
Internal Low Speed Oscillator Duty Cycle
32 kHz Period Jitter
24 MHz Trim Step Size
48 MHz Output Frequency
Jitter24M1 24 MHz Period Jitter (IMO) Peak-to-Peak
FMAX
Maximum frequency of signal on row input
or row output.
SRPOWER_ Power Supply Slew Rate
Min
23.04
Typ
24
Max
24.96[10,11]
Units
MHz
22.08
24
25.92[11,12]
MHz
23.94
24
24.06[11]
MHz
23.94
24
24.06[11]
MHz
0.093
0.093
0
24
12
48
24.96[10,11]
12.96[11,12]
49.92[10,11,13]
MHz
MHz
MHz
0
24
25.92[11,13]
MHz
15
5
32
–
64
–
kHz
kHz
20
–
–
46.08
50
100
50
48.0
80
–
49.92[10,12]
%
ns
kHz
MHz
–
–
300
–
12.96
ps
MHz
–
–
250
V/ms
–
16
100
ms
Notes
Trimmed for 5V operation using
factory trim values.
Trimmed for 3.3V operation
using factory trim values.
-10°C ≤ TA ≤ 85°C
4.35 ≤ Vdd ≤ 5.15
-0°C ≤ TA ≤ 70°C
3.15 ≤ Vdd ≤ 3.45
Refer to the AC Digital Block
Specifications.
After a reset and before the m8c
starts to run, the ILO is not
trimmed. See the System
Resets section of the PSoC
Technical Reference Manual for
details on timing this.
Trimmed. Utilizing factory trim
values.
Vdd slew rate during power up.
UP
TPOWERUP Time from End of POR to CPU Executing
Code
Power up from 0V. See the
System Resets section of the
PSoC Technical Reference
Manual.
Notes
10. 4.75V < Vdd < 5.25V.
11. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
12. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation
at 3.3V.
13. See the individual user module data sheets for information on maximum frequencies for user modules.
Document Number: 001-13108 Rev. *C
Page 23 of 37
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CY8CLED04
Figure 5. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F24M
AC General Purpose I/O Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 19. AC GPI/O Specifications
Symbol
FGPI/O
TRiseF
TFallF
TRiseS
TFallS
Description
GPI/O Operating Frequency
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
Min
0
3
2
10
10
Typ
–
–
–
27
22
Max
12
18
18
–
–
Units
MHz
ns
ns
ns
ns
Notes
Normal Strong Mode
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Figure 6. GPI/O Timing Diagram
90%
G PIO
Pin
O utput
Voltage
10%
TR iseF
TRiseS
TFallF
TFallS
AC Full-Speed USB Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -10°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -10°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 20. AC Full-Speed (12 Mbps) USB Specifications
Symbol
TRFS
TFSS
TRFMFS
TDRATEFS
Description
Transition Rise Time
Transition Fall Time
Rise/Fall Time Matching: (TR/TF)
Full-Speed Data Rate
Document Number: 001-13108 Rev. *C
Min
4
4
90
12 - 0.25%
Typ
–
–
–
12
Max
20
20
111
12 + 0.25%
Units
ns
ns
%
Mbps
Notes
For 50 pF load.
For 50 pF load.
For 50 pF load.
Page 24 of 37
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CY8CLED04
AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V.
Table 21. 5V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Rising Settling Time from 80% of ΔV to 0.1% of
ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Settling Time from 20% of ΔV to 0.1% of
ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Rising Slew Rate (20% to 80%)(10 pF load,
Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Slew Rate (20% to 80%)(10 pF load,
Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Noise at 1 kHz (Power = Medium, Opamp Bias
= High)
Min
Typ
Max
Units
–
–
–
–
–
–
3.9
0.72
0.62
μs
μs
μs
–
–
–
–
–
–
5.9
0.92
0.72
μs
μs
μs
0.15
1.7
6.5
–
–
–
–
–
–
V/μs
V/μs
V/μs
0.01
0.5
4.0
–
–
–
–
–
–
V/μs
V/μs
V/μs
0.75
3.1
5.4
–
–
–
–
100
–
–
–
–
MHz
MHz
MHz
nV/rt-Hz
Min
Typ
Max
Units
–
–
–
–
3.92
0.72
μs
μs
–
–
–
–
5.41
0.72
μs
μs
0.31
2.7
–
–
–
–
V/μs
V/μs
0.24
1.8
–
–
–
–
V/μs
V/μs
0.67
2.8
–
–
–
100
–
–
–
MHz
MHz
nV/rt-Hz
Notes
Table 22. 3.3V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Rising Settling Time from 80% of ΔV to 0.1%
of ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Falling Settling Time from 20% of ΔV to 0.1%
of ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Rising Slew Rate (20% to 80%)(10 pF load,
Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Falling Slew Rate (20% to 80%)(10 pF load,
Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Noise at 1 kHz (Power = Medium, Opamp
Bias = High)
Document Number: 001-13108 Rev. *C
Notes
Page 25 of 37
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CY8CLED04
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 7. Typical AGND Noise with P2[4] Bypass
dBV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 8. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
Document Number: 001-13108 Rev. *C
0.01
0.1
Freq (kHz)
1
10
100
Page 26 of 37
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CY8CLED04
AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C and are for design guidance only.
Table 23. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Min
–
Typ
–
Max
50
Units
μs
Notes
≥ 50 mV overdrive comparator
reference set within VREFLPC.
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 24. AC Digital Block Specifications
Function
Timer
Description
Capture Pulse Width
Maximum Frequency, No Capture
Maximum Frequency, With Capture
Counter
Dead
Band
Min
Typ
50[14]
Max
Units
–
–
ns
–
–
49.92
MHz
–
–
25.92
MHz
50[14]
–
–
ns
Maximum Frequency, No Enable Input
–
–
49.92
MHz
Maximum Frequency, Enable Input
–
–
25.92
MHz
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
50[14]
–
–
ns
Disable Mode
50[14]
–
–
ns
Enable Pulse Width
Notes
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
Kill Pulse Width:
Maximum Frequency
–
–
49.92
MHz
4.75V < Vdd < 5.25V.
CRCPRS Maximum Input Clock Frequency
(PRS
Mode)
–
–
49.92
MHz
4.75V < Vdd < 5.25V.
CRCPRS Maximum Input Clock Frequency
(CRC
Mode)
–
–
24.6
MHz
SPIM
Maximum Input Clock Frequency
–
–
8.2
MHz
SPIS
Maximum Input Clock Frequency
–
–
4.1
MHz
Width of SS_ Negated Between Transmissions
[14]
–
–
ns
50
Maximum data rate at 4.1 MHz due to
2 x over clocking.
Transmitter
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum data rate at 3.08 MHz due
to 8 x over clocking.
Receiver
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum data rate at 3.08 MHz due
to 8 x over clocking.
Note
14. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 001-13108 Rev. *C
Page 27 of 37
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CY8CLED04
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 25. AC External Clock Specifications
Symbol
FOSCEXT
Description
Frequency for USB Applications
Min
Typ
Max
Units
23.94
24
24.06
MHz
–
Duty Cycle
47
50
53
%
–
Power up to IMO Switch
150
–
–
μs
Notes
AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 26. 5V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOBSS
BWOBLS
Description
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Power = Low
Power = High
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Power = Low
Power = High
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF
Load
Power = Low
Power = High
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
Power = Low
Power = High
Document Number: 001-13108 Rev. *C
Min
Typ
Max
Units
–
–
–
–
2.5
2.5
μs
μs
–
–
–
–
2.2
2.2
μs
μs
0.65
0.65
–
–
–
–
V/μs
V/μs
0.65
0.65
–
–
–
–
V/μs
V/μs
0.8
0.8
–
–
–
–
MHz
MHz
300
300
–
–
–
–
kHz
kHz
Notes
Page 28 of 37
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CY8CLED04
Table 27. 3.3V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOBSS
BWOBLS
Description
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Power = Low
Power = High
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Power = Low
Power = High
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Power = Low
Power = High
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
Power = Low
Power = High
Min
Typ
Max
Units
–
–
–
–
3.8
3.8
μs
μs
–
–
–
–
2.6
2.6
μs
μs
0.5
0.5
–
–
–
–
V/μs
V/μs
0.5
0.5
–
–
–
–
V/μs
V/μs
0.7
0.7
–
–
–
–
MHz
MHz
200
200
–
–
–
–
kHz
kHz
Notes
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 28. AC Programming Specifications
Symbol
TRSCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
TERASEB
TWRITE
TDSCLK
TDSCLK3
TERASEAL
Description
Rise Time of SCLK
Fall Time of SCLK
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
Flash Erase Time (Block)
Flash Block Write Time
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
Flash Erase Time (Bulk)
Min
1
1
40
40
0
–
–
–
–
–
Typ
–
–
–
–
–
10
40
–
–
40
Max
20
20
–
–
8
–
–
45
50
–
Units
ns
ns
ns
ns
MHz
ms
ms
ns
ns
ms
–
–
100[15] ms
Vdd > 3.6
3.0 ≤ Vdd ≤ 3.6
Erase all blocks and
protection fields at once.
0°C ≤ TJ ≤ 100°C
–
–
200[15] ms
-40°C ≤ TJ ≤ 0°C
L
TPROGRA Flash Block Erase + Flash Block Write Time
Notes
M_HOT
TPROGRA Flash Block Erase + Flash Block Write Time
M_COLD
Note
15. For the full industrial range, the user must employ a Temperature Sensor User Module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
Document Number: 001-13108 Rev. *C
Page 29 of 37
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CY8CLED04
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 29. AC Characteristics of the I2C SDA and SCL Pins for Vdd
Symbol
FSCLI2C
THDSTAI2
C
TLOWI2C
THIGHI2C
TSUSTAI2
C
THDDATI2
Description
SCL Clock Frequency
Hold Time (repeated) START Condition.
After this period, the first clock pulse is
generated.
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Set-up Time for a Repeated START
Condition
Data Hold Time
Standard-Mode
Min
Max
0
100
4.0
–
Fast-Mode
Min
Max
0
400
0.6
–
Units
Notes
kHz
μs
4.7
4.0
4.7
–
–
–
1.3
0.6
0.6
–
–
–
μs
μs
μs
0
–
0
–
μs
250
–
100[16]
–
ns
4.0
–
0.6
–
μs
4.7
–
1.3
–
μs
–
–
0
50
ns
C
TSUDATI2
Data Set-up Time
C
TSUSTOI2 Set-up Time for STOP Condition
C
TBUFI2C
TSPI2C
Bus Free Time Between a STOP and START
Condition
Pulse Width of spikes are suppressed by the
input filter.
Figure 9. Definition for Timing for Fast-/Standard-Mode on the I2C Bus
SDA
TLOWI2C
TSPI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Note
16. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-13108 Rev. *C
Page 30 of 37
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CY8CLED04
Packaging Information
This section illustrates the package specification for the CY8CLED04 EZ-Color device, along with the thermal impedance for the
package and solder reflow peak temperatures.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Figure 10. 68-Pin (8X8X0.90 mm) QFN (Sawn Type)
001-09618 *C
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
Important Note Pinned vias for thermal conduction are not required for the low-power device.
Document Number: 001-13108 Rev. *C
Page 31 of 37
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CY8CLED04
Thermal Impedance
Package
Typical θJA [17, 18]
68 QFN
13.05°C/W
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to
achieve good solderability.
Package
68 QFN
Minimum Peak
Temperature[19]
240oC
Maximum Peak
Temperature
260oC
Notes
17. TJ = TA + POWER x θJA
18. To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane.
19. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
Document Number: 001-13108 Rev. *C
Page 32 of 37
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CY8CLED04
Development Tools
Software
CY3263-ColorLock Evaluation Kit
This section presents the development tools available for all
current PSoC device families including the CY8CLED04
EZ-Color.
The CY3263-ColorLock evaluation board demonstrates the
ability of the EZ-Color device to use real-time optical feedback to
control three primary, high brightness LEDs and create accurate,
mixed-color output. The kit includes:
PSoC Designer™
At the core of the PSoC development software suite is PSoC
Designer, used to generate PSoC firmware applications. PSoC
Designer is available free of charge at
http://www.cypress.com/psocdesigner and includes a free C
compiler.
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube In-Circuit Emulator and
PSoC MiniProg. PSoC programmer is available free of charge at
http://www.cypress.com/psocprogrammer.
Evaluation Tools
All evaluation tools can be purchased from the Cypress Online
Store.
CY3261A-RGB EZ-Color RGB Kit
The CY3261A-RGB board is a preprogrammed HB LED color
mix board with seven pre-set colors using the CY8CLED16
EZ-Color HB LED Controller. The board is accompanied by a CD
containing the color selector software application, PSoC
Designer, PSoC Programmer, and a suite of documents,
schematics, and firmware examples. The color selector software
application can be installed on a host PC and is used to control
the EZ-Color HB LED controller using the included USB cable.
The application enables you to select colors via a CIE 1931 chart
or by entering coordinates. The kit includes:
■ Training Board (CY8CLED16)
■ One mini-A to mini-B USB Cable
■
■
PSoC Designer CD-ROM
Design Files and Application Installation CD-ROM
To program and tune this kit via PSoC Designer you must use a
Mini Programmer Unit (CY3217 Kit) and a CY3240-I2CUSB kit.
Document Number: 001-13108 Rev. *C
■
CY3263-ColorLock Evaluation Board
■
Tools CD, which includes:
❐ PSoC Programmer
❐ .NET Framework 2.0 (for Windows 2000 and Windows XP)
❐ PSoC Designer
❐ ColorLock Express Pack
❐ CY3263-ColorLock EZ-Color Kit CD
❐ ColorLock Monitor Application
❐ Kit Documents (Quick Start, Kit Guide, Release Note, Application Note, Data Sheets, Schematics, and Layouts)
❐ Firmware
■
Retractable USB Cable (A to Mini-B)
■
PSoC MiniProg Programmer
■
Power Supply Adapter
CY3265-RGB EZ-Color Evaluation Kit
The CY3265-RGB evaluation board demonstrates the ability of
the EZ-Color device to use real-time temperature feedback to
control three primary, high brightness LEDs and create accurate,
mixed-color output. There are three variations of the kit available,
depending on the LED manufacturer of the LEDs on the board:
CY3265C-RGB (Cree LEDs), CY3265N-RGB (Nichia LEDs), or
CY3265O-RGB (OSRAM LEDs). The kit includes:
■
CY3265C-RGB Evaluation Board
■
Tools CD, which includes:
❐ PSoC Programmer
❐ PSoC Designer
❐ .NET Framework 2.0 (Windows XP 32 bit)
■
Kit Documents (Quick Start, Kit Guide, Release Note, Application Note, Data Sheets, Schematics, and Layouts) Firmware
■
Blue PCA Enclosure/Case
■
12V 1A Power Supply
■
Retractable USB Cable (A to Mini-B)
■
PSoC MiniProg Programmer
■
Quick Start Guide
Page 33 of 37
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CY8CLED04
CY3210-MiniProg1
The CY3210-MiniProg1 kit allows a user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■ MiniProg Programming Unit
■
MiniEval Socket Programming and Evaluation Board
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■
28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
PSoC Designer Software CD
Getting Started Guide
USB 2.0 Cable
■
■
■
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit
includes:
■
Evaluation Board with LCD Module
■
MiniProg Programming Unit
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
Device Programmers
All device programmers can be purchased from the Cypress
Online Store.
CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■
Modular Programmer Base
■
3 Programming Module Cards
■
MiniProg Programming Unit
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
Note CY3207ISSP needs special software and is not compatible
with PSoC Programmer. The kit includes:
■
CY3207 Programmer Unit
■
PSoC ISSP Software CD
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
USB 2.0 Cable
Accessories (Emulation and Programming)
Table 30. Emulation and Programming Accessories
Part #
Pin
Flex-Pod Kit[20]
Package
CY8CLED04-68LTXI 68 QFN
Adapter[21]
CY3250-LED04 Adapters can be
found at
http://www.emulati
on.com.
Third Party Tools
Several tools have been specially designed by the following
third-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools
can be found at http://www.cypress.com under Design Support
>> Development Kits/Boards.
Build a PSoC Emulator into Your Board
For details on how to emulate your circuit before going to volume
production using an on-chip debug (OCD) non-production PSoC
device, see Application Note “Debugging - Build a PSoC
Emulator into Your Board - AN2323”.
Notes
20. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
21. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
http://www.emulation.com.
Document Number: 001-13108 Rev. *C
Page 34 of 37
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CY8CLED04
Ordering Information
Key Device Features
The following table lists the CY8CLED04 EZ-Color device key package features and ordering codes.
Analog Blocks
Digital I/O Pins
Analog Inputs
Analog Outputs
XRES Pin
1K
Digital Blocks
16K
16K
Temperature
Range
CY8CLED04-68LTXI
CY8CLED04-68LTXIT
SRAM
(Bytes)
68-Pin (8X8 mm) Sawn
68-Pin (8X8 mm) Sawn
(Tape and Reel)
Flash
(Bytes)
Package
Ordering
Code
Table 31. Device Key Features and Ordering Information
-40C to +85C
-40C to +85C
4
4
6
6
56
56
48
48
2
2
Yes
Yes
Ordering Code Definitions
CY 8 C LED
xx - xx xxxx
Package Type:
Thermal Rating:
PX = PDIP Pb-Free
C = Commercial
SX = SOIC Pb-Free
I = Industrial
PVX = SSOP Pb-Free
E = Extended
LTX/LKX = QFN Pb-Free
AX = TQFP Pb-Free
Pin Count
Part Number
LED Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Document Number: 001-13108 Rev. *C
Page 35 of 37
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CY8CLED04
Document History Page
Document Title: CY8CLED04 EZ-Color™ HB LED Controller
Document Number: 001-13108
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
1148504
SFVTMP3
See ECN
*A
2657959
DPT/PYRS
02/11/2009
Added package diagram 001-09618 and updated Ordering Information table
*B
2794355
XBM
10/28/2009
Added “Contents” on page 3.
Updated “Development Tools” on page 7.
Corrected FCPU1 and FCPU2 parameters in “AC Chip-Level Specifications”
on page 23.
*C
2850593
FRE/DSG/HMT
01/14/2010
Removed pruned/obsolete parts (CY8CLED04-68LFXI).
Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as
follows:
Modified TWRITE specifications.
Replaced TRAMP time) specification with SRPOWER_UP (slew rate) specification.
Added note to Flash Endurance specification.
Added IOH, IOL, DCILO, F32K_U, TPOWERUP, TERASEALL,
TPROGRAM_HOT, and TPROGRAM_COLD specifications.
Corrected the Pod Kit part numbers.
Updated Development Tools.
Updated copyright and Sales, Solutions, and Legal Information URLs.
Updated 68-Pin QFN (Sawn Type) package diagram.
Document Number: 001-13108 Rev. *C
Description of Change
New document.
Page 36 of 37
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CY8CLED04
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC® Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2007-2009, 2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products
for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-13108 Rev. *C
Revised January 15, 2010
Page 37 of 37
PSoC Designer™ and EZ-Color™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corporation.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
All products and company names mentioned in this document may be the trademarks of their respective holders.
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