Advanced CAT25C03/05/09/17/33 2K/4K/8K/16K/32K SPI Serial CMOS E2PROM FEATURES ■ 1,000,000 Program/Erase Cycles ■ 10 MHz SPI Compatible ■ 100 Year Data Retention ■ 1.8 to 6.0 Volt Operation ■ Self-Timed Write Cycle ■ Hardware and Software Protection ■ 8-Pin DIP/SOIC, 16-Pin SOIC and 14-Pin TSSOP ■ Zero Standby Current ■ Page Write Buffer ■ Low Power CMOS Technology ■ Write Protection ■ SPI Modes (0,0 &1,1) – Protect First Page, Last Page, Any 1/4 Array or Lower 1/2 Array ■ Commercial, Industrial and Automotive Temperature Ranges DESCRIPTION input (SCK), data in (SI) and data out (SO) are required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. The CAT25C03/05/09/17/33 is designed with software and hardware write protection features. The device is available in 8-pin DIP, 8-pin SOIC, 16-pin SOIC, 8-pin TSSOP and 14-pin TSSOP packages. The CAT25C03/05/09/17/33 is a 2K/4K/8K/16K/32K-Bit SPI Serial CMOS E2PROM internally organized as 256x8/512x8/1024x8/2048x8/4096x8 bits. Catalyst’s advanced CMOS Technology substantially reduces device power requirements. The CAT25C03/05 features a 16-byte page write buffer. The 25C09/17/33 features a 32-byte page write buffer.The device operates via the SPI bus serial interface and is enabled though a Chip Select (CS). In addition to the Chip Select, the clock PIN CONFIGURATION TSSOP Package (U14) SOIC Package (S16) SOIC Package (S) DIP Package (P) CS SO NC NC NC WP VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC HOLD NC NC NC SCK SI CS SO NC 1 2 3 NC NC NC 4 WP VSS 5 6 7 8 16 15 14 13 12 11 10 9 VCC HOLD NC NC NC NC SCK SI CS SO WP VSS 1 2 3 8 7 6 VCC CS HOLD SO SCK WP 1 4 5 SI 4 VSS 2 3 8 7 6 5 TSSOP Package (U) VCC CS HOLD SO SCK SI WP VSS Serial Data Output SCK Serial Clock WP Write Protect VCC +1.8V to +6.0V Power Supply VSS Ground CS Chip Select SI Serial Data Input HOLD Suspends Serial Input NC No Connect SO SI CS WP HOLD SCK I/O CONTROL SPI CONTROL LOGIC BLOCK PROTECT LOGIC 6 5 XDEC COLUMN DECODERS E2PROM ARRAY DATA IN STORAGE HIGH VOLTAGE/ TIMING CONTROL STATUS REGISTER © 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CONTROL LOGIC SO 3 4 VCC HOLD SCL SI SENSE AMPS SHIFT REGISTERS WORD ADDRESS BUFFERS Function 8 7 BLOCK DIAGRAM PIN FUNCTIONS Pin Name 1 2 1 25C128 F02 Doc. No. 25068-00 2/98 Advanced CAT25C03/05/09/17/33 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to Ground(1) ............ –2.0V to +VCC +2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND (3) Parameter Endurance Min. Max. Units Reference Test Method 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033 TDR(3) Data Retention 100 Years MIL-STD-883, Test Method 1008 VZAP(3) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH(3)(4) Latch-Up 100 mA JEDEC Standard 17 D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Units Test Conditions ICC1 Power Supply Current (Operating Write) 5 mA VCC = 5V @ 5MHz SO=open; CS=Vss ICC2 Power Supply Current (Operating Read) 0.4 mA VCC = 5.5V FCLK = 5MHz ISB Power Supply Current (Standby) 0 µA CS = VCC VIN = VSS or VCC ILI Input Leakage Current 2 µA ILO Output Leakage Current 3 µA VIL(3) Input Low Voltage -1 VCC x 0.3 V VIH(3) Input High Voltage VCC x 0.7 VCC + 0.5 V VOL1 Output Low Voltage 0.4 V VOH1 Output High Voltage VOL2 Output Low Voltage VOH2 Output High Voltage VCC - 0.8 V 0.2 VCC-0.2 VOUT = 0V to VCC, CS = 0V 4.5V≤VCC<5.5V IOL = 3.0mA IOH = -1.6mA V 1.8V≤VCC<2.7V V IOL = 150µA IOH = -100µA Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. Doc. No. 25068-00 2/98 2 Advanced CAT25C03/05/09/17/33 Figure 1. Sychronous Data Timing tCS VIH CS VIL tCSH tCSS VIH tWH SCK VIL tH tSU VIH tWL VALID IN SI VIL tV VOH SO tHO tDIS HI-Z HI-Z VOL A.C. CHARACTERISTICS Limits 1.8, 2.5 SYMBOL PARAMETER Min. 4.5V-5.5V Max. Min. Test Max. UNITS Conditions tSU Data Setup Time 50 10 ns VIH = 2.4V tH Data Hold Time 50 20 ns CL = 100pF tWH SCK High Time 200 40 ns VOL = 0.8V tWL SCK Low Time 200 40 ns VOH = 2.0v fSCK Clock Frequency DC tLZ DC 10 MHz HOLD to Output Low Z 50 50 ns (1) Input Rise Time 2 2 µs (1) Input Fall Time 2 2 µs tRI tFI 2 tHD HOLD Setup Time 100 40 ns tCD HOLD HOLD Time 100 40 ns tWC Write Cycle Time 10 5 ms tV Output Valid from Clock Low 200 80 ns tHO Output HOLD Time tDIS Output Disable Time 250 75 ns tHZ HOLD to Output High Z 100 50 ns tCS CS High Time 250 100 ns tCSS CS Setup Time 250 100 ns tCSH CS HOLD Time 250 100 ns 0 0 CL = 50pF CL = 100pF ns NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter. 3 Doc. No. 25068-00 2/98 Advanced CAT25C03/05/09/17/33 and the 25C03/05/09/17/33. Opcodes, byte addresses, or data present on the SI pin are latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK. FUNCTIONAL DESCRIPTION The CAT25C03/05/09/17/33 supports the SPI bus data transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT25C03/05/09/17/33 to interface directly with many of today’s popular microcontrollers. The CAT25C03/05/09/17/33 contains an 8-bit instruction register. (The instruction set and the operation codes are detailed in the instruction set table) CS CS: Chip Select CS is the Chip select pin. CS low enables the CAT25C03/ 05/09/17/33 and CS high disables the CAT25C03/05/ 09/17/33. CS high takes the SO output pin to high impedance and forces the devices into a Standby Mode (unless an internal write operation is underway) The CAT25C03/05/09/17/33 draws ZERO current in the Standby mode. A high to low transition on CS is required prior to any sequence being initiated. A low to high transition on CS after a valid write sequence is what initiates an internal write cycle. After the device is selected with CS going low, the first byte will be received. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The first byte contains one of the six op-codes that define the operation to be performed. PIN DESCRIPTION WP WP: Write Protect WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When WP is tied low, all write operations to the device are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. SI: Serial Input SI is the serial data input pin. This pin is used to input all opcodes, byte addresses, and data to be written to the 25C03/05/09/17/33. Input data is latched on the rising edge of the serial clock. SO: Serial Output SO is the serial data output pin. This pin is used to transfer data out of the 25C03/05/09/17/33. During a read cycle, data is shifted out on the falling edge of the serial clock. HOLD HOLD: Hold HOLD is the HOLD pin. The HOLD pin is used to pause transmission to the CAT25C03/05/09/17/33 while in the middle of a serial sequence without having to re-transmit entire sequence at a later time. To pause, HOLD must be SCK: Serial Clock SCK is the serial clock pin. This pin is used to synchronize the communication between the microcontroller INSTRUCTION SET Instruction Opcode Operation WREN 0000 0110 Enable Write Operations WRDI 0000 0100 Disable Write Operations RDSR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register READ 0000 X011(1) Read Data from Memory WRITE 0000 X010(1) Write Data to Memory Power-Up Timing(2)(3) Symbol Parameter Max. Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms Note: (1) X=O for 25C03, 25C09, 25C17 and 25C33. X=A8 for 25C05 (2) This parameter is tested initially and after a design or process change that affects the parameter. (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. Doc. No. 25068-00 2/98 4 Advanced CAT25C03/05/09/17/33 STATUS REGISTER brought low while SCK is low. The SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is brought high, while SCK is low. (HOLD should be held high any time this function is not being used.) HOLD may be tied high directly to VCC or tied to VCC through a resistor. Figure 9 illustrates hold timing sequence. The status register defines the protection status of the device. The register features three protection bits which allow the user to protect the desirable part of the memory array. There are seven different variations for the protection mechanism. The protection can vary from one page to as much as half of the entire array. These areas and associated address ranges are protected by configuring the protection bits of the status register through WRSR instruction. Once the three protection bits are set, the associated memory can be read but not written until the protection bits are reset. STATUS REGISTER 7 6 5 4 3 2 1 0 0 0 0 0 0 IDL2 IDL1 IDL0 MEMORY PROTECTION IDL2 IDL1 IDL0 0 0 0 Non-Protection 0 0 1 Q1 Protected 0 1 0 Q2 Protected 0 1 1 Q3 Protected 1 0 0 Q4 Protected 1 0 1 H1 Protected 1 1 0 P0 Protected 1 1 1 Pn Protected 25C03 25C05 25C09 25C17 25C33 Q1 00-3F 000-07F 000-0FF 000-1FF 000-3FF Q2 40-7F 080-0FF 100-1FF 200-3FF 400-7FF Q3 80-BF 100-17F 200-2FF 400-5FF 800-BFF Q4 C0-FF 180-1FF 300-3FF 600-7FF C00-FFF H1 00-7F 000-0FF 000-1FF 000-3FF 000-7FF P0 00-0F 000-00F 000-01F 000-01F 000-01F Pn F0-FF 1F0-1FF 3E0-3FF 7E0-7FF FE0-FFF 5 Doc. No. 25068-00 2/98 Advanced CAT25C03/05/09/17/33 After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by pulling the CS high. Read sequece is illustrated in Figure 4. Reading status register is illustrated in Figure 5. To read the status register, RDSR instruction should be sent. The contents of the status register are shifted out on the SO line. If a non-volatile write is in progress, the RDSR instruction returns a high on SO. When the non-volatile write cycle is completed, the status register data is read out. DEVICE OPERATION Write Enable and Disable The CAT25C03/05/09/17/33 contains a write enable latch. This latch must be set before any write operation. The device powers up in a write disable state when Vcc is applied. WREN instruction will enable writes (set the latch) to the device. WRDI instruction will disable writes (reset the latch) to the device. Disabling writes will protect the device against inadvertent writes. READ Sequence The part is selected by pulling CS low. The 8-bit read instruction is transmitted to the CAT25C03/05/09/17/33, followed by the 16-bit address for 25C09/17/33 (only 10bit addresses are used for 25C09, 11-bit addresses are used for 25C17, and 12-bit addresses are used for 25C33. The rest of the bits are don't care bits) and 8-bit address for 25C03/05 (for the 25C05, bit 3 of the read data instruction contains address A8). Figure 2. WREN Instruction Timing SK CS SI 0 0 0 0 1 0 1 0 HIGH-Z SO Figure 3. WRDI Instruction Timing SK CS SI 0 SO 0 0 0 0 1 0 0 HIGH-Z 25C128 F05 Doc. No. 25068-00 2/98 6 Advanced CAT25C03/05/09/17/33 Byte Write Once the device is in a Write Enable state, the user may proceed with a write sequence by setting the CS low, issuing a write instruction via the SI line, followed by the 16-bit address for 25C09/17/33. (only 10-bit addresses are used for 25C09, 11-bit addresses are used for 25C17, and 12-bit addresses are used for 25C33. The rest of the bits are don't care bits) and 8-bit address for 25C03/05 (for the 25C05, bit 3 of the read data instruction contains address A8). Programming will start after the CS is brought high. The low to high transition of the CS pin must occur during the SCK low time, immediately after clocking the least significant bit of the data. Figure 6 illustrates byte write sequence. WRITE Sequence The CAT25C03/05/09/17/33 powers up in a Write Disable state. Prior to any write instructions, the WREN instruction must be sent to CAT25C03/05/09/17/33. The device goes into Write enable state by pulling the CS low and then clocking the WREN instruction into CAT25C03/05/09/17/33. The CS must be brought high after the WREN instruction to enable writes to the device. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. Also, for a successful write operation the address of the memory location(s) to be programmed must be outside the protected address field. Figure 4. Read Instruction Timing RESET 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 SK CS SI 0 0 0 0 0 0 1 BYTE ADDRESS* 1 SO 7 6 5 4 3 2 1 0 *Please check the instruction set table for address Figure 5. RDSR Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 2 1 SCK SI DATA OUT SO HIGH IMPEDANCE 7 6 5 4 3 0 MSB 25C03 F09 7 Doc. No. 25068-00 2/98 Advanced CAT25C03/05/09/17/33 Page Write The CAT25C03/05/09/17/33 features page write capability. After the initial byte, the host may continue to write up to 16 bytes of data to the CAT25C03/05 and 32 bytes of data for 25C09/17/33. After each byte of data received, lower order address bits are internally incremented by one; the high order bits of address willremain constant.The only restriction is that the X (X=16 for 25C03/05 and X=32 for 25C09/17/33) bytes must reside on the same page. If the address counter reaches the end of the page and clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been written. The CAT25C03/05/09/17/33 is automatically returned to the write disable state at the completion of the write cycle. Figure 8 illustrates the page write sequence. To write to the status register, the WRSR instruction should be sent. Figure 7 illustrates the sequence of writing to status register. Figure 6. Write Instruction Timing 0 1 2 3 4 5 6 7 8 21 22 23 24 25 26 27 28 29 30 31 SK CS SI 0 0 0 0 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 ADDRESS SO Figure 7. WRSR Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 1 0 SCK DATA IN INSTRUCTION 7 SI SO Doc. No. 25068-00 2/98 8 6 5 4 3 Advanced CAT25C03/05/09/17/33 DESIGN CONSIDERATIONS is ignored and programming is continued. On power up, SO is in a high impedance. If an invalid op code is received, no data will be shifted into the CAT25C03/05/ 09/17/33, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. The CAT25C03/05/09/17/33 powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued to perform any writes to the device after power up. Also,on power up CS should be brought low to enter a ready state and receive an instruction. After a successful byte/page write or status register write the CAT25C03/05/09/17/33 goes into a write disable mode. CS must be set high after the proper number of clock cycles to start an internal write cycle. Access to the array during an internal write cycle Figure 8. Page Write Instruction Timing 0 1 2 3 4 5 6 7 8 21 22 23 24-31 32-39 SK CS SI 0 0 0 0 0 0 1 0 ADDRESS Data Byte 1 Data Byte 2 Data Byte 3 Data Byte N SO Figure 9. HOLD Timing CS tCD tCD SCK tHD tHD HOLD tHZ SO tLZ 25C128 F10 9 Doc. No. 25068-00 2/98 Advanced CAT25C03/05/09/17/33 ORDERING INFORMATION Prefix CAT Optional Company ID Device # 25C17 Product Number 25C33: 32K 25C17:16K 25C09: 8K 25C05: 4K 25C03: 2K Suffix -1.8 I S Temperature Range Blank = Commercial (0˚C to +70˚C) I = Industrial (-40˚C to +85˚C) A = Automotive (-40˚ to +105˚C)* Package P = PDIP S = 8-pin SOIC S16 = 16-pin SOIC U=8-pin TSSOP U14 = 14-pin TSSOP TE13 Tape & Reel TE13: 2000/Reel Operating Voltage Blank (Vcc=2.5 to 6.0V) 1.8 (Vcc=1.8 to 6.0V) * -40˚C to +125˚C is available upon request Notes: (1) The device used in the above example is a 25C17SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage, Tape & Reel) Doc. No. 25068-00 2/98 10