NXP ADC1213D125HN/C1 Dual 12-bit adc; 65 msps, 80 msps, 105 msps or 125 msp Datasheet

ADC1213D series
Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps
Rev. 05 — 23 April 2010
Preliminary data sheet
1. General description
The ADC1213D is a dual-channel 12-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performances and low power at sample rates up to 125 Msps. Pipelined
architecture and output error correction ensure the ADC1213D is accurate enough to
guarantee zero missing codes over the entire operating range. Supplied from a 3 V
source for analog and a 1.8 V source for the output driver, it embeds two serial outputs.
Each lane is differential and complies with the JESD204A standard. An integrated Serial
Peripheral Interface (SPI) allows the user to easily configure the ADC. A set of IC
configurations is also available via the binary level control pins taken, which are used at
power-up. The device also includes a SPI programmable full-scale to allow flexible input
voltage range from 1 V to 2 V (peak-to-peak).
Excellent dynamic performance is maintained from the baseband to input frequencies of
170 MHz or more, making the ADC1213D ideal for use in communications, imaging, and
medical applications.
2. Features and benefits
„ SNR, 70 dBFS; SFDR, 86 dBc
„ Sample rate up to 125 Msps
„ Clock input divider by 2 for less jitter
contribution
„ 3 V, 1.8 V single supplies
„ Flexible input voltage range:
1 V to 2 V (peak-to-peak)
„ Two configurable serial outputs
„ INL ± 1 LSB; DNL ± 0.5 LSB
„ Pin compatible with the ADC1213D
series
„ HVQFN56 package
„ Input bandwidth, 600 MHz
„ Power dissipation, 995 mW at 80 Msps
„ SPI register programming
„ Duty cycle stabilizer
„ High IF capability
„ Offset binary, two’s complement, gray
code
„ Power-down mode and Sleep mode
„ Compliant with JESD204A serial
transmission standard
3. Applications
„ Wireless and wired broadband
communications
„ Spectral analysis
„ Ultrasound equipment
„ Portable instrumentation
„ Imaging systems
„ Software defined radio
ADC1213D series
NXP Semiconductors
ADC1213D series
4. Ordering information
Table 1.
Ordering information
Type number
Sampling
frequency
(Msps)
Package
Name
Description
ADC1213D125HN/C1
125
HVQFN56
plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8 × 8 × 0.85 mm
ADC1213D105HN/C1
105
HVQFN56
plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8 × 8 × 0.85 mm
ADC1213D080HN/C1
80
HVQFN56
plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8 × 8 × 0.85 mm
ADC1213D065HN/C1
65
HVQFN56
plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8 × 8 × 0.85 mm
Version
5. Block diagram
CFG (0 to 3)
SDIO/DCS
SCLK/DCS
ERROR
CORRECTION AND
DIGITAL
PROCESSING
CS
SPI
SYNCP
SYNCN
INAP
SWING_n
ADCA CORE
12-BIT
PIPELINED
FRAME ASSEMBLY
CLOCK INPUT
STAGE & DUTY
CYCLE CONTROL
CLKP
DLL
PLL
CLKM
ERROR
CORRECTION AND
DIGITAL
PROCESSING
8-bit
OTR
INBP
T/H
INPUT
STAGE
8-bit
ADCB CORE
12-BIT
PIPELINED
8-bit
ENCODER 8-bit/10-bit B
8-bit
SCRAMBLER A
OTR
INAM
ENCODER 8-bit/10-bit A
D11 to D0
SCRAMBLER B
T/H
INPUT
STAGE
SERIALIZER A
CMLPA
OUTPUT
BUFFER A
CMLNA
SERIALIZER B
CMLPB
OUTPUT
BUFFER B
CMLNB
10-bit
10-bit
D11 to D0
SWING_n
INBM
CLOCK INPUT
STAGE & DUTY
CYCLE CONTROL
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
ADC1213D
SCRAMBLER RESET
REFBT
REFAB
REFBB
REFAT
VCMB
VCMA
SENSE VREF
Fig 1.
005aaa120
Block diagram
ADC1213D_SER_5
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
2 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
6. Pinning information
43 SYNCP
44 SYNCN
45 DGND
46 VDDD
47 SWING-0
48 SWING_1
49 DNC
50 VDDA
51 AGND
52 AGND
53 VDDA
54 SENSE
55 VREF
56 VDDA
6.1 Pinning
INAP
1
42 DGND
INAM
2
41 DGND
VCMA
3
40 VDDD
REFAT
4
39 CMLPA
REFAB
5
38 CMLNA
AGND
6
37 VDDD
CLKP
7
CLKN
8
35 DGND
AGND
9
34 VDDD
36 DGND
ADC1213D
REFBB 10
33 CMLNB
REFBT 11
32 CMLPB
DGND 28
VDDD 27
CFG3 26
CFG2 25
CFG1 24
CFG0 23
SCRAMBLER 22
RESET 21
AGND 20
CS 19
SDIO/DCS 18
29 DGND
SCLK/DFS 17
30 DGND
INBP 14
VDDA 16
31 VDDD
INBM 13
VDDA 15
VCMB 12
005aaa121
Transparent top view
Fig 2.
Pinning diagram
6.2 Pin description
ADC1213D_SER_5
Preliminary data sheet
Table 2.
Pin description
Symbol
Pin
Type [1]
Description
INAP
1
I
channel A analog input
INAM
2
I
channel A complementary analog input
VCMA
3
O
channel A output common voltage
REFAT
4
O
channel A top reference
REFAB
5
O
channel A bottom reference
AGND
6
G
analog ground
CLKP
7
I
clock input
CLKM
8
I
complementary clock input
AGND
9
G
analog ground
REFBB
10
O
channel B bottom reference
REFBT
11
O
channel B top reference
VCMB
12
O
channel B output common voltage
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
3 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
Table 2.
Pin description …continued
Symbol
Pin
Type [1]
Description
INBM
13
I
channel B complementary analog input
INBP
14
I
channel B analog input
VDDA
15
P
analog power supply 3 V
VDDA
16
P
analog power supply 3 V
SCLK/DCS
17
I
SPI clock
data format select
SDIO/DCS
18
I/O
SPI data input/output
duty cycle stabilizer
ADC1213D_SER_5
Preliminary data sheet
CS
19
I
chip select bar
AGND
20
G
analog ground
RESET
21
I
JEDEC digital IP reset
SCRAMBLER
22
I
scrambler enable and disable
CFG0
23
I/O
see Table 28 (input) or OTRA (output)[2]
CFG1
24
I/O
see Table 28 (input) or OTRB (output)[2]
CFG2
25
I/O
see Table 28 (input)
CFG3
26
I/O
see Table 28 (input)
VDDD
27
P
digital power supply 1.8 V
DGND
28
G
digital ground
DGND
29
G
digital ground
DGND
30
G
digital ground
VDDD
31
P
digital power supply 1.8 V
CMLPB
32
O
channel B output
CMLNB
33
O
channel B complementary output
VDDD
34
P
digital power supply 1.8 V
DGND
35
G
digital ground
DGND
36
G
digital ground
VDDD
37
P
digital power supply 1.8 V
CMLNA
38
O
channel A complementary output
CMLPA
39
O
channel A output
VDDD
40
P
digital power supply 1.8 V
DGND
41
G
digital ground
DGND
42
G
digital ground
SYNCP
43
I
synchronization from FPGA
SYNCN
44
I
synchronization from FPGA
DGND
45
G
digital ground
VDDD
46
P
digital power supply 1.8 V
SWING_0
47
I
JESD204 serial buffer programmable output swing
SWING_1
48
I
JESD204 serial buffer programmable output swing
DNC
49
O
do not connect
VDDA
50
P
analog power supply 3 V
AGND
51
G
analog ground
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
4 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
Table 2.
Pin description …continued
Symbol
Pin
Type [1]
Description
AGND
52
G
analog ground
VDDA
53
P
analog power supply 3 V
SENSE
54
I
reference programming pin
VREF
55
I/O
voltage reference input/output
VDDA
56
P
analog power supply 3 V
[1]
P: power supply; G: ground; I: input; O: output; I/O: input/output.
[2]
OTRA stands for “OuT of Range” A. OTRB stands for “OuT of Range” B
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Min
Max
Unit
VDDA
analog supply voltage
Conditions
[1]
−0.4
+4.6
V
VDDD
digital supply voltage
[2]
−0.4
+2.5
V
ΔVCC
supply voltage difference
<tbd>
<tbd>
V
Tstg
storage temperature
−55
+125
°C
Tamb
ambient temperature
−40
+85
°C
Tj
junction temperature
-
125
°C
VDDA − VDDD
[1]
The supply voltage VDDA may have any value between −0.5 V and +7.0 V provided that the supply voltage
differences ΔVCC are respected.
[2]
The supply voltage VDDD may have any value between −0.5 V and +5.0 V provided that the supply voltage
differences ΔVCC are respected.
8. Thermal characteristics
Table 4.
Thermal characteristics
Symbol
Rth(j-a)
Rth(j-c)
[1]
Parameter
Conditions
Typ
Unit
thermal resistance from junction to ambient
[1]
17.8
K/W
thermal resistance from junction to case
[1]
6.8
K/W
Value for six layers board in still air with a minimum of 25 thermal vias.
9. Static characteristics
Table 5.
Characteristics[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDDA
analog supply voltage
2.85
3.0
3.4
V
VDDD
digital supply voltage
1.65
1.8
1.95
V
IDDA
analog supply current
-
343
-
mA
ADC1213D_SER_5
Preliminary data sheet
fclk = 125 Msps;
fi =70 MHz
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
5 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
Table 5.
Characteristics[1] …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IDDD
digital supply current
fclk = 125 Msps;
fi = 70 MHz
-
150
-
mA
Ptot
total power dissipation
fclk = 125 Msps
-
1270
-
mW
P
power dissipation
fclk = 105 Msps
-
1150
-
mW
fclk = 80 Msps
-
995
-
mW
fclk = 65 Msps
-
885
-
mW
power-down mode
-
30
-
mW
standby mode
-
200
-
mW
Digital inputs
Clock inputs: pins CLKP and CLKM, AC coupled
LVPECL
Vi(clk)dif
differential clock input
voltage
peak-to-peak
-
±0.8
-
V
differential clock input
voltage
peak-to-peak
-
±0.4
-
V
differential clock input
voltage
peak-to-peak
±0.8
±1.5
-
V
LVDS
Vi(clk)dif
SINE wave
Vi(clk)dif
LVCMOS mode
VIL
LOW-level input voltage
-
-
0.3VDDA
V
VIH
HIGH-level input voltage
0.7VDDA
-
-
V
Logic inputs, Power-down: pins CFG0 to CFG3, SCRAMBLER, SWING_0, and SWING_1
VIL
LOW-level input voltage
-
0
-
V
VIH
HIGH-level input voltage
-
0.66VDDD
-
V
IIL
LOW-level input current
−6
-
+6
μA
IIH
HIGH-level input current
−30
-
+30
μA
SPI: pins CS, SDIO/DCS, and SCLK/DCS
VIL
LOW-level input voltage
0
-
0.3VDDA
V
VIH
HIGH-level input voltage
0.7VDDA
-
VDDA
V
IIL
LOW-level input current
−10
-
+10
μA
IIH
HIGH-level input current
−50
-
+50
μA
CI
input capacitance
-
4
-
pF
ADC1213D_SER_5
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
6 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
Table 5.
Symbol
Characteristics[1] …continued
Parameter
Conditions
Min
Typ
Max
Unit
Analog inputs: pins INAP, INAM, INBP, and INBM
II
input current
track mode
−5
-
+5
μA
RI
input resistance
track mode
-
15
-
Ω
CI
input capacitance
track mode
-
5
-
pF
VI(cm)
common-mode input
voltage
track mode
0.9
1.5
2
V
Bi
input bandwidth
-
600
-
MHz
VI(dif)
differential input voltage
1
-
2
V
peak-to-peak
Voltage controlled regulator output: pins VCMA and VCMB
VO(cm)
common-mode output
voltage
-
0.5VDDA
-
V
IO(cm)
common-mode output
current
-
<tbd>
-
μA
output
0.5
-
1
V
input
0.5
-
1
V
-
pin AGND;
VVREF; VDDA
-
V
Reference voltage input/output: pin VREF
VVREF
voltage on pin VREF
Reference mode selection: pin SENSE
VSENSE
voltage on pin SENSE
Data outputs: CMLPA, CMLNA
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 000
VOL
VOH
LOW-level output
voltage
DC coupled; output
-
1.5
-
V
AC coupled
-
1.65
-
V
HIGH-level output
voltage
DC coupled; output
-
1.8
-
V
AC coupled
-
1.35
-
V
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 001
VOL
LOW-level output
voltage
DC coupled; output
-
1.45
-
V
AC coupled
-
1.625
-
V
VOH
HIGH-level output
voltage
DC coupled; output
-
1.8
-
V
AC coupled
-
1.275
-
V
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 010
VOL
VOH
LOW-level output
voltage
DC coupled; output
-
1.4
-
V
AC coupled
-
1.6
-
V
HIGH-level output
voltage
DC coupled; output
-
1.8
-
V
AC coupled
-
1.2
-
V
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 011
VOL
VOH
LOW-level output
voltage
DC coupled; output
-
1.35
-
V
AC coupled
-
1.575
-
V
HIGH-level output
voltage
DC coupled; output
-
1.8
-
V
AC coupled
-
1.125
-
V
ADC1213D_SER_5
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
7 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
Table 5.
Symbol
Characteristics[1] …continued
Parameter
Conditions
Min
Typ
Max
Unit
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 100
VOL
VOH
LOW-level output
voltage
DC coupled; output
-
1.3
-
V
AC coupled
-
1.55
-
V
HIGH-level output
voltage
DC coupled; output
-
1.8
-
V
AC coupled
-
1.05
-
V
Serial configuration: SYNCCP, SYNCCN
VIL
LOW-level input voltage
differential; input
-
0.95
-
V
VIH
High-level input voltage
differential; input
-
1.47
-
V
−5
±1
+5
LSB
−0.95
±0.5
+0.95
LSB
-
±2
-
mV
-
± 0.5
-
%
-
<tbd>
-
%
-
35
-
dBc
Accuracy
INL
integral non-linearity
DNL
differential non-linearity
Eoffset
offset error
EG
gain error
MG(CTC)
channel-to-channel gain
matching
no missing codes
guaranteed
full-scale
Supply
PSRR
[1]
power supply rejection
ratio
100 mV (p-p) on VDDA
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C. Minimum and maximum values are across the full temperature
range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V; VI (INAP, INBP) − VI (INAM, INBM) = −1 dBFS; internal reference mode;
100 Ω differential applied to serial outputs; unless otherwise specified.
ADC1213D_SER_5
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
8 of 41
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Table 6.
Characteristics[1]
Symbol
Parameter
Conditions
ADC1213D065
ADC1213D080
ADC1213D105
ADC1213D125
NXP Semiconductors
ADC1213D_SER_5
Preliminary data sheet
10. Dynamic characteristics
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fi = 3 MHz
-
87
-
-
87
-
-
86
-
-
88
-
dBc
fi = 30 MHz
-
86
-
-
86
-
-
86
-
-
87
-
dBc
fi = 70 MHz
-
85
-
-
85
-
-
84
-
-
85
-
dBc
Analog signal processing
α2H
α3H
Rev. 05 — 23 April 2010
All information provided in this document is subject to legal disclaimers.
THD
ENOB
SFDR
third harmonic level
total harmonic distortion
effective number of bits
signal-to-noise ratio
spurious-free dynamic
range
fi = 170 MHz
-
82
-
-
82
-
-
81
-
-
83
-
dBc
fi = 3 MHz
-
86
-
-
86
-
-
85
-
-
87
-
dBc
fi = 30 MHz
-
85
-
-
85
-
-
85
-
-
86
-
dBc
fi = 70 MHz
-
84
-
-
84
-
-
83
-
-
84
-
dBc
fi = 170 MHz
-
81
-
-
81
-
-
80
-
-
82
-
dBc
fi = 3 MHz
-
85
-
-
85
-
-
84
-
-
86
-
dBc
fi = 30 MHz
-
84
-
-
84
-
-
84
-
-
85
-
dBc
fi = 70 MHz
-
83
-
-
83
-
-
82
-
-
83
-
dBc
fi = 170 MHz
-
80
-
-
80
-
-
79
-
-
81
-
dBc
fi = 3 MHz
-
11.3
-
-
11.3
-
-
11.3
-
-
11.3
-
bits
fi = 30 MHz
-
11.3
-
-
11.3
-
-
11.3
-
-
11.2
-
bits
fi = 70 MHz
-
11.2
-
-
11.2
-
-
11.2
-
-
11.2
-
bits
fi = 170 MHz
-
11.1
-
-
11.1
-
-
11.1
-
-
11.1
-
bits
fi = 3 MHz
-
70.0
-
-
69.9
-
-
69.8
-
-
69.6
-
dBFS
fi = 30 MHz
-
69.5
-
-
69.5
-
-
69.5
-
-
69.4
-
dBFS
fi = 70 MHz
-
69.2
-
-
69.2
-
-
69.1
-
-
69.0
-
dBFS
-
68.8
-
-
68.8
-
-
68.7
-
-
68.6
-
dBFS
fi = 3 MHz
-
86
-
-
86
-
-
85
-
-
87
-
dBc
fi = 30 MHz
-
85
-
-
85
-
-
85
-
-
86
-
dBc
fi = 70 MHz
-
84
-
-
84
-
-
83
-
-
84
-
dBc
fi = 170 MHz
-
81
-
-
81
-
-
80
-
-
82
-
dBc
ADC1213D series
9 of 41
© NXP B.V. 2010. All rights reserved.
fi = 170 MHz
ADC1213D series
SNR
second harmonic level
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Characteristics[1] …continued
Symbol
Parameter
IMD
αct(ch)
[1]
Conditions
ADC1213D080
ADC1213D105
ADC1213D125
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
-
89
-
-
89
-
-
88
-
-
89
-
dBc
fi = 30 MHz
-
88
-
-
88
-
-
88
-
-
88
-
dBc
fi = 70 MHz
-
87
-
-
87
-
-
86
-
-
86
-
dBc
fi = 170 MHz
-
84
-
-
85
-
-
83
-
-
84
-
dBc
fi = 70 MHz
-
100
-
-
100
-
-
100
-
-
100
-
dBc
intermodulation distortion fi = 3 MHz
crosstalk between
channels
ADC1213D065
NXP Semiconductors
ADC1213D_SER_5
Preliminary data sheet
Table 6.
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C. Minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V,
VDDD = 1.8 V; VI (INAP, INBP) − VI (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless otherwise specified.
Rev. 05 — 23 April 2010
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ADC1213D series
ADC1213D series
10 of 41
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 7.
NXP Semiconductors
ADC1213D_SER_5
Preliminary data sheet
11. Clock and digital output timing
Characteristics[1]
Symbol Parameter
Conditions
ADC1213D065
ADC1213D080
ADC1213D105
ADC1213D125
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
20
-
65
60
-
80
75
-
105
100
-
125
Msps
Clock timing input: pins CLKP and CLKM
fclk
clock frequency
tlat(data)
data latency time
clock cycles
307
-
850
250
-
283
190
-
226
160
-
170
ns
δclk
clock duty cycle
DCS_EN = 1:
en
30
50
70
30
50
70
30
50
70
30
50
70
%
DCS_EN = 0:
dis
45
50
55
45
50
55
45
50
55
45
50
55
%
Rev. 05 — 23 April 2010
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td(s)
sampling delay time
-
0.8
-
-
0.8
-
-
0.8
-
-
0.8
-
ns
twake
wake-up time
-
<tbd>
-
-
<tbd>
-
-
<tbd>
-
-
<tbd>
-
ns
[1]
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C. Minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V,
VDDD = 1.8 V; VI (INAP, INBP) − VI (INAM, INBM) = −1 dBFS; internal reference mode; 100 W differential applied to serial outputs; unless otherwise specified.
ADC1213D series
ADC1213D series
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ADC1213D series
12. Serial output timings
The eye diagram of the serial output is shown in Figure 3 and Figure 4. Test conditions
are:
• 3.125 Gbps data rate
• Tamb = 25 °C
• DC coupling with two different receiver common-mode voltages
005aaa088
Fig 3.
Eye diagram at 1 V receiver common-mode
005aaa089
Fig 4.
ADC1213D_SER_5
Preliminary data sheet
Eye diagram at 2 V receiver common-mode
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13. SPI timing
Table 8.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
40
-
-
ns
Serial Peripheral Interface timings
tw(SCLK)
SCLK pulse width
tw(SCLKH)
SCLK HIGH pulse width
16
-
-
ns
tw(SCLKL)
SCLK LOW pulse width
16
-
-
ns
tsu
set-up time
data to SCLKH
5
-
-
ns
CS to SCLKH
5
-
-
ns
hold time
th
fclk(max)
[1]
data to SCLKH
2
-
-
ns
CS to SCLKH
2
-
-
ns
-
-
25
MHz
maximum clock frequency
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C. Minimum and maximum values are across the full temperature
range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V; VI (INAP, INBP) − VI (INAM,INBM) = −1 dBFS; internal reference mode;
100 Ω differential applied to serial outputs; unless otherwise specified.
tsu
tsu
th
CS
tw(SCLKL)
th
tw(SCLKH)
tw(SCLK)
SCLK
SDIO
R/W
W1
W0
A12
A11
D2
D1
D0
005aaa065
Fig 5.
SPI timings
14. Application information
14.1 Analog inputs
14.1.1 Input stage description
The analog input of the ADC1213D supports differential or single-ended input drive.
Optimal performance is achieved using differential inputs with the common-mode input
voltage (VI(cm)) on pins INxP and INxM set to 0.5VDDA.
The full scale analog input voltage range is configurable between ± 1 V (p-p) and
± 2 V (p-p) via a programmable internal reference (see Section 14.2 and Table 21 for
further details).
Figure 6 shows the equivalent circuit of the sample and hold input stage, including
ElectroStatic Discharge (ESD) protection and circuit and package parasitics.
ADC1213D_SER_5
Preliminary data sheet
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ADC1213D series
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ADC1213D series
Package
ESD
Parasitics
Switch
INAP
INBP
Ron = 15 Ω
1, 14
4 pF
Cs
Internal
clock
Switch
INAM
INBM
Ron = 15 Ω
2, 13
4 pF
Cs
Internal
clock
005aaa069
Fig 6.
Input sampling circuit
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
14.1.2 Anti-kickback circuitry
Anti-kickback circuitry (RC filter in Figure 7) is needed to counteract the effects of a
charge injection generated by the sampling capacitance.
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time excessively.
R
INP
C
R
INM
005aaa073
Fig 7.
Anti-kickback circuit
The component values are determined by the input frequency and should be selected so
as not to affect the input bandwidth.
ADC1213D_SER_5
Preliminary data sheet
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ADC1213D series
NXP Semiconductors
ADC1213D series
Table 9.
RC coupling versus input frequency - typical values
Input frequency
R
C
3 MHz
25 Ω
12 pF
70 MHz
12 Ω
8 pF
170 MHz
12 Ω
8 pF
14.1.3 Transformer
The configuration of the transformer circuit is determined by the input frequency. The
configuration shown in Figure 8 would be suitable for a baseband application.
100 nF
Analog
input
100 nF
25 Ω
ADT1-1WT
INAP
INBP
25 Ω
12 pF
100 nF
100 nF
25 Ω
25 Ω
INAM
INBM
VCM
100 nF
100 nF
005aaa070
Fig 8.
Single transformer configuration
ADT1-1WT
Analog
input
100 nF
ADT1-1WT
12 Ω
50 Ω
50 Ω
50 Ω
50 Ω
INAP
INBP
8.2 pF
100 nF
12 Ω
INAM
INBM
VCM
100 nF
100 nF
005aaa071
Fig 9.
Dual transformer configuration
The configuration shown in Figure 9 is recommended for high frequency applications. In
both cases, the choice of transformer will be a compromise between cost and
performance.
ADC1213D_SER_5
Preliminary data sheet
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ADC1213D series
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ADC1213D series
14.2 System reference and power management
14.2.1 Internal/external reference
The ADC1213D has a stable and accurate built-in internal reference voltage to adjust the
ADC full-scale. This reference voltage can be set internally via SPI or with pin VREF an
SENSE (see Figure 11, Figure 12, Figure 13 and Figure 14), in 1 dB steps between 0 dB
and −6 dB, via SPI control bits INTREF[2:0] (when bit INTREF_EN = 1; see Table 21).
The equivalent reference circuit is shown in Figure 10. External reference is also possible
by providing a voltage on pin VREF as described in Figure 13.
REFT
REFERENCE
AMP
REFB
VREF
EXT_ref
BUFFER
EXT_ref
BANDGAP
REFERENCE
ADC CORE
SENSE
SELECTION
LOGIC
005aaa164
Fig 10. Reference equivalent schematic
Table 10 shows how to choose between the different internal/external modes:
Table 10.
Reference modes
Mode
SPI bit, “Internal
reference”
SENSE pin
VREF pin
Full Scale,
V (p-p)
Internal (Figure 11)
0
GND
330 pF capacitor 2
to GND
Internal (Figure 12)
0
VREF pin = SENSE pin and
330 pF capacitor to GND
External (Figure 13)
0
VDDA
Internal, SPI mode
(Figure 14)
1
VREF pin = SENSE pin and
330 pF capacitor to GND
1
External voltage 1 to 2
from 0.5 V to 1 V
1 to 2
Figure 11 to Figure 14 indicate how to connect the SENSE and VREF pins.
ADC1213D_SER_5
Preliminary data sheet
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ADC1213D series
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ADC1213D series
VREF
VREF
330 pF
330
pF
REFERENCE
EQUIVALENT
SCHEMATIC
REFERENCE
EQUIVALENT
SCHEMATIC
SENSE
SENSE
005aaa117
005aaa116
Fig 11. Internal reference, 2 V (p-p) full-scale
Fig 12. Internal reference, 1 V (p-p) full-scale
VREF
VREF
V
0.1 μF
330 pF
REFERENCE
EQUIVALENT
SCHEMATIC
REFERENCE
EQUIVALENT
SCHEMATIC
SENSE
SENSE
VDDA
005aaa118
005aaa119
Fig 13. External reference, 1 V (p-p) to 2 V (p-p)
full-scale
Fig 14. Internal reference via SPI, 1 V (p-p) to 2 V (p-p)
full-scale
14.2.2 Reference gain control
The reference gain is programmable between 0 dB to −6 dB in steps of 1 dB via the SPI
(see Table 21). The corresponding full scale input voltage range varies between 2 V (p-p)
and 1 V (p-p), as shown in Table 11:
Table 11.
Reference SPI gain control
INTREF[2:0]
Level
Full Scale, V (p-p)
000
0 dB
2
001
−1 dB
1.78
010
−2 dB
1.59
011
−3 dB
1.42
100
−4 dB
1.26
101
−5 dB
1.12
110
−6 dB
1
111
not used
x
14.2.3 Common-mode output voltage (VI(cm))
An 0.1 μF filter capacitor should be connected between on the one hand the pins VCMA
and VCMB and on the other hand ground to ensure a low-noise common-mode output
voltage. When AC-coupled, these pins can be used to set the common-mode reference
for the analog inputs, for instance via a transformer middle point.
ADC1213D_SER_5
Preliminary data sheet
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ADC1213D series
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ADC1213D series
PACKAGE
ESD
PARASITICS
COMMON MODE
REFERENCE
1.5 V
VCMA
VCMB
0.1 μF
ADC CORE
005aaa077
Fig 15. Reference equivalent schematic
14.2.4 Biasing
The common-mode output voltage, VO(cm), should be set externally to 1.5 V (typical). The
common-mode input voltage, VI(cm), at the inputs to the sample and hold stage
(pins INAM, INBM, INAP, and INBP) must be between 0.9 V and 2 V for optimal
performance.
14.3 Clock input
14.3.1 Drive modes
The ADC1213D can be driven differentially (SINE, LVPECL or LVDS) with little or no
influence on dynamic performances. It can also be driven by a single-ended LVCMOS
signal connected to pin CLKP (CLKM should be connected to ground via a capacitor).
LVCMOS
clock input
CLKP
CLKP
CLKM
LVCMOS
clock input
005aaa174
a. Rising edge LVCMOS
CLKM
005aaa053
b. Falling edge LVCMOS
Fig 16. LVCMOS single-ended clock input
ADC1213D_SER_5
Preliminary data sheet
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ADC1213D series
NXP Semiconductors
ADC1213D series
Sine
clock input
CLKP
Sine
clock input
CLKP
CLKM
CLKM
005aaa173
005aaa054
a. Sine clock input
b. Sine clock input (with transformer)
CLKP
CLKP
LVPECL
clock input
LVDS
clock input
CLKM
CLKM
005aaa055
005aaa172
c. LVDS clock input
d. LVPECL clock input
Fig 17. Differential clock input
14.3.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 18. The common-mode
voltage of the differential input stage is set via internal resistors of 5 kΩ resistors.
Package
ESD
Parasitics
CLKP
Vcm(clk)
SE_SEL
SE_SEL
5 kΩ
5 kΩ
CLKM
005aaa081
Fig 18. Equivalent input circuit
Single-ended or differential clock inputs can be selected via the SPI (see Table 20). If
single-ended is selected, the input pin (CLKM or CLKP) is selected via control bit
SE_SEL.
ADC1213D_SER_5
Preliminary data sheet
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ADC1213D series
NXP Semiconductors
ADC1213D series
If single-ended is implemented without setting SE_SEL accordingly, the unused pin
should be connected to ground via a capacitor.
14.3.3 Clock input divider
The ADC1413D contains an input clock divider that divides the incoming clock by a factor
of 2 (when bit CLKDIV = 1; see Table 20). This feature allows the user to deliver a higher
clock frequency with better jitter performance, leading to a better SNR result once
acquisition has been performed.
14.3.4 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performances of the ADC by
compensating the input clock signal duty cycle. When the duty cycle stabilizer is active
(bit DCS_EN = 1; see Table 20), the circuit can handle signals with duty cycles of between
30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN = 0), the
input clock signal should have a duty cycle of between 45 % and 55 %.
Table 12.
Duty cycle stabilizer
DCS_enable SPI
Description
0
duty cycle stabilizer disable
1
duty cycle stabilizer enable
14.4 Digital outputs
14.4.1 Serial output equivalent circuit
The JESD204A standard specify that in case of connecting the receiver and the
transmitter in DC coupling, both of them need to be provided by the same supply.
VDDD
50 Ω
CMLPA/CLMPB
100 Ω
RECEIVER
CMLNA/CLMNB
+
−
12 mA to 26 mA
AGND
005aaa082
Fig 19. CML output connection to the receiver in DC coupling
The output should be terminated when 100 Ω (typical) has been reached at the receiver
side.
ADC1213D_SER_5
Preliminary data sheet
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© NXP B.V. 2010. All rights reserved.
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ADC1213D series
NXP Semiconductors
ADC1213D series
VDDD
50 Ω
CMLPA/CMLPB
10 nF
CMLNA/CMLNB
−
+
100 Ω
RECEIVER
10 nF
12 mA to 26 mA
005aaa083
Fig 20. CML output connection to the receiver in AC coupling
14.5 JESD204A serializer
14.5.1 Digital JESD204A formatter
The block placed after the ADC cores is used to implement all functionalities of the
JESD204A standard. This ensures signal integrity and guarantees the clock and the data
recovery at the receiver side.
The block is highly parameterized and can be configured in various ways depending on
the sampling frequency and the number of lanes used.
M CONVERTERS
N bits from Cr0 +
CS bits for control
L LANES
F octets
TX transport layer
FRAME
TO
OCTETS
SCRAMBLER
ALIGNMENT
CHARACTER
GENERATOR
8-bit/
10-bit
SER
LANE0
8-bit/
10-bit
SER
LANE1
TX CONTROLLER
SYNC~
samples stream to
lane stream mapping
N bits from CrM−1 +
CS bits for control
N' = N+CS
S samples per frame cycle
F octets
FRAME
TO
OCTETS
SCRAMBLER
ALIGNMENT
CHARACTER
GENERATOR
CF: position of controls bits
HD: frame boundary break
Padding with Tails bits (TT)
Mx(N'xS) bits
Lx(F) octets
L octets
005aaa084
Fig 21. General overview of the JESD204A serializer
ADC1213D_SER_5
Preliminary data sheet
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© NXP B.V. 2010. All rights reserved.
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ADC1213D series
NXP Semiconductors
ADC1213D series
ADC_MODE[1:0]
PRBS
DUMMY
SCRAMB_IN_MODE[1:0]
11
12 + 1
10
12 + 1
N
&
CS
LANE_MODE[1:0]
8
N + CS
ADC_PD
ADCA
PLL
AND
DLL
ADCB
frame CLK
×F
char CLK
12 + 1
01
10
00
'0'
01
'0/1'
10
PRBS
11
SWING_SEL[2:0]
bit CLK
PRBS
11
'0/1'
10
'0'
01
SER
00
PRBS
PRBS
SER
FSM (f assy,
char repl, ILA,
test mode)
FRAME
ASSEMBLY
ADC_D
DUMMY
LANE_POLARITY
00
×1
× 10F
8-bit/
10-bit
SCR
PRBS
12 + 1
00
12 + 1 10
12 + 1
N
&
CS
LANE_POLARITY
01
8-bit/
10-bit
SCR
N + CS
8
10
00
00
LANE_MODE[1:0]
11
SCAMB_IN_MODE[1:0]
ADC_MODE[1:0]
sync_request
005aaa175
Fig 22. Detailed view of the JESD204A serializer with debug functionality
14.5.2 ADC core output codes versus input voltage
Table 13 shows the data output codes for a given analog input voltage.
Table 13.
ADC1213D_SER_5
Preliminary data sheet
Output codes versus input voltage
INP-INM (V)
Offset binary
Two’s complement
OTR
< −1
0000 0000 0000
1000 0000 0000
1
−1.0000000
0000 0000 0000
1000 0000 0000
0
−0.9995117
0000 0000 0001
1000 0000 0001
0
−0.9990234
0000 0000 0010
1000 0000 0010
0
−0.9985352
0000 0000 0011
1000 0000 0011
0
−0.9980469
0000 0000 0100
1000 0000 0100
0
....
....
....
0
−0.0009766
0111 1111 1110
1111 1111 1110
0
−0.0004883
0111 1111 1111
1111 1111 1111
0
0.0000000
1000 0000 0000
0000 0000 0000
0
+0.0004883
1000 0000 0001
0000 0000 0001
0
+0.0009766
1000 0000 0010
0000 0000 0010
0
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ADC1213D series
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ADC1213D series
Table 13.
Output codes versus input voltage …continued
INP-INM (V)
Offset binary
Two’s complement
OTR
....
....
....
0
+0.9980469
1111 1111 1011
0111 1111 1011
0
+0.9985352
1111 1111 1100
0111 1111 1100
0
+0.9990234
1111 1111 1101
0111 1111 1101
0
+0.9995117
1111 1111 1110
0111 1111 1110
0
+1.0000000
1111 1111 1111
0111 1111 1111
0
> +1
1111 1111 1111
0111 1111 1111
1
14.6 Serial Peripheral Interface (SPI)
14.6.1 Register description
The ADC1213D serial interface is a synchronous serial communications port allowing for
easy interfacing with many industry microprocessors. It provides access to the registers
that control the operation of the chip in both read and write modes.
This interface is configured as a 3-wire type (SDIO as bidirectional pin).
SCLK acts as the serial clock, and CS acts as the serial chip select bar.
Each read/write operation is sequenced by the CS signal and enabled by a LOW level to
to drive the chip with 2 bytes to 5 bytes, depending on the content of the instruction byte
(see Table 14).
Table 14.
Instruction bytes for the SPI
MSB
Bit
7
6
5
4
3
2
1
0
Description
R/W[1]
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
[1]
R/W indicates whether a read or write transfer occurs after the instruction byte
Table 15.
Description
0
Write mode operation
1
Read mode operation
Bits W1 and W0 indicate the number of bytes transferred after the instruction byte.
Table 16.
Preliminary data sheet
Read or Write mode access description
R/W[1]
[1]
ADC1213D_SER_5
LSB
Number of bytes to be transferred
W1
W0
Number of bytes
0
0
1 byte transferred
0
1
2 bytes transferred
1
0
3 bytes transferred
1
1
4 or more bytes transferred
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ADC1213D series
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ADC1213D series
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is incremented to access subsequent addresses.
The steps involved in a data transfer are as follows:
1. The falling edge on CS in combination with a rising edge on SCLK determine the start
of communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can be vary in length but will
always be a multiple of 8 bits. The MSB is always sent first (for instruction and data
bytes):
CSB
SCLK
SDIO
R/W
W1
W0
A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Instruction bytes
D7
D6
D5
D4
D3
D2
Register N (data)
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Register N + 1 (data)
005aaa086
Fig 23. Transfer diagram for two data bytes (3-wire type)
14.6.2 Channel control
The two ADC channels can be configured at the same time or separately. By using the
register “Channel index”, the user can choose which ADC channel will receive the next
SPI-instruction. By default the channel A and B will receive the same instructions in write
mode. In read mode only A is active.
ADC1213D_SER_5
Preliminary data sheet
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Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Addr
Hex
NXP Semiconductors
ADC1213D_SER_5
Preliminary data sheet
Table 17.
Register allocation map
Register name
R/W[1] Bit definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Default[2]
Bin
Bit 0
ADC control register
Rev. 05 — 23 April 2010
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0003
Channel index
R/W
RESERVED[5:0]
0005
Reset and
Operating modes
R/W
SW_
RST
0006
Clock
R/W
-
-
-
0008
Vref
R/W
-
-
-
0013
Offset
R/W
-
-
0014
Test pattern 1
R/W
-
-
0015
Test pattern 2
R/W
0016
Test pattern 3
R/W
ADCB
RESERVED[2:0]
-
-
SE_SEL
DIFF_SE
-
-
INTREF_
EN
ADCA
PD[1:0]
CLKDIV2_
SEL
0000 0000
DCS_EN
INTREF[2:0]
-
-
0000 0000
TESTPAT_1[2:0]
0000 0000
TESTPAT_2[13:6]
TESTPAT_3[5:0]
0000
000X
0000 0000
DIG_OFFSET[5:0]
-
1111 1111
0000 0000
-
-
-
0000 0000
0
0
POR_TST
RESERVED
0000 0000
FSM_SW_
RST
0
0
0
0000 0000
JESD204A control
Ser_Status
R
0802
Ser_Reset
R/W
SW_
RST
0
0
0
0803
Ser_Cfg_Setup
R/W
0
0
0
0
0805
Ser_Control1
R/W
0
TriState_
CFG_PAD
SYNC_
POL
SYNC_SING
LEENDED
1
0806
Ser_Control2
R/W
0
0
0
0
0
0808
Ser_Analog_Ctrl
R/W
0
0
0
0
0
0
Ser_ScramblerA
R/W
080A
Ser_ScramblerB
R/W
080B
Ser_PRBS_Ctrl
R/W
0820
Cfg_0_DID
R/W*
RESERVED[2:0]
CFG_SETUP[3:0]
0000 ****
RESERVED[2:0]
0
SWAP_
LANE_1_2
0100 1001
SWAP_
ADC_0_1
SWING_SEL[2:0]
0000 00**
LSB_INIT[6:0]
0000 0000
MSB_INIT[7:0]
0
0
0
0
0
1111 1111
0
PRBS_TYPE[1:0]
DID[7:0]
0821
Cfg_1_BID
R/W*
0
0
0
0
0822
Cfg_3_SCR_L
R/W*
SCR
0
0
0
0
0823
Cfg_4_F
R/W*
0
0
0
0
0
0824
Cfg_5_K
R/W*
0
0
0
0825
Cfg_6_M
R/W*
0
0
0
BID[3:0]
0
0000 0000
1110 1101
0
0000 1010
0
L
F[2:0]
0
*000 000*
0000 0***
K[4:0]
0
0000 00**
000* ****
0
M
0000 000*
ADC1213D series
25 of 41
© NXP B.V. 2010. All rights reserved.
0809
RXSYNC_
ERROR
ADC1213D series
0801
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Register allocation map …continued
R/W[1] Bit definition
Default[2]
Bin
Rev. 05 — 23 April 2010
All information provided in this document is subject to legal disclaimers.
Addr
Hex
Register name
0826
Cfg_7_CS_N
R/W*
0827
Cfg_8_Np
R
0
0
0
0828
Cfg_9_S
R/W*
0
0
0
0
0
0
0829
Cfg_10_HD_CF
R/W*
HD
0
0
0
0
0
082C
Cfg_01_2_LID
R/W*
0
0
0
082D
Cfg_02_2_LID
R/W*
0
0
0
084C
Cfg01_13_FCHK
R
FCHK[7:0]
**** ****
084D
Cfg02_13_FCHK
R
FCHK[7:0]
**** ****
0870
LaneA_0_Ctrl
R/W
0
SCR_IN_
MODE
LANE_MODE[1:0]
0
LANE_
POL
LANE_CLK_
POS_EDGE
LANE_PD
0000 000*
0871
LaneB_0_Ctrl
R/W
0
SCR_IN_
MODE
LANE_MODE[1:0]
0
LANE_
POL
LANE_CLK_
POS_EDGE
LANE_PD
0000 000*
0890
ADCA_0_Ctrl
R/W
0
0
ADC_MODE[1:0]
0
0
0
ADC_PD
0000 000*
0891
ADCB_0_Ctrl
R/W
0
0
ADC_MODE[1:0]
0
0
0
ADC_PD
0000 000*
Bit 7
0
Bit 6
Bit 5
CS[0]
0
Bit 4
Bit 3
Bit 2
Bit 1
0
NXP Semiconductors
ADC1213D_SER_5
Preliminary data sheet
Table 17.
Bit 0
N[3:0]
0100 0***
NP[4:0]
0000 1111
0
S
CF[1:0]
0000 0000
*000 0000
LID[4:0]
0001 1011
LID[4:0]
0001 1100
[1]
an "*" in the Access column means that this register is subject to control access conditions in Write mode.
[2]
an "*" in the Default column replaces a bit of which the value depends on the binary level of external pins (e.g. CFG[3:0], Swing[1:0], Scrambler).
ADC1213D series
ADC1213D series
26 of 41
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ADC1213D series
NXP Semiconductors
ADC1213D series
14.6.3 Register description
14.6.3.1
Table 18.
ADC control register
Register channel Index (address 0003h)
Bit
Symbol
Access
Value
Description
7 to 2
RESERVED[5:0]
-
111111
reserved
1
ADCB
R/W
ADCB will get the next SPI command:
0
ADCB not selected
1
0
ADCA
Table 19.
ADCB selected
R/W
ADCA will get the next SPI command:
0
ADCA not selected
1
ADCA selected
Register reset and Power-down mode (address 0005h)
Bit
Symbol
Access
7
SW_RST
R/W
Value
Description
reset digital part:
0
no reset
1
performs a reset of the digital part
6 to 4
RESERVED[2:0]
-
000
reserved
3 to 2
-
-
00
not used
1 to 0
PD[1-0]
R/W
Table 20.
power-down mode:
00
normal (power-up)
01
full power-down
10
sleep
11
normal (power-up)
Register clock (address 0006h)
Bit
Symbol
Access
Value
Description
7 to 5
-
-
000
not used
4
SE_SEL
R/W
3
DIFF_SE
select SE clock input pin:
0
Select CLKM input
1
Select CLKP input
R/W
differential/single ended clock input select:
0
1
2
-
-
1
CLKDIV2_SEL
R/W
0
1
DCS_EN
ADC1213D_SER_5
Preliminary data sheet
Single-ended
not used
select clock input divider by 2:
0
0
Fully differential
R/W
disable
active
duty cycle stabilizer enable:
0
disable
1
active
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Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
27 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
Table 21.
Register Vref (address 0008h)
Bit
Symbol
Access
Value
Description
7 to 4
-
-
0000
not used
3
INTREF_EN
R/W
2 to 0
INTREF[2:0]
Table 22.
enable internal programmable VREF mode:
0
disable
1
active
R/W
programmable internal reference:
000
0 dB (FS=2 V)
001
−1 dB (FS=1.78 V)
010
−2 dB (FS=1.59 V)
011
−3 dB (FS=1.42 V)
100
−4 dB (FS=1.26 V)
101
−5 dB (FS=1.12 V)
110
−6 dB (FS=1 V)
111
not used
Digital offset adjustment (address 0013h)
Register offset: (address 0013h)
Decimal
DIG_OFFSET[5:0]
+31
011111
+31 LSB
...
...
...
0
000000
0
...
...
...
−32
100000
−32 LSB
Table 23.
Register test pattern 1 (address 0014h)
Bit
Symbol
Access
Value
Description
7 to 3
-
-
00000
not used
2 to 0
TESTPAT_1[2:0]
R/W
Table 24.
digital test pattern:
000
off
001
mid-scale
010
− FS
011
+ FS
100
toggle ‘1111..1111’/’0000..0000’
101
custom test pattern, to be written in register 0015h and 0016h
110
‘010101...’
111
‘101010...’
Register test pattern 2 (address 0015h)
Bit
Symbol
Access
Value
7 to 0
TESTPAT_2[13:6]
R/W
00000000 custom digital test pattern (bit 13 to 6)
ADC1213D_SER_5
Preliminary data sheet
Description
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Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
28 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
Table 25.
Register test pattern 3 (address 0016h)
Bit
Symbol
Access
Value
Description
7 to 3
TESTPAT_3[5:0]
R/W
00000
custom digital test pattern (bit 5 to 0)
2 to 0
-
-
000
not used
14.6.4 JESD204A digital control registers
Table 26.
SER status (address 0801h)
Bit
Symbol
Access
Value
Description
7
RXSYNC_ERROR
R/W
0
set to 1 when a synchronization error occurs
6 to 4
RESERVED[2:0]
-
010
reserved
3 to 2
-
-
0
not used
1
POR_TST
R
1
power-on-reset
0
RESERVED
-
-
reserved
Table 27.
SER reset (address 0802h)
Bit
Symbol
Access
Value
Description
7
SW_RST
R/W
0
initiates a software reset of the JEDEC204A unit
6 to 4
-
-
000
not used
3
FSM_SW_RST
R/W
0
initiates a software reset of the internal state machine of JEDEC204A
unit
2 to 0
-
-
000
not used
ADC1213D_SER_5
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
29 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
Table 28.
SER cfg set-up (address 0803h)[1]
Bit
Symbol
Access
Value
Description
7 to 4
-
R
0000
not used
3 to 0
CFG_SETUP[3:0]
R/W
0000
(reset)
defines quick JESD204A configuration. These settings overrule the
CFG_PAD configuration
0000
ADC0: ON; ADC1: ON; Lane0: ON; Lane1: ON; F = 2; HD = 0; K = 9;
M = 2; L = 2[2]
0001
ADC0: ON; ADC1: ON; Lane0: ON; Lane1: OFF; F = 4; HD = 0; K = 5;
M = 2; L = 1[2]
0010
ADC0: ON; ADC1: ON; Lane0: OFF[2]
0011
ADC0: ON; ADC1: OFF; Lane0: ON; Lane1: ON; F = 1; HD = 1; K = 17;
M = 1; L = 2[2]
0100
ADC0: OFF; ADC1: ON; Lane0: ON; Lane1: ON; F = 1; HD = 1; K = 17;
M = 1; L = 2; SWAP_ADC_0_1 = 1[2]
0101
ADC0: ON; ADC1: OFF; Lane0: ON; Lane1: OFF; F = 2; HD = 0; K = 9;
M = 1; L = 1[2]
0110
ADC0: ON; ADC1: OFF; Lane0: OFF; Lane1: ON; F = 2; HD = 0; K = 9;
M = 1; L = 1; SWAP_LANE_1_2 = 1[2]
0111
ADC0: OFF; ADC1: ON; Lane0: ON; Lane1: OFF; F = 2; HD = 0; K = 9;
M = 1; L = 1; SWAP_ADC_0_1 = 1[2]
1000
ADC0: OFF; ADC1: ON; Lane0: OFF; Lane1: ON; F = 2; HD = 0; K = 9;
M = 1; L = 1; SWAP_ADC_0_1[2]
1001 to
1101
reserved
1110
ADC0: OFF; ADC1: OFF; Lane0: ON; Lane1: ON; F = 2; HD = 0; K = 9;
M = 2; L = 2; loop alignment = 1[2]
1111
ADC0: OFF; ADC1: OFF; Lane0: OFF; Lane1: OFF; F = 2; HD = 0;
K = 9; M = 2; L = 2 → PD[2]
[1]
The default value for this register depends on the external pull-up/pull-down on CFG0, CFG1, CFG2 or CFG3. Writing to the register
overwrites this value.
[2]
F: number of byte per frame; HD: High density; K: number of frames per multi frame; M: number of converters; L: number of lanes
See the information about the JESD204A standard on the JEDEC web site.
Table 29.
SER control1 (address 0805h)
Bit
Symbol
Access
Value
Description
7
-
R
0
not used
6
TRISTATE_CFG_PAD
R/W
1
5
SYNC_POL
R/W
4
3
defines the sync signal polarity:
0
synchronization signal is active low
1
synchronization signal is active high
SYNC_SINGLE_ENDED R/W
-
ADC1213D_SER_5
Preliminary data sheet
R
CFG pads (3 to 0) are set to high-impedance. Switch to 0
automatically after start-up or reset.
defines the input mode of the sync signal:
0
synchronization input mode is set in Differential mode
1
synchronization input mode is set in Single-ended mode
1
not used
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
30 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
Table 29.
SER control1 (address 0805h) …continued
Bit
Symbol
Access
2
REV_SCR
-
Value
Description
enables swapping bits at the scrambler input
0
1
1
REV_ENCODER
LSB are swapped to MSB at the scrambler input
-
enables swapping bits at the 8b/10b encoder input:
0
1
0
REV_SERIAL
LSB are swapped to MSB at the 8b/10b encoder input
-
enables swapping bits at the lane input (before serializer):
0
1
Table 30.
LSB are swapped to MSB at the lane input
SER control2 (address 0806h)
Bit
Symbol
Access
Value
7 to 2
1
-
R
000000
SWAP_LANE_1_2
R/W
Description
not used
controls the JESD204A output multiplexer:
0
1
0
SWAP_ADC_0_1
outputs of the JESD204A unit are swapped. (Output0 is
connected to Lane1, Output1 is connected to Lane0)
R/W
controls the JESD204A input multiplexer:
0
1
Table 31.
inputs of the JESD204A unit are swapped. (ADC0 output is
connected to Input1, ADC1 is connected to Input0)
SER analog ctrl (address 0808h)
Bit
Symbol
Access
Value
Description
7 to 3
-
R
00000
not used
2 to 0
SWING_SEL[2:0]
R/W
0**
defines the swing output for the lane pads
Table 32.
SER scramblerA (address 0809h)
Bit
Symbol
Access
Value
Description
7
-
R
0
not used
6 to 0
LSB_INIT[6:0]
R/W
0000000
defines the initialization vector for the scrambler polynomial
(lower)
Table 33.
SER scramblerB (address 080Ah)
Bit
Symbol
Access
Value
Description
7 to 0
MSB_INIT[7:0]
R/W
11111111
defines the initialization vector for the scrambler polynomial
(upper)
ADC1213D_SER_5
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
31 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
Table 34.
SER PRBS Ctrl (address 080Bh)
Bit
Symbol
Access
Value
Description
7 to 2
-
R
000000
not used
1 to 0
PRBS_TYPE[1:0]
R/W
Table 35.
defines the type of Pseudo-Random Binary Sequence (PRBS)
generator to be used:
00 (reset)
PRBS-7
01
PRBS-7
10
PRBS-23
11
PRBS-31
Cfg_0_DID (address 0820h)
Bit
Symbol
Access
Value
7 to 0
DID[7:0]
R
11101101 defines the device (= link) identification number
Table 36.
Description
Cfg_1_BID (address 0821h)
Bit
Symbol
Access
Value
Description
7 to 4
-
R
0000
not used
3 to 0
BID[3:0]
R/W
1010
defines the bank ID – extension to DID
Table 37.
Cfg_3_SCR_L (address 0822h)
Bit
Symbol
Access
Value
Description
7
SCR
R/W
*
scrambling enabled
6 to 1
-
R
000000
not used
0
L
R/W
*
defines the number of lanes per converter device, minus 1
Description
Table 38.
Cfg_4_F (address 0823h)
Bit
Symbol
Access
Value
7 to 3
-
R
00000
not used
2 to 0
F[2:0]
R/W
***
defines the number of octets per frame, minus 1
Value
Description
Table 39.
Bit
Cfg_5_K (address 0824h)
Symbol
Access
7 to 5
-
R
000
not used
4 to 0
K[4:0]
R/W
*****
defines the number of frames per multiframe, minus 1
Description
Table 40.
Cfg_6_M (address 0825h)
Bit
Symbol
Access
Value
7 to 1
-
R
0000000
not used
0
M
R/W
*
defines the number of converters per device, minus 1
ADC1213D_SER_5
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
32 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
Table 41.
Cfg_7_CS_N (address 0826h)
Bit
Symbol
Access
Value
Description
7
-
R
0
not used
6
CS[0]
R/W
*
defines the number of control bits per sample, minus 1
5 to 4
-
R
00
not used
3 to 0
N[3:0]
R/W
****
defines the converter resolution
Table 42.
Cfg_8_Np (address 0827h)
Bit
Symbol
Access
Value
Description
7 to 5
-
R
000
not used
4 to 0
NP[4:0]
R/W
*****
defines the total number of bits per sample, minus 1
Table 43.
Cfg_9_S (address 0828h)
Bit
Symbol
Access
Value
Description
7 to 1
-
R
0000000
not used
0
S
R/W
1
defines number of samples per converter per frame cycle
Table 44.
Cfg_10_HD_CF (address 0829h)
Bit
Symbol
Access
Value
Description
7
HD
R/W
*
defines high density format
6 to 2
-
R
00000
not used
1 to 0
CF[1:0]
R/W
**
defines number of control words per frame clock cycle per link.
Table 45.
Cfg01_2_LID (address 082Ch)
Bit
Symbol
Access
Value
Description
7 to 5
-
R
000
not used
4 to 0
LID[4:0]
R/W
11011
defines lane1 identification number
Table 46.
Cfg02_2_LID (address 082Dh)
Bit
Symbol
Access
Value
Description
7 to 5
-
R
000
not used
4 to 0
LID[4:0]
R/W
11100
defines lane2 identification number
Table 47.
Cfg02_13_fchk (address 084Ch)
Bit
Symbol
Access
Value
Description
7 to 0
FCHK[7:0]
R
********
defines the checksum value for lane1
checksum corresponds to the sum of all the link configuration
parameters modulo 256 (as defined in JEDEC Standard
No.204A)
ADC1213D_SER_5
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
33 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
Table 48.
Cfg01_13_fchk (address 084Dh)
Bit
Symbol
Access
Value
Description
7 to 0
FCHK[7:0]
R
********
defines the checksum value for lane1
checksum corresponds to the sum of all the link configuration
parameters module 256 (as defined in JEDEC Standard
No.204A)
Table 49.
LaneA_0_ctrl (address 0870h)
Bit
Symbol
Access
Value
Description
7
-
R
0
not used
6
SCR_IN_MODE
R/W
5 to 4
LANE_MODE[1:0]
-
R
2
LANE_POL
R/W
0
0 (reset)
(normal mode) = Input of the scrambler and 8-bit/10-bit units is
the output of the frame assembly unit.
1
input of the scrambler and 8-bit/10-bit units is the PRSB
generator (PRBS type is defined with “PRBS_TYPE”
(Ser_PRBS_ctrl register)
R/W
3
1
defines the input type for scrambler and 8-bit/10-bit units:
defines output type of Lane output unit:
00 (reset)
normal mode: Lane output is the 8-bit/10-bit output unit
01
constant mode: Lane output is set to a constant (0 × 0)
10
toggle mode: Lane output is toggling between 0 × 0 and 0 × 1
11
PRBS mode: Lane output is the PRBS generator (PRBS type is
defined with “PRBS_TYPE” (Ser_PRBS_ctrl register)
0
not used
defines lane polarity:
0
lane polarity is normal
1
lane polarity is inverted
LANE_CLK_POS_EDGE R/W
Lane_PD
Table 50.
defines lane clock polarity:
0
lane clock provided to the serializer is active on positive edge
1
lane clock provided to the serializer is active on negative edge
R/W
lane power-down control:
0
lane is operational
1
lane is in Power-down mode
LaneB_0_ctrl (address 0871h)
Bit
Symbol
Access
Value
Description
7
-
R
0
not used
6
SCR_IN_MODE
R/W
ADC1213D_SER_5
Preliminary data sheet
defines the input type for scrambler and 8b/10b units:
0 (reset)
(normal mode) = Input of the scrambler and 8b/10b units is the
output of the Frame Assembly unit.
1
input of the scrambler and 8b/10b units is the PRBS generator
(PRBS type is defined with “PRBS_TYPE” (Ser_PRBS_ctrl
register)
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Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
34 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
Table 50.
LaneB_0_ctrl (address 0871h) …continued
Bit
Symbol
Access
5 to 4
LANE_MODE[1:0]
R/W
3
-
R
2
LANE_POL
R/W
1
0
Value
defines output type of lane output unit:
00 (reset)
normal mode: Lane output is the 8b/10b output unit
01
constant mode: Lane output is set to a constant (0x0)
10
toggle mode: Lane output is toggling between 0x0 and 0x1
11
PRBS mode: Lane output is the PRSB generator (PRBS type is
defined with “PRBS_TYPE” (Ser_PRBS_ctrl register)
0
not used
defines lane polarity:
0
lane polarity is normal
1
lane polarity is inverted
LANE_CLK_POS_EDGE R/W
Lane_PD
Table 51.
Description
defines lane clock polarity:
0
lane clock provided to the serializer is active on positive edge
1
lane clock provided to the serializer is active on negative edge
R/W
lane power-down control:
0
lane is operational
1
lane is in Power-down mode
ADCA_0_ctrl (address 0890h)
Bit
Symbol
Access
Value
Description
7 to 6
-
R
00
not used
5 to 4
ADC_MODE[1:0]
R/W
3 to 1
-
R
0
ADC_PD
R/W
Table 52.
defines input type of JESD204A unit:
00 (reset)
ADC output is connected to the JESD204A input
01
not used
10
JESD204A input is fed with a dummy constant, set to: OTR = 0
and ADC[11:0] = “100110111010”
11
JESD204A is fed with a PRBS generator (PRBS type is defined
with “PRBS_TYPE” (Ser_PRBS_ctrl register)
000
not used
ADC power-down control:
0
ADC is operational
1
ADC is in Power-down mode
ADCB_0_ctrl (address 0891h)
Bit
Symbol
Access
Value
Description
7 to 6
-
R
00
not used
5 to 4
ADC_MODE[1:0]
R/W
defines input type of JESD204A unit
00 (reset) ADC output is connected to the JESD204A input
3 to 1
-
ADC1213D_SER_5
Preliminary data sheet
R
01
not used
10
JESD204A input is fed with a dummy constant, set to: OTR = 0
and ADC[11:0] = “100110111010”
11
JESD204A is fed with a PRBS generator (PRBS type is defined
with “PRBS_TYPE” (Ser_PRBS_ctrl register)
000
not used
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
35 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
Table 52.
ADCB_0_ctrl (address 0891h) …continued
Bit
Symbol
Access
0
ADC_PD
R/W
ADC1213D_SER_5
Preliminary data sheet
Value
Description
ADC power-down control:
0
ADC is operational
1
ADC is in Power-down mode
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
36 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
15. Package outline
HVQFN56: plastic thermal enhanced very thin quad flat package; no leads;
56 terminals; body 8 x 8 x 0.85 mm
A
B
D
SOT684-7
terminal 1
index area
A
E
A1
c
detail X
e1
e
1/2 e
L
15
28
14
C
C A B
C
v
w
b
y1 C
y
29
e
e2
Eh
1/2 e
1
42
terminal 1
index area
56
43
X
Dh
0
2.5
scale
Dimensions
Unit
mm
5 mm
A(1)
A1
b
max 1.00 0.05 0.30
nom 0.85 0.02 0.21
min 0.80 0.00 0.18
c
D(1)
Dh
E(1)
Eh
0.2
8.1
8.0
7.9
5.95
5.80
5.65
8.1
8.0
7.9
6.55
6.40
6.25
e
e1
0.5
6.5
e2
L
v
6.5
0.5
0.4
0.3
0.1
w
y
0.05 0.05
y1
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
References
Outline
version
IEC
JEDEC
JEITA
SOT684-7
---
MO-220
---
sot684-7_po
European
projection
Issue date
08-11-19
09-03-04
Fig 24. Package outline SOT684-7 (HVQFN56)
ADC1213D_SER_5
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
37 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
16. Revision history
Table 53.
Revision history
Document ID
Release date
Data sheet status
Change
notice
Supersedes
ADC1213D_SER_5
20100423
Preliminary data sheet
-
ADC1213D_SER_4
Modifications:
ADC1213D_SER_4
•
Product status changed from Objective to Preliminary
20100412
Objective data sheet
-
ADC1213D065_080_105_125_3
ADC1213D065_080_105_125_3 20090617
Objective data sheet
-
ADC1213D065_080_105_125_2
ADC1213D065_080_105_125_2 20090604
Objective data sheet
-
ADC1213D065_080_105_125_1
ADC1213D065_080_105_125_1 20090528
Objective data sheet
-
-
ADC1213D_SER_5
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
38 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
ADC1213D_SER_5
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
39 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
ADC1213D_SER_5
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
40 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
19. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
6.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8
Thermal characteristics . . . . . . . . . . . . . . . . . . 5
9
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
11
Clock and digital output timing . . . . . . . . . . . 11
12
Serial output timings . . . . . . . . . . . . . . . . . . . 12
13
SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
14
Application information. . . . . . . . . . . . . . . . . . 13
14.1
Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 13
14.1.1
Input stage description . . . . . . . . . . . . . . . . . . 13
14.1.2
Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 14
14.1.3
Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 15
14.2
System reference and power management . . 16
14.2.1
Internal/external reference . . . . . . . . . . . . . . . 16
14.2.2
Reference gain control . . . . . . . . . . . . . . . . . . 17
14.2.3
Common-mode output voltage (VI(cm)) . . . . . . 17
14.2.4
Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
14.3
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
14.3.1
Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 18
14.3.2
Equivalent input circuit . . . . . . . . . . . . . . . . . . 19
14.3.3
Clock input divider . . . . . . . . . . . . . . . . . . . . . 20
14.3.4
Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 20
14.4
Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 20
14.4.1
Serial output equivalent circuit . . . . . . . . . . . . 20
14.5
JESD204A serializer. . . . . . . . . . . . . . . . . . . . 21
14.5.1
Digital JESD204A formatter . . . . . . . . . . . . . . 21
14.5.2
ADC core output codes versus input voltage . 22
14.6
Serial Peripheral Interface (SPI) . . . . . . . . . . . 23
14.6.1
Register description . . . . . . . . . . . . . . . . . . . . 23
14.6.2
Channel control . . . . . . . . . . . . . . . . . . . . . . . 24
14.6.3
Register description . . . . . . . . . . . . . . . . . . . . 27
14.6.3.1 ADC control register . . . . . . . . . . . . . . . . . . . . 27
14.6.4
JESD204A digital control registers . . . . . . . . . 29
15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 37
16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 38
17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 39
17.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 39
17.2
17.3
17.4
18
19
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
39
40
40
41
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 23 April 2010
Document identifier: ADC1213D_SER_5
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