DS90CR286A/DS90CR216A +3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link— 66 MHz, +3.3V Rising Edge Strobe LVDS Receiver 21-Bit Channel Link— 66 MHz General Description Features The DS90CR286A receiver converts the four LVDS data streams (Up to 1.848 Gbps throughput or 231 Megabytes/ sec bandwidth) back into parallel 28 bits of CMOS/TTL data. Also available is the DS90CR216A that converts the three LVDS data streams (Up to 1.386 Gbps throughput or 173 Megabytes/sec bandwidth) back into parallel 21 bits of CMOS/TTL data. Both Receivers’ outputs are Rising edge strobe. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. n n n n n n n n n n 20 to 66 MHz shift clock support 50% duty cycle on receiver output clock Best–in–Class Set & Hold Times on RxOUTPUTs Rx power consumption < 270 mW (typ) @66MHz Worst Case Rx Power-down mode < 200µW (max) ESD rating > 7 kV (HBM), > 700V (EIAJ) PLL requires no external components Compatible with TIA/EIA-644 LVDS standard Low profile 56-lead or 48-lead TSSOP package Operating Temperature: −40˚C to +85˚C Block Diagrams DS90CR286A DS90CR216A DS100873-31 Order Number DS90CR216AMTD See NS Package Number MTD48 DS100873-30 Order Number DS90CR286AMTD See NS Package Number MTD56 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2000 National Semiconductor Corporation DS100873 www.national.com DS90CR286A/DS90CR216A +3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link — 66 MHz, +3.3V Rising Edge Data Strobe LVDS Receiver 21-Bit Channel Link— 66 MHz June 1999 DS90CR286A/DS90CR216A Absolute Maximum Ratings (Note 1) Package Derating: DS90CR286A DS90CR216A ESD Rating (HBM, 1.5 kΩ, 100 pF) (EIAJ, 0Ω, 200 pF) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) −0.3V to +4V CMOS/TTL Output Voltage −0.3V to (VCC + 0.3V) LVDS Receiver Input Voltage −0.3V to (VCC + 0.3V) Junction Temperature +150˚C Storage Temperature −65˚C to +150˚C Lead Temperature (Soldering, 4 sec) +260˚C Maximum Package Power Dissipation Capacity @ 25˚C MTD56 (TSSOP) Package: DS90CR286A 1.61 W MTD48 (TSSOP) Package: DS90CR216A 1.89 W 12.4 mW/˚C above +25˚C 15 mW/˚C above +25˚C > 7 kV > 700V Recommended Operating Conditions Supply Voltage (VCC) Operating Free Air Temperature (TA) Receiver Input Range Supply Noise Voltage (VCC) Min 3.0 Nom 3.3 Max 3.6 −40 0 +25 +85 2.4 100 Units V ˚C V mVPP Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units CMOS/TTL DC SPECIFICATIONS VOH High Level Output Voltage IOH = −0.4 mA VOL Low Level Output Voltage IOL = 2 mA 0.06 0.3 V IOS Output Short Circuit Current VOUT = 0V −60 −120 mA 2.7 3.3 V LVDS RECEIVER DC SPECIFICATIONS VTH Differential Input High Threshold VTL Differential Input Low Threshold I IN Input Current V CM = +1.2V +100 −100 V IN = +2.4V, VCC = 3.6V V IN = 0V, VCC = 3.6V mV mV ± 10 ± 10 µA µA RECEIVER SUPPLY CURRENT ICCRW ICCRW ICCRW ICCRW ICCRZ Receiver Supply Current Worst Case Receiver Supply Current Worst Case Receiver Supply Current Worst Case Receiver Supply Current Worst Case CL = 8 pF, Worst Case Pattern, DS90CR286A (Figures 1, 2 ), TA=−10˚C to +70˚C f = 33 MHz 49 65 mA f = 37.5 MHz 53 70 mA f = 66 MHz 81 105 mA CL = 8 pF, Worst Case Pattern, DS90CR286A (Figures 1, 2 ), TA=−40˚C to +85˚C f = 40 MHz 53 70 mA f = 66 MHz 81 105 mA CL = 8 pF, Worst Case Pattern, DS90CR216A (Figures 1, 2 ), TA=−10˚C to +70˚C f = 33 MHz 49 55 mA f = 37.5 MHz 53 60 mA f = 66 MHz 78 90 mA CL = 8 pF, Worst Case Pattern, DS90CR216A (Figures 1, 2 ), TA=−40˚C to +85˚C f = 40 MHz 53 60 mA f = 66 MHz 78 90 mA 10 55 µA Receiver Supply Current Power Down = Low Power Down Receiver Outputs Stay Low during Power Down Mode www.national.com 2 (Continued) Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. Note 2: Typical values are given for VCC = 3.3V and TA = +25C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and ∆V OD). Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter CLHT CMOS/TTL Low-to-High Transition Time (Figure 2 ) CHLT CMOS/TTL High-to-Low Transition Time (Figure 2 ) RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 9, Figure 10) RSPos1 RSPos2 Min Typ Max Units 2 5 ns 1.8 5 ns 1.0 1.4 2.15 ns Receiver Input Strobe Position for Bit 1 4.5 5.0 5.8 ns Receiver Input Strobe Position for Bit 2 8.1 8.5 9.15 ns RSPos3 Receiver Input Strobe Position for Bit 3 11.6 11.9 12.6 ns RSPos4 Receiver Input Strobe Position for Bit 4 15.1 15.6 16.3 ns RSPos5 Receiver Input Strobe Position for Bit 5 18.8 19.2 19.9 ns RSPos6 Receiver Input Strobe Position for Bit 6 22.5 22.9 23.6 ns RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 9, Figure 10) 0.7 1.1 1.4 ns RSPos1 Receiver Input Strobe Position for Bit 1 2.9 3.3 3.6 ns RSPos2 Receiver Input Strobe Position for Bit 2 5.1 5.5 5.8 ns RSPos3 Receiver Input Strobe Position for Bit 3 7.3 7.7 8.0 ns RSPos4 Receiver Input Strobe Position for Bit 4 9.5 9.9 10.2 ns RSPos5 Receiver Input Strobe Position for Bit 5 11.7 12.1 12.4 ns RSPos6 Receiver Input Strobe Position for Bit 6 13.9 14.3 14.6 ns RSKM RxIN Skew Margin (Note 4) (Figure 11 ) RCOP f = 40 MHz f = 66 MHz f = 40 MHz 490 f = 66 MHz 400 RxCLK OUT Period (Figure 3) 15 ps ps T 50 ns RCOH RxCLK OUT High Time (Figure 3 ) 10.0 12.2 ns RCOL RxCLK OUT Low Time (Figure 3) 10.0 11.0 ns RSRC RxOUT Setup to RxCLK OUT (Figure 3 ) 6.5 11.6 ns RHRC RxOUT Hold to RxCLK OUT (Figure 3 ) 6.0 11.6 ns f = 40 MHz RCOH RxCLK OUT High Time (Figure 3 ) 5.0 7.6 ns RCOL RxCLK OUT Low Time (Figure 3) 5.0 6.3 ns RSRC RxOUT Setup to RxCLK OUT (Figure 3 ) 4.5 7.3 ns RHRC RxOUT Hold to RxCLK OUT (Figure 3 ) 4.0 6.3 RCCD RxCLK IN to RxCLK OUT Delay 25˚C, VCC = 3.3V (Note 5)(Figure 4 ) 3.5 5.0 f = 66 MHz ns 7.5 ns RPLLS Receiver Phase Lock Loop Set (Figure 5 ) 10 ms RPDD Receiver Power Down Delay (Figure 8 ) 1 µs Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 250 ps). Note 5: Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency for the 215/285 transmitter and 216A/286A receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period. 3 www.national.com DS90CR286A/DS90CR216A Electrical Characteristics DS90CR286A/DS90CR216A AC Timing Diagrams DS100873-2 FIGURE 1. “Worst Case” Test Pattern DS100873-4 FIGURE 2. DS90CR286A/DS90CR216A (Receiver) CMOS/TTL Output Load and Transition Times DS100873-5 FIGURE 3. DS90CR286A/DS90CR216A (Receiver) Setup/Hold and High/Low Times DS100873-6 FIGURE 4. DS90CR286A/DS90CR216A (Receiver) Clock In to Clock Out Delay www.national.com 4 DS90CR286A/DS90CR216A AC Timing Diagrams (Continued) DS100873-7 FIGURE 5. DS90CR286A/DS90CR216A (Receiver) Phase Lock Loop Set Time DS100873-9 FIGURE 6. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CR286A DS100873-10 FIGURE 7. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CR216A 5 www.national.com DS90CR286A/DS90CR216A AC Timing Diagrams (Continued) DS100873-8 FIGURE 8. DS90CR286A/DS90CR216A (Receiver) Power Down Delay DS100873-25 FIGURE 9. DS90CR286A (Receiver) LVDS Input Strobe Position www.national.com 6 DS90CR286A/DS90CR216A AC Timing Diagrams (Continued) DS100873-26 FIGURE 10. DS90CR216A (Receiver) LVDS Input Strobe Position 7 www.national.com DS90CR286A/DS90CR216A AC Timing Diagrams (Continued) DS100873-11 C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos — Transmitter output pulse position (min and max) RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 6) + ISI (Inter-symbol interference) (Note 7) Cable Skew — typically 10 ps–40 ps per foot, media dependent Note 6: Cycle-to-cycle jitter is less than TBD ps at 66 MHz. Note 7: ISI is dependent on interconnect length; may be zero. FIGURE 11. Receiver LVDS Input Skew Margin www.national.com 8 I/O No. RxIN+ Pin Name I 4 Positive LVDS differentiaI data inputs. Description RxIN− I 4 Negative LVDS differential data inputs. RxOUT O 28 RxCLK IN+ I 1 Positive LVDS differential clock input. RxCLK IN− I 1 Negative LVDS differential clock input. RxCLK OUT O 1 TTL Ievel clock output. The rising edge acts as data strobe. PWR DOWN I 1 TTL level input. When asserted (low input) the receiver outputs are low. V CC I 4 Power supply pins for TTL outputs. GND I 5 Ground pins for TTL outputs. PLL V CC I 1 Power supply for PLL. PLL GND I 2 Ground pin for PLL. LVDS V CC I 1 Power supply pin for LVDS inputs. LVDS GND I 3 Ground pins for LVDS inputs. TTL level data outputs. DS90CR216A Pin Description — 21-Bit Channel Link Receiver I/O No. Description RxIN+ Pin Name I 3 Positive LVDS differentiaI data inputs. (Note 8) RxIN− I 3 Negative LVDS differential data inputs. (Note 8) RxOUT O 21 RxCLK IN+ I 1 Positive LVDS differential clock input. RxCLK IN− I 1 Negative LVDS differential clock input. RxCLK OUT O 1 TTL Ievel clock output. The rising edge acts as data strobe. PWR DOWN I 1 TTL level input. When asserted (low input) the receiver outputs are low. V CC I 4 Power supply pins for TTL outputs. GND I 5 Ground pins for TTL outputs. PLL V CC I 1 Power supply for PLL. PLL GND I 2 Ground pin for PLL. LVDS V CC I 1 Power supply pin for LVDS inputs. LVDS GND I 3 Ground pins for LVDS inputs. TTL level data outputs. Note 8: These receivers have input failsafe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under these conditions receiver inputs will be in a HIGH state. If a clock signal is present, outputs will all be HIGH; if the clock input is also floating/terminated outputs will remain in the last valid state. A floating/terminated clock input will result in a LOW clock output. 9 www.national.com DS90CR286A/DS90CR216A DS90CR286A Pin Description — 28-Bit Channel Link Receiver DS90CR286A/DS90CR216A Pin Diagram DS90CR286A DS90CR216A DS100873-13 DS100873-23 www.national.com 10 DS90CR286A/DS90CR216A Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Molded Thin Shrink Small Outline Package, JEDEC Order Number DS90CR286AMTD NS Package Number MTD56 11 www.national.com DS90CR286A/DS90CR216A +3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link — 66 MHz, +3.3V Rising Edge Data Strobe LVDS Receiver 21-Bit Channel Link— 66 MHz Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Molded Thin Shrink Small Outline Package, JEDEC Order Number DS90CR216AMTD NS Package Number MTD48 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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