AD ADSP-21366SBBC-ENG Sharc processor Datasheet

a
SHARC® Processor
ADSP-21365/ADSP-21366
Preliminary Technical Data
SUMMARY
Single-Instruction Multiple-Data (SIMD) computational
architecture
On-chip memory—3M bit of on-chip SRAM and a dedicated
4M bit of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21365/6 is available with a 333 MHz core instruction rate and unique audio centric peripherals such as the
Digital Audio Interface, S/PDIF transceiver, DTCP (Digital
Content Transmission Protocol) available on the ADSP21365 only, serial ports, 8-channel asynchronous sample
rate converter, precision clock generators and more. For
complete ordering information, see Ordering Guide on
page 51
High performance 32-bit/40-bit floating point processor
optimized for high performance automotive audio
processing
Audio decoder and post processor-algorithm support with
32-bit floating-point implementations
Non-volatile memory may be configured to support audio
decoders and post processor-algorithms like PCM, Dolby
Digital EX, Dolby Prologic IIx, DTS 96/24, Neo:6, DTS ES,
MPEG2 AAC, MPEG2 2channel, MP3, and functions like
Bass management, Delay, Speaker equalization, Graphic
equalization, and more. Decoder/post-processor algorithm combination support will vary depending upon the
chip version and the system configurations. Please visit
www.analog.com/SHARC
4 BLOCKS OF ON-CHIP MEMORY
CORE PROCESSOR
BLOCK 0
INSTRUCTION
CACHE
32 X 48-BIT
TIMER
DAG1
8X4X32
DAG2
8X4X32
SRAM
1M BIT
ADDR
PROGRAM
SEQUENCER
ROM
2M BIT
DATA
BLOCK 1
SRAM
1M BIT
ADDR
SRAM
0.5M BIT
ROM
2M BIT
DATA
BLOCK 3
ADDR
SRAM
0.5M BIT
DATA
ADDR
DATA
32
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
32
64
DM DATA BUS
64
IOA
IOD
IOA
IOD
PX REGISTER
PROCESSING
ELEMENT
(PEX)
BLOCK 2
PROCESSING
ELEMENT
(PEY)
IOP REGISTERS
(MEMORY MAPPED)
6
JTAG TEST & EMULATION
IOA
IOD
SPI
SPORTS
IDP
PCG
TIMERS
SRC
SPDIF
DTCP
IOA
IOD
SIGNAL
ROUTING
UNIT
I/O PROCESSOR
AND PERIPHERALS
S
SEE “ADSP-21365/6 MEMORY
AND I/O INTERFACE FEATURES”
SECTION FOR DETAILS
Figure 1. Functional Block Diagram – Processor Core
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel:781.329.4700
www.analog.com
Fax:781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
ADSP-21365/6
Preliminary Technical Data
KEY FEATURES – PROCESSOR CORE
At 333 MHz (3.0 ns) core instruction rate, the ADSP-21365/6
performs 2 GFLOPS/666 MMACS
3M bit on-chip SRAM (1M Bit in blocks 0 and 1, and 0.50M Bit
in blocks 2 and 3) for simultaneous access by the core processor and DMA
4M bit on-chip mask-programmable ROM (2M bit in block 0
and 2M bit in block 1)
Dual Data Address Generators (DAGs) with modulo and bitreverse addressing
Zero-overhead looping with single-cycle loop setup, providing efficient program sequencing
Single Instruction Multiple Data (SIMD) architecture
provides:
Two computational processing elements
Concurrent execution
Code compatibility with other SHARC family members at
the assembly level
Parallelism in busses and computational units allows single cycle execution (with or without SIMD) of a multiply
operation, an ALU operation, a dual memory read or
write, and an instruction fetch
Transfers between memory and core at a sustained 5.4G
bytes/s bandwidth at 333 MHz core instruction rate
INPUT/OUTPUT FEATURES
DMA Controller supports:
25 DMA channels for transfers between ADSP-21365/6 internal memory and a variety of peripherals
32-bit DMA transfers at core clock speed, in parallel with fullspeed processor execution
Asynchronous parallel port provides access to asynchronous
external memory
16 multiplexed address/data lines support 24-bit address
external address range with 8-bit data or 16-bit address
external address range with 16-bit data
55M byte per sec transfer rate
External memory access in a dedicated DMA channel
8- to 32-bit and 16- to 32-bit packing options
Programmable data cycle duration: 2 to 31 CCLK
Digital Audio Interface (DAI) includes six serial ports, two
Precision Clock Generators, an Input Data Port, three timers, an S/PDIF transceiver, a DTCP cipher (ADSP-21365
only), an 8-channel asynchronous sample rate converter,
an SPI port, and a Signal Routing Unit
Six dual data line serial ports that operate at up to 50M bits/s
on each data line — each has a clock, frame sync and two
data lines that can be configured as either a receiver or
transmitter pair
Left-justified Sample Pair and I2S Support, programmable
direction for up to 24 simultaneous receive or transmit
channels using two I2S compatible stereo devices per serial
port
TDM support for telecommunications interfaces including
128 TDM channel support for newer telephony interfaces
such as H.100/H.110
Rev. PrA |
Up to 12 TDM stream support, each with 128 channels per
frame
Companding selection on a per channel basis in TDM mode
Input data port provides an additional input path to the processor core, configurable as eight channels of serial data or
seven channels of serial data and a single channel of up to
a 20-bit wide parallel data
Signal routing unit provides configurable and flexible connections between all DAI components–six serial ports, one
SPI port, eight channels of asynchronous sample rate converters, an S/PDIF receiver/transmitter, DTCP (Digital
Content Transmission Protocol (ADSP-21365 only), three
timers, an SPI port,10 interrupts, six flag inputs, six flag
outputs, and 20 SRU I/O pins (DAI_Px)
Two Serial Peripheral Interfaces (SPI): primary on dedicated
pins, secondary on DAI pins provide:
Master or slave serial boot through primary SPI , Fullduplex operation, Master-Slave mode multi-master support, Open drain outputs, Programmable baud rates, clock
polarities and phases
3 Muxed Flag/IRQ lines
1 Muxed Flag/Timer expired line
DEDICATED AUDIO COMPONENTS
S/PDIF Compatible Digital Audio receiver/transmitter supports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards
Left-justified, I2S or right-justified serial data input with
16, 18, 20 or 24-bit word widths (transmitter)
Two channel mode and Single Channel Double Frequency
(SCDF) mode
Digital Transmission Content Protection (DTCP)—a cryptographic protocol for protecting audio content from
unauthorized copying, intercepting, and tampering
(ADSP-21365 only).
Sample Rate Converter (SRC) Contains a Serial Input Port, Deemphasis Filter, Sample Rate Converter (SRC) and Serial
Output Port providing up to -128db SNR performance
Supports Left Justified, I2S, TDM and Right Justified 24, 20,
18 and 16-bit serial formats (input)
Pulse Width Modulation provides:
16 PWM outputs configured as four groups of four outputs
Supports center-aligned or edge-aligned PWM waveforms
Can generate complementary signals on two outputs in
paired mode or independent signals in non-paired mode
ROM Based Security features include:
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multiplier/divider ratios
Dual voltage: 3.3 V I/O, 1.2 V core
Available in 136-ball Mini-BGA and 144-lead LQFP Packages
(see Ordering Guide on page 51)
Page 2 of 54 | September 2004
Preliminary Technical Data
ADSP-21365/6
GENERAL DESCRIPTION
The ADSP-21365/6 SHARC processors are members of the
SIMD SHARC family of DSPs that feature Analog Devices'
Super Harvard Architecture. The ADSP-21365/6 are source
code compatible with the ADSP-2126x, and ADSP-2116x, DSPs
as well as with first generation ADSP-2106x SHARC processors
in SISD (Single-Instruction, Single-Data) mode. The ADSP21365/6 are 32-bit/40-bit floating point processors optimized
for high performance automotive audio applications with its
large on-chip SRAM and mask-programmable ROM, multiple
internal buses to eliminate I/O bottlenecks, and an innovative
Digital Audio Interface (DAI).
As shown in the functional block diagram on page 1, the
ADSP-21365/6 uses two computational units to deliver a significant performance increase over the previous SHARC
processors on a range of signal processing algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the
ADSP-21365/6 processor achieves an instruction cycle time of
3.0 ns at 333 MHz. With its SIMD computational hardware, the
ADSP-21365/6 can perform 2 GFLOPS running at 333 MHz.
Table 1 shows performance benchmarks for the ADSP-21365/6.
Table 1. ADSP-21365/6 Benchmarks (at 333 MHz)
Benchmark Algorithm
Speed
(at 333 MHz)
1024 Point Complex FFT (Radix 4, with reversal) 27.9 µs
FIR Filter (per tap)1
1.5 ns
1
IIR Filter (per biquad)
6.0 ns
Matrix Multiply (pipelined)
[3x3] × [3x1]
13.5 ns
[4x4] × [4x1]
23.9 ns
Divide (y/×)
10.5 ns
Inverse Square Root
16.3 ns
1
Assumes two files in multichannel SIMD mode
The ADSP-21365/6 continues SHARC’s industry leading standards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.
The block diagram of the ADSP-21365/6 on page 1, illustrates
the following architectural features:
• Two processing elements, each of which comprises an
ALU, Multiplier, Shifter and Data Register File
• Data Address Generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core processor cycle
• Three Programmable Interval Timers with PWM Generation, PWM Capture/Pulse width Measurement, and
External Event Counter Capabilities
• On-Chip mask-programmable ROM (4M bit)
• 8- or 16-bit Parallel port that supports interfaces to off-chip
memory peripherals
• JTAG test access port
The block diagram of the ADSP-21365/6 on page 6, illustrates
the following architectural features:
• DMA controller
• Six full duplex serial ports
• Two SPI-compatible interface ports—primary on dedicated pins, secondary on DAI pins
• Digital Audio Interface that includes two precision clock
generators (PCG), an input data port (IDP), an S/PDIF
receiver/transmitter, eight channels asynchronous sample
rate converters, DTCP cipher, six serial ports, eight serial
interfaces, a 20-bit parallel input port, 10 interrupts, six flag
outputs, six flag inputs, three timers, and a flexible signal
routing unit (SRU) buses
Figure 2 on page 4 shows one sample configuration of a SPORT
using the precision clock generators to interface with an I2S
ADC and an I2S DAC with a much lower jitter clock than the
serial port would generate itself. Many other SRU configurations are possible.
ADSP-21365/6 FAMILY CORE ARCHITECTURE
The ADSP-21365/6 is code compatible at the assembly level
with the ADSP-2126x, ADSP-21160 and ADSP-21161, and with
the first generation ADSP-2106x SHARC processors. The
ADSP-21365/6 shares architectural features with the ADSP2126x and ADSP-2116x SIMD SHARC processors, as detailed
in the following sections.
SIMD Computational Engine
The ADSP-21365/6 contains two computational processing elements that operate as a Single-Instruction Multiple-Data
(SIMD) engine. The processing elements are referred to as PEX
and PEY and each contains an ALU, multiplier, shifter and register file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both processing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive signal processing algorithms.
Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
• On-Chip SRAM (3M bit)
Rev. PrA |
Page 3 of 54 |
September 2004
ADSP-21365/6
Preliminary Technical Data
ADSP -21365/6
CLK OU T
C LK IN
X TA L
C LOC K
2
2
3
A DD R
D ATA
RD
FLA G3-1
S C LK 0
S FS0
S D 0A
S D 0B
D A I_P 18
WE
FLA G0
CS
PA R A LLEL
POR T
R AM , ROM
BOO T R OM
I /O D EVI CE
DATA
D A I_P1
DA I_ P2
DA I_ P3
SR U
OE
WR
ADDRESS
D AC
(OPTI ONA L)
C LK
FS
S D AT
LA TCH
B OOTC FG1 -0
CONTROL
A DC
(OPTI ONA L)
C LK
FS
S D AT
A LE
AD 1 5-0
C LK _C FG1-0
SP OR T0-5
TIME R S
SPD IF
SR C
ID P
S PI
D AI _P 19
DA I_ P2 0
C LK
FS
PC GA
P CG B
DAI
R ES ET
JTA G
6
Figure 2. ADSP-21365/6 System Sample Configuration
Independent, Parallel Computation Units
Single-Cycle Fetch of Instruction and Four Operands
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all operations in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit singleprecision floating-point, 40-bit extended precision floatingpoint, and 32-bit fixed-point data formats.
The ADSP-21365/6 features an enhanced Harvard architecture
in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data
(see Figure 1 on page 1). With the ADSP-21365/6’s separate
program and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a single cycle.
Data Register File
A general-purpose data register file is contained in each processing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2136x enhanced Harvard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0-R15 and in PEY as S0-S15.
Rev. PrA |
Instruction Cache
The ADSP-21365/6 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Address Generators With Zero-Overhead Hardware
Circular Buffer Support
The ADSP-21365/6’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital
Page 4 of 54 | September 2004
Preliminary Technical Data
ADSP-21365/6
signal processing, and are commonly used in digital filters and
Fourier transforms. The two DAGs of the ADSP-21365/6 contain sufficient registers to allow the creation of up to 32 circular
buffers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implementation.
Circular buffers can start and end at any memory location.
On-Chip Memory
The ADSP-21365/6 contains three megabits of internal SRAM
and four megabits of internal mask-programmable ROM. Each
block can be configured for different combinations of code and
data storage (see Table 2). Each memory block supports singlecycle, independent accesses by the core processor and I/O processor. The ADSP-21365/6 memory architecture, in
combination with its separate on-chip buses, allow two data
transfers from the core and one from the I/O processor, in a single cycle.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the
ADSP-21365/6 can conditionally execute a multiply, an add,
and a subtract in both processing elements while branching and
fetching up to four 32-bit values from memory—all in a single
instruction.
The ADSP-21365/6’s, SRAM can be configured as a maximum
of 96K words of 32-bit data, 192K words of 16-bit data, 64K
words of 48-bit instructions (or 40-bit data), or combinations of
different word sizes up to three megabits. All of the memory can
be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit
floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.
ADSP-21365/6 MEMORY AND I/O INTERFACE
FEATURES
The ADSP-21365/6 adds the following architectural features to
the SIMD SHARC family core.
Table 2. ADSP-21365/6 Internal Memory Space
IOP Registers 0x0000 0000 - 0003 FFFF
Long Word (64 bits)
Extended Precision Normal or Normal Word (32 bits)
Instruction Word (48 bits)
Short Word (16 bits)
BLOCK 0 ROM
0x0004 0000–0x0004 7FFF
BLOCK 0 ROM
0x0008 0000–0x0008 AAAA
BLOCK 0 ROM
0x0008 0000–0x0008 FFFF
BLOCK 0 ROM
0x0010 0000–0x0011 FFFF
Reserved
0x0009 0000–0x0009 7FFF
Reserved
0x0012 0000–0x0012 FFFF
Reserved
0x0004 8000–0x0004 BFFF
BLOCK 0 RAM
0x0004 C000–0x0004 FFFF
BLOCK 0 RAM
0x0009 0000–0x0009 5555
BLOCK 0 RAM
0x0009 8000–0x0009 FFFF
BLOCK 0 RAM
0x0013 0000–0x0013 FFFF
BLOCK 1 ROM
0x0005 0000–0x0005 7FFF
BLOCK 1 ROM
0x000A 0000–0x000A AAAA
BLOCK 1 ROM
0x000A 0000– 0x000A FFFF
BLOCK 1 ROM
0x0014 0000–0x0015 FFFF
Reserved
0x000B 0000– 0x000B 7FFF
Reserved
0x0016 0000–0x0016 FFFF
Reserved
0x0005 8000–0x0005 BFFF
BLOCK 1 RAM
0x0005 C000–0x0005 FFFF
BLOCK 1 RAM
0x000B 0000–0x000B 5555
BLOCK 1 RAM
0x000B 8000–0x000B FFFF
BLOCK 1 RAM
0x0017 0000–0x0017 FFFF
BLOCK 2 RAM
0x0006 0000–0x0006 1FFF
BLOCK 2 RAM
0x000C 0000–0x000C 2AAA
BLOCK 2 RAM
0x000C 0000–0x000C 3FFF
BLOCK 2 RAM
0x0018 0000–0x0018 7FFF
Reserved
0x000C 4000– 0x000D FFFF
Reserved
0x0018 8000–0x001B FFFF
BLOCK 3 RAM
0x000E 0000–0x000E 3FFF
BLOCK 3 RAM
0x001C 0000–0x001C 7FFF
Reserved
0x000E 4000–0x000F FFFF
Reserved
0x001C 8000–0x001F FFFF
Reserved
0x0006 2000– 0x0006 FFFF
BLOCK 3 RAM
0x0007 0000–0x0007 1FFF
BLOCK 3 RAM
0x000E 0000–0x000E 2AAA
Reserved
0x0007 2000– 0x0007 FFFF
Reserved
0x0020 0000–0xFFFF FFFF
Rev. PrA |
Page 5 of 54 |
September 2004
ADSP-21365/6
Preliminary Technical Data
Using the DM bus and PM buses, with one bus dedicated to
each memory block, assures single-cycle execution with two
data transfers. In this case, the instruction must be available in
the cache.
TO PROCESSOR BUSES AND
SYSTEM MEMORY
IO ADDRESS
BUS (18)
IO DATA
BUS (32)
DMA Controller
25 CHANNELS
CONTROL/GPIO
3
16
ADDRESS/DATA BUS/ GPIO
PARALLEL PORT
PWM (16)
4
SPI PORT (1)
4
SPI PORT (1)
Programs make these connections using the Signal Routing
Unit (SRU, shown in Figure 3).
SERIAL PORTS (6)
SIGNAL ROUTING UNIT
The Digital Audio Interface (DAI) provides the ability to connect various peripherals to any of the DSPs DAI pins
(DAI_P20–1).
4
DMA CONTROLLER
IOP REGISTERS
(MEMORY MAPPED)
Digital Audio Interface (DAI)
GPIO FLAGS/IRQ/TIMEXP
CONTROL, STATUS, & DATA BUFFERS
The ADSP-21365/6’s on-chip DMA controller allows data
transfers without processor intervention. The DMA controller
operates independently and invisibly to the processor core,
allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can
occur between the ADSP-21365/6’s internal memory and its
serial ports, the SPI-compatible (Serial Peripheral Interface)
ports, the IDP (Input Data Port), the Parallel Data Acquisition
Port (PDAP) or the parallel port. Twenty-five channels of DMA
are available on the ADSP-21365/6—two for the SPI interface,
twelve via the serial ports, eight via the Input Data Port, two for
DTCP (or memory-to-memory data transfer when DTCP is not
used), and one via the processor’s parallel port. Programs can be
downloaded to the ADSP-21365/6 using DMA transfers. Other
DMA features include interrupt generation upon completion of
DMA transfers, and DMA chaining for automatic linked DMA
transfers.
INPUT
DATA PORTS (8)
DTCP CIPHER
SPDIF (RX/TX)
SRC (8 CHANNELS)
PRECISION CLOCK
GENERATORS (2)
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with nonconfigurable signal paths.
The DAI also includes six serial ports, an S/PDIF receiver/transmitter, a DTCP cipher (ADSP-21365 only), a precision clock
generator (PCG), eight channels of asynchronous sample rate
converters, an input data port (IDP), an SPI port, six flag outputs and six flag inputs, and three timers. The IDP provides an
additional input path to the ADSP-21365/6 core, configurable
as either eight channels of I2S serial data or as seven channels
plus a single 20-bit wide synchronous parallel data acquisition
port. Each data channel has its own DMA channel that is independent from the ADSP-21365/6's serial ports.
3
TIMERS (3)
DIGITAL AUDIO INTERFACE
I/O PROCESSOR
Figure 3. ADSP-21365/6 I/O Processor and Peripherals Block Diagram
Serial ports are enabled via 12 programmable and simultaneous
receive or transmit pins that support up to 24 transmit or 24
receive channels of audio data when all six SPORTS are enabled,
or six full duplex TDM streams of 128 channels per frame.
For complete information on using the DAI, see the ADSP2136x SHARC Processor Hardware Reference.
The serial ports operate at a maximum data rate of 50M bits/s.
Serial port data can be automatically transferred to and from
on-chip memory via dedicated DMA channels. Each of the
serial ports can work in conjunction with another serial port to
provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals.
The frame sync and clock are shared.
Serial Ports
Serial ports operate in four modes:
The ADSP-21365/6 features six synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog devices AD183x
family of audio codecs, ADCs, and DACs. The serial ports are
made up of two data lines, a clock and frame sync. The data
lines can be programmed to either transmit or receive and each
data line has a dedicated DMA channel.
Rev. PrA |
• Standard DSP serial mode
• Multichannel (TDM) mode
• I2S mode
• Left-justified sample pair mode
Page 6 of 54 | September 2004
20
Preliminary Technical Data
ADSP-21365/6
Left-justified sample pair mode is a mode where in each frame
sync cycle two samples of data are transmitted/received—one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over various attributes of this mode.
Each of the serial ports supports the left-justified sample pair
and I2S protocols (I2S is an industry standard interface commonly used by audio codecs, ADCs and DACs such as the
Analog Devices AD183x family), with two data pins, allowing
four left-justified sample pair or I2S channels (using two stereo
devices) per serial port, with a maximum of up to 24 I2S channels. The serial ports permit little-endian or big-endian
transmission formats and word lengths selectable from 3 bits to
32 bits. For the left-justified sample pair and I2S modes, dataword lengths are selectable between 8 bits and 32 bits. Serial
ports offer selectable synchronization and transmit modes as
well as optional µ-law or A-law companding selection on a per
channel basis. Serial port clocks and frame syncs can be internally or externally generated.
Parallel Port
The Parallel Port provides interfaces to SRAM and peripheral
devices. The multiplexed address and data pins (AD15–0) can
access 8-bit devices with up to 24 bits of address, or 16-bit
devices with up to 16 bits of address. In either mode, 8- or 16bit, the maximum data transfer rate is 55M bytes/sec.
DMA transfers are used to move data to and from internal
memory. Access to the core is also facilitated through the parallel port register read/write functions. The RD, WR, and ALE
(Address Latch Enable) pins are the control pins for the parallel
port.
Serial Peripheral (Compatible) Interface
The ADSP-21365 SHARC processor contains two Serial Peripheral Interface ports (SPIs). The SPI is an industry standard
synchronous serial link, enabling the ADSP-21365/6 SPI compatible port to communicate with other SPI compatible devices.
The SPI consists of two data pins, one device select pin, and one
clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. The SPI port can operate
in a multimaster environment by interfacing with up to four
other SPI compatible devices, either acting as a master or slave
device. The ADSP-21365/6 SPI compatible peripheral implementation also features programmable baud rate and clock
phase and polarities. The ADSP-21365/6 SPI compatible port
uses open drain drivers to support a multimaster configuration
and to avoid data contention.
S/PDIF Compatible Digital Audio Receiver/Transmitter
and Synchronous/Asynchronous Sample Rate Converter
The S/PDIF transmitter has no separate DMA channels. It
receives audio data in serial format and converts it into a
biphase encoded signal. The serial data input to the transmitter
can be formatted as left justified, I2S or right justified with word
widths of 16, 18, 20, or 24 bits.
Rev. PrA |
Page 7 of 54 |
The serial data, clock, and frame sync inputs to the S/PDIF
transmitter are routed through the Signal Routing Unit (SRU).
They can come from a variety of sources such as the SPORTs,
external pins, the precision clock generators (PCGs), or the
sample rate converters (SRC) and are controlled by the SRU
control registers.
The sample rate converter (SRC) contains four SRC blocks and
is the same core as that used in the AD1896 192 kHz Stereo
Asynchronous Sample Rate Converter and provides up to
128dB SNR. The SRC block is used to perform synchronous or
asynchronous sample rate conversion across independent stereo
channels, without using internal processor resources. The four
SRC blocks can also be configured to operate together to convert multichannel audio data without phase mismatches.
Finally, the SRC is used to clean up audio data from jittery clock
sources such as the S/PDIF receiver.
Digital Transmission Content Protection
The DTCP specification defines a cryptographic protocol for
protecting audio entertainment content from illegal copying,
intercepting and tampering as it traverses high performance
digital buses, such as the IEEE 1394 standard. Only legitimate
entertainment content delivered to a source device via another
approved copy protection system (such as the DVD Content
Scrambling System) will be protected by this copy protection
system. This feature is only available on the ADSP-21365
processor.
Pulse Width Modulation
The PWM module is a flexible, programmable, PWM waveform
generator that can be programmed to generate the required
switching patterns for various applications related to motor and
engine control or audio power control. The PWM generator can
generate either center-aligned or edge-aligned PWM waveforms. In addition, it can generate complementary signals on
two outputs in paired mode or independent signals in non
paired mode (applicable to a single group of four PWM
waveforms).
The entire PWM module has four groups of four PWM outputs
each. Therefore, this module generates 16 PWM outputs in
total. Each PWM group produces two pairs of PWM signals on
the four PWM outputs.
The PWM generator is capable of operating in two distinct
modes while generating center-aligned PWM waveforms: single
update mode or double update mode. In single update mode the
duty cycle values are programmable only once per PWM period.
This results in PWM patterns that are symmetrical about the
mid-point of the PWM period. In double update mode, a second updating of the PWM registers is implemented at the midpoint of the PWM period. In this mode, it is possible to produce
asymmetrical PWM patterns that produce lower harmonic distortion in three-phase PWM inverters.
September 2004
ADSP-21365/6
Preliminary Technical Data
Timers
The ADSP-21365/6 has a total of four timers: a core timer that
can generate periodic software interrupts and three general purpose timers that can generate periodic interrupts and be
independently set to operate in one of three modes:
• Pulse Waveform Generation mode
• Pulse Width Count /Capture mode
• External Event Watchdog mode
The core timer can be configured to use FLAG3 as a Timer
Expired signal, and each general purpose timer has one bidirectional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bit period register, and a 32-bit pulse width register. A single control and status register enables or disables all three
general purpose timers independently.
ROM Based Security
Note that the analog supply (AVDD) powers the ADSP-21365/6’s
clock generator PLL. To produce a stable clock, programs
should provide an external circuit to filter the power input to
the AVDD pin. Place the filter as close as possible to the pin. For
an example circuit, see Figure 4. To prevent noise coupling, use
a wide trace for the analog ground (AVSS) signal and install a
decoupling capacitor as close as possible to the pin. Note that
the AVSS and AVDD pins specified in Figure 4 are inputs to the
processor and not the analog ground plane on the board. For
more information, see Electrical Characteristics on page 15.
10⍀
VDDINT
AVDD
0.1␮F
0.01␮F
AVSS
Figure 4. Analog Power (AVDD) Filter Circuit
The ADSP-21365/6 has a ROM security feature that provides
hardware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
When using this feature, the processor does not boot-load any
external code, executing exclusively from internal SRAM/ROM.
Additionally, the processor is not freely accessible via the JTAG
port. Instead, a unique 64-bit key, which must be scanned in
through the JTAG or Test Access Port will be assigned to each
customer. The device will ignore a wrong key. Emulation features and external boot modes are only available after the
correct key is scanned.
Program Booting
The internal memory of the ADSP-21365/6 boots at system
power-up from an 8-bit EPROM via the parallel port, an SPI
master, an SPI slave or an internal boot. Booting is determined
by the Boot Configuration (BOOTCFG1–0) pins (see Table 6 on
page 14). Selection of the boot source is controlled via the SPI as
either a master or slave device, or it can immediately begin executing from ROM.
Phase-Locked Loop
The ADSP-21365/6 uses an on-chip Phase-Locked Loop (PLL)
to generate the internal clock for the core. On power up, the
CLKCFG1–0 pins are used to select ratios of 32:1, 16:1, and 6:1
(see Table 7 on page 14). After booting, numerous other ratios
can be selected via software control.
The ratios are made up of software configurable numerator values from 1 to 64 and software configurable divisor values of 1, 2,
4, and 8.
Power Supplies
The ADSP-21365/6 has separate power supply connections for
the internal (VDDINT), external (VDDEXT), and analog
(AVDD/AVSS) power supplies. The internal and analog supplies
must meet the 1.2V requirement. The external supply must
meet the 3.3V requirement. All external supply pins must be
connected to the same power supply.
Rev. PrA |
Target Board JTAG Emulator Connector
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21365/6
processor to monitor and control the target board processor
during emulation. Analog Devices DSP Tools product line of
JTAG emulators provides emulation at full processor speed,
allowing inspection and modification of memory, registers, and
processor stacks. The processor's JTAG interface ensures that
the emulator will not affect target system loading or timing.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appropriate “Emulator Hardware User's Guide”.
DEVELOPMENT TOOLS
The ADSP-21365/6 is supported with a complete set of
CROSSCORE® software and hardware development tools,
including Analog Devices emulators and VisualDSP++® development environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-21365/6.
The VisualDSP++ project management environment lets programmers develop and debug an application. This environment
includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The SHARC has
architectural features that improve the efficiency of compiled
C/C++ code.
The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the
Page 8 of 54 | September 2004
Preliminary Technical Data
ADSP-21365/6
designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to non intrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
• View mixed C/C++ and assembly code (interleaved source
and object information)
• Insert breakpoints
• Set conditional breakpoints on registers, memory,
and stacks
• Trace instruction execution
• Perform linear or statistical profiling of program execution
• Fill, dump, and graphically plot the contents of memory
• Perform source level debugging
VisualDSP++ Component Software Engineering (VCSE) is
Analog Devices’ technology for creating, using, and reusing
software components (independent modules of substantial
functionality) to quickly and reliably assemble software applications. Download components from the Web and drop them into
the application. Publish component archives from within
VisualDSP++. VCSE supports component implementation in
C/C++ or assembly language.
Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data
to different areas of the processor or external memory with the
drag of the mouse, examine run time stack and heap usage. The
Expert Linker is fully compatible with the existing Linker Definition File (LDF), allowing the developer to move between the
graphical and textual environments.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hardware tools include SHARC processor PC plug-in cards. Third
party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.
Designing an Emulator-Compatible DSP Board (Target)
• Create custom debugger windows
The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the SHARC development tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:
• Control how the development tools process inputs and
generate outputs
• Maintain a one-to-one correspondence with the tool’s
command line switches
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the memory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
Threads, Critical and Unscheduled regions, Semaphores,
Events, and Device flags. The VDK also supports Priority-based,
Preemptive, Cooperative, and Time-Sliced scheduling
approaches. In addition, the VDK was designed to be scalable. If
the application does not use a specific feature, the support code
for that feature is excluded from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the generation of various VDK based objects, and visualizing the
system state, when debugging an application that uses the VDK.
Rev. PrA |
Page 9 of 54 |
The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG DSP. Nonintrusive incircuit emulation is assured by the use of the processor’s JTAG
interface—the emulator does not affect target system loading or
timing. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine
registers. The processor must be halted to send data and commands, but once an operation has been completed by the
emulator, the DSP system is set running at full speed with no
impact on system timing.
To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website (www.analog.com)—
use site search on “EE-68.” This document is updated regularly
to keep pace with improvements to emulator support.
Evaluation Kit
Analog Devices offers a range of EZ-KIT Lite evaluation platforms to use as a cost effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
includes an evaluation board along with an evaluation suite of
the VisualDSP++ development and debugging environment
with the C/C++ compiler, assembler, and linker. Also included
September 2004
ADSP-21365/6
Preliminary Technical Data
are sample application programs, power supply, and a USB
cable. All evaluation versions of the software tools are limited
for use only with the EZ-KIT Lite product.
The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user’s PC, enabling the
VisualDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute,
and debug programs for the EZ-KIT Lite system. It also allows
in-circuit programming of the on-board Flash device to store
user-specific boot code, enabling the board to run as a standalone unit without being connected to the PC.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP21365/6 architecture and functionality. For detailed information on the ADSP-2136x Family core architecture and
instruction set, refer to the ADSP-2136x SHARC Processor
Hardware Reference and the ADSP-2136x SHARC Processor
Programming Reference.
With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any custom defined system. Connecting one of Analog Devices JTAG
emulators to the EZ-KIT Lite board enables high-speed, nonintrusive emulation.
Rev. PrA |
Page 10 of 54 |
September 2004
Preliminary Technical Data
ADSP-21365/6
PIN FUNCTION DESCRIPTIONS
ADSP-21365/6 pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS and TDI). Inputs
identified as asynchronous (A) can be asserted asynchronously
to CLKIN (or to TCK for TRST). Tie or pull unused inputs to
VDDEXT or GND, except for the following:
• DAI_Px, SPICLK, MISO, MOSI, EMU, TMS, TRST, TDI,
and AD15–0 (NOTE: These pins have pullup resistors.)
The following symbols appear in the Type column of Table 3:
A = Asynchronous, G = Ground, I = Input, O = Output,
P = Power Supply, S = Synchronous, (A/D) = Active Drive,
(O/D) = Open Drain, and T = Three-State , (pd) = pulldown
resistor, (pu) = pullup resistor.
Table 3. Pin Descriptions
Pin
Type
AD15–0
I/O/T
(pu)
State During and
After Reset
Three-state with
pullup enabled
RD
O
(pu)
Three-state, driven
high1
WR
O
(pu)
Three-state, driven
high1
ALE
O
(pd)
Three-state, driven
low1
FLAG3–0
I/O/A
Three-state
Function
Parallel Port Address/Data. The ADSP-21365/6 parallel port and its corresponding
DMA unit output addresses and data for peripherals on these multiplexed pins. The
multiplex state is determined by the ALE pin. The parallel port can operate in either
8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ internal pullup resistor. See Address
Data Modes on page 14 for details of the AD pin operation.
For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper
16 external address bits, A23–8; ALE is used in conjunction with an external latch to
retain the values of the A23–8.
For 16-bit mode: ALE is automatically asserted whenever a change occurs in the
address bits, A15–0; ALE is used in conjunction with an external latch to retain the
values of the A15–0. To use these pins as flags (FLAGS15–0) or PWMs (PWM15–0), 1)
set (=1) bit 20 of the SYSCTL register to disable the parallel port, 2) set (=1) bits 22–25
of the SYSCTL register to enable FLAGS in groups of four (bit 22 for FLAGS3–0, bit 23
for FLAGS7–4 etc.) or, set (=1) bits 26–29 of the SYSCTL register to enable PWMs in
groups of four (bit 26 for PWM0–3, bit 27 for PWM4–7, and so on). When used as an
input, the IDP Channel 0 can use these pins for parallel input data.
Parallel Port Read Enable. RD is asserted low whenever the processor reads 8-bit or
16-bit data from an external memory device. When AD15–0 are flags, this pin remains
deasserted. RD has a 22.5 kΩ internal pullup resistor.
Parallel Port Write Enable. WR is asserted low whenever the processor writes 8-bit or
16-bit data to an external memory device. When AD15–0 are flags, this pin remains
deasserted. WR has a 22.5 kΩ internal pullup resistor.
Parallel Port Address Latch Enable. ALE is asserted whenever the processor drives
a new address on the parallel port address pins. On reset, ALE is active high. However,
it can be reconfigured using software to be active low. When AD15–0 are flags, this
pin remains deasserted. ALE has a 20 kΩ internal pulldown resistor.
Flag Pins. Each flag pin is configured via control bits as either an input or output. As
an input, it can be tested as a condition. As an output, it can be used to signal external
peripherals. These pins can be used as an SPI interface slave select output during SPI
mastering. These pins are also multiplexed with the IRQx and the TIMEXP signals.
In SPI master boot mode, FLAG0 is the slave select pin that must be connected to an
SPI EPROM. FLAG0 is configured as a slave select during SPI master boot. When bit 16
is set (=1) in the SYSCTL register, FLAG0 is configured as IRQ0.
When bit 17 is set (=1) in the SYSCTL register, FLAG1 is configured as IRQ1.
When bit 18 is set (=1) in the SYSCTL register, FLAG2 is configured as IRQ2.
When bit 19 is set (=1) in the SYSCTL register, FLAG3 is configured as TIMEXP which
indicates that the system timer has expired.
Rev. PrA |
Page 11 of 54 |
September 2004
ADSP-21365/6
Preliminary Technical Data
Table 3. Pin Descriptions (Continued)
Pin
Type
State During and
After Reset
Three-state with
programmable
pullup
DAI_P20–1
I/O/T
(pu)
SPICLK
I/O
(pu)
Three-state with
pullup enabled
SPIDS
I
Input only
MOSI
I/O (O/D)
(pu)
Three-state with
pullup enabled
MISO
I/O (O/D)
(pu)
Three-state with
pullup enabled
BOOTCFG1–0
I
Input only
Function
Digital Audio Interface Pins. These pins provide the physical interface to the SRU.
The SRU configuration registers define the combination of on-chip peripheral inputs
or outputs connected to the pin and to the pin’s output enable. The configuration
registers of these peripherals then determines the exact behavior of the pin. Any input
or output signal present in the SRU may be routed to any of these pins. The SRU
provides the connection from the Serial ports, Input data port, precision clock generators and timers, sample rate converters and SPI to the DAI_P20–1 pins These pins
have internal 22.5 kΩ pullup resistors which are enabled on reset. These pullups can
be disabled in the DAI_PIN_PULLUP register.
Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls
the rate at which data is transferred. The master may transmit data at a variety of baud
rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active
during data transfers, only for the length of the transferred word. Slave devices ignore
the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift
out and shift in the data driven on the MISO and MOSI lines. The data is always shifted
out on one clock edge and sampled on the opposite edge of the clock. Clock polarity
and clock phase relative to data are programmable into the SPICTL control register
and define the transfer format. SPICLK has a 22.5 kΩ internal pullup resistor.
Serial Peripheral Interface Slave Device Select. An active low signal used to select
the processor as an SPI slave device. This input signal behaves like a chip select, and
is provided by the master device for the slave devices. In multimaster mode the DSPs
SPIDS signal can be driven by a slave device to signal to the processor (as SPI master)
that an error has occurred, as some other device is also trying to be the master device.
If asserted low when the device is in master mode, it is considered a multimaster error.
For a single-master, multiple-slave configuration where flag pins are used, this pin
must be tied or pulled high to VDDEXT on the master device. For ADSP-21365/6 to
ADSP-21365/6 SPI interaction, any of the master ADSP-21365/6's flag pins can be used
to drive the SPIDS signal on the ADSP-21365/6 SPI slave device.
SPI Master Out Slave In. If the ADSP-21365/6 is configured as a master, the MOSI pin
becomes a data transmit (output) pin, transmitting output data. If the ADSP-21365/6
is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving
input data. In an ADSP-21365/6 SPI interconnection, the data is shifted out from the
MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI
has a 22.5 kΩ internal pullup resistor.
SPI Master In Slave Out. If the ADSP-21365/6 is configured as a master, the MISO pin
becomes a data receive (input) pin, receiving input data. If the ADSP-21365/6 is
configured as a slave, the MISO pin becomes a data transmit (output) pin, transmitting
output data. In an ADSP-21365/6 SPI interconnection, the data is shifted out from the
MISO output pin of the slave and shifted into the MISO input pin of the master. MISO
has a 22.5 kΩ internal pullup resistor. MISO can be configured as O/D by setting the
OPD bit in the SPICTL register.
Note: Only one slave is allowed to transmit data at any given time. To enable broadcast
transmission to multiple SPI-slaves, the processor's MISO pin may be disabled by
setting (=1) bit 5 (DMISO) of the SPICTL register.
Boot Configuration Select. This pin is used to select the boot mode for the processor.
The BOOTCFG pins must be valid before reset is asserted. See Table 6 for a description
of the boot modes.
Rev. PrA |
Page 12 of 54 |
September 2004
Preliminary Technical Data
ADSP-21365/6
Table 3. Pin Descriptions (Continued)
Pin
Type
CLKIN
I
State During and
After Reset
Input only
XTAL
O
Output only2
CLKCFG1–0
I
Input only
RSTOUT/CLKOUT O
Output only
RESET
I/A
Input only
TCK
I
Input only3
TMS
I/S
(pu)
I/S
(pu)
O
I/A
(pu)
Three-state with
pullup enabled
Three-state with
pullup enabled
Three-state4
Three-state with
pullup enabled
EMU
O (O/D)
(pu)
Three-state with
pullup enabled
VDDINT
P
VDDEXT
P
AVDD
P
AVSS
GND
G
G
TDI
TDO
TRST
Function
Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21365/6 clock input.
It configures the ADSP-21365/6 to use either its internal clock generator or an external
clock source. Connecting the necessary components to CLKIN and XTAL enables the
internal clock generator. Connecting the external clock to CLKIN while leaving XTAL
unconnected configures the ADSP-21365/6 to use the external clock source such as
an external clock oscillator. The core is clocked either by the PLL output or this clock
input depending on the CLKCFG1–0 pin settings. CLKIN may not be halted, changed,
or operated below the specified frequency.
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external
crystal.
Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Table 7
for a description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL multiplier
and divider in the PMCTL register at any time after the core comes out of reset.
Local Clock Out/ Reset Out. Drives out the core reset signal to an external device.
CLKOUT can also be configured as a reset out pin.The functionality can be switched
between the PLL output clock and reset out by setting bit 12 of the PMCTREG register.
The default is reset out.
Processor Reset. Resets the ADSP-21365/6 to a known state. Upon deassertion, there
is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins
program execution from the hardware reset vector address. The RESET input must be
asserted (low) at power-up.
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the ADSP-21365/6.
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ
internal pullup resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
22.5 kΩ internal pullup resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the ADSP-21365/6. TRST has a
22.5 kΩ internal pullup resistor.
Emulation Status. Must be connected to the ADSP-21365/6 Analog Devices DSP
Tools product line of JTAG emulators target board connector only. EMU has a 22.5 kΩ
internal pullup resistor.
Core Power Supply. Nominally +1.2 V dc and supplies the processor’s core
(13 pins on the Mini-BGA package, 32 pins on the LQFP package).
I/O Power Supply. Nominally +3.3 V dc. (6 pins on the Mini-BGA package, 10 pins on
the LQFP package).
Analog Power Supply. Nominally +1.2 V dc and supplies the processor’s internal PLL
(clock generator). This pin has the same specifications as VDDINT, except that added
filtering circuitry is required. For more information, see Power Supplies on page 8.
Analog Power Supply Return.
Power Supply Return. (54 pins on the Mini-BGA package, 39 pins on the LQFP
package).
1
RD, WR, and ALE are three-stated (and not driven) only when RESET is active.
Output only is a three-state driver with its output path always enabled.
3
Input only is a three-state driver with both output path and pullup disabled.
4
Three-state is a three-state driver with pullup disabled.
2
Rev. PrA |
Page 13 of 54 |
September 2004
ADSP-21365/6
Preliminary Technical Data
ADDRESS DATA PINS AS FLAGS
BOOT MODES
To use these pins as flags (FLAGS15–0) set (=1) bit 20 of the
SYSCTL register to disable the parallel port. Then set (=1) bits
22 to 25 in the SYSCTL register accordingly.
Table 4. AD15–0 to Flag Pin Mapping
AD Pin
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Flag Pin
FLAG8
FLAG9
FLAG10
FLAG11
FLAG12
FLAG13
FLAG14
FLAG15
AD Pin
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
Flag Pin
FLAG0
FLAG1
FLAG2
FLAG3
FLAG4
FLAG5
FLAG6
FLAG7
Table 6. Boot Mode Selection
BOOTCFG1–0
00
01
10
CORE INSTRUCTION RATE TO CLKIN RATIO MODES
For details on processor timing, see Timing Specifications and
Figure 5 on page 17.
Table 7. Core Instruction Rate/ CLKIN Ratio Selection
CLKCFG1–0
00
01
10
ADDRESS DATA MODES
The following table shows the functionality of the AD pins for
8-bit and 16-bit transfers to the parallel port. For 8-bit data
transfers, ALE latches address bits A23–A8 when asserted, followed by address bits A7–A0 and data bits D7–D0 when
deasserted. For 16-bit data transfers, ALE latches address bits
A15–A0 when asserted, followed by data bits D15–D0 when
deasserted.
Table 5. Address/ Data Mode Selection
EP Data
Mode
8-bit
8-bit
16-bit
16-bit
ALE
Asserted
Deasserted
Asserted
Deasserted
AD7–0
Function
A15–8
D7–0
A7–0
D7–0
AD15–8
Function
A23–16
A7–0
A15–8
D15–8
Rev. PrA |
Booting Mode
SPI Slave Boot
SPI Master Boot
Parallel Port boot via EPROM
Page 14 of 54 |
September 2004
Core to CLKIN Ratio
6:1
32:1
16:1
Preliminary Technical Data
ADSP-21365/6
ADSP-21365/6 SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter1
K Grade
B Grade
C Grade
Min
Max
Min
Max
Min
Max
Unit
VDDINT
Internal (Core) Supply Voltage
1.14
1.26
1.14
1.26
0.95
1.05
V
AVDD
Analog (PLL) Supply Voltage
1.14
1.26
1.14
1.26
0.95
1.05
V
VDDEXT
External (I/O) Supply Voltage
3.13
3.47
3.13
3.47
3.13
3.47
V
VIH
High Level Input Voltage @ VDDEXT = max
2.0
VDDEXT + 0.5
2.0
VDDEXT + 0.5
2.0
VDDEXT + 0.5
V
VIL2
Low Level Input Voltage @ VDDEXT = min
–0.5
+0.8
–0.5
+0.8
–0.5
+0.8
V
VIH_CLKIN3
High Level Input Voltage @ VDDEXT = max
1.74
VDDEXT + 0.5
1.74
VDDEXT + 0.5
1.74
VDDEXT + 0.5
V
VIL_CLKIN
Low Level Input Voltage @ VDDEXT = min
–0.5
+1.19
–0.5
+1.19
–0.5
+1.19
V
Ambient Operating Temperature
0
+70
–40
+85
–40
+105
°C
2
4, 5
TAMB
1
Specifications subject to change without notice.
Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, TRST.
3
Applies to input pin CLKIN.
4
See Thermal Characteristics on page 44 for information on thermal specifications.
5
See Engineer-to-Engineer Note (No. TBD) for further information.
2
ELECTRICAL CHARACTERISTICS
Parameter1
VOH2
VOL2
IIH4, 5
IIL4
IILPU5
IOZH6, 7
IOZL6
IOZLPU7
IDD-INTYP8, 9
AIDD10
CIN11, 12
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
Low Level Input Current
Low Level Input Current Pullup
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current Pullup
Supply Current (Internal)
Supply Current (Analog)
Input Capacitance
Test Conditions
@ VDDEXT = min, IOH = –1.0 mA3
@ VDDEXT = min, IOL = 1.0 mA3
@ VDDEXT = max, VIN = VDDEXT max
@ VDDEXT = max, VIN = 0 V
@ VDDEXT = max, VIN = 0 V
@ VDDEXT= max, VIN = VDDEXT max
@ VDDEXT = max, VIN = 0 V
@ VDDEXT = max, VIN = 0 V
tCCLK = min, VDDINT = nom
AVDD = max
fIN=1 MHz, TCASE=25°C, VIN=1.2V
1
Min
2.4
Specifications subject to change without notice.
Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL.
3
See Output Drive Currents on page 43 for typical drive current capabilities.
4
Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.
5
Applies to input pins with 22.5 kΩ internal pullups: TRST, TMS, TDI.
6
Applies to three-statable pins: FLAG3–0.
7
Applies to three-statable pins with 22.5 kΩ pullups: AD15–0, DAI_Px, SPICLK, EMU, MISO, MOSI.
8
Typical internal current data reflects nominal operating conditions.
9
See Engineer-to-Engineer Note (No. TBD) for further information.
10
Characterized, but not tested.
11
Applies to all signal pins.
12
Guaranteed, but not tested.
2
Rev. PrA |
Page 15 of 54 |
September 2004
Max
0.4
10
10
200
10
10
200
500
10
4.7
Unit
V
V
µA
µA
µA
µA
µA
µA
mA
mA
pF
ADSP-21365/6
Preliminary Technical Data
MAXIMUM POWER DISSIPATION
The data in this table is based on theta JA (θJA) established per
JEDEC standards JESD51-2 and JESD51-6. See Engineer-toEngineer note (EE-TBD) for further information. For information on package thermal specifications, see Thermal
Characteristics on page 44.
Max Ambient
Temp1
70°C
85°C
105°C
144 INT–HS
LQFP2
3.33W
2.42W
1.21W
144 INT–HS
LQFP3
2.10W
N/A
N/A
136 MiniBGA4
2.44W
1.77W
N/A
136 MiniBGA5
2.18W
N/A
N/A
1
Power Dissipation greater than that listed above may cause permanent damage to the device.
For more information, see Thermal Characteristics on page 44.
2
Heat slug soldered to PCB
3
Heat slug not soldered to PCB
4
Thermal vias in PCB
5
No thermal vias in PCB
ABSOLUTE MAXIMUM RATINGS
Parameter
Internal (Core) Supply Voltage (VDDINT)1
Analog (PLL) Supply Voltage (AVDD)1
External (I/O) Supply Voltage (VDDEXT)1
Input Voltage–0.5 V to VDDEXT1
Output Voltage Swing–0.5 V to VDDEXT1
Load Capacitance1
Storage Temperature Range1
Junction Temperature under Bias
1
Rating
–0.3 V to +1.5 V
–0.3 V to +1.5 V
–0.3 V to +4.6 V
+ 0.5 V
+ 0.5 V
200 pF
–65°C to +150°C
125°C
Stresses greater than those listed above may cause permanent damage to the device.
These are stress ratings only; functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
ESD SENSITIVITY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADSP-21365/6 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
TIMING SPECIFICATIONS
The ADSP-21365/6’s internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor
core, serial ports, and parallel port (as required for read/write
strobes in asynchronous access mode). During reset, program
the ratio between the processor’s internal clock frequency and
external (CLKIN) clock frequency with the CLKCFG1–0 pins
(see Table 7 on page 14). To determine switching frequencies
Rev. PrA |
Page 16 of 54 |
for the serial ports, divide down the internal clock, using the
programmable divider control of each port (DIVx for the serial
ports).
The ADSP-21365/6’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the
internal clock, the processor uses an internal phase-locked loop
September 2004
Preliminary Technical Data
ADSP-21365/6
(PLL). This PLL-based clocking minimizes the skew between
the system clock (CLKIN) signal and the processor’s internal
clock (the clock source for the parallel port logic and I/O pads).
Note the definitions of various clock periods that are a function
of CLKIN and the appropriate ratio control (Table 8).
Table 8. ADSP-21365/6 CLKOUT and CCLK Clock
Generation Operation
Timing
Requirements
CLKIN
CCLK
Description
Calculation
Input Clock
Core Clock
1/tCK
1/tCCLK
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Table 9. Clock Periods
Timing
Requirements
tCK
tCCLK
tPCLK
tSCLK
tSPICLK
1
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 38 on page 43 under Test Conditions for voltage reference levels.
Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Description1
CLKIN Clock Period
(Processor) Core Clock Period
(Peripheral) Clock Period = 2 × tCCLK
Serial Port Clock Period = (tPCLK) × SR
SPI Clock Period = (tPCLK) × SPIR
where:
SR = serial port-to-core clock ratio (wide range, determined by SPORT
CLKDIV)
SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register)
DAI_Px = Serial Port Clock
SPICLK = SPI Clock
Figure 5 shows Core to CLKIN ratios of 6:1, 16:1 and 32:1 with
external oscillator or crystal. Note that more ratios are possible
and can be set through software using the power management
control register (PMCTL). For more information, see the ADSP2136x SHARC Processor Programming Reference.
CLKOUT
CLKIN
XTAL
XTAL
OSC
PLLILCLK
PLL
6:1, 16:1,
32:1
CCLK
(CORE CLOCK)
CLK-CFG [1:0]
Figure 5. Core Clock and System Clock Relationship to CLKIN
Rev. PrA |
Page 17 of 54 |
September 2004
ADSP-21365/6
Preliminary Technical Data
Power-Up Sequencing
The timing requirements for processor startup are given in
Table 10.
Table 10. Power Up Sequencing Timing Requirements (Processor Startup)
Parameter
Timing Requirements
tRSTVDD
tIVDDEVDD
tCLKVDD1
tCLKRST
tPLLRST
Min
RESET Low Before VDDINT/VDDEXT on
VDDINT on Before VDDEXT
CLKIN Valid After VDDINT/VDDEXT Valid
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
0
–50
0
102
203
Switching Characteristic
Core Reset Deasserted After RESET Deasserted
tCORERST
Max
200
200
Unit
ns
ms
ms
µs
µs
4096tCK + 2 tCCLK 4, 5
1
Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for startup time.
Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Based on CLKIN cycles
4
Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
5
The 4096 cycle count depends on tSRST specification in Table 12. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097
cycles maximum.
RESET
tRSTVDD
VDDINT
tIVDDEVDD
VDDEXT
tCLKVDD
CLKIN
tCLKRST
CLK_CFG1-0
tCORERST
tPLLRST
RSTOUT
Figure 6. Power-Up Sequencing
Rev. PrA |
Page 18 of 54 |
September 2004
Preliminary Technical Data
ADSP-21365/6
Clock Input
Table 11. Clock Input
Parameter
Min
Timing Requirements
tCK
CLKIN Period
tCKL
CLKIN Width Low
tCKH
CLKIN Width High
tCKRF
CLKIN Rise/Fall (0.4V–2.0V)
tCCLK3
CCLK Period
333 MHz
Max
181
7.51
7.51
3.01
1
Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.
Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL.
3
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.
2
tCK
CLKIN
tCKH
tCKL
Figure 7. Clock Input
Clock Signals
The ADSP-21365/6 can use an external clock or a crystal. See
the CLKIN pin description in Table 3 on page 11. The programmer can configure the ADSP-21365/6 to use its internal clock
generator by connecting the necessary components to CLKIN
and XTAL. Figure 8 shows the component connections used for
a crystal operating in fundamental mode. Note that the clock
rate is achieved using a 16.67 MHz crystal and a PLL multiplier
ratio 16:1 (CCLK:CLKIN achieves a clock speed of 266 MHz).
To achieve the full core clock rate, programs need to configure
the multiplier bits in the PMCTL register.
CLKIN
C1
1M⍀
X1
XTAL
C2
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL
SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.
Figure 8. 333 MHz Operation (Fundamental Mode Crystal)
Rev. PrA |
Page 19 of 54 |
September 2004
TBD2
TBD2
TBD2
TBD
TBD
Unit
ns
ns
ns
ns
ns
ADSP-21365/6
Preliminary Technical Data
Reset
Table 12. Reset
Parameter
Timing Requirements
tWRST1
RESET Pulse Width Low
tSRST
RESET Setup Before CLKIN Low
1
Min
Max
Unit
4tCK
8
ns
ns
Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 100 µs while RESET is low, assuming
stable VDD and CLKIN (not including start-up time of external clock oscillator).
CLKIN
tSRST
tWRST
RESET
Figure 9. Reset
Interrupts
The following timing specification applies to the FLAG0,
FLAG1, and FLAG2 pins when they are configured as IRQ0,
IRQ1, and IRQ2 interrupts.
Table 13. Interrupts
Parameter
Timing Requirement
tIPW
IRQx Pulse Width
Min
2 × tPCLK +2
DAI_P20-1
FLAG2-0
(IRQ2-0)
tIPW
Figure 10. Interrupts
Rev. PrA |
Page 20 of 54 |
September 2004
Max
Unit
ns
Preliminary Technical Data
ADSP-21365/6
Core Timer
The following timing specification applies to FLAG3 when it is
configured as the core timer (CTIMER).
Table 14. Core Timer
Parameter
Switching Characteristic
tWCTIM
CTIMER Pulse width
Min
Max
4 × tPCLK – 1
Unit
ns
tWCTIM
FLAG3
(CTIMER)
Figure 11. Core Timer
Timer PWM_OUT Cycle Timing
The following timing specification applies to Timer0, Timer1,
and Timer2 in PWM_OUT (pulse width modulation) mode.
Timer signals are routed to the DAI_P20–1 pins through the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins.
Table 15. Timer PWM_OUT Timing
Parameter
Switching Characteristic
tPWMO
Timer Pulse Width Output
Min
Max
Unit
2 tPCLK – 1
2(231 – 1) tPCLK
ns
tPWMO
DAI_P20-1
(TIMER2-0)
Figure 12. Timer PWM_OUT Timing
Rev. PrA |
Page 21 of 54 |
September 2004
ADSP-21365/6
Preliminary Technical Data
Timer WDTH_CAP Timing
The following timing specification applies to Timer0, Timer1,
and Timer2 in WDTH_CAP (pulse width count and capture)
mode. Timer signals are routed to the DAI_P20–1 pins through
the SRU. Therefore, the timing specification provided below are
valid at the DAI_P20–1 pins.
Table 16. Timer Width Capture Timing
Parameter
Timing Requirement
tPWI
Timer Pulse Width
Min
Max
Unit
2 tPCLK
2(231– 1) tPCLK
ns
tPWI
DAI_P20-1
(TIMER2-0)
Figure 13. Timer Width Capture Timing
DAI Pin to Pin Direct Routing
For direct pin connections only (for example DAI_PB01_I to
DAI_PB02_O).
Table 17. DAI Pin to Pin Routing
Parameter
Timing Requirement
tDPIO
Delay DAI Pin Input Valid to DAI Output Valid
Min
Max
Unit
1.5
10
ns
DAI_Pn
DAI_Pm
tDPIO
Figure 14. DAI Pin to Pin Direct Routing
Rev. PrA |
Page 22 of 54 |
September 2004
Preliminary Technical Data
ADSP-21365/6
inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is no timing data available. All Timing Parameters and Switching Characteristics apply to external DAI pins
(DAI_P07 – DAI_P20).
Precision Clock Generator (Direct Pin Routing)
This timing is only valid when the SRU is configured such that
the Precision Clock Generator (PCG) takes its inputs directly
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG’s
Table 18. Precision Clock Generator (Direct Pin Routing)
Parameter
Timing Requirements
tPCGIW
Input Clock Period
tSTRIG
PCG Trigger Setup Before Falling Edge of PCG Input Clock
PCG Trigger Hold After Falling Edge of PCG Input Clock
tHTRIG
Min
24
2
2
Switching Characteristics
PCG Output Clock and Frame Sync Active Edge Delay After
tDPCGIO
PCG Input Clock
tDTRIG
PCG Output Clock and Frame Sync Delay After PCG Trigger
Output Clock Period
tPCGOW
2.5
10
ns
2.5 + 2.5 × tPCGOW 10 + 2.5 × tPCGOW ns
48
tSTRIG
DAI_Pn
PCG_TRIGx_I
tPCGIW
tHTRIG
DAI_Pm
PCG_EXTx_I
(CLKIN)
tDPCGIO
DAI_Py
PCG_CLKx_O
tPCGOW
DAI_Pz
PCG_FSx_O
tDTRIG
Figure 15. Precision Clock Generator (Direct Pin Routing)
Rev. PrA |
Page 23 of 54 |
September 2004
Max
Unit
ns
ns
ADSP-21365/6
Preliminary Technical Data
Flags
The timing specifications provided below apply to the FLAG3–0
and DAI_P20–1 pins, the parallel port, and the serial peripheral
interface (SPI). See Table 3, “Pin Descriptions,” on page 11 for
more information on flag use.
Table 19. Flags
Parameter
Timing Requirement
tFIPW
FLAG3–0 IN Pulse Width
Min
Switching Characteristic
tFOPW
FLAG3–0 OUT Pulse Width
ns
2 × tPCLK – 1
ns
tFIPW
DAI_P20-1
(FLAG3-0OUT )
(AD15-0)
tFOPW
Figure 16. Flags
Page 24 of 54 |
Unit
2 × tPCLK + 3
DAI_P20-1
(FLAG3-0IN)
(AD15-0)
Rev. PrA |
Max
September 2004
Preliminary Technical Data
ADSP-21365/6
Memory Read—Parallel Port
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) when the
ADSP-21365/6 is accessing external memory space.
Table 20. 8-Bit Memory Read Cycle
Parameter
Timing Requirements
Address/Data 7–0 Setup Before RD High
tDRS
tDRH
Address/Data 7–0 Hold After RD High
tDAD
Address 15–8 to Data Valid
Min
Unit
D + tPCLK – 5
ns
ns
ns
3.3
0
Switching Characteristics
tALEW
ALE Pulse Width
2 × tPCLK – 2.0
tADAS1
Address/Data 15–0 Setup Before ALE Deasserted
tPCLK – 2.5
tRRH
Delay Between RD Rising Edge to Next Falling Edge.
H + tPCLK – 1
tALERW
ALE Deasserted to Read Asserted
2 × tPCLK – 2
Read Deasserted to ALE Asserted
F + H + 0.5
tRWALE
tADAH1
Address/Data 15–0 Hold After ALE Deasserted
tPCLK – 0.8
1
tALEHZ
ALE Deasserted to Address/Data7–0 in High Z
tPCLK – 0.8
tRW
RD Pulse Width
D–2
tRDDRV
RD Address Drive After Read High
F + H + tPCLK – 1
tADRH
Address/Data 15–8 Hold After RD High
H
D = (Data Cycle Duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × tPCLK
H = tPCLK (if a hold cycle is specified, else H = 0)
F = 7 x tPCLK (if FLASH_MODE is set else F = 0)
tPCLK = (Peripheral) Clock Period = 2 × tCCLK
1
Max
ns
ns
ns
ns
ns
tPCLK
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
tRWALE
tALERW
ALE
tALEW
tRRH
RD
tRW
tRDDRV
WR
tADAS
AD15-8
tADRH
tADAH
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
tDAD
AD7-0
VALID ADDRESS
tDRS
VALID
DATA
tALEHZ
Figure 17. Read Cycle For 8-Bit Memory Timing
Rev. PrA |
Page 25 of 54 |
September 2004
VALID
ADDRESS
tDRH
VALID
DATA
VALID
ADDRESS
ns
ns
ns
ns
ADSP-21365/6
Preliminary Technical Data
Table 21. 16-bit Memory Read Cycle
Parameter
Timing Requirements
tDRS
tDRH
Min
Address/Data 15–0 Setup Before RD High
Address/Data 15–0 Hold After RD High
3.3
0
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
t RW ALE
t ALERW
ALE
t ALEW
tRRH
RD
t RW
t RDDRV
WR
tALEHZ
t ADAS
AD15-0
t ADAH
VALID ADDRESS
t DRS
tDRH
VALID DATA
Figure 18. Read Cycle For 16-Bit Memory Timing
Rev. PrA |
Page 26 of 54 |
September 2004
Unit
ns
ns
Switching Characteristics
tALEW
ALE Pulse Width
2 × tPCLK – 2
Address/Data 15–0 Setup Before ALE Deasserted
tPCLK – 2.5
tADAS1
tALERW
ALE Deasserted to Read Asserted
2 × tPCLK – 2
tRRH
Delay Between RD Rising Edge to Next Falling Edge.
H + tPCLK – 1
tRWALE
Read Deasserted to ALE Asserted
F + H + 0.5
tRDDRV
RD Address Drive After Read High
F + H + tPCLK – 1
tADAH1
Address/Data 15–0 Hold After ALE Deasserted
tPCLK – 0.8
ALE Deasserted to Address/Data15–0 in High Z
tPCLK – 0.8
tALEHZ1
tRW
RD Pulse Width
D–2
D = (Data Cycle Duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × tPCLK
H = tPCLK (if a hold cycle is specified, else H = 0)
F = 7 x tPCLK (if FLASH_MODE is set else F = 0)
1
Max
VALID
ADDRESS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Preliminary Technical Data
ADSP-21365/6
Memory Write—Parallel Port
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) when the
ADSP-21365/6 is accessing external memory space.
Table 22. 8-bit Memory Write Cycle
Parameter
Min
Switching Characteristics:
ALE Pulse Width
2 × tPCLK – 2
tALEW
tADAS1
Address/Data 15–0 Setup Before ALE Deasserted
tPCLK – 2.5
tALERW
ALE Deasserted to Read/Write Asserted
2 × tPCLK – 2
tRWALE
Write Deasserted to ALE Asserted
H + 0.5
tWRH
Delay Between WR Rising Edge to next WR Falling Edge
F + H + tPCLK – 2
tADAH1
Address/Data 15–0 Hold After ALE Deasserted
tPCLK – 0.5
WR Pulse Width
D–F–2
tWW
tADWL
Address/Data 15–8 to WR Low
tPCLK – 1.5
tADWH
Address/Data 15–8 Hold After WR High
H
tDWS
Address/Data 7–0 Setup Before WR High
D – F + tPCLK – 4
tDWH
Address/Data 7–0 Hold After WR High
H
tDAWH
Address/Data to WR High
D – F + tPCLK – 4
D = (Data Cycle Duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × tPCLK
H = tPCLK (if a hold cycle is specified, else H = 0)
F = 7 x tPCLK (if FLASH_MODE is set else F = 0)
1
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
ALE
tALERW
tALEW
tRWALE
tWW
WR
tWRH
tADWL
tDAWH
RD
tADAS
tADAH
tADWH
AD15-8
VALID
ADDRESS
VALID ADDRESS
VALID ADDRESS
tDWH
tDWS
AD7-0
VALID
ADDRESS
VALID DATA
VALID DATA
Figure 19. Write Cycle For 8-Bit Memory Timing
Rev. PrA |
Page 27 of 54 |
September 2004
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-21365/6
Preliminary Technical Data
Table 23. 16-bit Memory Write Cycle
Parameter
Min
Switching Characteristics
tALEW
ALE Pulse Width
2 × tPCLK – 2
tADAS1
Address/Data 15–0 Setup Before ALE Deasserted
tPCLK – 2.5
tALERW
ALE Deasserted to Write Asserted
2 × tPCLK – 2
tRWALE
Write Deasserted to ALE Asserted
H + 0.5
Delay Between WR Rising Edge to next WR Falling Edge
F + H + tPCLK – 2
tWRH
1
tADAH
Address/Data 15–0 Hold After ALE Deasserted
tPCLK – 0.5
tWW
WR Pulse Width
D–F–2
tALEHZ1
ALE Deasserted to Address/Data15–0 in High Z
tPCLK – 1.5
tDWS
Address/Data 15–0 Setup Before WR High
D – F + tPCLK – 4
tDWH
Address/Data 15–0 Hold After WR High
H
D = (Data Cycle Duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × tPCLK
H = tPCLK (if a hold cycle is specified, else H = 0)
F = 7 x tPCLK (if FLASH_MODE is set else F = 0)
1
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
tALEW
tALERW
ALE
tRWALE
tWW
WR
tWRH
RD
tADAS
AD15-0
tDWH
tADAH
VALID
ADDRESS
VALID DATA
VALID DATA
tDWS
Figure 20. Write Cycle For 16-Bit Memory Timing
Rev. PrA |
Page 28 of 54 |
September 2004
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Preliminary Technical Data
ADSP-21365/6
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Serial port signals (SCLK, FS, data channel A,/data channel B)
are routed to the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 24. Serial Ports—External Clock
Parameter
Timing Requirements
tSFSE1
FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode)
tHFSE1
FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode)
1
tSDRE
Receive Data Setup Before Receive SCLK
tHDRE1
Receive Data Hold After SCLK
tSCLKW
SCLK Width
tSCLK
SCLK Period
Switching Characteristics
tDFSE2
FS Delay After SCLK
(Internally Generated FS in either Transmit or Receive Mode)
tHOFSE2
FS Hold After SCLK
(Internally Generated FS in either Transmit or Receive Mode)
tDDTE2
Transmit Data Delay After Transmit SCLK
tHDTE2
Transmit Data Hold After Transmit SCLK
1
2
Min
Max
Unit
2.5
ns
2.5
2.5
2.5
24
48
ns
ns
ns
ns
ns
7
ns
7
ns
ns
ns
2
2
Referenced to sample edge.
Referenced to drive edge.
Table 25. Serial Ports—Internal Clock
Parameter
Timing Requirements
tSFSI1
FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode)
FS Hold After SCLK
tHFSI1
(Externally Generated FS in either Transmit or Receive Mode)
1
tSDRI
Receive Data Setup Before SCLK
tHDRI1
Receive Data Hold After SCLK
Switching Characteristics
tDFSI2
FS Delay After SCLK (Internally Generated FS in Transmit Mode)
FS Hold After SCLK (Internally Generated FS in Transmit Mode)
tHOFSI2
2
tDFSI
FS Delay After SCLK (Internally Generated FS in Receive or Mode)
tHOFSI2
FS Hold After SCLK (Internally Generated FS in Receive Mode)
tDDTI2
Transmit Data Delay After SCLK
2
tHDTI
Transmit Data Hold After SCLK
tSCLKIW
Transmit or Receive SCLK Width
1
2
Referenced to the sample edge.
Referenced to drive edge.
Rev. PrA |
Page 29 of 54 |
September 2004
Min
Max
Unit
7
ns
2.5
7
2.5
ns
ns
ns
3
–1.0
3
–1.0
3
–1.0
0.5tSCLK – 2
0.5tSCLK + 2
ns
ns
ns
ns
ns
ns
ns
ADSP-21365/6
Preliminary Technical Data
Table 26. Serial Ports—Enable and Three-State
Parameter
Switching Characteristics
tDDTEN1
Data Enable from External Transmit SCLK
Data Disable from External Transmit SCLK
tDDTTE1
tDDTIN1
Data Enable from Internal Transmit SCLK
1
Min
Max
Unit
7
ns
ns
ns
Max
Unit
7
ns
ns
2
–1
Referenced to drive edge.
Table 27. Serial Ports—External Late Frame Sync
Parameter
Min
Switching Characteristics
tDDTLFSE1
Data Delay from Late External Transmit FS or External Receive FS
with MCE = 1, MFD = 0
tDDTENFS1
Data Enable for MCE = 1, MFD = 0
0.5
1
The tDDTLFSE and tDDTENFS parameters apply to Left-justified Sample Pair as well as DSP serial mode, and MCE = 1, MFD = 0.
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
DAI_P20-1
(SCLK)
DRIVE
SAMPLE
tSFSE/I
DRIVE
tHFSE/I
DAI_P20-1
(FS)
tDDTE/I
tDDTENFS
tHDTE/I
DAI_P20-1
(DATA CHANNEL A/B)
1ST BIT
2ND BIT
tDDTLFSE
LATE EXTERNAL TRANSMIT FS
DAI_P20-1
(SCLK)
DRIVE
SAMPLE
tSFSE/I
DRIVE
tHFSE/I
DAI_P20-1
(FS)
tDDTE/I
tDDTENFS
tHDTE/I
DAI_P20-1
(DATA CHANNEL A/B)
1ST BIT
2ND BIT
tDDTLFSE
NOTE
SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20-1 PINS
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1 PINS.
Figure 21. External Late Frame Sync1
1
This figure reflects changes made to support Left-justified Sample Pair mode.
Rev. PrA |
Page 30 of 54 |
September 2004
Preliminary Technical Data
ADSP-21365/6
DATA RECEIVE— EXTERNAL CLOCK
DATA RECEIVE— INTERNAL CLOCK
DRIVE EDGE
DRIVE EDGE
SAMPLE EDGE
SAMPLE EDGE
tSCLKIW
tSCLKW
DAI_P20-1
(SCLK)
DAI_P20-1
(SCLK)
tDFSI
tDFSE
tHFSI
tSFSI
tHOFSI
DAI_P20-1
(FS)
tHFSE
tSFSE
tHOFSE
DAI_P20-1
(FS)
tSDRI
tHDRI
DAI_P20-1
(DATA CHANNEL A/B)
tSDRE
tHDRE
DAI_P20-1
(DATA CHANNEL A/B)
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT — INTERNAL CLOCK
DRIVE EDGE
DATA TRANSMIT — EXTERNAL CLOCK
SAMPLE EDGE
DRIVE EDGE
SAMPLE EDGE
tSCLKIW
tSCLKW
DAI_P20-1
(SCLK)
DAI_P20-1
(SCLK)
tDFSI
tHOFSI
tDFSE
tHFSI
tSFSI
tHOFSE
tSFSE
tHFSE
DAI_P20-1
(FS)
DAI_P20-1
(FS)
tDDTI
tHDTI
tHDTE
tDDTE
DAI_P20-1
(DATA CHANNEL A/B)
DAI_P20-1
(DATA CHANNEL A/B)
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE EDGE
DRIVE EDGE
DAI_P20-1
SCLK (EXT)
SCLK
tDDTEN
tDDTTE
DAI_P20-1
(DATA CHANNEL A/B)
DRIVE EDGE
DAI_P20-1
SCLK (INT)
tDDTIN
DAI_P20-1
(DATA CHANNEL A/B)
Figure 22. Serial Ports
Rev. PrA |
Page 31 of 54 |
September 2004
ADSP-21365/6
Preliminary Technical Data
Input Data Port
The timing requirements for the IDP are given in Table 28.IDP
Signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P20–1 pins.
Table 28. IDP
Parameter
Timing Requirements
tSIFS1
FS Setup Before SCLK Rising Edge
1
tSIHFS
FS Hold After SCLK Rising Edge
SData Setup Before SCLK Rising Edge
tSISD1
tSIHD1
SData Hold After SCLK Rising Edge
tIDPCLKW
Clock Width
tIDPCLK
Clock Period
1
Min
Max
2.5
2.5
2.5
2.5
9
24
Unit
ns
ns
ns
ns
ns
ns
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.
SAMPLE EDGE
tSISCLKW
DAI_P20-1
(SCLK)
tSIHFS
tSISFS
DAI_P20-1
(FS)
tSISD
DAI_P20-1
(SDATA)
Figure 23. IDP Master Timing
Rev. PrA |
Page 32 of 54 |
September 2004
tSIHD
Preliminary Technical Data
ADSP-21365/6
ence. Note that the most significant 16 bits of external PDAP
data can be provided through either the parallel port AD15–0 or
the DAI_P20–5 pins. The remaining 4 bits can only be sourced
through DAI_P4–1. The timing below is valid at the
DAI_P20–1 pins or at the AD15–0 pins.
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 29. PDAP is the parallel mode operation of channel 0 of
the IDP. For details on the operation of the IDP, see the IDP
chapter of the ADSP-2136x SHARC Processor Hardware ReferTable 29. Parallel Data Acquisition Port (PDAP)
1
Parameter
Timing Requirements
tSPCLKEN1
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge
1
tHPCLKEN
PDAP_CLKEN Hold After PDAP_CLK Sample Edge
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge
tPDSD1
tPDHD1
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge
tPDCLKW
Clock Width
tPDCLK
Clock Period
Min
Max
Unit
2.5
2.5
2.5
2.5
7
24
ns
ns
ns
ns
ns
ns
Switching Characteristics
tPDHLDD
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word
tPDSTRB
PDAP Strobe Pulse Width
2 × tCCLK
1 × tCCLK – 1
ns
ns
Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.
SAMPLE EDGE
t PDCLK
t PDCLKW
DAI_P20-1
(PDAP_CLK)
t SPCLKEN
t HPCLKEN
DAI_P20-1
(PDAP_CLKEN)
t PDSD
t PDHD
DATA
DAI_P20-1
(PDAP_STROBE)
tPDSTRB
t PDHLDD
Figure 24. PDAP Timing
Rev. PrA |
Page 33 of 54 |
September 2004
ADSP-21365/6
Preliminary Technical Data
Sample Rate Converter—Serial Input Port
The SRC input signals (SCLK, FS, and SDATA) are routed from
the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided in Table 30 are valid at the DAI_P20–1 pins.
Table 30. SRC, Serial Input Port
Parameter
Timing Requirements
FS Setup Before SCLK Rising Edge
tSIFS1
tSIHFS1
FS Hold After SCLK Rising Edge
tSISD1
SData Setup Before SCLK Rising Edge
1
tSIHD
SData Hold After SCLK Rising Edge
tIDPCLKW
Clock Width
tIDPCLK
Clock Period
1
Min
Max
4
5.5
4
5.5
9
20
Unit
ns
ns
ns
ns
ns
ns
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.
SAMPLE EDGE
t IDPCLKW
DAI_P20-1
(SCLK)
t SIHFS
tSISFS
DAI_P20-1
(FS)
t SISD
DAI_P20-1
(SDATA)
Figure 25. SRC Serial Input Port Timing
Rev. PrA |
Page 34 of 54 |
September 2004
tSIHD
Preliminary Technical Data
ADSP-21365/6
Sample Rate Converter—Serial Output Port
and delay specification with regard to SCLK. Note that SCLK
rising edge is the sampling edge and the falling edge is the drive
edge.
For the serial output port, the frame-sync is an input and it
should meet setup and hold times with regard to SCLK on the
output port. The serial data output, SDATA, has a hold time
Table 31. SRC, Serial Output Port
Parameter
Timing Requirements
FS Setup Before SCLK Rising Edge
tSIFS1
tSIHFS1
FS Hold Before SCLK Rising Edge
tSRCTDD1
Transmit Data Delay After SCLK Falling Edge
1
tSRCTDH
Transmit Data Hold After SCLK Falling Edge
1
Min
Max
4
5.5
7
2
Unit
ns
ns
ns
ns
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.
SAMPLE EDGE
t SISCLKW
DAI_P20-1
(SCLK)
t SIHFS
tSIFS
DAI_P20-1
(FS)
t SR CTDH
tSRCTDD
DAI_P20-1
(SDATA)
Figure 26. SRC Serial Output Port Timing
Rev. PrA |
Page 35 of 54 |
September 2004
ADSP-21365/6
Preliminary Technical Data
SPDIF Transmitter
Serial data input to the SPDIF transmitter can be formatted as
left justified, I2S or right justified with word widths of 16, 18, 20,
or 24 bits. The following sections provide timing for the
transmitter.
SPDIF Transmitter—Serial Input Waveforms
Figure 27 shows the right-justified mode. LRCLK is HI for the
left channel and LO for the right channel. Data is valid on the
rising edge of SCLK. The MSB is delayed 12-bit clock periods
(in 20-bit output mode) or 16-bit clock periods (in 16-bit output
LRCLK
mode) from an LRCLK transition, so that when there are 64
SCLK periods per LRCLK period, the LSB of the data will be
right-justified to the next LRCLK transition.
RIGHT CHANNEL
LEFT CHANNEL
SCLK
SDATA
LSB
MSB
MSB-1
MSB-2
LSB+2 LSB+1
LSB
MSB
MSB-1 MSB-2
LSB+2
LSB+1
LSB
Figure 27. Right-Justified Mode
Figure 28 shows the default I2S-justified mode. LRCLK is LO
for the left channel and HI for the right channel. Data is valid on
the rising edge of SCLK. The MSB is left-justified to an LRCLK
transition but with a single SCLK period delay.
RIGHT CHANNEL
LRCLK
LEFT CHANNEL
SCLK
SDATA
MSB
MSB-1 MSB-2
LSB+2 LSB+1
LSB
MSB
MSB-1
MSB-2
LSB+2
LSB+1
LSB
MSB
Figure 28. I2S-Justified Mode
Figure 29 shows the left-justified mode. LRCLK is HI for the left
channel and LO for the right channel. Data is valid on the rising
edge of SCLK. The MSB is left-justified to an LRCLK transition
with no MSB delay.
LRCLK
RIGHT CHANNEL
LEFT CHANNEL
SCLK
SDATA
MSB
MSB-1
MSB-2
LSB+2
LSB+1
LSB
MSB
MSB-1
MSB-2
Figure 29. Left-Justified Mode
Rev. PrA |
Page 36 of 54 |
September 2004
LSB+2
LSB+1
LSB
MSB
MSB+1
Preliminary Technical Data
ADSP-21365/6
SPDIF Transmitter Input Data Timing
The timing requirements for the Input port are given in
Table 32. Input Signals (SCLK, FS, SDATA) are routed to the
DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.
Table 32. SPDIF Transmitter Input Data Timing
Parameter
Timing Requirements
tSIFS1
FS Setup Before SCLK Rising Edge
tSIHFS1
FS Hold After SCLK Rising Edge
tSISD1
SData Setup Before SCLK Rising Edge
tSIHD1
SData Hold After SCLK Rising Edge
Clock Width
tSISCLKW
tSISCLK
Clock Period
1
Min
Max
4
5.5
4
5.5
9
20
Unit
ns
ns
ns
ns
ns
ns
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.
SAMPLE EDGE
t SISCLKW
DAI_P20-1
(SCLK)
tSIHFS
tSISFS
DAI_P20-1
(FS)
t SISD
tSIH D
DAI_P20-1
(SDATA)
Figure 30. SPDIF Transmitter Input Timing
Over Sampling Clock (TXCLK) Switching Characteristics
SPDIF Transmitter has an over sampling clock. This TXCLK
input is divided down to generate the Biphase Clock.
Table 33. Over Sampling Clock (TXCLK) Switching Characteristics
Parameter
TXCLK Frequency for TXCLK = 768 × FS
TXCLK Frequency for TXCLK = 512 × FS
TXCLK Frequency for TXCLK = 384 × FS
TXCLK Frequency for TXCLK = 256 × FS
Frame Rate
Min
Rev. PrA |
Page 37 of 54 |
September 2004
Max
147.5
98.4
73.8
49.2
192.0
Unit
MHz
MHz
MHz
MHz
MHz
ADSP-21365/6
Preliminary Technical Data
SPDIF Receiver
The following sections describe timing as it relates to the SPDIF
receiver.
Internal Digital PLL Mode
In internal Digital Phase-locked Loop mode the internal PLL
(Digital PLL) generates the 512 × Fs clock.
Table 34. SPDIF Receiver Internal Digital PLL Mode Timing
Parameter
Switching Characteristics
LRCLK Delay After SCLK
tDFSI
tHOFSI
LRCLK Hold After SCLK
tDDTI
Transmit Data Delay After SCLK
tHDTI
Transmit Data Hold After SCLK
tSCLKIW1
Transmit SCLK Width
tCCLK
Core Clock Period
1
Min
Max
Unit
5
ns
ns
ns
ns
ns
ns
–2
5
–2
40
5
SCLK frequency is 64 x FS where FS = the frequency of LRCLK.
DRIVE EDGE
SAMPLE EDGE
tSCLKIW
DAI_P20-1
(SCLK)
tDFSI
tSFSI
tHOFSI
tHFSI
DAI_P20-1
(FS)
tHDTI
tDDTI
DAI_P20-1
(DATA CHANNEL A/B)
Figure 31. SPDIF Receiver Internal Digital PLL Mode Timing
Rev. PrA |
Page 38 of 54 |
September 2004
Preliminary Technical Data
ADSP-21365/6
External PLL Mode
In External PLL Mode internal Digital PLL is disabled and the
receiver runs on the PLL that is connected to the processor
externally. This external PLL generates the 512 x Fs clock
(MCLK) from the reference clock (LRCLK) and gives it to
SPDIF receiver.
Table 35. SPDIF Receiver External PLL Mode Timing
Parameter
Timing Requirements
tMCP
FMCLK
tBDM
tLDM
tDDP
tDDS
tDDH
Min
MCLK Period
MCLK Frequency (1/tMCP)
SCLK Propagation Delay from MCLK to the Falling Edge
LRCLK Propagation Delay From MCLK
Data Propagation Delay From MCLK
Data Output Setup To SCLK
Data Output Hold From SCLK
Max
10
100
30
30
30
1/2 SCLK Period
1/2 SCLK Period
MCLK INPUT
(NOT TO SCALE)
BCLK OUTPUT
tBDM
LRCLK
OUTPUT
tLDM
tDDS
SDATA OUTPUT
I2S-JUSTIFIED
MSB
MODE
tDDH
tDDP
tDDS
tDDS
SDATA OUTPUT
RIGHT-JUSTIFIED
MODE
MSB
tDDH
tDDP
Figure 32. SPDIF Receiver External PLL Mode Timing
Rev. PrA |
Page 39 of 54 |
September 2004
LSB
tDDH
Unit
ns
MHz
ns
ns
ns
ns
ns
ADSP-21365/6
Preliminary Technical Data
SPI Interface—Master
The ADSP-21365/6 contains two SPI ports. The primary has
dedicated pins and the secondary is available through the DAI.
The timing provided in Table 36 and Table 37 on page 41
applies to both.
Table 36. SPI Interface Protocol — Master Switching and Timing Specifications
Parameter
Timing Requirements
tSSPIDM
Data Input Valid To SPICLK Edge (Data Input Set-up Time)
tHSPIDM
SPICLK Last Sampling Edge To Data Input Not Valid
Switching Characteristics
tSPICLKM
Serial Clock Cycle
SErial Clock High Period
tSPICHM
tSPICLM
Serial Clock Low Period
tDDSPIDM
SPICLK Edge to Data Out Valid (Data Out Delay Time)
tHDSPIDM
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
tSDSCIM
FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge
tHDSM
Last SPICLK Edge to FLAG3–0IN High
Sequential Transfer Delay
tSPITDM
Min
Max
8
2
ns
ns
8 × tPCLK
4 × tPCLK
4 × tPCLK – 2
ns
ns
ns
0
2
4 × tPCLK – 2
4 × tPCLK – 1
4 × tPCLK – 1
ns
ns
ns
ns
FLAG3-0
(OUTPUT)
t SD SCIM
t SPI CH M
t SPIC LM
t SPIC LM
t SPI CHM
t SPIC LK M
t HDSM
tSPIT DM
SPICLK
(CP = 0)
(OUTPUT)
SPICLK
(CP = 1)
(OUTPUT)
t HDSPIDM
t DDSPI DM
MOSI
(OUTPUT)
MSB
LSB
t SSPID M
CPHASE=1
t SSPI DM
MSB
VALID
LSB
VALID
t DDSPIDM
MOSI
(OUTPUT)
CPHASE=0
MISO
(INPUT)
t HSPIDM
t HSSPIDM
MISO
(INPUT)
t HDSPIDM
MSB
t SSPIDM
LSB
tH SPID M
MSB
VALID
LSB
VALID
Figure 33. SPI Master Timing
Rev. PrA |
Page 40 of 54 |
Unit
September 2004
Preliminary Technical Data
ADSP-21365/6
SPI Interface—Slave
Table 37. SPI Interface Protocol —Slave Switching and Timing Specifications
Parameter
Timing Requirements
tSPICLKS
tSPICHS
tSPICLS
tSDSCO
tHDS
tSSPIDS
tHSPIDS
tSDPPW
Min
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0
Data Input Valid to SPICLK edge (Data Input Set-up Time)
SPICLK Last Sampling Edge to Data Input Not Valid
SPIDS Deassertion Pulse Width (CPHASE=0)
Switching Characteristics
tDSOE
SPIDS Assertion to Data Out Active
tDSDHI
SPIDS Deassertion to Data High Impedance
tDDSPIDS
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
tHDSPIDS
tDSOV
SPIDS Assertion to Data Out Valid (CPHASE=0)
Max
4 × tPCLK
2 × tPCLK
2 × tPCLK – 2
ns
ns
ns
ns
2 × tPCLK
2 × tPCLK
2 × tPCLK
2
2
2 × tPCLK
ns
ns
ns
ns
0
0
4
4
9.4
2 × tPCLK
5 × tPCLK
SPIDS
(INPUT)
t S P I C HS
tS P I C L S
tSPICLKS
tHD S
SPICLK
(CP = 0)
(INPUT)
tS P I C L S
t S D S CO
SPICLK
(CP = 1)
(INPUT)
t D SD H I
t D D S PI D S
MISO
(OUTPUT)
t SD P P W
t S P IC HS
t DD S P ID S
tD S O E
t H DL S B S
MSB
LSB
t H S PI D S
t S S P ID S
CPHASE=1
MOSI
(INPUT)
t S S P I DS
LSB
VALID
MSB
VALID
tD S O V
MISO
(OUTPUT)
tHDLSBS
tD D S P ID S
t D S OE
LSB
MSB
CPHASE=0
MOSI
(INPUT)
t HS P I D S
t SS P ID S
LSB
VALID
MSB
VALID
Figure 34. SPI Slave Timing
Rev. PrA |
Page 41 of 54 |
September 2004
Unit
t D S DH I
ns
ns
ns
ns
ns
ADSP-21365/6
Preliminary Technical Data
JTAG Test Access Port and Emulation
Table 38. JTAG Test Access Port and Emulation
Parameter
Timing Requirements
tTCK
TCK Period
tSTAP
TDI, TMS Setup Before TCK High
tHTAP
TDI, TMS Hold After TCK High
tSSYS1
System Inputs Setup Before TCK Low
1
tHSYS
System Inputs Hold After TCK Low
tTRSTW
TRST Pulse Width
Min
tCK
5
6
7
18
4tCK
Switching Characteristics
tDTDO
TDO Delay from TCK Low
2
System Outputs Delay After TCK Low
tDSYS
1
2
Max
ns
ns
ns
ns
ns
ns
7
10
System Inputs = AD15–0, SPIDS, CLKCFG1–0, RESET, BOOTCFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.
System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU, ALE.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 35. IEEE 1149.1 JTAG Test Access Port
Rev. PrA |
Page 42 of 54 |
September 2004
Unit
tHSYS
ns
ns
Preliminary Technical Data
ADSP-21365/6
OUTPUT DRIVE CURRENTS
CAPACITIVE LOADING
Figure 36 shows typical I-V characteristics for the output drivers of the ADSP-21365/6. The curves represent the current drive
capability of the output drivers as a function of output voltage.
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 37). Figure 41 shows graphically
how output delays and holds vary with load capacitance. The
graphs of Figure 39, Figure 40, and Figure 41 may not be linear
outside the ranges shown for Typical Output Delay vs. Load
Capacitance and Typical Output Rise Time (20%-80%, V=Min)
vs. Load Capacitance.
40
VOH
3.3V, 25° C
20
3.47V, -45° C
12
10
3.11V, 125° C
10
0
-10
3.11V, 125° C
-20
3.3V, 25° C
-30
VOL
-40
0
3.47V, -45° C
0.5
1
1.5
2
2.5
SWEEP (VDDEXT) VOLTAGE (V)
3
y = 0.0467x + 1.6323
RISE AND FALL TIMES (ns)
SOURCE (VDDEXT) CURRENT (mA)
30
3.5
RISE
FALL
8
6
4
y = 0.045x + 1.524
2
Figure 36. ADSP-21365/6 Typical Drive
0
0
50
TEST CONDITIONS
100
150
200
250
LOAD CAPACITANCE (pF)
The ac signal specifications (timing parameters) appear
Table 12 on page 20 through Table 38 on page 42. These include
output disable time, output enable time, and capacitive loading.
The timing specifications for the SHARC apply for the voltage
reference levels in Figure 37.
50⍀
TO
OUTPUT
PIN
1.5V
30pF
12
RISE
10
RISE AND FALL TIMES (ns)
Timing is measured on signals when they cross the 1.5 V level as
described in Figure 38. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.
Figure 39. Typical Output Rise/Fall Time (20%-80%,
VDDEXT = Max)
y = 0.049x + 1.5105
FALL
8
6
y = 0.0482x + 1.4604
4
2
0
Figure 37. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
0
50
100
150
200
LOAD CAPACITANCE (pF)
INPUT
1.5V
OR
OUTPUT
Figure 40. Typical Output Rise/Fall Time (20%-80%,
VDDEXT =Min)
1.5V
Figure 38. Voltage Reference Levels for AC Measurements
Rev. PrA |
Page 43 of 54 |
September 2004
250
ADSP-21365/6
Preliminary Technical Data
Values of θJA are provided for package comparison and PCB
design considerations. θJA can be used for a first order approximation of TJ by the equation:
10
OUTPUT DELAY OR HOLD (ns)
8
T J = T A + ( θ JA × P D )
Y = 0.0488X - 1.5923
6
where:
4
TA = Ambient Temperature °C
2
Values of θJC are provided for package comparison and PCB
design considerations when an external heatsink is required.
0
Values of θJB are provided for package comparison and PCB
design considerations. Note that the thermal characteristics values provided in Table 39 through Table 42 are modeled values.
-2
-4
0
50
100
150
200
LOAD CAPACITANCE (pF)
Figure 41. Typical Output Delay or Hold vs. Load Capacitance
(at Ambient Temperature)
THERMAL CHARACTERISTICS
The ADSP-21365/6 processor is rated for performance to a
maximum junction temperature of 125°C.
Table 39 through Table 42 airflow measurements comply with
JEDEC standards JESD51-2 and JESD51-6 and the junction-toboard measurement complies with JESD51-8. Test board and
thermal via design comply with JEDEC standards JESD51-9
(Mini-BGA) and JESD51-5 (Integrated Heatsink LQFP). The
junction-to-case measurement complies with MIL- STD-883.
All measurements use a 2S2P JEDEC test board.
Industrial applications using the Mini-BGA package require
thermal vias, to an embedded ground plane, in the PCB. Refer
to JEDEC Standard JESD51-9 for printed circuit board thermal
ball land and thermal via design information. Industrial applications using the LQFP package require thermal trace squares and
thermal vias, to an embedded ground plane, in the PCB. The
bottom side heat slug must be soldered to the thermal trace
squares. Refer to JEDEC Standard JESD51-5 for more
information.
To determine the Junction Temperature of the device while on
the application PCB, use:
T J = T CASE + ( Ψ JT × P D )
where:
TJ = Junction temperature °C
TCASE = Case temperature (°C) measured at the top center of
the package
ΨJT = Junction-to-Top (of package) characterization parameter
is the Typical value from Table 39 and Table 41.
PD = Power dissipation (see EE Note #TBD)
Rev. PrA |
Page 44 of 54 |
Table 39. Thermal Characteristics for 136 Ball Mini-BGA
(No thermal vias in PCB)
Parameter
θJA
θJMA
θJMA
θJC
ΨJT
ΨJMT
ΨJMT
Condition
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
Typical
25.20
21.70
20.80
5.00
0.140
0.330
0.410
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Table 40. Thermal Characteristics for 136 Ball Mini-BGA
(Thermal vias in PCB)
Parameter
θJA
θJMA
θJMA
θJC
ΨJT
ΨJMT
ΨJMT
Condition
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
Typical
22.50
19.30
18.40
5.00
0.130
0.300
0.360
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Table 41. Thermal Characteristics for 144-Lead Integrated
Heatsink (INT–HS) LQFP (With heat slug not soldered to
PCB)
Parameter
θJA
θJMA
θJMA
θJC
ΨJT
ΨJMT
ΨJMT
September 2004
Condition
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
Typical
26.08
24.59
23.77
6.83
0.236
0.427
0.441
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Preliminary Technical Data
ADSP-21365/6
Table 42. Thermal Characteristics for 144-Lead Integrated
Heatsink (INT–HS) LQFP (With heat slug soldered to PCB)
Parameter
θJA
θJMA
θJMA
θJC
ΨJT
ΨJMT
ΨJMT
Condition
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
Typical
16.50
15.14
14.35
6.83
0.129
0.255
0.261
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Rev. PrA |
Page 45 of 54 |
September 2004
ADSP-21365/6
Preliminary Technical Data
136-BALL BGA PIN CONFIGURATIONS
The following table shows the ADSP-21365/6’s pin names and
their default function after reset (in parentheses).
Table 43. 136-Ball Mini-BGA Pin Assignments
Pin Name
CLKCFG0
XTAL
TMS
TCK
TDI
CLKOUT
TDO
EMU
MOSI
MISO
SPIDS
VDDINT
GND
GND
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
FLAG3
BGA
Pin#
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
E01
E02
E04
E05
E06
E09
E10
E11
E13
E14
Pin Name
CLKCFG1
GND
VDDEXT
CLKIN
TRST
AVSS
AVDD
VDDEXT
SPICLK
RESET
VDDINT
GND
GND
GND
FLAG1
FLAG0
GND
GND
GND
GND
GND
GND
FLAG2
DAI_P20 (SFS45)
Rev. PrA |
BGA
Pin#
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
F01
F02
F04
F05
F06
F09
F10
F11
F13
F14
Pin Name
BOOTCFG1
BOOTCFG0
GND
GND
GND
VDDINT
BGA
Pin#
C01
C02
C03
C12
C13
C14
AD7
VDDINT
VDDEXT
DAI_P19 (SCLK45)
G01
G02
G13
G14
Page 46 of 54 |
September 2004
Pin Name
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
BGA
Pin#
D01
D02
D04
D05
D06
D09
D10
D11
D13
D14
AD6
VDDEXT
DAI_P18 (SD5B)
DAI_P17 (SD5A)
H01
H02
H13
H14
Preliminary Technical Data
ADSP-21365/6
Table 43. 136-Ball Mini-BGA Pin Assignments (Continued)
Pin Name
AD5
AD4
GND
GND
GND
GND
GND
GND
VDDINT
DAI_P16 (SD4B)
AD15
ALE
RD
VDDINT
VDDEXT
AD8
VDDINT
DAI_P2 (SD0B)
VDDEXT
DAI_P4 (SFS0)
VDDINT
VDDINT
GND
DAI_P10 (SD2B)
BGA
Pin#
J01
J02
J04
J05
J06
J09
J10
J11
J13
J14
N01
N02
N03
N04
N05
N06
N07
N08
N09
N10
N11
N12
N13
N14
Pin Name
AD3
VDDINT
GND
GND
GND
GND
GND
GND
GND
DAI_P15 (SD4A)
AD14
AD13
AD12
AD11
AD10
AD9
DAI_P1 (SD0A)
DAI_P3 (SCLK0)
DAI_P5 (SD1A)
DAI_P6 (SD1B)
DAI_P7 (SCLK1)
DAI_P8 (SFS1)
DAI_P9 (SD2A)
DAI_P11 (SD3A)
Rev. PrA |
BGA
Pin#
K01
K02
K04
K05
K06
K09
K10
K11
K13
K14
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
Pin Name
AD2
AD1
GND
GND
GND
GND
GND
GND
GND
DAI_P14 (SFS23)
Page 47 of 54 |
September 2004
BGA
Pin#
L01
L02
L04
L05
L06
L09
L10
L11
L13
L14
Pin Name
AD0
WR
GND
GND
DAI_P12 (SD3B)
DAI_P13 (SCLK23)
BGA
Pin#
M01
M02
M03
M12
M13
M14
ADSP-21365/6
Preliminary Technical Data
14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
KEY
VDDINT
GND*
AVDD
VDDEXT
AVSS
I/O SIGNALS
*USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE
THERMAL PATHWAYS TO YOUR PRINTED
CIRCUIT BOARD’S GROUND PLANE.
Figure 42. 136-Ball Mini-BGA Pin Assignments (Bottom View, Summary)
Rev. PrA |
Page 48 of 54 |
September 2004
Preliminary Technical Data
ADSP-21365/6
144-LEAD LQFP PIN CONFIGURATIONS
The following table shows the ADSP-21365/6’s pin names and
their default function after reset (in parentheses).
Table 44. 144-Lead LQFP Pin Assignments
Pin Name
VDDINT
CLKCFG0
CLKCFG1
BOOTCFG0
BOOTCFG1
GND
VDDEXT
GND
VDDINT
GND
VDDINT
GND
VDDINT
GND
FLAG0
FLAG1
AD7
GND
VDDINT
GND
VDDEXT
GND
VDDINT
AD6
AD5
AD4
VDDINT
GND
AD3
AD2
VDDEXT
GND
AD1
AD0
WR
VDDINT
LQFP
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Pin Name
VDDINT
GND
RD
ALE
AD15
AD14
AD13
GND
VDDEXT
AD12
VDDINT
GND
AD11
AD10
AD9
AD8
DAI_P1 (SD0A)
VDDINT
GND
DAI_P2 (SD0B)
DAI_P3 (SCLK0)
GND
VDDEXT
VDDINT
GND
DAI_P4 (SFS0)
DAI_P5 (SD1A)
DAI_P6 (SD1B)
DAI_P7 (SCLK1)
VDDINT
GND
VDDINT
GND
DAI_P8 (SFS1)
DAI_P9 (SD2A)
VDDINT
LQFP
Pin No.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Rev. PrA |
Pin Name
LQFP
Pin No.
VDDEXT
73
GND
74
VDDINT
75
GND
76
DAI_P10 (SD2B)
77
DAI_P11 (SD3A)
78
DAI_P12 (SD3B)
79
DAI_P13 (SCLK23) 80
DAI_P14 (SFS23)
81
DAI_P15 (SD4A)
82
VDDINT
83
GND
84
GND
85
DAI_P16 (SD4B)
86
DAI_P17 (SD5A)
87
DAI_P18 (SD5B)
88
DAI_P19 (SCLK45) 89
VDDINT
90
GND
91
GND
92
VDDEXT
93
DAI_P20 (SFS45)
94
GND
95
VDDINT
96
FLAG2
97
FLAG3
98
VDDINT
99
GND
100
101
VDDINT
GND
102
VDDINT
103
GND
104
VDDINT
105
GND
106
VDDINT
107
VDDINT
108
Page 49 of 54 |
September 2004
Pin Name
GND
VDDINT
GND
VDDINT
GND
VDDINT
GND
VDDEXT
GND
VDDINT
GND
VDDINT
RESET
SPIDS
GND
VDDINT
SPICLK
MISO
MOSI
GND
VDDINT
VDDEXT
AVDD
AVSS
GND
CLKOUT
EMU
TDO
TDI
TRST
TCK
TMS
GND
CLKIN
XTAL
VDDEXT
LQFP
Pin No.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
ADSP-21365/6
Preliminary Technical Data
PACKAGE DIMENSIONS
The ADSP-21365/6 is available in a 136-ball Mini-BGA package
and a 144-lead integrated heatsink LQFP package.
10.40 BSC SQ
12.00 BSC SQ
0.80
BSC
TYP
PIN A1 INDICATOR
A
B
C
D
E
F
G
H
J
K
L
M
N
P
0.80
BSC
TYP
14 13 12 11 10 9 8 7 6 5 4 3 2 1
BOTTOM VIEW
TOP VIEW
1.70
MAX
DETAIL A
0.25
1. DIMENSIONS ARE IN MILIMETERS (MM).
MIN
2. THE ACTUAL POSITION OF THE BALL GRID IS
WITHIN 0.15 MM OF ITS IDEAL POSITION RELATIVE
TO THE PACKAGE EDGES.
3. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.08 MM
OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID.
4. COMPLIANT TO JEDEC STANDARD MO-205-AE, EXCEPT FOR
THE BALL DIAMETER.
5. CENTER DIMENSIONS ARE NOMINAL.
0.50
0.45
0.40
(BALL
DIAMETER)
DETAIL A
Figure 43. 136-ball Mini-BGA (BC-136-2)
Rev. PrA |
Page 50 of 54 |
September 2004
SEATING
PLANE
0.12 MAX (BALL
COPLANARITY)
Preliminary Technical Data
ADSP-21365/6
22.00 BSC SQ
20. 00 BSC SQ
0.27
0.22 TYP
0.17
144
0.50
BSC
TYP
(LEAD
PITCH)
SEATING
PLANE
10 9
1
108
PIN 1 INDICA TOR
13.71
0.08 MAX (LEAD
COPLANARITY)
13.21 DIA
12.71
0.15
0.05
0.75
0.60 TYP
0.45
1. 45
1. 40
1. 35
1.60 MAX
36
72
37
DE TAIL A
DETAIL A
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH
JEDEC STANDARD MS-026-BFB-HD.
2. ACTUAL PO SITION OF EACH LEAD IS WITHIN 0.08 OF ITS
IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTI ON.
3. CENTER DIMENSIONS ARE NOMINAL.
4. HEATSLUG IS COINCIDENT WI TH BO TTOM SURFACE AND DOES
NOT PROTRUDE BEYOND IT.
HEATSLUG ON BOTTOM
(NOTE 4)
TOP VIE W (P INS DO WN)
Figure 44. 144-Lead LQFP (ST-144-3)
ORDERING GUIDE
Analog Devices offers a wide variety of audio algorithms and
combinations to run on the ADSP-21365/6 processor. These
products are sold as part of a chip set, bundled with necessary
application software under special part numbers. For a complete
list, visit our web site at www.analog.com/SHARC.
These product also may contain 3rd party IPs that may require
users to have authorization from the respective IP holders to
receive them. Royalty for use of the 3rd party IPs may also be
payable by users.
Rev. PrA |
Page 51 of 54 |
September 2004
ADSP-21365/6
Preliminary Technical Data
Table 45. ADSP-21365 Ordering Guide
Part Number1, 2, 3
ADSP-21365SKBCZENG
ADSP-21365SKBC-ENG
ADSP-21365SKSQZENG
ADSP-21365SKSQ-ENG
ADSP-21365SBBCZENG4
ADSP-21365SBBC-ENG4
ADSP-21365SBSQZENG5
ADSP-21365SBSQ-ENG5
ADSP-21365SCSQZENG5
ADSP-21365SCSQ-ENG5
Ambient
Temperature
Range °C
0 to 70
0 to 70
0 to 70
0 to 70
–40 to 85
–40 to 85
–40 to 85
–40 to 85
–40 to 105
–40 to 105
Instruction
Rate
On-Chip
SRAM
ROM
333MHz
333MHz
333MHz
333MHz
333MHz
333MHz
333MHz
333MHz
200MHz
200MHz
3M bit
3M bit
3M bit
3M bit
3M bit
3M bit
3M bit
3M bit
3M bit
3M bit
4M bit
4M bit
4M bit
4M bit
4M bit
4M bit
4M bit
4M bit
4M bit
4M bit
Operating Voltage
Internal/External
Volts
1.2/3.3
1.2/3.3
1.2/3.3
1.2/3.3
1.2/3.3
1.2/3.3
1.2/3.3
1.2/3.3
1.0/3.3
1.0/3.3
Package
136 Mini-BGA Pb-free
136 Mini-BGA
144 INT–HS LQFP Pb-free
144 INT–HS LQFP
136 Mini-BGA Pb-free
136 Mini-BGA
144 INT–HS LQFP Pb-free
144 INT–HS LQFP
144 INT–HS LQFP Pb-free
144 INT–HS LQFP
1
Z indicates Lead Free package. For more information about lead free package offerings, please visit www.analog.com.
See Thermal Characteristics on page 44 for information on package thermal specifications.
3
See Engineer–to–Engineer Note TBD for further information.
4
PCB must have thermal vias. See Thermal Characteristics on page 44. For more information see Jedec Standard JESD51-9.
5
Heat slug must be soldered to the PCB. See Thermal Characteristics on page 44. For more information see Jedec Standard JESD51-5.
2
Table 46. ADSP-21366 Ordering Guide
Part Number1, 2, 3
ADSP-21366SKBCZENG
ADSP-21366SKBC-ENG
ADSP-21366SKSQZENG
ADSP-21366SKSQ-ENG
ADSP-21366SBBCZENG4
ADSP-21366SBBC-ENG4
ADSP-21366SBSQZENG5
ADSP-21366SBSQ-ENG5
ADSP-21366SCSQZENG5
ADSP-21366SCSQ-ENG5
Ambient
Temperature
Range °C
0 to 70
0 to 70
0 to 70
0 to 70
–40 to 85
–40 to 85
–40 to 85
–40 to 85
–40 to 105
–40 to 105
Instruction
Rate
On-Chip
SRAM
ROM
333MHz
333MHz
333MHz
333MHz
333MHz
333MHz
333MHz
333MHz
200MHz
200MHz
3M bit
3M bit
3M bit
3M bit
3M bit
3M bit
3M bit
3M bit
3M bit
3M bit
4M bit
4M bit
4M bit
4M bit
4M bit
4M bit
4M bit
4M bit
4M bit
4M bit
Operating Voltage
Internal/External
Volts
1.2/3.3
1.2/3.3
1.2/3.3
1.2/3.3
1.2/3.3
1.2/3.3
1.2/3.3
1.2/3.3
1.0/3.3
1.0/3.3
1
Z indicates Lead Free package. For more information about lead free package offerings, please visit www.analog.com.
See Thermal Characteristics on page 44 for information on package thermal specifications.
3
See Engineer–to–Engineer Note TBD for further information.
4
PCB must have thermal vias. See Thermal Characteristics on page 44. For more information see JEDEC Standard JESD51-9.
5
Heat slug must be soldered to the PCB. See Thermal Characteristics on page 44. For more information see JEDEC Standard JESD51-5.
2
Rev. PrA |
Page 52 of 54 |
September 2004
Package
136 Mini-BGA Pb-free
136 Mini-BGA
144 INT–HS LQFP Pb-free
144 INT–HS LQFP
136 Mini-BGA Pb-free
136 Mini-BGA
144 INT–HS LQFP Pb-free
144 INT–HS LQFP
144 INT–HS LQFP Pb-free
144 INT–HS LQFP
Preliminary Technical Data
Rev. PrA |
ADSP-21365/6
Page 53 of 54 |
September 2004
ADSP-21365/6
Preliminary Technical Data
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR04625-0-10/04(PrA)
Rev. PrA |
Page 54 of 54 |
September 2004