Harris CD4070B Cmos quad exclusive-or and exclusive-nor gate Datasheet

CD4070B,
CD4077B
Semiconductor
CMOS Quad Exclusive-OR
and Exclusive-NOR Gate
June 1998
Features
Description
• High-Voltage Types (20V Rating)
The Harris CD4070B contains four independent ExclusiveOR gates. The Harris CD4077B contains four independent
Exclusive-NOR gates.
• CD4070B - Quad Exclusive-OR Gate
• CD4077B - Quad Exclusive-NOR Gate
The CD4070B and CD4077B provide the system designer
with a means for direct implementation of the Exclusive-OR
and Exclusive-NOR functions, respectively.
• Medium Speed Operation
- tPHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF
• 100% Tested for Quiescent Current at 20V
Ordering Information
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
PART NUMBER
• Maximum Input Current of 1µA at 18V Over Full
Package Temperature Range
- 100nA at 18V and 25oC
• Noise Margin (Over Full Package Temperature Range)
- 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Standard No. 13B,
“Standard Specifications for Description of ‘B’ Series
CMOS Devices
Applications
TEMP.
RANGE (oC)
PACKAGE
PKG.
NO.
CD4070BE
-55 to 125
14 Ld PDIP
E14.3
CD4077BE
-55 to 125
14 Ld PDIP
E14.3
CD4070BF
-55 to 125
14 Ld CERDIP
F14.3
CD4077BF
-55 to 125
14 Ld CERDIP
F14.3
CD4070BM
-55 to 125
14 Ld SOIC
M14.15
CD4077BM
-55 to 125
14 Ld SOIC
M14.15
• Logical Comparators
• Adders/Subtractors
• Parity Generators and Checkers
Pinouts
CD4070B
(PDIP, CERDIP, SOIC)
TOP VIEW
CD4077B
(PDIP, CERDIP, SOIC)
TOP VIEW
A 1
14 VDD
A 1
14 VDD
B 2
13 H
B 2
13 H
J=A⊕B 3
12 G
J=A⊕B 3
12 G
K=C⊕D 4
11 M = G ⊕ H
K=C⊕D 4
11 M = G ⊕ H
C 5
10 L = E ⊕ F
C 5
10 L = E ⊕ F
D 6
9 F
D 6
9 F
VSS 7
8 E
VSS 7
8 E
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1998
1
File Number
910.1
CD4070B, CD4077B
Functional Diagrams
CD4070B
1
A
J=A⊕B
K=C⊕D
M=G⊕ H
L=E⊕F
VSS = 7
VDD = 14
5
C
4
6
D
8
E
10
9
F
H
3
2
B
G
CD4077B
12
11
13
A
J
B
J =A
K=C
K
L
⊕B
⊕D
⊕H
=E⊕F
C
D
M=G
E
L
F
G
M
H
1
3
2
5
4
6
8
10
9
12
11
13
J
K
L
M
VDD
VDD
VDD
p
VDD
B†
p
2(5,9,12)
n
p
1(6,8,13)
n
p
n
J
p
n
3(4,10,11)
n
VDD
n
p
p
J
VDD
p
VSS
†
n
VSS
VDD
A†
2(5,9,12)
n
VSS
p
B†
p
A†
p
1(6,8,13)
n
n
VSS
VSS
†
INPUTS PROTECTED
BY CMOS PROTECTION
NETWORK
3(4,10,11)
n
VSS
VDD
INPUTS PROTECTED
BY CMOS PROTECTION
NETWORK
VSS
VSS
FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070B
(1 OF 4 IDENTICAL GATES)
FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077B
(1 OF 4 IDENTICAL GATES)
CD4070B TRUTH TABLE (1 OF 4 GATES)
CD4077B TRUTH TABLE (1 OF 4 GATES)
A
B
J
A
B
J
0
0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
0
1
1
1
NOTE:
1 = High Level
0 = Low Level
J=A⊕B
NOTE:
1 = High Level
0 = Low Level
J=A⊕B
2
CD4070B, CD4077B
(Continued)
tPHL, tPLH, PROPAGATION DELAY TIME (ns)
tTHL, tTLH, TRANSITION TIME (ns)
Typical Performance Curves
TA = 25oC
200
SUPPLY VOLTAGE (VDD) = 5V
150
100
10V
50
15V
0
0
20
40
60
80
100
TA = 25oC
300
200
SUPPLY VOLTAGE (VDD) = 5V
100
10V
15V
0
0
110
20
105
TA = 25oC
LOAD CAPACITANCE CL = 50pF
300
200
100
0
5
10
15
80
60
100
FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE
PD, POWER DISSIPATION (µW)
tPHL, tPLH, PROPAGATION DELAY TIME (ns)
FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
0
40
CL, LOAD CAPACITANCE (pF)
CL, LOAD CAPACITANCE (pF)
VDD, SUPPLY VOLTAGE (V)
FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF SUPPLY VOLTAGE
V
104
)=
15
D
E
AG
LT
O
YV
PL
103
102
(V D
P
SU
10
10V
CL = 50pF
10V
CL = 15pF
5V
1
10-1
10-1
20
TA = 25oC
1
102
103
10
fI, INPUT FREQUENCY (kHz)
104
FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A
FUNCTION OF INPUT FREQUENCY
5
CD4070B, CD4077B
Dual-In-Line Plastic Packages (PDIP)
E14.3 (JEDEC MS-001-AA ISSUE D)
N
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
-B-AE
D
BASE
PLANE
A2
-C-
SEATING
PLANE
A
L
D1
e
B1
D1
B
0.010 (0.25) M
A1
eC
C A B S
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8
eA
C
0.008
0.014
D
0.735
0.775
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm).
6
0.204
0.355
18.66
19.68
5
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
eA
0.300 BSC
eB
-
L
0.115
N
14
2.54 BSC
-
7.62 BSC
6
0.430
-
0.150
2.93
14
10.92
7
3.81
4
9
Rev. 0 12/93
CD4070B, CD4077B
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)
LEAD FINISH
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
-A-
BASE
METAL
INCHES
(c)
SYMBOL
E
M
-Bbbb S
C A-B S
Q
-C-
SEATING
PLANE
S1
-
0.200
-
5.08
-
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.785
-
19.94
5
E
0.220
0.310
5.59
7.87
5
eA
b2
b
ccc M
C A-B S
e
D S
eA/2
NOTES
b
α
A A
MAX
A
A
L
MIN
M
(b)
D
BASE
PLANE
MILLIMETERS
MAX
b1
SECTION A-A
D S
MIN
c
aaa M C A - B S D S
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
α
90o
105o
90o
105o
-
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
N
14
14
8
Rev. 0 4/94
7
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