ADS5444-SP www.ti.com SGLS391C – MARCH 2008 – REVISED JANUARY 2014 CLASS V, 13 BIT, 250 MSPS ANALOG-TO-DIGITAL CONVERTER Check for Samples: ADS5444-SP FEATURES 1 • • • • • • • • • • • • APPLICATIONS 13 Bit Resolution 250 MSPS Sample Rate SNR = 67.6 dBc at 230 MHz IF and 250 MSPS SFDR = 74.0 dBc at 230 MHz IF and 250 MSPS 2.2 VPP Differential Input Voltage Fully Buffered Analog Inputs 5 V Analog Supply Voltage LVDS Compatible Outputs Total Power Dissipation: 2 W Offset Binary Output Format Pin Compatible With the ADS5440 Military Temperature Range ( –55°C to 125°C Tcase) • • • • • • Test and Measurement Software-Defined Radio Multichannel Base Station Receivers Base Station Tx Digital Predistortion Communications Instrumentation Engineering Evaluation (/EM) Samples are Available (1) RELATED PRODUCTS • • • (1) ADS5424 - 14 Bit, 105 MSPS ADC ADS5423 - 14 Bit, 80 MSPS ADC ADS5440 - 13 Bit, 210 MSPS ADC These units are intended for engineering evaluation only. They are processed to a non-compliant flow (e.g. no burn-in, etc.) and are tested to temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance on full MIL specified temperature range of -55°C to 125°C or operating life. DESCRIPTION The ADS5444 is a 13 bit 250 MSPS analog-to-digital converter (ADC) that operates from a 5 V supply, while providing LVDS-compatible digital outputs from a 3.3 V supply. The ADS5444 input buffer isolates the internal switching of the onboard track and hold (T&H) from disturbing the signal source. An internal reference generator is also provided to further simplify the system design. The ADS5444 has outstanding low noise and linearity over input frequency. AVDD AIN AIN A1 TH1 + TH2 Σ A2 + TH3 ADC1 Reference A3 ADC3 − − VREF Σ DVDD DAC1 ADC2 5 DAC2 5 5 Digital Error Correction CLK CLK Timing OVR OVR DRY DRY D[12:0] GND B0061-01 The ADS5444 is available in a 84 pin ceramic nonconductive tie-bar package (HFG). The ADS5444 is built on a state-of-the-art Texas Instruments complementary bipolar process (BiCom3X) and is specified over the full military temperature range (–55°C to 125°C Tcase). 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2014, Texas Instruments Incorporated ADS5444-SP SGLS391C – MARCH 2008 – REVISED JANUARY 2014 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating temperature range (unless otherwise noted) (1) VALUE/UNIT Supply voltage AVDD to GND 6V DRVDD to GND 5V Analog input to GND –0.3 V to AVDD + 0.3 V Clock input to GND –0.3 V to AVDD + 0.3 V CLK to CLK ±2.5 V Digital data output to GND TC Characterized case operating temperature range TJ Maximum junction temperature Tstg Storage temperature range –0.3 V to DRVDD + 0.3 V –55°C to 125°C 150°C –65°C to 150°C ESD Human Body Model (HBM) (1) 2.5 kV Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond those specified is not implied. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT 4.75 5 5.25 V 3 3.3 3.6 V SUPPLIES AVDD Analog supply voltage DRVDD Output driver supply voltage ANALOG INPUT VCM Differential input range 2.2 VPP Input common mode 2.4 V CLOCK INPUT ADCLK input sample rate (sine wave) 10 250 Clock amplitude, differential sine wave 3 Clock duty cycle TC 2 Operating case temperature Submit Documentation Feedback MSPS VPP 50% –55 125 °C Copyright © 2008–2014, Texas Instruments Incorporated ADS5444-SP www.ti.com SGLS391C – MARCH 2008 – REVISED JANUARY 2014 ELECTRICAL CHARACTERISTICS Typical values at TC = 25°C, full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3 VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Resolution TYP MAX UNIT 13 Bits 2.2 Vpp 1 kΩ Differential input capacitance 1.5 pF Analog input bandwidth 800 MHz ANALOG INPUTS Differential input range Differential input resistance (DC) INTERNAL REFERENCE VOLTAGE VREF Reference voltage 2.38 2.4 2.42 V DYNAMIC ACCURACY No missing codes DNL INL Differential linearity error Integral linearity error Assured fIN = 100 MHz Full temp range fIN = 100 MHz TC = 25°C and TC,MAX –2.8 2.8 TC = TC,MIN –4.8 4.8 Full temp range –0.6 Offset error –0.98 Offset temperature coefficient ±0.4 2 Full temp range –5 Gain temperature coefficient LSB 0.6 0.0005 Gain error LSB %FS %FS/°C 5 –0.02 %FS %FS/°C POWER SUPPLY IAVDD Analog supply current IDRVDD Output buffer supply current VIN = full scale, fIN = 170 MHz, FS = 250 MSPS Power dissipation 340 410 mA 80 100 mA 2 2.29 W DYNAMIC AC CHARACTERISTICS fIN = 10 MHz TC = 25°C 68.0 TC = TC,MAX 66.8 TC = TC,MIN 63.2 TC = 25°C 67.3 TC = TC,MAX 66.5 TC = TC,MIN 62.1 TC = 25°C 66.5 TC = TC,MAX 66.1 TC = TC,MIN 60.8 fIN = 70 MHz fIN = 100 MHz SNR Signal-to-noise ratio fIN = 170 MHz 69.1 69.0 68.9 dBc 68.4 fIN = 230 MHz 67.6 fIN = 300 MHz 66.5 fIN = 400 MHz 65.5 Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 ADS5444-SP SGLS391C – MARCH 2008 – REVISED JANUARY 2014 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Typical values at TC = 25°C, full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3 VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS fIN = 10 MHz MIN TYP TC = 25°C 75.0 84.0 TC = TC,MAX 74.0 TC = TC,MIN 75.0 TC = 25°C 62.0 TC = TC,MAX 74.5 TC = TC,MIN 63.0 TC = 25°C 63.0 TC = TC,MAX 65.0 TC = TC,MIN 59.0 fIN = 70 MHz fIN = 100 MHz SFDR Spurious free dynamic range fIN = 170 MHz 65.8 60.5 TC = 25°C 75.0 TC = TC,MAX 74.0 TC = TC,MIN 76.5 TC = 25°C 62.0 TC = TC,MAX 76.0 TC = TC,MIN 63.0 TC = 25°C 63.0 TC = TC,MAX 65.0 TC = TC,MIN 59.0 fIN = 70 MHz Second harmonic fIN = 170 MHz 74.0 65.8 fIN = 100 MHz Submit Documentation Feedback dBc 73.0 fIN = 300 MHz 60.6 TC = 25°C 81.0 Full temp range 78.5 TC = 25°C 72.0 TC = TC,MAX 74.5 TC = TC,MIN 65.0 TC = 25°C 65.0 TC = TC,MAX 69.0 TC = TC,MIN 63.0 fIN = 70 MHz 4 67.4 fIN = 230 MHz fIN = 10 MHz Third harmonic 92.0 71.8 fIN = 400 MHz HD3 dBc 70.0 fIN = 300 MHz fIN = 400 MHz HD2 67.4 74.0 fIN = 100 MHz fIN = 170 MHz UNIT 71.8 fIN = 230 MHz fIN = 10 MHz MAX 84.0 72.8 78.4 70.1 fIN = 230 MHz 94.0 fIN = 300 MHz 77.7 fIN = 400 MHz 64.1 dBc Copyright © 2008–2014, Texas Instruments Incorporated ADS5444-SP www.ti.com SGLS391C – MARCH 2008 – REVISED JANUARY 2014 ELECTRICAL CHARACTERISTICS (continued) Typical values at TC = 25°C, full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3 VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS fIN = 10 MHz MIN TYP TC = 25°C 80.0 89.0 TC = TC,MAX 81.0 TC = TC,MIN 75.0 TC = 25°C 74.0 TC = TC,MAX 78.0 TC = TC,MIN 69.0 TC = 25°C 70.0 TC = TC,MAX 78.0 TC = TC,MIN 64.0 fIN = 70 MHz fIN = 100 MHz Worst other harmonic/spur (other than HD2 and HD3) fIN = 170 MHz 83.6 82.0 TC = 25°C 74.5 TC = TC,MAX 73.0 TC = TC,MIN 74.0 TC = 25°C 61.5 TC = TC,MAX 73.0 TC = TC,MIN 60.0 TC = 25°C 62.0 TC = TC,MAX 63.5 TC = TC,MIN 58.0 fIN = 70 MHz Total harmonic distortion fIN = 170 MHz 83.0 68.9 67.0 dBc 68.2 fIN = 230 MHz 73.2 fIN = 300 MHz 65.5 fIN = 400 MHz fIN = 10 MHz 59.0 TC = 25°C 67.7 TC = TC,MAX 66.4 TC = TC,MIN 62.9 TC = 25°C 62.2 TC = TC,MAX 66.2 TC = TC,MIN 59.4 TC = 25°C 61.7 TC = TC,MAX 62.9 TC = TC,MIN 57.6 fIN = 70 MHz fIN = 100 MHz SINAD dBc 88.2 fIN = 300 MHz fIN = 400 MHz THD 86.6 81.8 fIN = 100 MHz Signal-to-noise and distortion fIN = 170 MHz 69.2 69.2 68.9 dBc 68.3 fIN = 230 MHz 67.5 fIN = 300 MHz 66.6 fIN = 400 MHz 65.4 Copyright © 2008–2014, Texas Instruments Incorporated UNIT 82.7 fIN = 230 MHz fIN = 10 MHz MAX Submit Documentation Feedback 5 ADS5444-SP SGLS391C – MARCH 2008 – REVISED JANUARY 2014 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Typical values at TC = 25°C, full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3 VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS fIN = 10 MHz ENOB Effective number of bits fIN = 100 MHz MIN TYP TC = 25°C 10.9 11.3 TC = TC,MAX 10.7 TC = TC,MIN 10.1 TC = 25°C 10.0 TC = TC,MAX 10.7 TC = TC,MIN 9.5 TC = 25°C fIN = 170 MHz RMS idle channel noise 10.1 TC = TC,MIN 9.2 UNIT Bits 11.3 9.9 TC = TC,MAX MAX 11.2 Inputs tied to common-mode 0.4 LSB DIGITAL CHARACTERISTICS – LVDS DIGITAL OUTPUTS Differential output voltage 247 Output offset voltage 452 1.125 1.25 1.375 mV V TIMING CHARACTERISTICS tA N+3 N AIN N+1 N+2 tCLK CLK, CLK tCLKH N+1 N N+4 tCLKL N+2 N+3 tC_DR D[12:0], OVR, OVR N−3 tr N−2 tf N+4 tsu_c N−1 th_c N th_DR tsu_DR DRY, DRY tDR T0073-01 Figure 1. Timing Diagram 6 Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated ADS5444-SP www.ti.com SGLS391C – MARCH 2008 – REVISED JANUARY 2014 TIMING CHARACTERISTICS Typical values at TC = 25°C, 50% clock duty cycle, sampling rate = 250 MSPS, AVDD = 5 V, DRVDD = 3.3 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tA Aperture delay 500 ps tJ Clock slope independent aperture uncertainty (jitter) 200 fs RMS Latency 4 cycles tCLK Clock period 4 ns tCLKH Clock pulse width high 2 ns tCLKL Clock pulse width low 2 ns Clock Input Clock to DataReady (DRY) tDR Clock rising to DataReady falling tC_DR Clock rising to DataReady rising Clock to DATA, OVR 1.1 Clock duty cycle = 50% (1) 2.7 3.1 ns 3.5 ns (2) tr Data rise time (20% to 80%) 0.6 ns tf Data fall time(80% to 20%) 0.6 ns tsu_c Data valid to clock (setup time) 3.1 ns th_c Clock to invalid data (hold time) 0.2 ns DataReady (DRY)/DATA, OVR (2) tsu(DR) Data valid to DRY 1.5 2 ns th(DR) DRY to invalid data 0.9 1.3 ns (1) (2) tC_DR = tDR + tCLKH for clock duty cycles other than 50% Data is updated with clock falling edge or DRY rising edge. Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 ADS5444-SP SGLS391C – MARCH 2008 – REVISED JANUARY 2014 www.ti.com DEVICE INFORMATION GND D5 D6 D5 GND D6 D7 DVDD D8 D7 D9 D8 D10 D9 D11 D10 D12 D11 DRY DRY D12 HFG PACKAGE (TOP VIEW) GND 1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 D4 DVDD 2 62 D4 GND 3 61 D3 AVDD 4 60 D3 NC 5 59 D2 NC 6 58 D2 VREF 7 57 D1 GND 8 56 D1 AVDD 9 55 GND GND 10 54 DVDD CLK 11 53 D0 CLK 12 52 D0 ADS5444 45 OVR AVDD 20 44 OVR 43 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 GND AVDD AVDD GND GND GND 19 AVDD NC GND GND 46 AVDD 18 GND NC AIN NC 47 GND 17 GND NC AIN AVDD 48 NC 16 GND NC GND GND 49 AVDD 15 GND NC AVDD GND NC 50 GND 51 14 AVDD 13 AVDD GND AVDD TERMINAL FUNCTIONS TERMINAL NAME DESCRIPTION NO. 4, 9, 14, 15, 20, 23, 25, 27, 29, 33, 37, 39, Analog power supply 41 AVDD DVDD 2, 54, 70 Output driver power supply 1, 3, 8, 10, 13, 16, 19, 21, 22, 24, 26, 28, 30, Ground 32, 34, 36, 38, 40, 42, 43, 55, 64, 69 GND VREF 7 Reference voltage CLK 11 Differential input clock (positive). Conversion initiated on rising edge. CLK 12 Differential input clock (negative) AIN 17 Differential input signal (positive) AIN 18 Differential input signal (negative) OVR, OVR 44, 45 Over range indicator LVDS output. A logic high signals an analog input in excess of the fullscale range. D0, D0 52, 53 LVDS digital output pair, least-significant bit (LSB) D1–D4, D1–D4 56–63 LVDS digital output pairs D5–D6, D5–D6 65–68 LVDS digital output pairs 8 Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated ADS5444-SP www.ti.com SGLS391C – MARCH 2008 – REVISED JANUARY 2014 TERMINAL FUNCTIONS (continued) TERMINAL NAME DESCRIPTION NO. D7–D11, D7–D11 71–80 LVDS digital output pairs D12, D12 81, 82 LVDS digital output pair, most-significant bit (MSB) DRY, DRY 83, 84 Data ready LVDS output pair NC 5, 6, 31, 35, 46–51 No connect THERMAL CHARACTERISTICS TYP UNIT RθJA Junction-to-free-air thermal resistance PARAMETER Board mounted, per JESD 51-5 methodology TEST CONDITIONS 21.813 °C/W RθJC Junction-to-case thermal resistance MIL-STD-883 Test Method 1012 0.849 °C/W THERMAL NOTES This CQFP package has built in vias that electrically and thermally connect the bottom of the die to a pad on the bottom of the package. To efficiently remove heat and provide a low-impedance ground path, a thermal land is required on the surface of the PCB directly underneath the body of the package. During normal surface mount flow solder operations, the heat pad on the underside of the package is soldered to this thermal land creating an efficient thermal path. Normally, the PCB thermal land has a number of thermal vias within it that provide a thermal path to internal copper areas (or to the opposite side of the PCB) that provide for more efficient heat removal. TI typically recommends an 11,9-mm2 board-mount thermal pad. This allows maximum area for thermal dissipation, while keeping leads away from the pad area to prevent solder bridging. A sufficient quantity of thermal/electrical vias must be included to keep the device within recommended operating conditions. This pad must be electrically at ground potential. Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 ADS5444-SP SGLS391C – MARCH 2008 – REVISED JANUARY 2014 www.ti.com 1000.00 Years estimated life 100.00 Electromigration Fail Mode ` 10.00 1.00 80 90 100 110 120 130 140 150 160 170 180 Continuous Tj (°C) Figure 2. ADS5444 Estimated Device Life at Elevated Temperatures Electromigration Fail Mode DEFINITION OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low frequency value. Aperture Delay The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine wave clock results in a 50% duty cycle. Maximum Conversion Rate The maximum sampling rate at which certified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. Minimum Conversion Rate The minimum sampling rate at which the ADC functions. Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSB. Integral Nonlinearity (INL) The INL is the deviation of the ADCs transfer function from a best fit line determined by a least squares curve fit of that transfer function. The INL at each analog input value is the difference between the actual transfer function and this best fit line, measured in units of LSB. Gain Error The gain error is the deviation of the ADCs actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. 10 Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated ADS5444-SP www.ti.com SGLS391C – MARCH 2008 – REVISED JANUARY 2014 DEFINITION OF SPECIFICATIONS (continued) Offset Error Offset error is the deviation of output code from mid-code when both inputs are tied to commonmode. Temperature Drift Temperature drift (with respect to gain error and offset error) specifies the change from the value at the nominal temperature to the value at TMIN or TMAX. It is computed as the maximum variation the parameters over the whole temperature range divided by TMIN – TMAX. Signal-to-Noise Ratio (SNR) SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc and the first five harmonics. P S SNR + 10log 10 P N (1) SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range. Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding dc. P S SINAD + 10log 10 P ) P N D (2) SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range. Effective Resolution Bandwidth The highest input frequency where the SNR (dB) is dropped by 3 dB for a fullscale input amplitude. Total Harmonic Distortion (THD) THD is the ratio of the power of the fundamental (PS) to the power of the first five harmonics (PD). P S THD + 10log 10 P D (3) THD is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion IMD3 is the ratio of the power of the fundamental (at frequencies f1, f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1). IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range. Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback 11 ADS5444-SP SGLS391C – MARCH 2008 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS AC Performance vs Input Amplitude (230 MHz) Performance - dB Performance - dB AC Performance vs Input Amplitude (100 MHz) Input Amplitude - dBFS Input Amplitude - dBFS Figure 4. SFDR vs Clock Level SNR vs Clock Level Clock Amplitude - VP-P Clock Amplitude - VP-P Figure 6. SFDR vs AVDD Across Temperture SNR vs AVDD Across Temperture SNR - Signal-to_Noise Ratio - dBc SFDR - Spurious-Free Dynamic Range - dBc Figure 5. AVDD - Supply Voltage - V Figure 7. 12 fIN = 230 MHz SNR - Signal-to-Noise Ratio - dBc SFDR - Spurious-Free Dynamic Range - dBc Figure 3. Submit Documentation Feedback AVDD - Supply Voltage - V Figure 8. Copyright © 2008–2014, Texas Instruments Incorporated ADS5444-SP www.ti.com SGLS391C – MARCH 2008 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS (continued) SNR vs DRVDD Across Temperture SFDR - Spurious-Free Dynamic Range - dBc SNR - Signal-to-Noise Ratio - dBc SFDR vs DRVDD Across Temperture DRVDD - Supply Voltage - V DRVDD - Supply Voltage - V Figure 9. Figure 10. SNR vs Input Frequency and Sampling Frequency SFDR vs Input Frequency and Sampling Frequency Figure 11. Figure 12. Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback 13 ADS5444-SP SGLS391C – MARCH 2008 – REVISED JANUARY 2014 www.ti.com APPLICATION INFORMATION Theory of Operation The ADS5444 is a 13 bit, 250 MSPS, monolithic pipeline analog-to-digital converter (ADC). Its bipolar analog core operates from a 5 V supply, while the output uses a 3.3 V supply to provide LVDS compatible outputs. The conversion process is initiated by the rising edge of the external input clock. At that instant, the differential input signal is captured by the input track and hold (T&H) and the input sample is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in a data latency of four clock cycles, after which the output data is available as a 13 bit parallel word, coded in offset binary format. Input Configuration The analog input for the ADS5444 consists of an analog differential buffer followed by a bipolar T&H. The analog buffer isolates the source driving the input of the ADC from any internal switching. The input common mode is set internally through a 500 Ω resistor connected from 2.4 V to each of the inputs. This results in a differential input impedance of 1 kΩ. For a full-scale differential input, each of the differential lines of the input signal (pins 17 and 18) swings symmetrically between 2.4 + 0.55 V and 2.4 – 0.55 V. This means that each input has a maximum signal swing of 1.1 VPP for a total differential input signal swing of 2.2 VPP. The maximum swing is determined by the internal reference voltage generator eliminating the need for any external circuitry for this purpose. The ADS5444 obtains optimum performance when the analog inputs are driven differentially. The circuit in Figure 13 shows one possible configuration using an RF transformer with termination either on the primary or on the secondary of the transformer. If voltage gain is required, a step up transformer can be used. For voltage gains that would require an impractical transformer turn ratio, a single-ended amplifier driving the transformer is shown in Figure 14. Z0 50 W R0 50 W AIN 1:1 R 50 W AC Signal Source ADS5444 AIN ADT1-1WT Figure 13. Converting a Single-Ended Input to a Differential Signal Using RF Transformers 5V VIN −5 V RS 100 Ω + OPA695 − 0.1 µF 1000 µF RIN 1:1 RT 100 Ω RIN AIN CIN ADS5444 AIN R1 400 Ω R2 57.5 Ω AV = 8V/V (18 dB) Figure 14. Using the OPA695 with the ADS5444 14 Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated ADS5444-SP www.ti.com SGLS391C – MARCH 2008 – REVISED JANUARY 2014 From VIN 50 Ω Source 100 Ω 78.9 Ω 348 Ω 13 Bit 250 MSPS +5V 49.9 Ω 0.22 µF 100 Ω THS4509 49.9 Ω 18 pF AIN ADS5444 AIN CM 49.9 Ω 0.22 µF 78.9 Ω VREF 49.9 Ω 0.22 µF 348 Ω 0.1 µF 0.1 µF Figure 15. Using the THS4509 with the ADS5444 Besides the OPA695, TI offers a wide selection of single-ended operational amplifiers that can be selected depending on the application. An RF gain block amplifier, such as the TI THS9001, can also be used with an RF transformer for high input frequency applications. For applications requiring dc-coupling with the signal source, a differential input/differential output amplifier like the THS4509 (see Figure 15) is a good solution, as it minimizes board space and reduces the number of components. In this configuration, the THS4509 amplifier circuit provides 10 dB of gain, converts the single-ended input to differential, and sets the proper input common-mode voltage to the ADS5444. The 50 Ω resistors and 18 pF capacitor between the THS4509 outputs and ADS5444 inputs (along with the input capacitance of the ADC) limit the bandwidth of the signal to about 70 MHz (–3 dB). Input termination is accomplished via the 78.9 Ω resistor and 0.22 μF capacitor to ground in conjunction with the input impedance of the amplifier circuit. A 0.22 μF capacitor and 49.9 Ω resistor are inserted to ground across the 78.9 Ω resistor and 0.22 μF capacitor on the alternate input to balance the circuit. Gain is a function of the source impedance, termination, and 348 Ω feedback resistor. See the THS4509 data sheet for further component values to set proper 50 Ω termination for other common gains. Because the ADS5444 recommended input common-mode voltage is 2.4 V, the THS4509 is operated from a single power supply input with VS+ = 5 V and VS– = 0 V (ground). This maintains maximum headroom on the internal transistors of the THS4509. Clock Inputs The ADS5444 clock input can be driven with either a differential clock signal or a single-ended clock input, with little or no difference in performance between both configurations. In low-input frequency applications, where jitter may not be a big concern, the use of single-ended clock (see Figure 16) could save some cost and board space without any trade-off in performance. When driven on this configuration, it is best to connect CLK to ground with a 0.01 μF capacitor, while CLK is ac-coupled with a 0.01 μF capacitor to the clock source, as shown in Figure 16. Square Wave or Sine Wave CLK 0.01 µF ADS5444 CLK 0.01 µF Figure 16. Single-Ended Clock Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback 15 ADS5444-SP SGLS391C – MARCH 2008 – REVISED JANUARY 2014 www.ti.com 0.1 µF Clock Source 1:4 CLK MA3X71600LCT−ND ADS5444 CLK Figure 17. Differential Clock For jitter-sensitive applications, the use of a differential clock has some advantages (as with any other ADC) at the system level. The first advantage is that it allows for common-mode noise rejection at the PCB level. A differential clock also allows for the use of bigger clock amplitudes without exceeding the absolute maximum ratings. In the case of a sinusoidal clock, this results in higher slew rates and reduces the impact of clock noise on jitter. See Clocking High Speed Data Converters (SLYT075) for more details. Figure 17 shows this approach. The back-to-back Schottky diodes can be added to limit the clock amplitude in cases where this would exceed the absolute maximum ratings, even when using a differential clock. 100 nF MC100EP16DT 100 nF D D CLK Q VBB Q 499 W 100 nF 100 nF ADS5444 CLK 499 W 50 Ω 50 Ω 100 nF 113 Ω Figure 18. Differential Clock Using PECL Logic Another possibility is the use of a logic-based clock, such as PECL. In this case, the slew rate of the edges is most likely much higher than the one obtained for the same clock amplitude based on a sinusoidal clock. This solution would minimize the effect of the slope dependent ADC jitter. Using logic gates to square a sinusoidal clock may not produce the best results, as logic gates may not have been optimized to act as comparators, adding too much jitter while squaring the inputs. The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1 kΩ resistors. It is recommended to use ac coupling, but if this scheme is not possible due to, for instance, asynchronous clocking, the ADS5444 features good tolerance to clock common-mode variation. Additionally, the internal ADC core uses both edges of the clock for the conversion process. Ideally, a 50% duty cycle clock signal should be provided. Digital Outputs The ADC provides 13 data outputs (D12 to D0, with D12 being the MSB and D0 the LSB), a data-ready signal (DRY), and an over-range indicator (OVR) that equals a logic high when the output reaches the full-scale limits. The output format is offset binary. It is recommended to use the DRY signal to capture the output data of the ADS5444. The ADS5444 digital outputs are LVDS compatible. 16 Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated ADS5444-SP www.ti.com SGLS391C – MARCH 2008 – REVISED JANUARY 2014 Power Supplies The use of low-noise power supplies with adequate decoupling is recommended. Linear supplies are the preferred choice versus switched ones, which tend to generate more noise components that can be coupled to the ADS5444. The ADS5444 uses two power supplies. For the analog portion of the design, a 5 V AVDD is used, while for the digital outputs supply (DRVDD) TI recommends the use of 3.3 V. All the ground pins are marked as GND, although AGND pins and DRGND pins are not tied together inside the package. Layout Information The evaluation board represents a good guideline of how to lay out the board to obtain the maximum performance out of the ADS5444. General design rules such as the use of multilayer boards, single ground plane for ADC ground connections and local decoupling ceramic chip capacitors should be applied. The input traces should be isolated from any external source of interference or noise including the digital outputs, as well as the clock traces. The clock signal traces should also be isolated from other signals, especially in applications where low jitter is required as high IF sampling. Besides performance-oriented rules, care has to be taken when considering the heat dissipation out of the device. Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback 17 ADS5444-SP SGLS391C – MARCH 2008 – REVISED JANUARY 2014 www.ti.com REVISION HISTORY Changes from Revision B (February 2012) to Revision C Page • Added /EM bullet to FEATURES .......................................................................................................................................... 1 • Deleted ORDERING INFORMATION table .......................................................................................................................... 1 18 Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 19-Dec-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty 5962-0720701VXC ACTIVE CFP HFG 84 ADS5444HFG/EM ACTIVE CFP HFG 84 1 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking TBD Call TI Call TI -55 to 125 59620720701VXC ADS5444MHFG-V TBD Call TI N / A for Pkg Type 25 Only ADS5444HFG/EM EVAL ONLY (4/5) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF ADS5444-SP : • Catalog: ADS5444 • Enhanced Product: ADS5444-EP NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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