20 mW Power, 2.3 V to 5.5 V, 75 MHz Complete DDS AD9834 Capability for phase modulation and frequency modulation is provided. The frequency registers are 28 bits; with a 75 MHz clock rate, resolution of 0.28 Hz can be achieved. Similarly, with a 1 MHz clock rate, the AD9834 can be tuned to 0.004 Hz resolution. Frequency and phase modulation are affected by loading registers through the serial interface and toggling the registers using software or the FSELECT pin and PSELECT pin, respectively. FEATURES Narrow-band SFDR >72 dB 2.3 V to 5.5 V power supply Output frequency up to 37.5 MHz Sine output/triangular output On-board comparator 3-wire SPI® interface Extended temperature range: −40°C to +105°C Power-down option 20 mW power consumption at 3 V 20-lead TSSOP The AD9834 is written to using a 3-wire serial interface. This serial interface operates at clock rates up to 40 MHz and is compatible with DSP and microcontroller standards. The device operates with a power supply from 2.3 V to 5.5 V. The analog and digital sections are independent and can be run from different power supplies, for example, AVDD can equal 5 V with DVDD equal to 3 V. APPLICATIONS Frequency stimulus/waveform generation Frequency phase tuning and modulation Low power RF/communications systems Liquid and gas flow measurement Sensory applications: proximity, motion, and defect detection Test and medical equipment The AD9834 has a power-down pin (SLEEP) that allows external control of the power-down mode. Sections of the device that are not being used can be powered down to minimize the current consumption. For example, the DAC can be powered down when a clock output is being generated. GENERAL DESCRIPTION The part is available in a 20-lead TSSOP. The AD9834 is a 75 MHz low power DDS device capable of producing high performance sine and triangular outputs. It also has an on-board comparator that allows a square wave to be produced for clock generation. Consuming only 20 mW of power at 3 V makes the AD9834 an ideal candidate for power-sensitive applications. FUNCTIONAL BLOCK DIAGRAM AVDD AGND DGND DVDD CAP/2.5V REFOUT ON-BOARD REFERENCE REGULATOR MCLK VCC 2.5V FULL-SCALE CONTROL FSELECT 28-BIT FREQ0 REG PHASE ACCUMULATOR (28-BIT) MUX 28-BIT FREQ1 REG Σ FS ADJUST 12 SIN ROM 10-BIT DAC MUX COMP IOUT IOUTB MSB 12-BIT PHASE0 REG 12-BIT PHASE1 REG MUX MUX DIVIDED BY 2 16-BIT CONTROL REGISTER MUX SIGN BIT OUT SERIAL INTERFACE AND CONTROL LOGIC COMPARATOR VIN FSYNC SCLK SDATA PSELECT SLEEP RESET 02705-001 AD9834 Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2003–2011 Analog Devices, Inc. All rights reserved. AD9834 TABLE OF CONTENTS Features .............................................................................................. 1 Control Register ......................................................................... 18 Applications....................................................................................... 1 Frequency and Phase Registers ................................................ 20 General Description ......................................................................... 1 Writing to a Frequency Register............................................... 21 Functional Block Diagram .............................................................. 1 Writing to a Phase Register....................................................... 21 Revision History ............................................................................... 3 RESET Function ......................................................................... 21 Specifications..................................................................................... 4 SLEEP Function.......................................................................... 21 Timing Characteristics ................................................................ 6 SIGN BIT OUT Pin.................................................................... 22 Absolute Maximum Ratings............................................................ 7 The IOUT and IOUTB Pins...................................................... 22 ESD Caution.................................................................................. 7 Applications Information .............................................................. 23 Pin Configuration and Function Descriptions............................. 8 Grounding and Layout .................................................................. 26 Typical Performance Characteristics ........................................... 10 Interfacing to Microprocessors..................................................... 27 Terminology .................................................................................... 14 AD9834 to ADSP-21xx Interface ............................................. 27 Theory of Operation ...................................................................... 15 AD9834 to 68HC11/68L11 Interface....................................... 27 Circuit Description......................................................................... 16 AD9834 to 80C51/80L51 Interface .......................................... 28 Numerically Controlled Oscillator Plus Phase Modulator ... 16 AD9834 to DSP56002 Interface ............................................... 28 SIN ROM ..................................................................................... 16 Evaluation Board ............................................................................ 29 Digital-to-Analog Converter (DAC) ....................................... 16 System Development Platform................................................. 29 Comparator ................................................................................. 16 AD9834 to SPORT Interface..................................................... 29 Regulator...................................................................................... 17 XO vs. External Clock................................................................ 29 Output Voltage Compliance...................................................... 17 Power Supply............................................................................... 29 Functional Description .................................................................. 18 Evaluation Board Schematics ................................................... 30 Serial Interface ............................................................................ 18 Evaluation Board Layout........................................................... 32 Powering Up the AD9834 ......................................................... 18 Outline Dimensions ....................................................................... 35 Latency......................................................................................... 18 Ordering Guide .......................................................................... 35 Rev. C | Page 2 of 36 AD9834 REVISION HISTORY 2/11—Rev. B to Rev. C Changes to IDD Parameter, Table 1 ..................................................5 Changes to FS ADJUST Description, Table 4................................8 Added Output Voltage Compliance Section................................17 Changes to Figure 31 ......................................................................23 Changes to Figure 32 ......................................................................24 Deleted Using the AD9834 Evaluation Board Section and the Prototyping Area Section ...............................................................28 Added System Development Platform Section, AD9834 to SPORT Interface Section, Figure 39, and Figure 40; Renumbered Sequentially ..............................................................29 Changes to XO vs. External Clock Section and Power Supply Section ..............................................................................................29 Deleted Bill of Materials, Table 19; Renumbered Sequentially ..............................................................30 Added Evaluation Board Schematics Section and Figure 41 ....30 Added Figure 42 ..............................................................................31 Added Evaluation Board Layout Section and Figure 43 ............32 Added Figure 44 ..............................................................................33 Added Figure 45 ..............................................................................34 Changes to Ordering Guide...........................................................35 4/10—Rev. A to Rev. B Changes to Comparator Section ...................................................15 Added Figure 28 ..............................................................................16 Changes to Serial Interface Section ..............................................17 8/06—Rev. 0 to Rev. A Updated Format ................................................................. Universal Changed to 75 MHz Complete DDS ............................... Universal Changes to Features Section ............................................................1 Changes to Table 1 ............................................................................4 Changes to Table 2 ............................................................................6 Changes to Table 3 ............................................................................8 Added Figure 10, Figures Renumbered Sequentially ...................9 Added Figure 16 and Figure 17, Figures Renumbered Sequentially......................................................................................10 Changes to Table 6 ..........................................................................19 Changes to Writing a Frequency Register Section .....................20 Changes to Figure 29 ......................................................................21 Changes to Table 19 ........................................................................30 Changes to Figure 38 ......................................................................28 2/03—Revision 0: Initial Version Rev. C | Page 3 of 36 AD9834 SPECIFICATIONS VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, RSET = 6.8 kΩ, RLOAD = 200 Ω for IOUT and IOUTB, unless otherwise noted. Table 1. 2 Parameter SIGNAL DAC SPECIFICATIONS Resolution Update Rate IOUT Full Scale 3 VOUT Max VOUT Min Output Compliance 4 DC Accuracy Integral Nonlinearity Differential Nonlinearity DDS SPECIFICATIONS Dynamic Specifications Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range (SFDR) Wideband (0 to Nyquist) Narrow Band (±200 kHz) B Grade C Grade Clock Feedthrough Wake-Up Time COMPARATOR Input Voltage Range Input Capacitance Input High-Pass Cutoff Frequency Input DC Resistance Input Leakage Current OUTPUT BUFFER Output Rise/Fall Time Output Jitter VOLTAGE REFERENCE Internal Reference REFOUT Output Impedance 5 Reference Temperature Coefficient LOGIC INPUTS Input High Voltage, VINH Min Grade B, Grade C 1 Typ Max 10 75 3.0 0.6 30 0.8 ±1 ±0.5 55 Bits MSPS mA V mV V 60 −66 −56 dB dBc fMCLK = 75 MHz, fOUT = fMCLK/4096 fMCLK = 75 MHz, fOUT = fMCLK/4096 −60 −56 dBc fMCLK = 75 MHz, fOUT = fMCLK/75 −78 −74 −50 1 −67 −65 dBc dBc dBc ms fMCLK = 50 MHz, fOUT = fMCLK/50 fMCLK = 75 MHz, fOUT = fMCLK/75 1 V p-p pF MHz MΩ μA AC-coupled internally ns ps rms Using a 15 pF load 3 MHz sine wave, 0.6 V p-p 10 12 120 1.18 1 100 1.24 1.7 2.0 2.8 Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN Test Conditions/Comments LSB LSB 10 4 5 1.12 Unit 0.6 0.7 0.8 10 3 Rev. C | Page 4 of 36 V kΩ ppm/°C V V V V V V μA pF 2.3 V to 2.7 V power supply 2.7 V to 3.6 V power supply 4.5 V to 5.5 V power supply 2.3 V to 2.7 V power supply 2.7 V to 3.6 V power supply 4.5 V to 5.5 V power supply AD9834 2 Parameter POWER SUPPLIES AVDD DVDD IAA 6 IDD6 B Grade C Grade IAA + IDD6 B Grade C Grade Low Power Sleep Mode B Grade C Grade Grade B, Grade C 1 Typ Max Min Unit Test Conditions/Comments V V mA fMCLK = 75 MHz, fOUT = fMCLK/4096 3.8 5.5 5.5 5 2.0 2.7 3 3.7 mA mA IDD code dependent (see Figure 8) IDD code dependent (see Figure 8) 5.8 6.5 8 8.7 mA mA 2.3 2.3 0.5 0.6 mA mA DAC powered down, MCLK running DAC powered down, MCLK running 1 B grade: MCLK = 50 MHz; C grade: MCLK = 75 MHz. For specifications that do not specify a grade, the value applies to both grades. Operating temperature range is as follows: B, C versions: −40°C to +105°C, typical specifications are at 25°C. 3 For compliance, with specified load of 200 Ω, IOUT full scale should not exceed 4 mA. 4 Guaranteed by design. 5 Applies when REFOUT is sourcing current. The impedance is higher when REFOUT is sinking current. 6 Measured with the digital inputs static and equal to 0 V or DVDD. 2 RSET 6.8kΩ 10nF REFOUT CAP/2.5V REGULATOR ON-BOARD REFERENCE 12 AD9834 SIN ROM FS ADJUST FULL-SCALE CONTROL 10-BIT DAC AVDD 10nF COMP IOUT RLOAD 200Ω Figure 2. Test Circuit Used to Test the Specifications Rev. C | Page 5 of 36 20pF 02705-002 100nF AD9834 TIMING CHARACTERISTICS DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted. Table 2. Parameter 1 t1 t2 t3 t4 t5 t6 t7 t8 MIN t8 MAX t9 t10 t11 t11A t12 1 Limit at TMIN to TMAX 20/13.33 8/6 8/6 25 10 10 5 10 t4 − 5 5 3 8 8 5 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min ns min ns min ns min ns min Test Conditions/Comments MCLK period: 50 MHz/75 MHz MCLK high duration: 50 MHz/75 MHz MCLK low duration: 50 MHz/75 MHz SCLK period SCLK high duration SCLK low duration FSYNC-to-SCLK falling edge setup time FSYNC-to-SCLK hold time Data setup time Data hold time FSELECT, PSELECT setup time before MCLK rising edge FSELECT, PSELECT setup time after MCLK rising edge SCLK high to FSYNC falling edge setup time Guaranteed by design, not production tested. Timing Diagrams t1 MCLK 02705-003 t2 t3 Figure 3. Master Clock MCLK FSELECT, PSELECT VALID DATA VALID DATA VALID DATA 02705-004 t11A t11 Figure 4. Control Timing t5 t12 t4 SCLK t7 t6 t8 FSYNC SDATA D15 D14 D2 t10 D1 Figure 5. Serial Timing Rev. C | Page 6 of 36 D0 D15 D14 02705-005 t9 AD9834 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to AGND DVDD to DGND AVDD to DVDD AGND to DGND CAP/2.5V Digital I/O Voltage to DGND Analog I/O Voltage to AGND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature TSSOP Package θJA Thermal Impedance θJC Thermal Impedance Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature Reflow Soldering (Pb-Free) Peak Temperature Time at Peak Temperature Ratings −0.3 V to +6 V −0.3 V to +6 V −0.3 V to +0.3 V −0.3 V to +0.3 V 2.75 V −0.3 V to DVDD + 0.3 V −0.3 V to AVDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −40°C to +105°C −65°C to +150°C 150°C 143°C/W 45°C/W 300°C 220°C 260°C (+0/–5) 10 sec to 40 sec Rev. C | Page 7 of 36 AD9834 FS ADJUST 1 20 IOUTB REFOUT 2 19 IOUT COMP 3 18 AGND 17 VIN 16 SIGN BIT OUT CAP/2.5V 6 15 FSYNC DGND 7 14 SCLK MCLK 8 13 SDATA FSELECT 9 12 SLEEP PSELECT 10 11 RESET AVDD 4 DVDD 5 AD9834 TOP VIEW (Not to Scale) 02705-006 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 6. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description ANALOG SIGNAL AND REFERENCE 1 FS ADJUST Full-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. This determines the magnitude of the full-scale DAC current. The relationship between RSET and the full-scale current is as follows: IOUT FULL SCALE = 18 × FSADJUST/RSET FSADJUST = 1.15 V nominal, RSET = 6.8 kΩ typical. 2 REFOUT Voltage Reference Output. The AD9834 has an internal 1.20 V reference that is made available at this pin. 3 COMP DAC Bias Pin. This pin is used for decoupling the DAC bias voltage. 17 VIN Input to Comparator. The comparator can be used to generate a square wave from the sinusoidal DAC output. The DAC output should be filtered appropriately before being applied to the comparator to improve jitter. When Bit OPBITEN and Bit SIGN/PIB in the control register are set to 1, the comparator input is connected to VIN. 19, 20 IOUT, Current Output. This is a high impedance current source. A load resistor of nominally 200 Ω should be connected IOUTB between IOUT and AGND. IOUTB should preferably be tied through an external load resistor of 200 Ω to AGND, but it can be tied directly to AGND. A 20 pF capacitor to AGND is also recommended to prevent clock feedthrough. POWER SUPPLY 4 AVDD Positive Power Supply for the Analog Section. AVDD can have a value from 2.3 V to 5.5 V. A 0.1 μF decoupling capacitor should be connected between AVDD and AGND. 5 DVDD Positive Power Supply for the Digital Section. DVDD can have a value from 2.3 V to 5.5 V. A 0.1 μF decoupling capacitor should be connected between DVDD and DGND. 6 CAP/2.5V The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated from DVDD using an on-board regulator (when DVDD exceeds 2.7 V). The regulator requires a decoupling capacitor of typically 100 nF that is connected from CAP/2.5 V to DGND. If DVDD is equal to or less than 2.7 V, CAP/2.5 V should be shorted to DVDD. 7 DGND Digital Ground. 18 AGND Analog Ground. DIGITAL INTERFACE AND CONTROL 8 MCLK Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The output frequency accuracy and phase noise are determined by this clock. 9 FSELECT Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase accumulator. The frequency register to be used can be selected using Pin FSELECT or Bit FSEL. When Bit FSEL is used to select the frequency register, the FSELECT pin should be tied to CMOS high or low. 10 PSELECT Phase Select Input. PSELECT controls which phase register, PHASE0 or PHASE1, is added to the phase accumulator output. The phase register to be used can be selected using Pin PSELECT or Bit PSEL. When the phase registers are being controlled by Bit PSEL, the PSELECT pin should be tied to CMOS high or low. 11 RESET Active High Digital Input. RESET resets appropriate internal registers to zero; this corresponds to an analog output of midscale. RESET does not affect any of the addressable registers. 12 SLEEP Active High Digital Input. When this pin is high, the DAC is powered down. This pin has the same function as Control Bit SLEEP12. Rev. C | Page 8 of 36 AD9834 Pin No. 13 14 15 Mnemonic SDATA SCLK FSYNC 16 SIGN BIT OUT Description Serial Data Input. The 16-bit serial data-word is applied to this input. Serial Clock Input. Data is clocked into the AD9834 on each falling SCLK edge. Active Low Control Input. This is the frame synchronization signal for the input data. When FSYNC is taken low, the internal logic is informed that a new word is being loaded into the device. Logic Output. The comparator output is available on this pin or, alternatively, the MSB from the NCO can be output on this pin. Setting Bit OPBITEN in the control register to 1 enables this output pin. Bit SIGN/PIB determines whether the comparator output or the MSB from the NCO is output on the pin. Rev. C | Page 9 of 36 AD9834 TYPICAL PERFORMANCE CHARACTERISTICS 4.0 0 AVDD = DVDD = 3V TA = 25°C TA = 25°C 3.5 –10 3.0 –20 SFDR (dBc) 5V 2.0 3V 1.5 –30 –40 –50 1.0 –60 0.5 –70 15 0 30 45 MCLK FREQUENCY (MHz) 60 75 fOUT = 1MHz –80 02705-007 0 SFDR dB MCLK/7 0 10 20 30 40 50 MCLK FREQUENCY (MHz) 60 02705-010 IDD (mA) 2.5 70 Figure 10. Wideband SFDR vs. MCLK Frequency Figure 7. Typical Current Consumption (IDD) vs. MCLK Frequency 4.0 0 TA = 25°C 5V 3.5 –10 3.0 AVDD = DVDD = 3V TA = 25°C –20 3V SFDR (dBc) IDD (mA) 2.5 2.0 1.5 –30 50MHz CLOCK –40 –50 –60 0.5 –70 1k 10k 100k fOUT (Hz) 1M 10M 100M –80 0.001 02705-008 0 100 0.1 1.0 fOUT/fMCLK 10 100 Figure 11. Wideband SFDR vs. fOUT/fMCLK for Various MCLK Frequencies Figure 8. Typical IDD vs. fOUT for fMCLK = 50 MHz –60 –40 AVDD = DVDD = 3V TA = 25°C –45 –70 –50 SNR (dB) –65 –75 SFDR dB MCLK/50 –80 TA = 25°C AVDD = DVDD = 3V fOUT = MCLK/4096 –55 –60 –85 –65 –90 0 15 30 45 MCLK FREQUENCY (MHz) 60 75 –70 1.0 5.0 10.0 12.5 MCLK FREQUENCY (MHz) Figure 12. SNR vs. MCLK Frequency Figure 9. Narrow-Band SFDR vs. MCLK Frequency Rev. C | Page 10 of 36 25.0 50.0 02705-012 SFDR dB MCLK/7 02705-009 SFDR (dBc) 0.01 02705-011 30MHz CLOCK 1.0 1000 0.20 950 0.18 900 0.16 2.3V 850 DVDD = 3.3V DVDD = 2.3V DVDD = 5.5V 0.14 5.5V 700 0.12 0.10 0.08 650 0.06 600 0.04 550 0.02 500 –40 25 TEMPERATURE (°C) 105 0 –40 Figure 13. Wake-Up Time vs. Temperature –20 0 20 40 60 TEMPERATURE (°C) 80 100 02705-037 750 DVDD (V) 800 02705-013 WAKE-UP TIME (µs) AD9834 Figure 16. SIGN BIT OUT Low Level, ISINK = 1 mA 5.5 1.250 DVDD = 5.5V 5.0 1.225 4.5 DVDD = 4.5V UPPER RANGE 4.0 DVDD (V) 1.175 LOWER RANGE 3.5 DVDD = 3.3V 3.0 1.150 DVDD = 2.7V 2.5 1.125 2.0 25 TEMPERATURE (°C) 105 1.5 –40 02705-014 1.100 –40 DVDD = 2.3V –20 0 20 40 60 TEMPERATURE (°C) 80 100 02705-038 V(REFOUT) (V) 1.200 Figure 17. SIGN BIT OUT High Level, ISINK = 1 mA Figure 14. VREFOUT vs. Temperature 0 –100 AVDD = DVDD = 5V TA = 25°C –10 –110 –20 –30 (dB) –40 –130 –50 –60 –70 –140 –80 –150 1k 10k FREQUENCY (Hz) 100k 200k Figure 15. Output Phase Noise, fOUT = 2 MHz, MCLK = 50 MHz 0 RWB 100 VWB 30 FREQUENCY (Hz) 100k ST 100 SEC 02705-016 –160 100 –90 –100 02705-015 (dBc/Hz) –120 Figure 18. fMCLK = 10 MHz; fOUT = 2.4 kHz, Frequency Word = 000FBA9 Rev. C | Page 11 of 36 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 5M ST 50 SEC –10 –20 –20 –30 –30 –40 –40 (dB) –10 –50 –60 –60 –70 –70 –80 –80 –90 –90 VWB 300 FREQUENCY (Hz) 5M ST 50 SEC –100 Figure 20. fMCLK = 10 MHz; fOUT = 3.33 MHz = fMCLK/3, Frequency Word = 5555555 –10 –10 –20 –20 –30 –30 –40 –40 (dB) 0 –50 –60 –70 –70 –80 –80 –90 –90 160k ST 200 SEC Figure 21. fMCLK = 50 MHz; fOUT = 12 kHz, Frequency Word = 000FBA9 –100 02705-019 VWB 30 FREQUENCY (Hz) VWB 300 FREQUENCY (Hz) 25M ST 200 SEC –50 –60 0 RWB 100 0 RWB 1k Figure 23. fMCLK = 50 MHz; fOUT = 1.2 MHz, Frequency Word = 0624DD3 0 –100 1.6M ST 200 SEC –50 02705-018 (dB) 0 0 RWB 1k VWB 300 FREQUENCY (Hz) Figure 22. fMCLK = 50 MHz; fOUT = 120 kHz, Frequency Word = 009D496 0 –100 0 RWB 100 02705-021 VWB 300 FREQUENCY (Hz) 0 RWB 1k VWB 300 FREQUENCY (Hz) 25M ST 200 SEC 02705-022 0 RWB 1k Figure 19. fMCLK = 10 MHz; fOUT = 1.43 MHz = fMCLK/7, Frequency Word = 2492492 (dB) –50 02705-020 (dB) 0 02705-017 (dB) AD9834 Figure 24. fMCLK = 50 MHz; fOUT = 4.8 MHz, Frequency Word = 189374C Rev. C | Page 12 of 36 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 0 RWB 1k VWB 300 FREQUENCY (Hz) 25M ST 200 SEC –100 Figure 25. fMCLK = 50 MHz; fOUT = 7.143 MHz = fMCLK/7, Frequency Word = 2492492 0 RWB 1k VWB 300 FREQUENCY (Hz) 25M ST 200 SEC Figure 26. fMCLK = 50 MHz; fOUT = 16.667 MHz = fMCLK/3, Frequency Word = 5555555 Rev. C | Page 13 of 36 02705-024 (dB) 0 02705-023 (dB) AD9834 AD9834 TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale, a point 0.5 LSB below the first code transition (000 . . . 00 to 000 . . . 01), and full scale, a point 0.5 LSB above the last code transition (111 . . . 10 to 111 . . . 11). The error is expressed in LSBs. Differential Nonlinearity (DNL) DNL is the difference between the measured and ideal 1 LSB change between two adjacent codes in the DAC. A specified DNL of ±1 LSB maximum ensures monotonicity. Output Compliance The output compliance refers to the maximum voltage that can be generated at the output of the DAC to meet the specifications. When voltages greater than that specified for the output compliance are generated, the AD9834 may not meet the specifications listed in the data sheet. Spurious-Free Dynamic Range (SFDR) Along with the frequency of interest, harmonics of the fundamental frequency and images of these frequencies are present at the output of a DDS device. The SFDR refers to the largest spur or harmonic present in the band of interest. The wideband SFDR gives the magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the 0 to Nyquist bandwidth. The narrow-band SFDR gives the attenuation of the largest spur or harmonic in a bandwidth of ±200 kHz about the fundamental frequency. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the rms value of the fundamental. For the AD9834, THD is defined as THD = 20log V2 2 + V32 + V4 2 + V5 2 + V6 2 V1 where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second harmonic through the sixth harmonic. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency. The value for SNR is expressed in decibels. Clock Feedthrough There is feedthrough from the MCLK input to the analog output. Clock feedthrough refers to the magnitude of the MCLK signal relative to the fundamental frequency in the output spectrum of the AD9834. Rev. C | Page 14 of 36 AD9834 THEORY OF OPERATION Sine waves are typically thought of in terms of their magnitude form a(t) = sin (ωt). However, these are nonlinear and not easy to generate except through piecewise construction. On the other hand, the angular information is linear in nature, that is, the phase angle rotates through a fixed angle for each unit of time. The angular rate depends on the frequency of the signal by the traditional rate of ω = 2πf. Knowing that the phase of a sine wave is linear and given a reference interval (clock period), the phase rotation for that period can be determined. ΔPhase = ωΔt Solving for ω, ω = ΔPhase/Δt = 2πf MAGNITUDE +1 0 Solving for f and substituting the reference clock frequency for the reference period (1/fMCLK = Δt), 6π 4π 2π f = ΔPhase × fMCLK/2π –1 2π PHASE 4π 6π 02705-025 2p 0 Figure 27. Sine Wave The AD9834 builds the output based on this simple equation. A simple DDS chip can implement this equation with three major subcircuits: numerically controlled oscillator + phase modulator, SIN ROM, and digital-to-analog converter (DAC). Each of these subcircuits is discussed in the Circuit Description section. Rev. C | Page 15 of 36 AD9834 CIRCUIT DESCRIPTION The AD9834 is a fully integrated direct digital synthesis (DDS) chip. The chip requires one reference clock, one low precision resistor, and eight decoupling capacitors to provide digitally created sine waves up to 37.5 MHz. In addition to the generation of this RF signal, the chip is fully capable of a broad range of simple and complex modulation schemes. These modulation schemes are fully implemented in the digital domain, allowing accurate and simple realization of complex modulation algorithms using DSP techniques. The internal circuitry of the AD9834 consists of the following main sections: a numerically controlled oscillator (NCO), frequency and phase modulators, SIN ROM, a DAC, a comparator, and a regulator. NUMERICALLY CONTROLLED OSCILLATOR PLUS PHASE MODULATOR This consists of two frequency select registers, a phase accumulator, two phase offset registers, and a phase offset adder. The main component of the NCO is a 28-bit phase accumulator. Continuous time signals have a phase range of 0 π to 2π. Outside this range of numbers, the sinusoid functions repeat themselves in a periodic manner. The digital implementation is no different. The accumulator simply scales the range of phase numbers into a multibit digital word. The phase accumulator in the AD9834 is implemented with 28 bits. Therefore, in the AD9834, 2π = 228. Likewise, the ΔPhase term is scaled into this range of numbers: 0 < ΔPhase < 228 − 1. Making these substitutions into the previous equation f = ΔPhase × fMCLK/228 where 0 < ΔPhase < 228 − 1. The input to the phase accumulator can be selected either from the FREQ0 register or FREQ1 register and is controlled by the FSELECT pin or the FSEL bit. NCOs inherently generate continuous phase signals, thus avoiding any output discontinuity when switching between frequencies. Following the NCO, a phase offset can be added to perform phase modulation using the 12-bit phase registers. The contents of one of these phase registers is added to the MSBs of the NCO. The AD9834 has two phase registers, the resolution of these registers being 2π/4096. SIN ROM To make the output from the NCO useful, it must be converted from phase information into a sinusoidal value. Phase information maps directly into amplitude; therefore, the SIN ROM uses the digital phase information as an address to a look-up table and converts the phase information into amplitude. Although the NCO contains a 28-bit phase accumulator, the output of the NCO is truncated to 12 bits. Using the full resolution of the phase accumulator is impractical and unnecessary because it requires a look-up table of 228 entries. It is necessary only to have sufficient phase resolution such that the errors due to truncation are smaller than the resolution of the 10-bit DAC. This requires the SIN ROM to have two bits of phase resolution more than the 10-bit DAC. The SIN ROM is enabled using the OPBITEN and MODE bits in the control register. This is explained further in Table 18. DIGITAL-TO-ANALOG CONVERTER (DAC) The AD9834 includes a high impedance current source 10-bit DAC capable of driving a wide range of loads. The full-scale output current can be adjusted for optimum power and external load requirements using a single external resistor (RSET). The DAC can be configured for either single-ended or differential operation. IOUT and IOUTB can be connected through equal external resistors to AGND to develop complementary output voltages. The load resistors can be any value required, as long as the full-scale voltage developed across it does not exceed the voltage compliance range. Because full-scale current is controlled by RSET, adjustments to RSET can balance changes made to the load resistors. COMPARATOR The AD9834 can be used to generate synthesized digital clock signals. This is accomplished by using the on-board self-biasing comparator that converts the sinusoidal signal of the DAC to a square wave. The output from the DAC can be filtered externally before being applied to the comparator input. The comparator reference voltage is the time average of the signal applied to VIN. The comparator can accept signals in the range of approximately 100 mV p-p to 1 V p-p. As the comparator input is ac-coupled, to operate correctly as a zero crossing detector, it requires a minimum input frequency of typically 3 MHz. The comparator output is a square wave with an amplitude from 0 V to DVDD. Rev. C | Page 16 of 36 AD9834 The AD9834 is a sampled signal with its output following Nyquist sampling theorem. Specifically, its output spectrum contains the fundamental plus aliased signals (images) that occur at multiples of the reference clock frequency and the selected output frequency. A graphical representation of the sampled spectrum, with aliased images, is shown in Figure 28. REGULATOR The AD9834 has separate power supplies for the analog and digital sections. AVDD provides the power supply required for the analog section, and DVDD provides the power supply for the digital section. Both of these supplies can have a value of 2.3 V to 5.5 V and are independent of each other. For example, the analog section can be operated at 5 V, and the digital section can be operated at 3 V, or vice versa. The prominence of the aliased images is dependent on the ratio of fOUT to MCLK. If ratio is small, the aliased images are very prominent and of a relatively high energy level as determined by the sin(x)/x roll-off of the quantized DAC output. In fact, depending on the fOUT/reference clock relationship, the first aliased image can be on the order of −3 dB below the fundamental. The internal digital section of the AD9834 is operated at 2.5 V. An on-board regulator steps down the voltage applied at DVDD to 2.5 V. The digital interface (serial port) of the AD9834 also operates from DVDD. These digital signals are level shifted within the AD9834 to make them 2.5 V compatible. A low-pass filter is generally placed between the output of the DAC and the input of the comparator to further suppress the effects of aliased images. Obviously, consideration must be given to the relationship of the selected output frequency and the reference clock frequency to avoid unwanted (and unexpected) output anomalies. To apply the AD9834 as a clock generator, limit the selected output frequency to <33% of reference clock frequency, and thereby avoid generating aliased signals that fall within, or close to, the output band of interest (generally dcselected output frequency). This practice eases the complexity (and cost) of the external filter requirement for the clock generator application. Refer to the AN-837 Application Note for more information. When the applied voltage at the DVDD pin of the AD9834 is equal to or less than 2.7 V, Pin CAP/2.5V and Pin DVDD should be tied together, thus bypassing the on-board regulator. OUTPUT VOLTAGE COMPLIANCE The AD9834 has a maximum current density, set by the RSET, of 4 mA. The maximum output voltage from the AD9834 is VDD − 1.5 V. This is to ensure that the output impedance of the internal switch does not change, affecting the spectral performance of the part. For a minimum supply of 2.3 V, the maximum output voltage is 0.8 V. Specifications in Table 1 are guaranteed with an RSET of 6.8 kΩ and an RLOAD of 200 Ω. To enable the comparator, Bit SIGN/PIB and Bit OPBITEN in the control resister are set to 1. This is explained further in Table 17. fOUT 0Hz fC – fOUT fC + fOUT 2fC – fOUT 2fC + fOUT fC 3fC – fOUT 2fC 3 fC FIRST IMAGE SECOND IMAGE THIRD IMAGE FOURTH IMAGE SYSTEM CLOCK FREQUENCY (Hz) Figure 28. The DAC Output Spectrum Rev. C | Page 17 of 36 FIFTH IMAGE 3fC + fOUT SIXTH IMAGE 02705-040 SIGNAL AMPLITUDE sin x/x ENVELOPE x = π (f/fC) AD9834 FUNCTIONAL DESCRIPTION SERIAL INTERFACE The AD9834 has a standard 3-wire serial interface that is compatible with SPI, QSPI™, MICROWIRE™, and DSP interface standards. Data is loaded into the device as a 16-bit word under the control of a serial clock input (SCLK). The timing diagram for this operation is given in Figure 5. For a detailed example of programming the AD9833 and AD9834 devices, refer to the AN-1070 Application Note. The FSYNC input is a level triggered input that acts as a frame synchronization and chip enable. Data can only be transferred into the device when FSYNC is low. To start the serial data transfer, FSYNC should be taken low, observing the minimum FSYNC-to-SCLK falling edge setup time (t7). After FSYNC goes low, serial data is shifted into the input shift register of the device on the falling edges of SCLK for 16 clock pulses. FSYNC can be taken high after the 16th falling edge of SCLK, observing the minimum SCLK falling edge to FSYNC rising edge time (t8). Alternatively, FSYNC can be kept low for a multiple of 16 SCLK pulses and then brought high at the end of the data transfer. In this way, a continuous stream of 16-bit words can be loaded while FSYNC is held low, with FSYNC only going high after the 16th SCLK falling edge of the last word is loaded. The SCLK can be continuous, or alternatively, the SCLK can idle high or low between write operations but must be high when FSYNC goes low (t12). POWERING UP THE AD9834 The flow chart in Figure 31 shows the operating routine for the AD9834. When the AD9834 is powered up, the part should be reset. This resets appropriate internal registers to 0 to provide an analog output of midscale. To avoid spurious DAC outputs during AD9834 initialization, the RESET bit/pin should be set to 1 until the part is ready to begin generating an output. RESET does not reset the phase, frequency, or control registers. These registers contain invalid data, and, therefore, should be set to a known value by the user. The RESET bit/pin should then be set to 0 to begin generating an output. The data appears on the DAC output eight MCLK cycles after RESET is set to 0. LATENCY Latency is associated with each operation. When Pin FSELECT and Pin PSELECT change value, there is a pipeline delay before control is transferred to the selected register. When the t11 and t11A timing specifications are met (see Figure 4), FSELECT and PSELECT have latencies of eight MCLK cycles. When the t11 and t11A timing specifications are not met, the latency is increased by one MCLK cycle. Similarly, there is a latency associated with each asynchronous write operation. If a selected frequency/phase register is loaded with a new word, there is a delay of eight to nine MCLK cycles before the analog output changes. There is an uncertainty of one MCLK cycle because it depends on the position of the MCLK rising edge when the data is loaded into the destination register. The negative transition of the RESET and SLEEP functions are sampled on the internal falling edge of MCLK. Therefore, they also have a latency associated with them. CONTROL REGISTER The AD9834 contains a 16-bit control register that sets up the AD9834 as the user wants to operate it. All control bits, except MODE, are sampled on the internal negative edge of MCLK. Table 6 describes the individual bits of the control register. The different functions and the various output options from the AD9834 are described in more detail in the Frequency and Phase Registers section. To inform the AD9834 that the contents of the control register are to be altered, DB15 and DB14 must be set to 0 as shown in Table 5. Table 5. Control Register DB15 0 Rev. C | Page 18 of 36 DB14 0 DB13 . . . DB0 CONTROL bits AD9834 SLEEP12 SLEEP1 PHASE ACCUMULATOR (28-BIT) SIN ROM 0 (LOW POWER) 10-BIT DAC MUX 1 MODE + OPBITEN 0 MUX IOUT IOUTB MSB COMPARATOR DIVIDE BY 2 1 1 MUX SIGN BIT OUT 02705-026 0 DIGITAL OUTPUT (ENABLE) VIN SIGN/PIB OPBITEN Figure 29. Function of Control Bits DB15 0 DB14 0 DB13 B28 DB12 HLB DB11 FSEL DB10 PSEL DB9 PIN/SW DB8 RESET DB7 SLEEP1 DB6 SLEEP12 DB5 OPBITEN DB4 SIGN/PIB DB3 DIV2 DB2 0 DB1 MODE DB0 0 Table 6. Description of Bits in the Control Register Bit DB13 Name B28 DB12 HLB DB11 FSEL DB10 PSEL DB9 PIN/SW DB8 RESET DB7 SLEEP1 DB6 SLEEP12 Description Two write operations are required to load a complete word into either of the frequency registers. B28 = 1 allows a complete word to be loaded into a frequency register in two consecutive writes. The first write contains the 14 LSBs of the frequency word and the next write contains the 14 MSBs. The first two bits of each 16-bit word define the frequency register the word is loaded to and should, therefore, be the same for both of the consecutive writes. Refer to Table 10 for the appropriate addresses. The write to the frequency register occurs after both words have been loaded. An example of a complete 28-bit write is shown in Table 11. Note however, that consecutive 28-bit writes to the same frequency register are not allowed, switch between frequency registers to do this type of function. B28 = 0, the 28-bit frequency register operates as two 14-bit registers, one containing the 14 MSBs and the other containing the 14 LSBs. This means that the 14 MSBs of the frequency word can be altered independent of the 14 LSBs, and vice versa. To alter the 14 MSBs or the 14 LSBs, a single write is made to the appropriate frequency address. The Control Bit DB12 (HLB) informs the AD9834 whether the bits to be altered are the 14 MSBs or 14 LSBs. This control bit allows the user to continuously load the MSBs or LSBs of a frequency register ignoring the remaining 14 bits. This is useful if the complete 28-bit resolution is not required. HLB is used in conjunction with DB13 (B28). This control bit indicates whether the 14 bits being loaded are being transferred to the 14 MSBs or 14 LSBs of the addressed frequency register. DB13 (B28) must be set to 0 to be able to change the MSBs and LSBs of a frequency word separately. When DB13 (B28) = 1, this control bit is ignored. HLB = 1 allows a write to the 14 MSBs of the addressed frequency register. HLB = 0 allows a write to the 14 LSBs of the addressed frequency register. The FSEL bit defines whether the FREQ0 register or the FREQ1 register is used in the phase accumulator. See Table 8 to select a frequency register. The PSEL bit defines whether the PHASE0 register data or the PHASE1 register data is added to the output of the phase accumulator. See Table 9 to select a phase register. Functions that select frequency and phase registers, reset internal registers, and power down the DAC can be implemented using either software or hardware. PIN/SW selects the source of control for these functions. PIN/SW = 1 implies that the functions are being controlled using the appropriate control pins. PIN/SW = 0 implies that the functions are being controlled using the appropriate control bits. RESET = 1 resets internal registers to 0, this corresponds to an analog output of midscale. RESET = 0 disables RESET. This function is explained in the RESET Function section. SLEEP1 = 1, the internal MCLK is disabled. The DAC output remains at its present value as the NCO is no longer accumulating. SLEEP1 = 0, MCLK is enabled. This function is explained in the SLEEP Function section. SLEEP12 = 1 powers down the on-chip DAC. This is useful when the AD9834 is used to output the MSB of the DAC data. SLEEP12 = 0 implies that the DAC is active. This function is explained in the SLEEP Function section. Rev. C | Page 19 of 36 AD9834 Bit DB5 Name OPBITEN DB4 SIGN/PIB DB3 DIV2 DB2 DB1 Reserved MODE DB0 Reserved Description The function of this bit is to control whether there is an output at the SIGN BIT OUT pin. This bit should remain at 0 if the user is not using the SIGN BIT OUT pin. OPBITEN = 1 enables the SIGN BIT OUT pin. OPBITEN = 0, the SIGN BIT OUT output buffer is put into a high impedance state, therefore no output is available at the SIGN BIT OUT pin. The function of this bit is to control what is output at the SIGN BIT OUT pin. SIGN/PIB = 1, the on-board comparator is connected to SIGN BIT OUT. After filtering the sinusoidal output from the DAC, the waveform can be applied to the comparator to generate a square waveform. Refer to Table 17. SIGN/PIB = 0, the MSB (or MSB/2) of the DAC data is connected to the SIGN BIT OUT pin. Bit DIV2 controls whether it is the MSB or MSB/2 that is output. DIV2 is used in association with SIGN/PIB and OPBITEN. Refer to Table 17. DIV2 = 1, the digital output is passed directly to the SIGN BIT OUT pin. DIV2 = 0, the digital output/2 is passed directly to the SIGN BIT OUT pin. This bit must always be set to 0. The function of this bit is to control what is output at the IOUT pin/IOUTB pin. This bit should be set to 0 if the Control Bit OPBITEN = 1. MODE = 1, the SIN ROM is bypassed, resulting in a triangle output from the DAC. MODE = 0, the SIN ROM is used to convert the phase information into amplitude information, resulting in a sinusoidal signal at the output. See Table 18. This bit must always be set to 0. FREQUENCY AND PHASE REGISTERS The AD9834 contains two frequency registers and two phase registers. These are described in Table 7. Table 7. Frequency/Phase Registers Register FREQ0 Size 28 bits FREQ1 28 bits PHASE0 12 bits PHASE1 12 bits Description Frequency Register 0. When either the FSEL bit or FSELECT pin = 0, this register defines the output frequency as a fraction of the MCLK frequency. Frequency Register 1. When either the FSEL bit or FSELECT pin = 1, this register defines the output frequency as a fraction of the MCLK frequency. Phase Offset Register 0. When either the PSEL bit or PSELECT pin = 0, the contents of this register are added to the output of the phase accumulator. Phase Offset Register 1. When either the PSEL bit or PSELECT pin = 1, the contents of this register are added to the output of the phase accumulator. The analog output from the AD9834 is fMCLK/228 × FREQREG where FREQREG is the value loaded into the selected frequency register. This signal is phase shifted by 2π/4096 × PHASEREG where PHASEREG is the value contained in the selected phase register. Consideration must be given to the relationship of the selected output frequency and the reference clock frequency to avoid unwanted output anomalies. Access to the frequency and phase registers is controlled by both the FSELECT and PSELECT pins, and the FSEL and PSEL control bits. If the Control Bit PIN/SW = 1, the pins control the function; whereas, if PIN/SW = 0, the bits control the function. This is outlined in Table 8 and Table 9. If the FSEL and PSEL bits are used, the pins should be held at CMOS logic high or low. Control of the frequency/phase registers is interchangeable from the pins to the bits. Table 8. Selecting a Frequency Register FSELECT 0 1 X X FSEL X X 0 1 PIN/SW 1 1 0 0 Selected Register FREQ0 REG FREQ1 REG FREQ0 REG FREQ1 REG Table 9. Selecting a Phase Register PSELECT 0 1 X X PSEL X X 0 1 PIN/SW 1 1 0 0 Selected Register PHASE0 REG PHASE1 REG PHASE0 REG PHASE1 REG The FSELECT pin and PSELECT pin are sampled on the internal falling edge of MCLK. It is recommended that the data on these pins does not change within a time window of the falling edge of MCLK (see Figure 4 for timing). If FSELECT or PSELECT changes value when a falling edge occurs, there is an uncertainty of one MCLK cycle because it pertains to when control is transferred to the other frequency/phase register. The flow charts in Figure 32 and Figure 33 show the routine for selecting and writing to the frequency and phase registers of the AD9834. Rev. C | Page 20 of 36 AD9834 WRITING TO A FREQUENCY REGISTER Table 13. Writing 00FF to the 14 MSBs of FREQ0 REG When writing to a frequency register, Bit DB15 and Bit DB14 give the address of the frequency register. SDATA Input 0001 0000 0000 0000 Table 10. Frequency Register Bits DB15 0 1 DB14 1 0 DB13 . . . DB0 14 FREQ0 REG BITS 14 FREQ1 REG BITS 0100 0000 1111 1111 If the user wants to alter the entire contents of a frequency register, two consecutive writes to the same address must be performed because the frequency registers are 28 bits wide. The first write contains the 14 LSBs, and the second write contains the 14 MSBs. For this mode of operation, Control Bit B28 (DB13) should be set to 1. An example of a 28-bit write is shown in Table 11. Note however that continuous writes to the same frequency register are not recommended. This results in intermediate updates during the writes. If a frequency sweep, or something similar, is required, it is recommended that users alternate between the two frequency registers. Table 11. Writing FFFC000 to FREQ0 REG SDATA Input 0010 0000 0000 0000 0100 0000 0000 0000 0111 1111 1111 1111 Result of Input Word Control word write (DB15, DB14 = 00), B28 (DB13) = 1, HLB (DB12) = X FREQ0 REG write (DB15, DB14 = 01), 14 LSBs = 0000 FREQ0 REG write (DB15, DB14 = 01), 14 MSBs = 3FFF In some applications, the user does not need to alter all 28 bits of the frequency register. With coarse tuning, only the 14 MSBs are altered; though with fine tuning only the 14 LSBs are altered. By setting Control Bit B28 (DB13) to 0, the 28-bit frequency register operates as two 14-bit registers, one containing the 14 MSBs and the other containing the 14 LSBs. This means that the 14 MSBs of the frequency word can be altered independent of the 14 LSBs, and vice versa. Bit HLB (DB12) in the control register identifies the 14 bits that are being altered. Examples of this are shown in Table 12 and Table 13. Table 12. Writing 3FFF to the 14 LSBs of FREQ1 REG SDATA Input 0000 0000 0000 0000 1011 1111 1111 1111 Result of Input Word Control word write (DB15, DB14 = 00), B28 (DB13) = 0, HLB (DB12) = 0, that is, LSBs FREQ1 REG write (DB15, DB14 = 10), 14 LSBs = 3FFF Result of Input Word Control word write (DB15, DB14 = 00), B28 (DB13) = 0, HLB (DB12) = 1, that is, MSBs FREQ0 REG write (DB15, DB14 = 01), 14 MSBs = 00FF WRITING TO A PHASE REGISTER When writing to a phase register, Bit DB15 and Bit DB14 are set to 11. Bit DB13 identifies which phase register is being loaded. Table 14. Phase Register Bits DB15 1 1 DB14 1 1 DB13 0 1 DB12 X X DB11 MSB 12 PHASE0 bits MSB 12 PHASE1 bits DB0 LSB LSB RESET FUNCTION The RESET function resets appropriate internal registers to 0 to provide an analog output of midscale. RESET does not reset the phase, frequency, or control registers. When the AD9834 is powered up, the part should be reset. To reset the AD9834, set the RESET pin/bit to 1. To take the part out of reset, set the pin/bit to 0. A signal appears at the DAC output seven MCLK cycles after RESET is set to 0. The RESET function is controlled by both the RESET pin and the RESET control bit. If the Control Bit PIN/SW = 0, the RESET bit controls the function, whereas if PIN/SW = 1, the RESET pin controls the function. Table 15. Applying RESET RESET Pin 0 1 X X RESET Bit X X 0 1 PIN/SW Bit 1 1 0 0 Result No reset applied Internal registers reset No reset applied Internal registers reset The effect of asserting the RESET pin is evident immediately at the output, that is, the zero-to-one transition of this pin is not sampled. However, the negative transition of RESET is sampled on the internal falling edge of MCLK. SLEEP FUNCTION Sections of the AD9834 that are not in use can be powered down to minimize power consumption by using the SLEEP function. The parts of the chip that can be powered down are the internal clock and the DAC. The DAC can be powered down through hardware or software. The pin/bits required for the SLEEP function are outlined in Table 16. Rev. C | Page 21 of 36 AD9834 from the DAC, the waveform can be applied to the comparator to generate a square waveform. Table 16. Applying the SLEEP Function SLEEP Pin 0 1 SLEEP1 Bit X X SLEEP12 Bit X X PIN/SW Bit 1 1 X X 0 0 0 1 0 0 X 1 0 0 X 1 1 0 Result No power-down DAC powered down No power-down DAC powered down Internal clock disabled MSB from the NCO Both the DAC powered down and the internal clock disabled OPBITEN Bit 0 1 1 1 1 1 DAC Powered Down This is useful when the AD9834 is used to output the MSB of the DAC data only. In this case, the DAC is not required and can be powered down to reduce power consumption. Internal Clock Disabled The MSB from the NCO can be output from the AD9834. By setting the SIGN/PIB (DB4) control bit to 0, the MSB of the DAC data is available at the SIGN BIT OUT pin. This is useful as a coarse clock source. This square wave can also be divided by two before being output. Bit DIV2 (DB3) in the control register controls the frequency of this output from the SIGN BIT OUT pin. Table 17. Various Outputs from SIGN BIT OUT MODE Bit X 0 0 0 0 1 SIGN/PIB Bit X 0 0 1 1 X DIV2 Bit X 0 1 0 1 X SIGN BIT OUT Pin High impedance DAC data MSB/2 DAC data MSB Reserved Comparator output Reserved THE IOUT AND IOUTB PINS When the internal clock of the AD9834 is disabled, the DAC output remains at its present value because the NCO is no longer accumulating. New frequency, phase, and control words can be written to the part when the SLEEP1 control bit is active. The synchronizing clock remains active, meaning that the selected frequency and phase registers can also be changed either at the pins or by using the control bits. Setting the SLEEP1 bit to 0 enables the MCLK. Any changes made to the registers when SLEEP1 is active are observed at the output after a certain latency. The effect of asserting the SLEEP pin is evident immediately at the output, that is, the zero-to-one transition of this pin is not sampled. However, the negative transition of SLEEP is sampled on the internal falling edge of MCLK. SIGN BIT OUT PIN The AD9834 offers a variety of outputs from the chip. The digital outputs are available from the SIGN BIT OUT pin. The available outputs are the comparator output or the MSB of the DAC data. The bits controlling the SIGN BIT OUT pin are outlined in Table 17. This pin must be enabled before use. The enabling/disabling of this pin is controlled by the Bit OPBITEN (DB5) in the control register. When OPBITEN = 1, this pin is enabled. Note that the MODE bit (DB1) in the control register should be set to 0 if OPBITEN = 1. The analog outputs from the AD9834 are available from the IOUT and IOUTB pins. The available outputs are a sinusoidal output or a triangle output. Sinusoidal Output The SIN ROM converts the phase information from the frequency and phase registers into amplitude information, resulting in a sinusoidal signal at the output. To have a sinusoidal output from the IOUT and IOUTB pins, set Bit MODE (DB1) to 0. Triangle Output The SIN ROM can be bypassed so that the truncated digital output from the NCO is sent to the DAC. In this case, the output is no longer sinusoidal. The DAC produces 10-bit linear triangular function. To have a triangle output from the IOUT and IOUTB pins, set Bit MODE (DB1) to 1. Note that the SLEEP pin and SLEEP12 bit must be 0 (that is, the DAC is enabled) when using the IOUT and IOUTB pins. Table 18. Various Outputs from IOUT and IOUTB OPBITEN Bit 0 0 1 1 MODE Bit 0 1 0 1 IOUT and IOUTB Pins Sinusoid Triangle Sinusoid Reserved VOUT MAX The AD9834 has an on-board comparator. To connect this comparator to the SIGN BIT OUT pin, the SIGN/PIB (DB4) control bit must be set to 1. After filtering the sinusoidal output VOUT MIN Rev. C | Page 22 of 36 3π/2 7π/2 Figure 30. Triangle Output 11π/2 02705-027 Comparator Output AD9834 APPLICATIONS INFORMATION pin, causing the AD9834 to modulate the carrier frequency between the two values. Because of the various output options available from the part, the AD9834 can be configured to suit a wide variety of applications. The AD9834 has two phase registers, enabling the part to perform PSK. With phase shift keying, the carrier frequency is phase shifted, the phase being altered by an amount that is related to the bit stream that is input to the modulator. One of the areas where the AD9834 is suitable is in modulation applications. The part can be used to perform simple modulation such as FSK. More complex modulation schemes such as GMSK and QPSK can also be implemented using the AD9834. The AD9834 is also suitable for signal generator applications. With the on-board comparator, the device can be used to generate a square wave. In an FSK application, the two frequency registers of the AD9834 are loaded with different values. One frequency represents the space frequency, and the other represents the mark frequency. The digital data stream is fed to the FSELECT With its low current consumption, the part is suitable for applications where it is used as a local oscillator. DATA WRITE SEE FIGURE 33 SELECT DATA SOURCES SEE FIGURE 34 WAIT 8/9 MCLK CYCLES SEE TIMING DIAGRAM FIGURE 3 INITIALIZATION SEE FIGURE 32 DAC OUTPUT VOUT = VREFOUT × 18 × RLOAD/RSET × (1 + (SIN(2π(FREQREG × fMCLK × t/228 + PHASEREG/212)))) YES CHANGE PHASE? NO CHANGE FSEL/ FSELECT? YES NO YES CHANGE FREQUENCY? NO YES NO CHANGE PHASE REGISTER? YES CHANGE DAC OUTPUT FROM SIN TO RAMP? CHANGE FREQUENCY REGISTER? YES NO CONTROL REGISTER WRITE YES CHANGE OUTPUT AT SIGN BIT OUT PIN? NO Figure 31. Flow Chart for Initialization and Operation Rev. C | Page 23 of 36 02705-028 YES CHANGE PSEL/ PSELECT? AD9834 INITIALIZATION APPLY RESET USING PIN USING CONTROL BIT (CONTROL REGISTER WRITE) (CONTROL REGISTER WRITE) RESET = 1 PIN/SW = 0 PIN/SW = 1 SET RESET PIN = 1 WRITE TO FREQUENCY AND PHASE REGISTERS FREQ0 REG = fOUT0/fMCLK × 228 FREQ1 REG = fOUT1/fMCLK × 228 PHASE0 AND PHASE1 REG = (PHASESHIFT × 2 12)/2π (SEE FIGURE 33) SET RESET = 0 SELECT FREQUENCY REGISTERS SELECT PHASE REGISTERS USING PIN (CONTROL REGISTER WRITE) (APPLY SIGNALS AT PINS) RESET BIT = 0 FSEL = SELECTED FREQUENCY REGISTER PSEL = SELECTED PHASE REGISTER PIN/SW = 0 RESET PIN = 0 FSELECT = SELECTED FREQUENCY REGISTER PSELECT = SELECTED PHASE REGISTER 02705-029 USING CONTROL BIT Figure 32. Initialization DATA WRITE WRITE A FULL 28-BIT WORD TO A FREQUENCY REGISTER? YES (CONTROL REGISTER WRITE) B28 (D13) = 1 NO WRITE 14 MSBs OR LSBs TO A FREQUENCY REGISTER? NO WRITE TO PHASE REGISTER? YES YES (CONTROL REGISTER WRITE) B28 (D13) = 0 HLB (D12) = 0/1 (16-BIT WRITE) (SEE TABLE 11 FOR EXAMPLE) YES WRITE ANOTHER FULL 28-BIT TO A FREQUENCY REGISTER? NO WRITE A 16-BIT WORD (SEE TABLES 12 AND 13 FOR EXAMPLES) WRITE 14 MSBs OR LSBs TO A FREQUENCY REGISTER? NO Figure 33. Data Write Rev. C | Page 24 of 36 YES WRITE TO ANOTHER PHASE REGISTER? NO YES 02705-030 WRITE TWO CONSECUTIVE 16-BIT WORDS D15, D14 = 11 D13 = 0/1 (CHOOSE THE PHASE REGISTER) D12 = X D11 ... D0 = PHASE DATA AD9834 SELECT DATA SOURCES FSELECT AND PSELECT PINS BEING USED? YES SET FSELECT AND PSELECT NO (CONTROL REGISTER WRITE) (CONTROL REGISTER WRITE) PIN/SW = 1 02705-031 PIN/SW = 0 SET FSEL BIT SET PSEL BIT Figure 34. Selecting Data Sources Rev. C | Page 25 of 36 AD9834 GROUNDING AND LAYOUT The printed circuit board (PCB) that houses the AD9834 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can easily be separated. A minimum etch technique is generally best for ground planes because it gives the best shielding. Digital and analog ground planes should only be joined in one place. If the AD9834 is the only device requiring an AGND-to-DGND connection, the ground planes should be connected at the AGND and DGND pins of the AD9834. If the AD9834 is in a system where multiple devices require AGND-to-DGND connections, the connection should be made at one point only, establishing a star ground point as close as possible to the AD9834. Avoid running digital lines under the device because these couple noise onto the die. The analog ground plane should be allowed to run under the AD9834 to avoid noise coupling. The power supply lines to the AD9834 should use as large a track as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other to reduce the effects of feedthrough through the board. A microstrip technique is by far the best, but it is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes and signals are placed on the other side. Good decoupling is important. The analog and digital supplies to the AD9834 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. All analog and digital supplies should be decoupled to AGND and DGND, respectively, with 0.1 μF ceramic capacitors in parallel with 10 μF tantalum capacitors. To achieve the best performance from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. In systems where a common supply is used to drive both the AVDD and DVDD of the AD9834, it is recommended that the system’s AVDD supply be used. This supply should have the recommended analog supply decoupling between the AVDD pins of the AD9834 and AGND, and the recommended digital supply decoupling capacitors between the DVDD pins and DGND. Proper operation of the comparator requires good layout strategy. The strategy must minimize the parasitic capacitance between VIN and the SIGN BIT OUT pin by adding isolation using a ground plane. For example, in a multilayered board, the VIN signal could be connected to the top layer, and the SIGN BIT OUT could be connected to the bottom layer so that isolation is provided by the power and ground planes between them. Rev. C | Page 26 of 36 AD9834 INTERFACING TO MICROPROCESSORS The AD9834 has a standard serial interface that allows the part to interface directly with several microprocessors. The device uses an external serial clock to write the data/control information into the device. The serial clock can have a frequency of 40 MHz maximum. The serial clock can be continuous, or it can idle high or low between write operations. When data/control information is being written to the AD9834, FSYNC is taken low and is held low until the 16 bits of data are written into the AD9834. The FSYNC signal frames the 16 bits of information being loaded into the AD9834. AD9834 TO 68HC11/68L11 INTERFACE Figure 36 shows the serial interface between the AD9834 and the 68HC11/68L11 microcontroller. The microcontroller is configured as the master by setting Bit MSTR in the SPCR to 1, providing a serial clock on SCK while the MOSI output drives the serial data line SDATA. Because the microcontroller does not have a dedicated frame sync pin, the FSYNC signal is derived from a port line (PC7). The setup conditions for correct operation of the interface are as follows: • SCK idles high between write operations (CPOL = 0) Figure 35 shows the serial interface between the AD9834 and the ADSP-21xx. The ADSP-21xx should be set up to operate in the SPORT transmit alternate framing mode (TFSW = 1). The ADSP-21xx is programmed through the SPORT control register and should be configured as follows: • Internal clock operation (ISCLK = 1) • Active low framing (INVTFS = 1) • 16-bit word length (SLEN = 15) • Data is valid on the SCK falling edge (CPHA = 1) When data is being transmitted to the AD9834, the FSYNC line is taken low (PC7). Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data into the AD9834, PC7 is held low after the first eight bits are transferred and a second serial write operation is performed to the AD9834. Only after the second eight bits have been transferred should FSYNC be taken high again. 68HC11/68L111 • Internal frame sync signal (ITFS = 1) • Generate a frame sync for each write (TFSR = 1) Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. The data is clocked out on each rising edge of the serial clock and clocked into the AD9834 on the SCLK falling edge. TFS FSYNC DT SDATA SCLK SCLK 1ADDITIONAL PINS OMITTED FOR CLARITY. PC7 FSYNC MOSI SDATA SCK SCLK 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 36. 68HC11/68L11 to AD9834 Interface AD98341 02705-032 ADSP-21xx1 AD98341 Figure 35. ADSP-21xx to AD9834 Interface Rev. C | Page 27 of 36 02705-033 AD9834 TO ADSP-21xx INTERFACE AD9834 AD9834 TO 80C51/80L51 INTERFACE AD9834 TO DSP56002 INTERFACE Figure 37 shows the serial interface between the AD9834 and the 80C51/80L51 microcontroller. The microcontroller is operated in Mode 0 so that TXD of the 80C51/80L51 drives SCLK of the AD9834, and RXD drives the serial data line (SDATA). The FSYNC signal is derived from a bit programmable pin on the port (P3.3 is shown in the diagram). When data is to be transmitted to the AD9834, P3.3 is taken low. The 80C51/80L51 transmits data in 8-bit bytes, thus only eight falling SCLK edges occur in each cycle. To load the remaining eight bits to the AD9834, P3.3 is held low after the first eight bits have been transmitted, and a second write operation is initiated to transmit the second byte of data. P3.3 is taken high following the completion of the second write operation. SCLK should idle high between the two write operations. The 80C51/80L51 outputs the serial data in an LSBfirst format. The AD9834 accepts the MSB first (the four MSBs being the control information, the next four bits being the address, and the eight LSBs containing the data when writing to a destination register). Therefore, the transmit routine of the 80C51/80L51 must take this into account and rearrange the bits so that the MSB is output first. Figure 38 shows the interface between the AD9834 and the DSP56002. The DSP56002 is configured for normal mode asynchronous operation with a gated internal clock (SYN = 0, GCK = 1, SCKD = 1). The frame sync pin is generated internally (SC2 = 1), the transfers are 16 bits wide (WL1 = 1, WL0 = 0), and the frame sync signal frames the 16 bits (FSL = 0). The frame sync signal is available on Pin SC2, but needs to be inverted before being applied to the AD9834. The interface to the DSP56000/ DSP56001 is similar to that of the DSP56002. AD98341 P3.3 FSYNC RXD SDATA TXD SCLK 1ADDITIONAL PINS OMITTED FOR CLARITY. 02705-034 80C51/80L511 Figure 37. 80C51/80L51 to AD9834 Interface Rev. C | Page 28 of 36 AD98341 SC2 FSYNC STD SDATA SCK SCLK 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 38. DSP56002 to AD9834 Interface 02705-035 DSP560021 AD9834 EVALUATION BOARD SYSTEM DEVELOPMENT PLATFORM The system development platform (SDP) is a hardware and software evaluation tool for use in conjunction with product evaluation boards. The SDP board is based on the Blackfin® BF527 processor with USB connectivity to the PC through a USB 2.0 high speed port. For more information about this device, go to: www.analog.com/en/embedded-processingdsp/blackfin/bf527sdp-hw/processors/product.html. Note that the SDP board is sold separately from the AD9834 evaluation board. AD9834 TO SPORT INTERFACE 02705-042 The Analog Devices SDP board has a SPORT serial port that is used to control the serial inputs to the AD9834 . The connections are shown in Figure 39. Figure 40. AD9834 Evaluation Software AD9834 SPORT_DTO FSYNC The DDS evaluation kit includes a populated, tested AD9834 PCB. Software is available with the evaluation board that allows the user to easily program the AD9834. The schematics of the AD9834 evaluation board are shown in Figure 41 and Figure 42. The software runs on any IBM-compatible PC that has Microsoft® Windows® 95, Windows 98, Windows ME, Windows 2000 NT®, or Windows 7 installed. SCLK SDATA ADSP-BF527 02705-041 SPORT_TFS SPORT_TSCLK Figure 39. SDP to AD9834 Interface The AD9834 evaluation board allows designers to evaluate the high performance AD9834 DDS modulator with a minimum of effort. The GUI interface for the AD9834 evaluation board is shown in Figure 40. Additional details can be found in the EVAL-AD9834EB data sheet that is available on the software CD and the AD9834 product page. XO vs. EXTERNAL CLOCK The AD9834 can operate with master clocks up to 75 MHz. A 75 MHz general oscillator is included on the evaluation board. However, this oscillator can be removed and, if required, an external CMOS clock can be connected to the part. Two options for the general oscillator are: • AEL 301 series crystals oscillators, AEL Crystals, Ltd. • SG-310SCN oscillators, Epson Toyocom Corporation POWER SUPPLY Power to the AD9834 evaluation board can be provided from USB connector or externally through pin connections. The power leads should be twisted to reduce ground loops. Rev. C | Page 29 of 36 AD9834 EVALUATION BOARD SCHEMATICS 02705-043 Figure 41. AD9834 Evaluation Board Schematic, Part A Rev. C | Page 30 of 36 AD9834 02705-044 Figure 42. AD9834 Evaluation Board Schematic, Part B—J1 Header Connector Rev. C | Page 31 of 36 AD9834 02705-045 EVALUATION BOARD LAYOUT Figure 43. AD9834 Evaluation Board Component Side Rev. C | Page 32 of 36 02705-046 AD9834 Figure 44. AD9834 Evaluation Board Silkscreen Rev. C | Page 33 of 36 02705-047 AD9834 Figure 45. AD9834 Evaluation Board Solder Side Rev. C | Page 34 of 36 AD9834 OUTLINE DIMENSIONS 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 8° 0° SEATING PLANE 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 46. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2 AD9834BRU AD9834BRU-REEL AD9834BRU-REEL7 AD9834BRUZ AD9834BRUZ-REEL AD9834BRUZ-REEL7 AD9834CRUZ AD9834CRUZ-REEL7 EVAL-AD9834SDZ 1 2 Maximum MCLK (MHz) 50 50 50 50 50 50 75 75 75 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] Evaluation Board (To Be Used in Conjunction with a SDP Board) Z = RoHS Compliant Part. For the EVAL-AD9834SDZ, a SDP board is required. Rev. C | Page 35 of 36 Package Option RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 AD9834 NOTES ©2003–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02705-0-2/11(C) Rev. C | Page 36 of 36