FDMS86102LZ N-Channel Power Trench® MOSFET 100 V, 22 A, 25 mΩ Features General Description Max rDS(on) = 25 mΩ at VGS = 10 V, ID = 7 A This N-Channel logic Level MOSFETs are produced using Fairchild Semiconductor's advanced Power Trench® process that has been special tailored to minimize the on-state resistance and yet maintain superior switching performance. G-S zener has been added to enhance ESD voltage level. Max rDS(on) = 37 mΩ at VGS = 4.5 V, ID = 5.8 A HBM ESD protection level > 6 KV typical (Note 4) 100% UIL Tested RoHS Compliant Applications DC - DC Conversion Inverter Synchronous Rectifier Bottom Top Pin 1 S D D D S S G D 5 4 G D 6 3 S D 7 2 S D 8 1 S D Power 56 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage Drain Current -Continuous (Package limited) ID TC = 25 °C -Continuous (Silicon limited) TC = 25 °C -Continuous TA = 25 °C PD TJ, TSTG Units V ±20 V 22 37 (Note 1a) -Pulsed 7 A 40 Single Pulse Avalanche Energy EAS Ratings 100 (Note 3) Power Dissipation TC = 25 °C Power Dissipation TA = 25 °C 84 69 (Note 1a) Operating and Storage Junction Temperature Range 2.5 -55 to +150 mJ W °C Thermal Characteristics RθJC Thermal Resistance, Junction to Case RθJA Thermal Resistance, Junction to Ambient 1.8 (Note 1a) 50 °C/W Package Marking and Ordering Information Device Marking FDMS86102Z Device FDMS86102LZ ©2011 Fairchild Semiconductor Corporation FDMS86102LZ Rev.C Package Power 56 1 Reel Size 13 ’’ Tape Width 12 mm Quantity 3000 units www.fairchildsemi.com FDMS86102LZ N-Channel Power Trench® MOSFET May 2011 Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±10 μA 2.5 V 100 V 70 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C VGS = 10 V, ID = 7 A 18.6 rDS(on) Static Drain to Source On Resistance VGS = 4.5 V, ID = 5.8 A 23.5 37 VGS = 10 V, ID = 7 A, TJ = 125 °C 31.2 42 gFS Forward Transconductance 1.0 1.5 -6 mV/°C 25 mΩ VDS = 5 V, ID = 7 A 26 S VDS = 50 V, VGS = 0 V, f = 1 MHz 979 1305 pF 175 235 pF 8.9 15 pF Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance Ω 0.9 Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time Qg(TOT) Total Gate Charge VGS = 0 V to 10 V Qg(TOT) Total Gate Charge VGS = 0 V to 4.5 V Qgs Total Gate Charge Qgd Gate to Drain “Miller” Charge VDD = 50 V, ID = 7 A, VGS = 10 V, RGEN = 6 Ω VDD = 50 V, ID = 7 A 6.7 14 2.6 10 ns ns 19 35 ns 2.5 10 ns 16 22 nC 7.8 11 nC 2.4 nC 2.6 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 7 A (Note 2) 0.81 1.3 VGS = 0 V, IS = 2 A (Note 2) 0.72 1.2 IF = 7 A, di/dt = 100 A/μs V 35 57 ns 25 40 nC NOTES: 1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. a. 50 °C/W when mounted on a 1 in2 pad of 2 oz copper b. 125 °C/W when mounted on a minimum pad of 2 oz copper 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3. Starting TJ = 25 °C; N-ch: L = 1 mH, IAS = 13 A, VDD = 90 V, VGS = 10 V. 4. The diode connected between gate and source serves only as protection against ESD. No gate overvoltage rating is implied. ©2011 Fairchild Semiconductor Corporation FDMS86102LZ Rev. C 2 www.fairchildsemi.com FDMS86102LZ N-Channel Power Trench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted 40 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 6 ID, DRAIN CURRENT (A) VGS = 3.5 V 30 VGS = 10 V PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 4.5 V 20 VGS = 3 V 10 VGS = 2.5 V 0 0 1 2 3 4 5 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 5 VGS = 2.5 V 4 VGS = 3 V 3 VGS = 3.5 V 2 VGS = 4.5 V 1 VGS = 10 V 0 0 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 1. On-Region Characteristics 40 100 ID = 7 A 1.8 VGS = 10 V rDS(on), DRAIN TO 1.6 1.4 1.2 1.0 0.8 0.6 -75 -50 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 30 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 2.0 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX ID = 7 A 80 60 TJ = 125 oC 40 20 0 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) TJ = 25 oC 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On-Resistance vs Junction Temperature Figure 4. On-Resistance vs Gate to Source Voltage 40 IS, REVERSE DRAIN CURRENT (A) 40 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX ID, DRAIN CURRENT (A) 20 ID, DRAIN CURRENT (A) 30 VDS = 5 V 20 TJ = 150 oC TJ = 25 oC 10 TJ = -55 oC 0 1.0 1.5 2.0 2.5 3.0 3.5 TJ = 150 oC 1 TJ = 25 oC 0.1 TJ = -55 oC 0.01 0.001 0.0 4.0 VGS, GATE TO SOURCE VOLTAGE (V) 0.2 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics ©2011 Fairchild Semiconductor Corporation FDMS86102LZ Rev. C VGS = 0 V 10 Figure 6. Source to Drain Diode Forward Voltage vs Source Current 3 www.fairchildsemi.com FDMS86102LZ N-Channel Power Trench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted 5000 ID = 7 A Ciss VDD = 50 V 1000 8 VDD = 25 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 75 V 6 4 Coss 100 Crss 10 2 f = 1 MHz VGS = 0 V 0 0 4 8 12 1 0.1 16 1 Figure 7. Gate Charge Characteristics 100 Figure 8. Capacitance vs Drain to Source Voltage 40 ID, DRAIN CURRENT (A) 50 IAS, AVALANCHE CURRENT (A) 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) TJ = 25 oC 10 TJ = 100 oC TJ = 125 oC 32 24 VGS = 10 V 16 VGS = 4.5 V Limited by Package 8 o RθJC = 1.8 C/W 1 0.001 0.01 0.1 1 0 25 10 20 50 75 100 125 150 o TC, CASE TEMPERATURE ( C) tAV, TIME IN AVALANCHE (ms) Figure 9. Unclamped Inductive Switching Capability Figure 10. Maximum Continuous Drain Current vs Case Temperature -1 50 VDS = 0 V -2 10 -3 ID, DRAIN CURRENT (A) Ig, GATE LEAKAGE CURRENT (A) 10 10 -4 10 TJ = 125 oC -5 10 -6 10 TJ = 25 oC -7 10 10 100 us 1 ms 1 0.1 -8 10 0.01 0.005 0.01 -9 10 0 4 8 12 16 20 24 28 32 100 ms SINGLE PULSE TJ = MAX RATED 1s RθJA = 125 oC/W 10 s TA = 25 oC 0.1 1 DC 10 100 500 VDS, DRAIN to SOURCE VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V) Figure 11. Gate Leakage Current vs Gate to Source Voltage ©2011 Fairchild Semiconductor Corporation FDMS86102LZ Rev. C 10 ms THIS AREA IS LIMITED BY rDS(on) Figure 12. Forward Bias Safe Operating Area 4 www.fairchildsemi.com FDMS86102LZ N-Channel Power Trench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted P(PK), PEAK TRANSIENT POWER (W) 1000 100 10 SINGLE PULSE o RθJA = 125 C/W o TA = 25 C 1 0.5 -4 10 -3 -2 10 -1 10 10 1 100 10 1000 t, PULSE WIDTH (sec) Figure 13. Single Pulse Maximum Power Dissipation 2 DUTY CYCLE-DESCENDING ORDER NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 125 C/W 0.001 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 14. Junction-to-Ambient Transient Thermal Response Curve ©2011 Fairchild Semiconductor Corporation FDMS86102LZ Rev. C 5 www.fairchildsemi.com FDMS86102LZ N-Channel Power Trench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted FDMS86102LZ N-Channel Power Trench® MOSFET Dimensional Outline and Pad Layout ©2011 Fairchild Semiconductor Corporation FDMS86102LZ Rev. C 6 www.fairchildsemi.com tm tm tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. 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Preliminary First Production Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I54 ©2011 Fairchild Semiconductor Corporation FDMS86102LZ Rev.C 7 www.fairchildsemi.com FDMS86102LZ N-Channel Power Trench® MOSFET TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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