[ /Title (CD74H C40103, CD74H CT4010 3) /Subject (High Speed CMOS Logic 8- CD54HC40103, CD74HC40103, CD74HCT40103 Data sheet acquired from Harris Semiconductor SCHS221D High-Speed CMOS Logic 8-Stage Synchronous Down Counters November 1997 - Revised October 2003 Features Description • Synchronous or Asynchronous Preset The ’HC40103 and CD74HCT40103 are manufactured with high speed silicon gate technology and consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The 40103 contains a single 8-bit binary counter. Each has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the TC output are active-low logic. • Cascadable in Synchronous or Ripple Mode • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times In normal operation, the counter is decremented by one count on each positive transition of the CLOCK (CP). Counting is inhibited when the TE input is high. The TC output goes low when the count reaches zero if the TE input is low, and remains low for one full clock period. • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V When the PE input is low, data at the P0-P7 inputs are clocked into the counter on the next positive clock transition regardless of the state of the TE input. When the PL input is low, data at the P0-P7 inputs are asynchronously forced into the counter regardless of the state of the PE, TE, or CLOCK inputs. Input P0-P7 represent a single 8-bit binary word for the 40103. When the MR input is low, the counter is asynchronously cleared to its maximum count of 25510, regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth table. • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Ordering Information TEMP. RANGE (oC) PACKAGE CD54HC40103F3A -55 to 125 16 Ld CERDIP CD74HC40103E -55 to 125 16 Ld PDIP CD74HC40103M -55 to 125 16 Ld SOIC CD74HC40103MT -55 to 125 16 Ld SOIC CD74HC40103M96 -55 to 125 16 Ld SOIC CD74HCT40103E -55 to 125 16 Ld PDIP CD74HCT40103M -55 to 125 16 Ld SOIC CD74HCT40103MT -55 to 125 16 Ld SOIC CD74HCT40103M96 -55 to 125 16 Ld SOIC PART NUMBER If all control inputs except TE are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 10016 or 25610 clock pulses long. The 40103 may be cascaded using the TE input and the TC output, in either a synchronous or ripple mode. These circuits possess the low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL circuits and can drive up to 10 LSTTL loads. NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD54HC40103, CD74HC40103, CD74HCT40103 Pinout CD54HC40103 (CERDIP) CD74HC40103, CD74HCT40103 (PDIP, SOIC) TOP VIEW CP 1 16 VCC MR 2 15 PE (SYNC) TE 3 14 TC P0 4 13 P7 P1 5 12 P6 P2 6 11 P5 P3 7 10 P4 9 PL (ASYNC) GND 8 Functional Diagram TC 14 13 12 11 10 7 6 5 P7 P6 P5 P4 P3 P2 P1 P0 15 9 3 1 2 VCC GND MR TE CP PL PE 4 16 8 TRUTH TABLE CONTROL INPUTS MR PL PE TE PRESET MODE 1 1 1 1 Synchronous 1 1 1 0 Count Down 1 1 0 X Preset On Next Positive Clock Transition 1 0 X X 0 X X X Asynchronously ACTION Inhibit Counter Preset Asychronously Clear to Maximum Count 1 = High Level. 0 = Low Level. X = Don’t Care. Clock connected to clock input. Synchronous Operation: changes occur on negative-to-positive clock transitions. Load Inputs: MSB = P7, LSB = P0. 2 CD54HC40103, CD74HC40103, CD74HCT40103 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 1) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VIH - - 2 1.5 - - 1.5 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V MIN TYP MAX MIN MAX MIN MAX UNITS - 1.5 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 3 CD54HC40103, CD74HC40103, CD74HCT40103 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER 25oC VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC and GND 0 5.5 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC (Note 2) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS (NOTE) P0-P7 0.20 TE, MR 0.40 CP 0.60 PE 0.80 PL 1.35 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC. Prerequisite for Switching Specifications 25oC PARAMETER -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tW 2 165 - - 205 - 250 - ns 4.5 33 - - 41 - 50 - ns 6 28 - - 35 - 43 - ns 2 125 - - 155 - 190 - ns 4.5 25 - - 31 - 38 - ns 6 21 - - 26 - 32 - ns HC TYPES CP Pulse Width PL Pulse Width tW 4 CD54HC40103, CD74HC40103, CD74HCT40103 Prerequisite for Switching Specifications (Continued) 25oC PARAMETER MR Pulse Width CP Max. Frequency (Note 3) P to CP Set-up Time PE to CP Set-up Time TE to CP Set-up Time P to CP Hold Time TE to CP Hold Time MR to CP Removal Time PE to CP Hold Time -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tW 2 125 - - 135 - 190 - ns 4.5 25 - - 31 - 38 - ns 6 21 - - 26 - 32 - ns 2 3 - - 2 - 2 - MHz 4.5 15 - - 12 - 10 - MHz 6 18 - - 14 - 12 - MHz 2 100 - - 125 - 150 - ns 4.5 20 - - 25 - 30 - ns 6 17 - - 21 - 26 - ns 2 75 - - 95 - 110 - ns 4.5 15 - - 19 - 22 - ns 6 13 - - 16 - 19 - ns 2 150 - - 190 - 225 - ns 4.5 30 - - 38 - 45 - ns 6 26 - - 33 - 38 - ns 2 5 - - 5 - 5 - ns 4.5 5 - - 5 - 5 - ns 6 5 - - 5 - 5 - ns fCP(MAX) tSU tSU tSU tH tH tREM tH 2 0 - - 0 - 0 - ns 4.5 0 - - 0 - 0 - ns 6 0 - - 0 - 0 - ns 2 50 - - 65 - 75 - ns 4.5 10 - - 13 - 15 - ns 6 9 - - 11 - 13 - ns 2 2 - - 2 - 2 - ns 4.5 2 - - 2 - 2 - ns 6 2 - - 2 - 2 - ns tW 4.5 35 - - 44 - 53 - ns PL Pulse Width tW 4.5 43 - - 54 - 65 - ns MR Pulse Width tW 4.5 35 - - 44 - 53 - ns CP Max. Frequency (Note 3) fCP(MAX) 4.5 14 - - 11 - 9 - MHz P to CP Set-up Time tSU 4.5 24 - - 30 - 36 - ns PE to CP Set-up Time tSU 4.5 20 - - 25 - 30 - ns TE to CP Set-up Time tSU 4.5 40 - - 50 - 60 - ns P to CP Hold Time tH 4.5 5 - - 5 - 5 - ns TE to CP Hold Time tH 4.5 0 - - 0 - 0 - ns tREM 4.5 10 - - 13 - 15 - ns tH 4.5 2 - - 2 - 2 - ns HCT TYPES CP Pulse Width MR to CP Removal Time PE to CP Hold Time 5 CD54HC40103, CD74HC40103, CD74HCT40103 Switching Specifications Input tr, tf = 6ns -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS CL = 50pF 2 - - 300 - 375 - 450 ns CL = 50pF 4.5 - - 60 - 75 - 90 ns CL = 15pF 5 - 25 - - CL = 50pF 6 - - 51 - 64 - 77 ns CL = 50pF 2 - - 300 - 375 - 450 ns CL = 50pF 4.5 - - 60 - 75 - 90 ns CL = 15pF 5 - 25 - - - - - ns CL = 50pF 6 - - 51 - 64 - 77 ns CL = 50pF 2 - - 200 - 250 - 300 ns CL = 50pF 4.5 - - 40 - 50 - 60 ns CL = 15pF 5 - 17 - - - - - ns CL = 50pF 6 - - 34 - 43 - 51 ns CL = 50pF 2 - - 275 - 345 - 415 ns CL = 50pF 4.5 - - 55 - 69 - 83 ns CL = 15pF 5 - 23 - - - - - ns CL = 50pF 6 - - 47 - 59 - 71 ns CL = 50pF 2 - - 275 - 345 - 415 ns CL = 50pF 4.5 - - 55 - 69 - 83 ns CL = 15pF 5 - 23 - - - - - ns CL = 50pF 6 - - 47 - 59 - 71 ns CL = 50pF 2 - - 75 - 95 - 110 ns CL = 50pF 4.5 - - 15 - 19 - 22 ns CL = 50pF 6 - - 13 - 16 - 19 ns CI CL = 50pF - - - 10 - 10 - 10 pF CP Maximum Frequency fMAX CL = 15pF 5 - 25 - - - - - MHz Power Dissipation Capacitance (Notes 4, 5) CPD - 5 - 25 - - - - - pF tPLH, tPHL CL = 50pF 4.5 - - 60 - 75 - 90 ns CL = 15pF 5 - 25 - - - - - ns CL = 50pF 4.5 - - 63 - 79 - 95 ns CL = 15pF 5 - 26 - - - - - ns CL = 50pF 4.5 - - 50 - 63 - 75 ns CL = 15pF 5 - 21 - - - - - ns CL = 50pF 4.5 - - 68 - 85 - 102 ns CL = 15pF 5 - 28 - - - - - ns PARAMETER TEST SYMBOL CONDITIONS -40oC TO 85oC 25oC HC TYPES Propagation Delay CP to any TC (Async Preset) CP to TC (Sync Preset) TE to TC PL to TC MR to TC Output Transition Time Input Capacitance tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tTLH, tTHL - ns HCT TYPES Propagation Delay CP to TC (Async Preset) CE to TC (Sync Preset) TE to TC PL to TC tPLH, tPHL tPLH, tPHL tPLH, tPHL 6 CD54HC40103, CD74HC40103, CD74HCT40103 Switching Specifications Input tr, tf = 6ns (Continued) TEST SYMBOL CONDITIONS -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS CL = 50pF 4.5 - - 55 - 69 - 83 ns CL = 15pF 5 - 23 - - - - - ns tTHL, tTLH CL = 50pF 4.5 - - 15 - 19 - 22 ns CIN CL = 50pF - - - 10 - 10 - 10 pF CP Maximum Frequency fMAX CL = 15pF 5 - 25 - - - - - MHz Power Dissipation Capacitance (Notes 4, 5) CPD - 5 - 27 - - - - - pF PARAMETER MR to TC tPLH, tPHL Output Transition Time Input Capacitance NOTES: 3. Noncascaded operation only. With cascaded counters clock-to-terminal count propagation delays, count enables (PE or TE)-to-clock SET UP TIMES, and count enables (PE or TE)-to-clock HOLD TIMES determine maximum clock frequency. For example, with these HC devices: 1 1 C P f MAX = ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ = ----------------------------- ≈ 11MHz CP-to-TC prop delay + TE-to-CP Setup Time + TE-to-CP Hold Time 60 + 30 + 0 4. CPD is used to determine the dynamic power consumption, per package. 5. PD = VCC2 fi + CL VCC2 fo where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage, fo = Output Frequency. Timing Diagrams CP MR TE PE PL P0 P1 P2 P3 P4 P5 P6 P7 TC HC/HCT40103 COUNT 255 254 3 2 1 0 255 254 254 253 FIGURE 1. 7 8 7 6 5 4 255 254 253 252 CD54HC40103, CD74HC40103, CD74HCT40103 Test Circuits and Waveforms tr tf tPHL tW INPUT LEVEL 90% 10% tW 1/fMAX CP VS INPUT LEVEL VS MR GND GND tPLH TC 10% 90% tREM VS CP tTHL VS tTLH GND FIGURE 2. FIGURE 3. tf tf INPUT LEVEL 10% 90% TE INPUT LEVEL GND tPHL tSU tPLH 10% 90% TC INPUT LEVEL VS MR VS VS th INPUT LEVEL VS CP GND tTHL tTLH FIGURE 4. FIGURE 5. VALID INPUT LEVEL INPUTS VS GND P0 - P7 tSU PE INPUT LEVEL VS tSU CP TE OR PE th th GND tREC tSU CP 10% GND GND tfCL 90% GND INPUT LEVEL VS FIGURE 6. CLOCK th INPUT LEVEL VS trCL INPUT LEVEL VS FIGURE 7. tWL + tWH = I fCL tWL 50% tfCL = 6ns I fCL 3V VCC 50% 10% tWL + tWH = trCL = 6ns CLOCK 50% 2.7V 0.3V GND 1.3V 0.3V tWL tWH 1.3V 1.3V GND tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 9. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH FIGURE 8. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH 8 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-9055301EA ACTIVE CDIP J 16 5HC40103F3AS228 OBSOLETE CDIP J 16 1 Lead/Ball Finish TBD A42 SNPB TBD Call TI MSL Peak Temp (3) N / A for Pkg Type Call TI CD54HC40103F ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HC40103F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD74HC40103E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC40103EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC40103M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC40103M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC40103M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC40103M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC40103ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC40103MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC40103MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC40103MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC40103MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT40103E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT40103EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT40103M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT40103M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT40103M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT40103M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT40103ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT40103MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT40103MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT40103MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT40103MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC40103M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HCT40103M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC40103M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HCT40103M96 SOIC D 16 2500 333.2 345.9 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID RF/IF and ZigBee® Solutions amplifier.ti.com dataconverter.ti.com dsp.ti.com www.ti.com/clocks interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com www.ti-rfid.com www.ti.com/lprf Applications Audio Automotive Broadband Digital Control Medical Military Optical Networking Security Telephony Video & Imaging Wireless www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/medical www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2008, Texas Instruments Incorporated