Cypress CY7C64343-32LQXI Encore v full speed usb controller Datasheet

CY7C6431x
CY7C6434x, CY7C6435x
enCoRe™ V Full Speed USB Controller
Features
Powerful Harvard Architecture Processor
❐ M8C processor speeds running up to 24 MHz
❐ Low power at high processing speeds
❐ Interrupt controller
❐ 3.0V to 5.5V operating voltage without USB
❐ Operating voltage with USB enabled:
• 3.15V to 3.45V when supply voltage is around 3.3V
• 4.35V to 5.25V when supply voltage is around 5.0V
❐ Commercial temperature range: 0°C to +70°C
❐ Industrial temperature range: -40°C to +85°C
■ Flexible On-Chip Memory
❐ Up to 32K Flash program storage:
• 50,000 erase and write cycles
• Flexible protection modes
❐ Up to 2048 bytes SRAM data storage
❐ In-System Serial Programming (ISSP)
■ Complete Development Tools
❐ Free development tool (PSoC Designer™)
❐ Full featured, in-circuit emulator and programmer
❐ Full speed emulation
❐ Complex breakpoint structure
❐ 128K trace memory
■ Precision, Programmable Clocking
❐ Crystal-less oscillator with support for an external crystal or
resonator
❐ Internal ±5.0% 6, 12, or 24 MHz main oscillator:
• 0.25% accuracy with Oscillator Lock to USB data, no
external components required
• Internal low speed oscillator at 32 kHz for watchdog and
sleep. The frequency range is 19 to 50 kHz with a 32 kHz
typical value
■
■
■
■
enCoRe V Block Diagram
Programmable Pin Configurations
❐ Up to 36 GPIO (Depending on Package)
❐ 25 mA sink current on all GPIO
❐ Pull Up, High Z, Open Drain, CMOS drive modes on all GPIO
❐ CMOS Drive Mode (5 mA Source Current) on Ports 0 and 1:
• 20 mA (at 3.0V) Total Source Current
❐ Low dropout voltage regulator for Port 1 pins:
• Programmable to output 3.0, 2.5, or 1.8V
❐ Selectable, regulated digital I/O on Port 1
❐ Configurable input threshold for Port 1
❐ Hot-swappable Capability on Port 1
Full-Speed USB (12 Mbps)
❐ Eight unidirectional endpoints
❐ One bidirectional control endpoint
❐ USB 2.0 compliant
❐ Dedicated 512 bytes buffer
❐ No external crystal required
Additional System Resources
❐ Configurable communication speeds
2
❐ I C slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• Implementation requires no clock stretching
• Implementation during sleep modes with less than 100 μA
• Hardware address detection
❐ SPI master and SPI slave:
• Configurable between 46.9 kHz and 12 MHz
❐ Three 16-bit timers
❐ 10-bit ADC used to monitor battery voltage or other signals
with external components
❐ Watchdog and sleep timers
❐ Integrated supervisory circuit
Port 4
Port 3
Port 2
Port 1
Port 0
Prog. LDO
enCoRe V
CORE
System Bus
SRAM
2048 Bytes
SROM
8K/16K/32K Flash
Sleep and
Watchdog
CPU Core (M8C)
Interrupt
Controller
6/12/24 MHz Internal Main Oscillator
ADC
3 16-Bit
Timers
I2C Slave/SPI
Master-Slave
POR and LVD
System Resets
Full
Speed
USB
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 001-12394 Rev *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 15, 2009
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Functional Overview
Figure 1. USB Transceiver Regulator
The enCoRe V family of devices are designed to replace multiple
traditional full-speed USB microcontroller system components
with one, low cost single-chip programmable component.
Communication peripherals (I2C/SPI), a fast CPU, Flash
program memory, SRAM data memory, and configurable I/O are
included in a range of convenient pinouts.
1.5K
The architecture for this device family, as illustrated in the
“enCoRe V Block Diagram” on page 1, consists of two main
areas: the CPU core and the system resources. Depending on
the enCoRe V package, up to 36 general purpose I/O (GPIO) are
also included.
DP
TD
DM
RECEIVERS
PDN
The enCoRe V Core
DMO
System resources provide additional capability, such as a configurable I2C slave and SPI master-slave communication interface
and various system resets supported by the M8C.
Full-Speed USB
The enCoRe V USB system resource adheres to the USB 2.0
Specification for full speed devices operating at 12 Mb/second
with one upstream port and one USB address. enCoRe V USB
consists of these components:
■
Serial Interface Engine (SIE) block.
■
PSoC Memory Arbiter (PMA) block.
■
512 bytes of dedicated SRAM.
■
A full-speed USB Transceiver with internal regulator and two
dedicated USB pins.
Document Number: 001-12394 Rev *I
5K
TEN
This product is an enhanced version of Cypress’s successful full
speed-USB peripheral controllers. Enhancements include faster
CPU at lower voltage operation, lower current consumption,
twice the RAM and Flash, hot-swappable I/Os, I2C hardware
address recognition, new very low current sleep mode, and new
package options.
The enCoRe V Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four-MIPS, 8-bit Harvard
architecture microprocessor.
PS2 Pull Up
VOLTAGE
REGULATOR
5V 3.3V
TRANSMITTER
RD
DPO
RSE0
At the enCoRe V system level, the full-speed USB system
resource interfaces to the rest of the enCoRe V by way of the
M8C's register access instructions and to the outside world by
way of the two USB pins. The SIE supports nine endpoints
including a bidirectional control endpoint (endpoint 0) and eight
unidirectional data endpoints (endpoints 1 to 8). The unidirectional data endpoints are individually configurable as either IN or
OUT.
The USB Serial Interface Engine (SIE) allows the enCoRe V
device to communicate with the USB host at full speed data rates
(12 Mb/s). The SIE simplifies the interface to USB traffic by
automatically handling the following USB processing tasks
without firmware intervention:
■
Translates the encoded received data and formats the data to
be transmitted on the bus.
■
Generates and checks CRCs. Incoming packets failing
checksum verification are ignored.
■
Checks addresses. Ignores all transactions not addressed to
the device.
■
Sends appropriate ACK/NAK/Stall handshakes.
■
Identifies token type (SETUP, IN, OUT) and sets the appropriate token bit once a valid token in received.
■
Identifies Start-of-Frame (SOF) and saves the frame count.
■
Sends data to or retrieves data from the USB SRAM, by way
of the PSoC Memory Arbiter (PMA).
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Firmware is required to handle various parts of the USB
interface. The SIE issues interrupts after key USB events to
direct firmware to appropriate tasks:
■
Fill and empty the USB data buffers in USB SRAM.
■
Enable PMA channels appropriately.
■
Coordinate enumeration by decoding USB device requests.
■
Suspend and resume coordination.
■
Verify and select data toggle values.
Input Mux or the temperature sensor with an input voltage range
of 0V to 1.3 V, where 1.3V is 72 percent of full scale.
In the ADC only configuration (the ADC MUX selects the Analog
Mux Bus, not the default temperature sensor connection), an
external voltage can be connected to the input of the modulator
for voltage conversion. The ADC is run for a number of cycles
set by the timer, depending upon the desired resolution of the
ADC. A counter counts the number of trips by the comparator,
which is proportional to the input voltage. The Temp Sensor block
clock speed is 36 MHz and is divided down to 1 to 12 MHz for
ADC operation.
10-bit ADC
SPI
The ADC on enCoRe V device is an independent block with a
state machine interface to control accesses to the block. The
ADC is housed together with the temperature sensor core and
can be connected to this or the Analog Mux Bus. As a default
operation, the ADC is connected to the temperature sensor
diodes to give digital values of the temperature.
The Serial Peripheral Interconnect (SPI) 3-wire protocol uses
both edges of the clock to enable synchronous communication
without the need for stringent setup and hold requirements.
Figure 2. ADC System Performance Block Diagram
VIN
TEMP SENSOR/ ADC
Figure 3. Basic SPI Configuration
SPI Master
SPI Slave
Data is output by
Data is registered at the
both the Master
input of both devices on the
and Slave on
opposite edge of the clock.
one edge of the
clock.
SCLK
MOSI
MISO
TEMP
DIODES
ADC
SYSTEM BUS
INTERFACE BLOCK
COMMAND/ STATUS
A device can be a master or slave. A master outputs clock and
data to the slave device and inputs slave data. A slave device
inputs clock and data from the master device and outputs data
for input to the master. Together, the master and slave are essentially a circular Shift register, where the master generates the
clocking and initiates data transfers.
A basic data transfer occurs when the master sends eight bits of
data, along with eight clocks. In any transfer, both master and
slave transmit and receive simultaneously. If the master only
sends data, the received data from the slave is ignored. If the
master wishes to receive data from the slave, the master must
send dummy bytes to generate the clocking for the slave to send
data back.
Figure 4. SPI Block Diagram
SPI Block
MOSI,
MISO
SCLK
DATA_IN DATA_OUT
CLK_IN
CLK_OUT
SCLK
INT
SYSCLK
Interface to the M8 C
( Processor ) Core
MOSI,
MISO
SS_
Registers
The ADC User Module contains an integrator block and one
comparator with positive and negative input set by the MUXes.
The input to the integrator stage comes from the Analog Global
Document Number: 001-12394 Rev *I
CONFIGURATION[7:0]
CONTROL[7:0]
TRANSMIT[7:0]
RECEIVE[7:0]
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SPI configuration register (SPI_CFG) sets master/slave
functionality, clock speed, and interrupt select. SPI control
register (SPI_CR) provides four control bits and four status bits
for device interfacing and synchronization.
The SPIM hardware has no support for driving the Slave Select
(SS_) signal. The behavior and use of this signal is dependent
on the application and enCoRe V device and, if required, must
be implemented in firmware.
There is an additional data input in the SPIS, Slave Select (SS_),
which is an active low signal. SS_ must be asserted to enable
the SPIS to receive and transmit. SS_ has two high level
functions:
■
To allow for the selection of a given slave in a multi-slave
environment.
■
To provide additional clocking for TX data queuing in SPI modes
0 and 1.
I2C Slave
The I2C slave enhanced communications block is a
serial-to-parallel processor, designed to interface the enCoRe V
device to a two-wire I2C serial communications bus. To eliminate
the need for excessive CPU intervention and overhead, the block
provides I2C-specific support for status detection and generation
of framing bits. By default, the I2C Slave Enhanced module is
firmware compatible with the previous generation of I2C slave
functionality. However, this module provides new features that
are configurable to implement significant flexibility for both
internal and external interfacing. The basic I2C features include:
■
Slave, transmitter, and receiver operation.
■
Byte processing for low CPU overhead.
■
Interrupt or polling CPU interface.
■
Support for clock rates of up to 400 kHz.
■
7- or 10-bit addressing (through firmware support).
■
SMBus operation (through firmware support).
Enhanced features of the I2C Slave Enhanced Module include:
■
Support for 7-bit hardware address compare.
■
Flexible data buffering schemes.
■
A "no bus stalling" operating mode.
■
A low power bus monitoring mode.
The I2C block controls the data (SDA) and the clock (SCL) to the
external I2C interface through direct connections to two
dedicated GPIO pins. When I2C is enabled, these GPIO pins are
not available for general purpose use. The enCoRe V CPU
firmware interacts with the block through I/O register reads and
writes, and firmware synchronization is implemented through
polling and/or interrupts.
In the default operating mode, which is firmware compatible with
previous versions of I2C slave modules, the I2C bus is stalled
upon every received address or byte, and the CPU is required to
read the data or supply data as required before the I2C bus
continues. However, this I2C Slave Enhanced module provides
new data buffering capability as an enhanced feature. In the
EZI2C buffering mode, the I2C slave interface appears as a
32-byte RAM buffer to the external I2C master. Using a simple
predefined protocol, the master controls the read and write
pointers into the RAM. When this method is enabled, the slave
never stalls the bus. In this protocol, the data available in the
RAM (this is managed by the CPU) is valid.
Figure 5. I2C Block Diagram
I2C Plus
Slave
I2C Core
To/From
GPIO
Pins
SCL_IN
CPU Port
I2C Basic
Configuration
I2C_BUF
I2C_CFG
SDA_OUT
SCL_OUT
I2C_EN
I2C_SCR
32 Byte RAM
I2C_DR
HW Addr Cmp
I2C_ADDR
Buffer Ctl
I2C_BP
Plus Features
Document Number: 001-12394 Rev *I
System Bus
SDA_IN
Buffer Module
SYSCLK
I2C_CP
I2C_XCFG
MCU_BP
I2C_XSTAT
MCU_CP
STANDBY
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Additional System Resources
Development Kits
System resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include low voltage detection and power on
reset. The following statements describe the merits of each
system resource.
Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark. Under
Product Categories, click USB (Universal Serial Bus) to view a
current list of available items.
■
Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (power
on reset) circuit eliminates the need for a system supervisor.
■
The 5V maximum input, 1.8, 2.5, or 3V selectable output, low
dropout regulator (LDO) provides regulation for I/Os. A register
controlled bypass mode enables the user to disable the LDO.
■
Standard Cypress PSoC IDE tools are available for debugging
the enCoRe V family of parts.
Getting Started
The quickest path to understanding the enCoRe V silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the enCoRe V integrated circuit and presents specific pin,
register, and electrical specifications. For in-depth information,
along with detailed programming information, reference the
PSoC Programmable System-on-Chip Technical Reference
Manual, which can be found on http://www.cypress.com/psoc.
For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest enCoRe V device data sheets
on the web at http://www.cypress.com.
Document Number: 001-12394 Rev *I
Technical Training Modules
Free technical training (on demand, webinars, and workshops)
is available online at www.cypress.com/training. The training
covers a wide variety of topics and skill levels to assist you in
your designs.
Consultants
Certified USB consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC
Consultant go to www.cypress.com/cypros.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at
1-800-541-4736.
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
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Development Tools
PSoC Designer™ is a Microsoft® Windows-based, integrated
development environment for the enCoRe and PSoC devices.
The PSoC Designer IDE and application runs on Windows XP
and Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party assemblers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the enCoRe and PSoC families.
PSoC Designer Software Subsystems
Chip-Level View
The chip-level view is a traditional integrated development
environment (IDE) based on PSoC Designer 4.4. You choose a
base device to work with and then select different onboard
analog and digital components called user modules that use the
PSoC blocks. Examples of user modules are ADCs, DACs,
Amplifiers, and Filters. You configure the user modules for your
chosen application and connect them to each other and to the
proper pins. Then you generate your project. This prepopulates
your project with APIs and libraries that you can use to program
your application.
The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration
allows for changing configurations at run time.
System-Level View
The system-level view is a drag-and-drop visual embedded
system design environment based on PSoC Designer.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share common code
editor, builder, and common debug, emulation, and programming
tools.
Code Generation Tools
PSoC Designer supports multiple third-party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Document Number: 001-12394 Rev *I
Assemblers. The assemblers allow assembly code to be
merged seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the enCoRe and PSoC families of devices. The
products enable you to create complete C programs for the
PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program flash, read and write data memory, read and write I/O
registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural help and quick reference,
each functional subsystem has its own context-sensitive help.
This system also provides tutorials and links to FAQs and an
Online Support Forum to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all enCoRe and PSoC devices. Emulation pods for each device
family are available separately. The emulation pod takes the
place of the PSoC device in the target board and performs full
speed (24 MHz) operation.
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Designing with PSoC Designer
The development process for the enCoRe V device differs from
that of a traditional fixed function microprocessor. Powerful
PSoC Designer tools get the core of your design up and running
in minutes instead of hours.
The development process can be summarized in the following
four steps:
1. Select Components
2. Configure Components
3. Organize and Connect
4. Generate, Verify, and Debug
Select Components
The chip-level view provides a library of pre-built, pre-tested
hardware peripheral components. These components are called
“user modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed-signal varieties.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application.
The chip-level user modules are documented in data sheets that
are viewed directly in PSoC Designer. These data sheets explain
the internal operation of the component and provide performance specifications. Each data sheet describes the use of each
user module parameter and contains other information you may
need to successfully implement your design.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system.
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high level functions to
control and respond to hardware events at run time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s Debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the In-Circuit
Emulator (ICE) where it runs at full speed. PSoC Designer
debugging capabilities rival those of systems costing many times
more. In addition to traditional single-step, run-to-breakpoint and
watch-variable features, the debug interface provides a large
trace buffer and allows you to define complex breakpoint events
that include monitoring address and data bus values, memory
locations and external signals.
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins, or connect system-level
inputs, outputs, and communication interfaces to each other with
valuator functions. In the chip-level view, you perform the
selection, configuration, and routing so that you have complete
control over the use of all on-chip resources.
Document Number: 001-12394 Rev *I
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Document Conventions
Acronyms Used
Units of Measure
The following table lists the acronyms that are used in this
document.
A units of measure table is located in the Electrical Specifications
section. Table 7 on page 16 lists all the abbreviations used to
measure the enCoRe V devices.
Acronym
Description
API
application programming interface
CPU
central processing unit
GPIO
general purpose IO
ICE
in-circuit emulator
ILO
internal low speed oscillator
IMO
internal main oscillator
IO
input/output
LSb
least significant bit
LVD
low voltage detect
MSb
most significant bit
POR
power on reset
PPOR
precision power on reset
PSoC®
Programmable System-on-Chip™
SLIMO
slow IMO
SRAM
static random access memory
Document Number: 001-12394 Rev *I
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are
decimal.
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Pin Configuration
The enCoRe V USB device is available in a variety of packages which are listed and illustrated in the subsequent tables.
16-Pin Part Pinout
P2[5]
P0[1]
P0[3]
P0[7]
15
14
13
6
7
8
D+
D–
Vdd
12
QFN
11
(Top View) 10
9
5
P1[5]
P1[1]
1
2
3
4
Vss
P2[3]
P1[7]
16
Figure 6. CY7C64315/CY7C64316 16-Pin enCoRe V USB Device
P0[4]
XRES
P1[4]
P1[0]
Table 1. 16-Pin Part Pinout (QFN)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Type
I/O
IOHR
IOHR
IOHR
Power
USB line
USB line
Power
IOHR
IOHR
Input
IOH
IOH
IOH
IOH
I/O
Name
P2[3]
P1[7]
P1[5]
P1[1](1, 2)
Vss
D+
D–
Vdd
P1[0](1, 2)
P1[4]
XRES
P0[4]
P0[7]
P0[3]
P0[1]
P2[5]
Description
Digital I/O, Crystal Input (Xin)
Digital I/O, SPI SS, I2C SCL
Digital I/O, SPI MISO, I2C SDA
Digital I/O, ISSP CLK, 12C SCL, SPI MOSI
Ground connection
USB PHY
USB PHY
Supply
Digital I/O, ISSP DATA, I2C SDA, SPI CLK
Digital I/O, optional external clock input (EXTCLK)
Active high external reset with internal pull down
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O, Crystal Output (Xout)
LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output
Notes
1. During power up or reset event, device P1[0] and P1[1] may disturb the I2C bus. Use alternate pins if issues are encountered.
2. These are the in-system serial programming (ISSP) pins that are not High Z at power on reset (POR).
Document Number: 001-12394 Rev *I
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32-Pin Part Pinout
P0[5]
P0[7]
Vdd
P0[6]
P0[4]
P0[2]
30
29
28
27
26
25
Vss
P0[3]
32
31
Figure 7. CY7C64343/CY7C64345 32-Pin enCoRe V USB Device
P0[1]
1
24
P2[5]
P2[3]
P2[1]
P1[7]
2
23
P2[6]
3
4
5
22
21
20
P2[4]
P2[2]
P2[0]
P1[5]
6
19
P3[2]
P1[3]
P1[1]
7
8
18
P3[0]
17
XRES
QFN
11
12
13
14
15
16
D–
Vdd
P1[0]
P1[2]
P1[4]
P1[6]
D+
Vss
9
10
( Top View )
P0[0]
Table 2. 32-Pin Part Pinout (QFN)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CP
Type
IOH
I/O
I/O
I/O
IOHR
IOHR
IOHR
IOHR
Power
I/O
I/O
Power
IOHR
IOHR
IOHR
IOHR
Reset
I/O
I/O
I/O
I/O
I/O
I/O
IOH
IOH
IOH
IOH
Power
IOH
IOH
IOH
Power
Power
Name
P0[1]
P2[5]
P2[3]
P2[1]
P1[7]
P1[5]
P1[3]
P1[1](1, 2)
Vss
D+
D–
Vdd
P1[0](1, 2)
P1[2]
P1[4]
P1[6]
XRES
P3[0]
P3[2]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
P0[7]
P0[5]
P0[3]
Vss
Vss
Description
Digital I/O
Digital I/O, Crystal Output (Xout)
Digital I/O, Crystal Input (Xin)
Digital I/O
Digital I/O, I2C SCL, SPI SS
Digital I/O, I2C SDA, SPI MISO
Digital I/O, SPI CLK
Digital I/O, ISSP CLK, I2C SCL, SPI MOSI
Ground
USB PHY
USB PHY
Supply voltage
Digital I/O, ISSP DATA, I2C SDA, SPI CLK
Digital I/O
Digital I/O, optional external clock input (EXTCLK)
Digital I/O
Active high external reset with internal pull down
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Supply voltage
Digital I/O
Digital I/O
Digital I/O
Ground
Ensure the center pad is connected to ground
LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output
Document Number: 001-12394 Rev *I
Page 10 of 32
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CY7C6431x
CY7C6434x, CY7C6435x
48-Pin Part Pinout
P0[0]
38
37
39
Vdd
P0[6]
P0[4]
P0[2]
42
41
40
NC
NC
P0[7]
43
P0[5]
45
44
46
47
QFN
(Top View)
19
20
21
22
23
24
D+
DVdd
P1[0]
26
25
P2[6]
P2[4]
P2[2]
P2[0]
P4[2]
P4[0]
P3[6]
P3[4]
P3[2]
P3[0]
XRES
P1[6]
P1[4]
18
Vss
P1[2]
17
P1[1]
30
29
28
27
16
15
36
35
34
33
32
31
P1[3]
11
12
P1[5]
P3[1]
P1[7]
3
4
5
6
7
8
9
10
13
14
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
1
2
NC
NC
NC
P2[7]
P2[5]
48
P0[1]
Vss
P0[3]
Figure 8. CY7C64355/CY7C64356 48-Pin enCoRe V USB Device
Table 3. 48-Pin Part Pinout (QFN)
Pin No.
Type
Pin Name
Description
1
NC
NC
No connection
2
I/O
P2[7]
Digital I/O
3
I/O
P2[5]
Digital I/O, Crystal Out (Xout)
4
I/O
P2[3]
Digital I/O, Crystal In (Xin)
5
I/O
P2[1]
Digital I/O
6
I/O
P4[3]
Digital I/O
7
I/O
P4[1]
Digital I/O
8
I/O
P3[7]
Digital I/O
9
I/O
P3[5]
Digital I/O
10
I/O
P3[3]
Digital I/O
11
I/O
P3[1]
Digital I/O
12
IOHR
P1[7]
Digital I/O, I2C SCL, SPI SS
13
IOHR
P1[5]
Digital I/O, I2C SDA, SPI MISO
14
NC
NC
No connection
15
NC
NC
No connection
16
IOHR
P1[3]
Digital I/O, SPI CLK
17
IOHR
P1[1](1, 2)
Digital I/O, ISSP CLK, I2C SCL, SPI MOSI
18
Power
Vss
Supply ground
19
I/O
D+
USB
20
I/O
D–
USB
21
Power
Vdd
Supply voltage
22
IOHR
P1[0](1, 2)
Digital I/O, ISSP DATA, I2C SDA, SPI CLK
23
IOHR
P1[2]
Digital I/O,
24
IOHR
P1[4]
Digital I/O, optional external clock input (EXTCLK)
25
IOHR
P1[6]
Digital I/O
Document Number: 001-12394 Rev *I
Page 11 of 32
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CY7C6434x, CY7C6435x
Table 3. 48-Pin Part Pinout (QFN) (continued)
Pin No.
Type
Pin Name
Description
26
XRES
Ext Reset
Active high external reset with internal pull down
27
I/O
P3[0]
Digital I/O
28
I/O
P3[2]
Digital I/O
29
I/O
P3[4]
Digital I/O
30
I/O
P3[6]
Digital I/O
31
I/O
P4[0]
Digital I/O
32
I/O
P4[2]
Digital I/O
33
I/O
P2[0]
Digital I/O
34
I/O
P2[2]
Digital I/O
35
I/O
P2[4]
Digital I/O
36
I/O
P2[6]
Digital I/O
37
IOH
P0[0]
Digital I/O
38
IOH
P0[2]
Digital I/O
39
IOH
P0[4]
Digital I/O
40
IOH
P0[6]
Digital I/O
41
Power
Vdd
Supply voltage
42
NC
NC
No connection
43
NC
NC
No connection
44
IOH
P0[7]
Digital I/O
45
IOH
P0[5]
Digital I/O
46
IOH
P0[3]
Digital I/O
47
Power
Vss
Supply ground
48
IOH
CP
Power
P0[1]
Digital I/O
Vss
Ensure the center pad is connected to ground
LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output
Document Number: 001-12394 Rev *I
Page 12 of 32
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CY7C6434x, CY7C6435x
Register Reference
The section discusses the registers of the enCoRe V device. It lists all the registers in mapping tables, in address order.
Register Conventions
Register Mapping Tables
The register conventions specific to this section are listed in the
following table.
The enCoRe V device has a total register address space of 512
bytes. The register space is also referred to as IO space and is
broken into two parts: Bank 0 (user space) and Bank 1 (configuration space). The XIO bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XIO bit is
set, the user is said to be in the “extended” address space or the
“configuration” registers.
Table 4. Register Conventions
Convention
Description
R
Read register or bits
W
Write register or bits
L
Logical register or bits
C
Clearable register or bits
#
Access is bit specific
Document Number: 001-12394 Rev *I
Page 13 of 32
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CY7C6434x, CY7C6435x
Table 5. Register Map Bank 0 Table: User Space
Name
PRT0DR
PRT0IE
Addr (0,Hex) Access
Name
00
RW
EP1_CNT0
01
RW
EP1_CNT1
02
EP2_CNT0
03
EP2_CNT1
PRT1DR
04
RW
EP3_CNT0
PRT1IE
05
RW
EP3_CNT1
06
EP4_CNT0
07
EP4_CNT1
PRT2DR
08
RW
EP5_CNT0
PRT2IE
09
RW
EP5_CNT1
0A
EP6_CNT0
0B
EP6_CNT1
PRT3DR
0C
RW
EP7_CNT0
PRT3IE
0D
RW
EP7_CNT1
0E
EP8_CNT0
0F
EP8_CNT1
PRT4DR
10
RW
PRT4IE
11
RW
12
13
14
15
16
17
18
PMA0_DR
19
PMA1_DR
1A
PMA2_DR
1B
PMA3_DR
1C
PMA4_DR
1D
PMA5_DR
1E
PMA6_DR
1F
PMA7_DR
20
21
22
23
24
PMA8_DR
25
PMA9_DR
26
PMA10_DR
27
PMA11_DR
28
PMA12_DR
SPI_TXR
29
W
PMA13_DR
SPI_RXR
2A
R
PMA14_DR
SPI_CR
2B
#
PMA15_DR
2C
TMP_DR0
2D
TMP_DR1
2E
TMP_DR2
2F
TMP_DR3
30
USB_SOF0
31
R
USB_SOF1
32
R
USB_CR0
33
RW
USBIO_CR0
34
#
USBIO_CR1
35
#
EP0_CR
36
#
EP0_CNT0
37
#
EP0_DR0
38
RW
EP0_DR1
39
RW
EP0_DR2
3A
RW
EP0_DR3
3B
RW
EP0_DR4
3C
RW
EP0_DR5
3D
RW
EP0_DR6
3E
RW
EP0_DR7
3F
RW
Gray fields are reserved; do not access these fields.
Document Number: 001-12394 Rev *I
Addr (0,Hex) Access
40
#
41
RW
42
#
43
RW
44
#
45
RW
46
#
47
RW
48
#
49
RW
4A
#
4B
RW
4C
#
4D
RW
4E
#
4F
RW
50
51
52
53
54
55
56
57
58
RW
59
RW
5A
RW
5B
RW
5C
RW
5D
RW
5E
RW
5F
RW
60
61
62
63
64
RW
65
RW
66
RW
67
RW
68
RW
69
RW
6A
RW
6B
RW
6C
RW
6D
RW
6E
RW
6F
RW
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
# Access is bit specific.
Name
PT0_CFG
PT0_DATA1
PT0_DATA0
PT1_CFG
PT1_DATA1
PT1_DATA0
PT2_CFG
PT2_DATA1
PT2_DATA0
Addr (0,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
Access
Name
I2C_XCFG
I2C_XSTAT
I2C_ADDR
I2C_BP
I2C_CP
CPU_BP
CPU_CP
I2C_BUF
CUR_PP
STK_PP
IDX_PP
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK2
INT_MSK1
INT_MSK0
INT_SW_EN
INT_VC
RES_WDT
INT_MSK3
RW
RW
RW
RW
RW
RW
RW
RW
RW
CPU_F
CPU_SCR1
CPU_SCR0
Addr (0,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
R
RW
R
R
RW
R
RW
RW
RW
RW
RW
RW
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
RW
RL
#
#
Page 14 of 32
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CY7C6434x, CY7C6435x
Table 6. Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
PRT0DM1
Addr (1,Hex) Access
Name
Addr (1,Hex) Access
00
RW
PMA4_RA
40
RW
01
RW
PMA5_RA
41
RW
02
PMA6_RA
42
RW
03
PMA7_RA
43
RW
PRT1DM0
04
RW
PMA8_WA
44
RW
PRT1DM1
05
RW
PMA9_WA
45
RW
06
PMA10_WA
46
RW
07
PMA11_WA
47
RW
PRT2DM0
08
RW
PMA12_WA
48
RW
PRT2DM1
09
RW
PMA13_WA
49
RW
0A
PMA14_WA
4A
RW
0B
PMA15_WA
4B
RW
PRT3DM0
0C
RW
PMA8_RA
4C
RW
PRT3DM1
0D
RW
PMA9_RA
4D
RW
0E
PMA10_RA
4E
RW
0F
PMA11_RA
4F
RW
PRT4DM0
10
RW
PMA12_RA
50
RW
PRT4DM1
11
RW
PMA13_RA
51
RW
12
PMA14_RA
52
RW
13
PMA15_RA
53
RW
14
EP1_CR0
54
#
15
EP2_CR0
55
#
16
EP3_CR0
56
#
17
EP4_CR0
57
#
18
EP5_CR0
58
#
19
EP6_CRO
59
#
1A
EP7_CR0
5A
#
1B
EP8_CR0
5B
#
1C
5C
1D
5D
1E
5E
1F
5F
20
60
21
61
22
62
23
63
24
64
25
65
26
66
27
67
28
68
SPI_CFG
29
RW
69
2A
6A
2B
6B
2C
TMP_DR0
6C
RW
2D
TMP_DR1
6D
RW
2E
TMP_DR2
6E
RW
2F
TMP_DR3
6F
RW
USB_CR1
30
#
70
31
71
32
72
USBIO_CR2
33
RW
73
PMA0_WA
34
RW
74
PMA1_WA
35
RW
75
PMA2_WA
36
RW
76
PMA3_WA
37
RW
77
PMA4_WA
38
RW
78
PMA5_WA
39
RW
79
PMA6_WA
3A
RW
7A
PMA7_WA
3B
RW
7B
PMA0_RA
3C
RW
7C
PMA1_RA
3D
RW
7D
PMA2_RA
3E
RW
7E
PMA3_RA
3F
RW
7F
Gray fields are reserved; do not access these fields.
# Access is bit specific.
Document Number: 001-12394 Rev *I
Name
Addr (1,Hex) Access
Name
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
IO_CFG
9D
OUT_P1
9E
9F
A0
OSC_CR0
A1
ECO_CFG
A2
OSC_CR2
A3
VLT_CR
A4
VLT_CMP
A5
A6
A7
A8
IMO_TR
A9
ILO_TR
AA
AB
SLP_CFG
AC
SLP_CFG2
AD
SLP_CFG3
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
CPU_F
B8
B9
BA
BB
BC
BD
BE
BF
Addr (1,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
RW
RW
#
RW
RW
R
W
W
RW
RW
RW
RL
Page 15 of 32
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CY7C6431x
CY7C6434x, CY7C6435x
Electrical Specifications
This section presents the DC and AC electrical specifications of the enCoRe V USB devices. For the most up to date electrical
specifications, verify that you have the most recent data sheet available by visiting the company web site at http://www.cypress.com
Figure 9. Voltage versus CPU Frequency
Figure 10. IMO Frequency Trim Options
5.5V
5.5V
Vdd Voltage
Vdd Voltage
lid ng
Va rati n
e io
Op eg
R
SLIMO
Mode
= 01
SLIMO
Mode
= 00
SLIMO
Mode
= 10
3.0V
3.0V
5.7 MHz
750 kHz
24 MHz
3 MHz
6 MHz 12 MHz 24 MHz
IMO Frequency
CPU Frequency
The following table lists the units of measure that are used in this section.
Table 7. Units of Measure
Symbol
oC
dB
fF
Hz
KB
Kbit
kHz
kΩ
MHz
MΩ
μA
μF
μH
μs
μV
μVrms
Unit of Measure
degree Celsius
decibels
femto farad
hertz
1024 bytes
1024 bits
kilohertz
kilohm
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microvolts
microvolts root-mean-square
Document Number: 001-12394 Rev *I
Symbol
μW
mA
ms
mV
nA
ns
nV
Ω
pA
pF
pp
ppm
ps
sps
σ
V
Unit of Measure
microwatts
milli-ampere
milli-second
milli-volts
nanoampere
nanosecond
nanovolts
ohm
picoampere
picofarad
peak-to-peak
parts per million
picosecond
samples per second
sigma: one standard deviation
volts
Page 16 of 32
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CY7C6434x, CY7C6435x
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 8. Absolute Maximum Ratings
Symbol
Description
[3]
Conditions
Min
Typ
Max
Units
Higher storage temperatures reduces data
retention time. Recommended Storage
Temperature is +25°C ± 25°C. Extended
duration storage temperatures above 85oC
degrades reliability.
–55
+25
+125
°C
–0.5
–
+6.0
V
TSTG
Storage Temperature
Vdd
Supply Voltage Relative to Vss
VIO
DC Input Voltage
Vss – 0.5
–
Vdd + 0.5
V
VIOZ
DC Voltage Applied to Tristate
Vss –0.5
–
Vdd + 0.5
V
IMIO
Maximum Current into any Port Pin
ESD
Electro Static Discharge Voltage
Human Body Model ESD
LU
Latch up Current
In accordance with JESD78 standard
–25
–
+50
mA
2000
–
–
V
–
–
200
mA
Min
Typ
Max
Units
–40
–
+85
°C
+70
°C
+100
°C
+85
°C
Operating Temperature
Table 9. Operating Temperature
Symbol
Description
Conditions
TAI
Ambient Industrial Temperature
TAC
Ambient Commercial Temperature
TJI
Operational Industrial Die
Temperature[4]
The temperature rise from ambient to junction
is package specific. Refer the table “Thermal
Impedances per Package” on page 29. The
user must limit the power consumption to
comply with this requirement.
–40
Operational Commercial Die
Temperature
The temperature rise from ambient to junction
is package specific. Refer the table “Thermal
Impedances per Package” on page 29. The
user must limit the power consumption to
comply with this requirement.
0
TJC
0
–
Notes
3. Higher storage temperatures reduce data retention time. Recommended storage temperature is +25°C ± 25°C. Extended duration storage temperatures above 85oC
degrade reliability.
4. The temperature rise from ambient to junction is package specific. See Package Handling on page 29. The user must limit the power consumption to comply with this
requirement.
Document Number: 001-12394 Rev *I
Page 17 of 32
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CY7C6434x, CY7C6435x
DC Electrical Characteristics
DC Chip Level Specifications
Table 10 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 10.DC Chip Level Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
Vdd
Operating Voltage
No USB Activity.
3.0
–
5.5
V
IDD24,3
Supply Current, CPU= 24 MHz
Conditions are Vdd = 3.0V, TA = 25oC,
CPU = 24 MHz,
No USB/I2C/SPI.
–
2.9
4.0
mA
IDD12,3
Supply Current, CPU= 12 MHz
Conditions are Vdd = 3.0V, TA = 25oC,
CPU = 12 MHz,
No USB/I2C/SPI.
–
1.7
2.6
mA
IDD6,3
Supply Current, CPU= 6 MHz
Conditions are Vdd = 3.0V, TA = 25oC,
CPU = 6 MHz,
No USB/I2C/SPI.
–
1.2
1.8
mA
ISB1,3
Standby Current with POR, LVD, and
Sleep Timer
Vdd = 3.0V, TA = 25oC, I/O regulator
turned off.
–
1.1
1.5
μA
ISB0,3
Deep Sleep Current
Vdd = 3.0V, TA = 25oC, I/O regulator
turned off.
–
0.1
–
μA
VddUSB
Operating Voltage
USB Activity
4.35
–
5.25
V
IDD24,5
Supply Current, CPU= 24 MHz
Conditions are Vdd = 5.0V, TA = 25oC,
CPU = 24 MHz, IMO = 24 MHz
USB Active, No I2C/SPI.
–
7.1
–
mA
IDD12,5
Supply Current, CPU= 12 MHz
Conditions are Vdd = 5.0V, TA = 25oC,
CPU = 12 MHz, IMO = 24 MHz
USB Active, No I2C/SPI.
–
6.2
–
mA
IDD6,5
Supply Current, CPU= 6 MHz
Conditions are Vdd = 5.0V, TA = 25oC,
CPU = 6 MHz, IMO = 24 MHz
USB Active, No I2C/SPI
–
5.8
–
mA
ISB1,5
Standby Current with POR, LVD, and
Sleep Timer
Vdd = 5.0V, TA = 25oC, I/O regulator
turned off.
–
1.1
–
μA
ISB0,5
Deep Sleep Current
Vdd = 5.0V, TA = 25oC, I/O regulator
turned off.
–
0.1
–
μA
Min
Typ
Max
Units
Table 11.DC Characteristics – USB Interface
Symbol
Description
Conditions
Rusbi
USB D+ Pull Up Resistance
With idle bus
0.900
-
1.575
kΩ
Rusba
USB D+ Pull Up Resistance
While receiving traffic
1.425
-
3.090
kΩ
Vohusb
Static Output High
2.8
-
3.6
V
Volusb
Static Output Low
-
0.3
V
Vdi
Differential Input Sensitivity
0.2
-
–
V
Vcm
Differential Input Common Mode Range
0.8
-
2.5
V
Vse
Single Ended Receiver Threshold
0.8
Cin
Transceiver Capacitance
Iio
High Z State Data Line Leakage
Rps2
PS/2 Pull Up Resistance
Rext
External USB Series Resistor
Document Number: 001-12394 Rev *I
On D+ or D- line
In series with each USB pin
-
2.0
V
-
50
pF
-10
-
+10
μA
3
5
7
kΩ
21.78
22.0
22.22
Ω
Page 18 of 32
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CY7C6434x, CY7C6435x
ADC Electrical Specifications
Table 12. ADC User Module Electrical Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
VREFADC
V
5
pF
Input
VIN
Input Voltage Range
CIIN
Input Capacitance
RIN
Input Resistance
0
Equivalent switched cap input
resistance for 8-, 9-, or 10-bit
resolution
1/(500fF*
1/(400fF*
1/(300fF*
Data Clock) Data Clock) Data Clock)
Ω
Reference
VREFADC
ADC Reference Voltage
1.14
1.26
V
2.25
6
MHz
Conversion Rate
FCLK
Data Clock
Source is chip’s internal main
oscillator. See AC Chip-Level
Specifications for accuracy
S8
8-bit Sample Rate
Data Clock set to 6 MHz.
Sample Rate = 0.001/
(2^Resolution/Data Clock)
23.4375
ksps
S10
10-bit Sample Rate
Data Clock set to 6 MHz.
Sample Rate = 0.001/
(2^Resolution/Data Clock)
5.859
ksps
RES
Resolution
Can be set to 8-, 9-, or 10-bit
DNL
Differential Nonlinearity
-1
+2
LSB
INL
Integral Nonlinearity
-2
+2
LSB
EOffset
Offset Error
DC Accuracy
Egain
Gain Error
8
10
bits
8-bit resolution
0
3.2
19.2
LSB
10-bit resolution
0
12.8
76.8
LSB
For any resolution
-5
+5
%FSR
2.6
mA
Power
IADC
Operating Current
PSRR
Power Supply Rejection
Ratio
Document Number: 001-12394 Rev *I
2.1
PSRR (Vdd>3.0V)
24
dB
PSRR (Vdd<3.0V)
30
dB
Page 19 of 32
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CY7C6434x, CY7C6435x
DC General Purpose IO Specifications
Table 13 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 5.5V and package
specific temperature range. Typical parameters apply to 5V and 3.3V at 25°C. These are for design guidance only.
Table 13. 3.0V and 5.5V DC GPIO Specifications
Symbol
RPU
VOH1
VOL
Description
Pull Up Resistor
High Output Voltage
Port 2 or 3 Pins
High Output Voltage
Port 2 or 3 Pins
High Output Voltage
Port 0 or 1 Pins with LDO Regulator
Disabled
High Output Voltage
Port 0 or 1 Pins with LDO Regulator
Disabled
High Output Voltage
Port 1 Pins with LDO Regulator Enabled
for 3V Out
High Output Voltage
Port 1 Pins with LDO Regulator Enabled
for 3V Out
High Output Voltage
Port 1 Pins with LDO Enabled for 2.5V
Out
High Output Voltage
Port 1 Pins with LDO Enabled for 2.5V
Out
High Output Voltage
Port 1 Pins with LDO Enabled for 1.8V
Out
High Output Voltage
Port 1 Pins with LDO Enabled for 1.8V
Out
Low Output Voltage
VIL
VIH
VH
IIL
CPIN
Input Low Voltage
Input High Voltage
Input Hysteresis Voltage
Input Leakage (Absolute Value)
Pin Capacitance
VOH2
VOH3
VOH4
VOH5
VOH6
VOH7
VOH8
VOH9
VOH10
Document Number: 001-12394 Rev *I
Conditions
Min
4
IOH < 10 µA, maximum of 10 mA source Vdd - 0.2
current in all I/Os.
IOH = 1 mA, maximum of 20 mA source Vdd - 0.9
current in all I/Os.
IOH < 10 µA, maximum of 10 mA source Vdd - 0.2
current in all I/Os.
Typ
5.6
–
Max
8
–
Units
kΩ
V
–
–
V
–
–
V
IOH = 5 mA, maximum of 20 mA source Vdd - 0.9
current in all I/Os.
–
–
V
IOH < 10 μA, Vdd > 3.1V, maximum of
4 I/Os all sourcing 5 mA
2.85
3.00
3.3
V
IOH = 5 mA, Vdd > 3.1V, maximum of
20 mA source current in all I/Os
2.20
–
–
V
IOH < 10 μA, Vdd > 3.0V, maximum of
20 mA source current in all I/Os
2.35
2.50
2.75
V
IOH = 2 mA, Vdd > 3.0V, maximum of
20 mA source current in all I/Os
1.90
–
–
V
IOH < 10 μA, Vdd > 3.0V, maximum of
20 mA source current in all I/Os
1.60
1.80
2.1
V
IOH = 1 mA, Vdd > 3.0V, maximum of
20 mA source current in all I/Os
1.20
–
–
V
IOL = 25 mA, Vdd > 3.3V, maximum of
60 mA sink current on even port pins
(for example, P0[2] and P1[4]) and 60
mA sink current on odd port pins (for
example, P0[3] and P1[5]).
–
–
0.75
V
–
2.0
–
0.5
–
–
80
0.001
1.7
0.8
V
V
mV
µA
pF
Package and pin dependent.
Temp = 25oC.
1
5
Page 20 of 32
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DC POR and LVD Specifications
Table 14 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 14. DC POR and LVD Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
-
2.82
2.95
V
–
–
2.85
2.95
3.06
––
4.62
–
–
2.92
3.02
3.13
–
–
4.73
–
–
2.99
3.09
3.20
–
–
4.83
V
V
V
V
V
V
V
V
Typ
–
Max
5.25
Units
V
5
25
mA
–
VIL
V
–
–
V
–
0.2
mA
–
1.5
mA
–
Vss + 0.75
V
–
VddIWRITE
V
–
–
20
–
Cycle
s
Years
[5]
VPPOR
Vdd Value for PPOR Trip
PORLEV[1:0] = 10b, HPOR = 1
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
DC Programming Specifications
Table 15 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 15. DC Programming Specifications
Symbol
Description
Conditions
Min
VddIWRITE Supply Voltage for Flash Write Opera1.71
tions
IDDP
Supply Current During Programming or
–
Verify
VILP
Input Low Voltage During Programming See appropriate DC General
–
or Verify
Purpose IO Specifications table
VIHP
Input High Voltage During Programming
0.65xVddIWRITE
or Verify
IILP
Input Current when Applying Vilp to
–
P1[0] or P1[1] During Programming or
Verify[6]
IIHP
Input Current when Applying Vihp to
–
P1[0] or P1[1] During Programming or
Verify[6]
VOLP
Output Low Voltage During
–
Programming or Verify
VOHP
Output High Voltage During
VddIWRITE Programming or Verify
0.9V
FlashENPB Flash Write Endurance[7]
50,000
FlashDR
Flash Data Retention[8]
10
Notes
5. Always greater than 50 mV above VPPOR (PORLEV = 10) for falling supply.
6. Driving internal pull down resistor.
7. Erase/write cycles per block.
8. Following maximum Flash write cycles at Tamb = 55C and Tj = 70C.
Document Number: 001-12394 Rev *I
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AC Electrical Characteristics
AC Chip Level Specifications
The following tables list guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 16. AC Chip Level Specifications
Symbol
FCPU
F32K1
F32K_U
Description
Conditions
Processing Frequency[9]
Internal Low Speed Oscillator Frequency
Trimmed[10]
Internal Low Speed Oscillator (ILO) Untrimmed
Frequency)
F32K2
Internal Low Speed Oscillator Frequency
Untrimmed
FIMO24
Internal Main Oscillator Stability for 24 MHz ±
5%(12)
FIMO12
Internal Main Oscillator Stability for 12 MHz[10]
FIMO6
Internal Main Oscillator Stability for 6 MHz[10]
DCIMO
Duty Cycle of IMO
DCILO
Internal Low Speed Oscillator Duty Cycle
SRPOWER_UP Power Supply Slew Rate
TXRST
External Reset Pulse Width at Power Up
After supply voltage
is valid
[11]
TXRST2
External Reset Pulse Width after Power Up
Applies after part
has booted
Min
5.7
19
13
Typ
–
32
32
Max
25.2
50
82
Units
MHz
kHz
kHz
13
22.8
32
24
82
25.2
kHz
MHz
11.4
5.7
40
40
–
1
12
6.0
50
50
–
–
12.6
6.3
60
60
250
–
MHz
MHz
%
%
V/ms
ms
10
–
–
μs
Min
Typ
Max
Units
Table 17.AC Characteristics – USB Data Timings
Symbol
Description
Conditions
Tdrate
Full speed data rate
Average bit rate
11.97
12
12.03
MHz
Tdjr1
Receiver data jitter tolerance
To next transition
-18.5
–
18.5
ns
Tdjr2
Receiver data jitter tolerance
To pair transition
-9
–
9
ns
Tudj1
Driver differential jitter
To next transition
-3.5
–
3.5
ns
Tudj2
Driver differential jitter
To pair transition
-4.0
–
4.0
ns
Tfdeop
Source jitter for differential transition
To SE0 transition
-2
–
5
ns
175
Tfeopt
Source SE0 interval of EOP
160
–
Tfeopr
Receiver SE0 interval of EOP
82
–
ns
Tfst
Width of SE0 interval during differential
transition
–
–
14
ns
Min
Typ
Max
Units
ns
Table 18.AC Characteristics – USB Driver
Symbol
Description
Conditions
Tr
Transition rise time
50 pF
4
–
20
ns
Tf
Transition fall time
50 pF
4
–
20
ns
TR
Rise/fall time matching
90.00
–
111.1
%
Vcrs
Output signal crossover voltage
1.3
–
2.0
V
Notes
9. Vdd = 3.0V and TJ = 85oC, CPU speed.
10. Trimmed for 3.3V operation using factory trim values.
11. The minimum required XRES pulse length is longer when programming the device (see Table
Document Number: 001-12394 Rev *I
21 on page 24).
Page 22 of 32
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AC General Purpose I/O Specifications
Table 19 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 19. AC GPIO Specifications
Symbol
FGPIO
Description
GPIO Operating Frequency
TRise23
Rise Time, Strong Mode
Ports 2, 3
Rise Time, Strong Mode
Ports 0, 1
Fall Time, Strong Mode
All Ports
TRise01
TFall
Conditions
Normal Strong Mode,
Ports 0, 1
Vdd = 3.0 to 3.6V,
10% - 90%
Vdd = 3.0 to 3.6V,
10% - 90%
Vdd = 3.0 to 3.6V,
10% - 90%
Min
-
Typ
–
Max
12
Units
MHz
15
–
80
ns
10
–
50
ns
10
–
50
ns
Max
Units
Figure 11. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TFall
TRise23
TRise01
AC External Clock Specifications
Table 20 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 20. AC External Clock Specifications
Symbol
Description
Conditions
Min
Typ
FOSCEXT
Frequency
0.750
–
25.2
MHz
–
High Period
20.6
–
5300
ns
–
Low Period
20.6
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Document Number: 001-12394 Rev *I
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AC Programming Specifications
Table 21 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 21. AC Programming Specifications
Symbol
TRSCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
TERASEB
TWRITE
TDSCLK1
TDSCLK2
TXRST3
Description
Rise Time of SCLK
Fall Time of SCLK
Data Setup Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
Flash Erase Time (Block)
Flash Block Write Time
Data Out Delay from Falling Edge of SCLK,
Data Out Delay from Falling Edge of SCLK
External Reset Pulse Width after Power Up
Conditions
Vdd > 3.6V
3.0V<Vdd<3.6V
Required to enter programming
mode when coming out of sleep
Min
1
1
40
40
0
–
–
–
–
263
Typ
–
–
–
–
–
–
–
–
–
–
Max
20
20
–
–
8
18
25
60
85
–
Units
ns
ns
ns
ns
MHz
ms
ms
ns
ns
μs
Figure 12. Timing Diagram - AC Programming Cycle
Document Number: 001-12394 Rev *I
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AC I2C Specifications
Table 22 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 22. AC Characteristics of the I2C SDA and SCL Pins
Symbol
Description
FSCLI2C
SCL Clock Frequency
THDSTAI2C Hold Time (repeated) START Condition. After this period, the first
clock pulse is generated
TLOWI2C
LOW Period of the SCL Clock
THIGHI2C HIGH Period of the SCL Clock
TSUSTAI2C Setup Time for a Repeated START Condition
THDDATI2C Data Hold Time
TSUDATI2C Data Setup Time
TSUSTOI2C Setup Time for STOP Condition
TBUFI2C
Bus Free Time Between a STOP and START Condition
Pulse Width of spikes are suppressed by the input filter
TSPI2C
Standard Mode
Min
Max
0
100
4.0
–
4.7
4.0
4.7
0
250
4.0
4.7
–
–
–
–
–
–
–
–
–
Fast Mode
Min
Max
0
400
0.6
–
1.3
0.6
0.6
0
100[12]
0.6
1.3
0
Units
kHz
μs
μs
μs
μs
μs
ns
μs
μs
ns
–
–
–
–
–
–
–
50
Figure 13. Definition of Timing for Fast/Standard Mode on the I2C Bus
SDA
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Note
12. A Fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement tSUDAT ≥ 250 ns must then be met. This is automatically the case
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line trmax + tSUDAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification) before the SCL line is released.
Document Number: 001-12394 Rev *I
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Table 23. SPI Master AC Specifications
Symbol
Description
Conditions
Min
FSCLK
SCLK clock frequency
DC
SCLK duty cycle
–
TSETUP
MISO to SCLK setup time
THOLD
SCLK to MISO hold time
TOUT_VAL
SCLK to MOSI valid time
TOUT_HIGH
MOSI high time
Min
Typ
Max
Units
–
6
MHz
50
–
%
60
–
–
ns
40
–
–
ns
–
–
40
ns
40
–
–
ns
Typ
Max
Units
12
MHz
Table 24.SPI Slave AC Specifications
Symbol
Description
Conditions
FSCLK
SCLK clock frequency
0.0469
TLOW
SCLK low time
41.67
ns
THIGH
SCLK high time
41.67
ns
TSETUP
MOSI to SCLK setup time
30
ns
THOLD
SCLK to MOSI hold time
50
ns
TSS_MISO
SS high to MISO valid
153
ns
TSCLK_MISO
SCLK to MISO valid
125
ns
TSS_HIGH
SS high time
50
ns
TSS_CLK
Time from SS low to first SCLK
2/SCLK
ns
TCLK_SS
Time from last SCLK to SS high
2/SCLK
ns
Document Number: 001-12394 Rev *I
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Package Diagram
This section illustrates the packaging specifications for the enCoRe V USB device, along with the thermal impedances for each
package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the enCoRe V emulation tools and their dimensions, refer to the development kit.
Packaging Dimensions
Figure 14. 16-Pin (3 x 3 mm) QFN (001-09116)
001-09116 *D
Document Number: 001-12394 Rev *I
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Figure 15. 32-Pin (5 x 5 x 0.55 mm) QFN (001-42168)
001-42168 *C
Figure 16. 48-Pin QFN (7 x 7x 0.90 mm) Sawn (001-13191)
001-13191 *D
Document Number: 001-12394 Rev *I
Page 28 of 32
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Package Handling
Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving
the factory. A label on the package has details about the actual bake temperature and the minimum bake time to remove this moisture.
The maximum bake time is the aggregate time that the parts exposed to the bake temperature. Exceeding this exposure may degrade
device reliability.
Table 25.Package Handling
Parameter
Description
Minimum
TBAKETEMP
Bake Temperature
TBAKETIME
Bake Time
Typical
Maximum
125
See package label
See package label
Unit
o
C
72
hours
Thermal Impedances
Table 26. Thermal Impedances per Package
Typical θJA[13]
32.69 oC/W
19.51 oC/W
17.68oC/W
Package
16 QFN
32 QFN[14]
48 QFN[14]
Capacitance on Crystal Pins
Table 27. Typical Package Capacitance on Crystal Pins
Package
Package Capacitance
32 QFN
3.2 pF
48 QFN
3.3 pF
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 28.Solder Reflow Peak Temperature
Package
Minimum Peak Temperature[15]
Maximum Peak Temperature
16 QFN
240oC
260oC
32 QFN
240oC
260oC
48 QFN
240oC
260oC
Notes
13. TJ = TA + Power x θJA.
14. To achieve the thermal impedance specified for the package, solder the center thermal pad to the PCB ground plane.
15. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5°C with Sn-Pb or 245 ± 5°C with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
Document Number: 001-12394 Rev *I
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Ordering Information
Table 29.Ordering Code - Commercial Parts
Ordering Code
Package
Information
Flash SRAM No. of GPIOs
Target Applications
CY7C64315-16LKXC
16-Pin QFN
(3x3 mm)
16K
1K
11
Mid-tier Full-Speed USB dongle,
Remote Control Host Module, Various
CY7C64315-16LKXCT
16-Pin QFN
(Tape and Reel), (3x3 mm)
16K
1K
11
Mid-tier Full-Speed USB dongle,
Remote Control Host Module, Various
CY7C64316-16LKXC
16-Pin QFN
(3x3 mm)
32K
2K
11
Feature-rich Full-Speed USB dongle,
Remote Control Host Module, Various
CY7C64316-16LKXCT
16-Pin QFN
(Tape and Reel), (3x3 mm)
32K
2K
11
Feature-rich Full-Speed USB dongle,
Remote Control Host Module, Various
CY7C64343-32LQXC
32-Pin QFN
(5x5x0.55 mm)
8K
1K
25
Full-speed USB mouse, Various
CY7C64343-32LQXCT
32-Pin QFN
(Tape and Reel), (5X5 mm)
8K
1K
25
Full-speed USB mouse, Various
CY7C64345-32LQXC
32-Pin QFN
(5x5x mm)
16K
1K
25
Full-speed USB mouse, Various
CY7C64345-32LQXCT
32-Pin QFN
(Tape and Reel), (5x5x mm)
16K
1K
25
Full-speed USB mouse, Various
CY7C64355-48LTXC
48-Pin QFN
(7x7 mm)
16K
1K
36
Full-speed USB keyboard, Various
CY7C64355-48LTXCT
48-Pin QFN
(Tape and Reel), (7x7 mm)
16K
1K
36
Full-speed USB keyboard, Various
CY7C64356-48LTXC
48-Pin QFN
(7x7 mm)
32K
2K
36
Feature-rich Full-Speed USB
keyboard, Various
CY7C64356-48LTXCT
48-Pin QFN
(Tape and Reel), (7x7 mm)
32K
2K
36
Feature-rich Full-Speed USB
keyboard, Various
Table 30.Ordering Code - Industrial Parts
Ordering Code
Package
Information
Flash SRAM No. of GPIOs
Target Applications
CY7C64315-16LKXI
16-Pin QFN, Industrial
(3x3 mm)
16K
1K
11
Mid-tier Full-Speed USB dongle,
Remote Control Host Module, Various
CY7C64315-16LKXIT
16-Pin QFN, Industrial
(Tape and Reel), (3x3 mm)
16K
1K
11
Mid-tier Full-Speed USB dongle,
Remote Control Host Module, Various
CY7C64343-32LQXI
32-Pin QFN, Industrial
(5x5x0.55 mm)
8K
1K
25
Full-speed USB mouse, Various
CY7C64343-32LQXIT
32-Pin QFN, Industrial
(Tape and Reel), (5X5 mm)
8K
1K
25
Full-speed USB mouse, Various
CY7C64345-32LQXI
32-Pin QFN, Industrial
(5x5x mm)
16K
1K
25
Full-speed USB mouse, Various
CY7C64345-32LQXIT
32-Pin QFN, Industrial
(Tape and Reel), (5x5x mm)
16K
1K
25
Full-speed USB mouse, Various
CY7C64356-48LTXI
48-Pin QFN, Industrial
(7x7 mm)
32K
2K
36
Feature-rich Full-Speed USB
keyboard, Various
CY7C64356-48LTXIT
48-Pin QFN, Industrial
(Tape and Reel), (7x7 mm)
32K
2K
36
Feature-rich Full-Speed USB
keyboard, Various
Document Number: 001-12394 Rev *I
Page 30 of 32
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CY7C6431x
CY7C6434x, CY7C6435x
Document History Page
Document Title: CY7C6431x, CY7C6434x, CY7C6435x enCoRe™ V Full Speed USB Controller
Document Number: 001-12394
Rev. ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
626256
TYJ
See ECN
New data sheet.
*A
735718
TYJ/ARI
See ECN
Filled in TBDs, added new block diagram, and corrected some values. Part numbers
updated as per new specifications.
*B
1120404
ARI
See ECN
Corrected the block diagram and Figure 3, which is the 16-pin enCoRe V device.
Corrected the description to pin 29 on Table 2, the Typ/Max values for ISB0 on the DC
chip-level specifications, the current value for the latch-up current in the Electrical
Characteristics section, and corrected the 16 QFN package information in the
Thermal Impedance table.
Corrected some of the bulleted items on the first page.
Added DC Characteristics–USB Interface table.
Added AC Characteristics–USB Data Timings table.
Added AC Characteristics–USB Driver table.
Corrected Flash Write Endurance minimum value in the DC Programming Specifications table.
Corrected the Flash Erase Time max value and the Flash Block Write Time max value
in the AC Programming Specifications table.
Implemented new latest template.
Include parameters: Vcrs, Rpu (USB, active), Rpu (USB suspend), Tfdeop, Tfeopr2,
Tfeopt, Tfst.
Added register map tables.
Corrected a value in the DC Chip-Level Specifications table.
*C
1241024
TYJ/ARI
See ECN
Corrected Idd values in Table 6 - DC Chip-Level Specifications.
*D
1639963
AESA
See ECN
Post to www.cypress.com
*E
2138889
TYJ/PYRS
See ECN
Updated Ordering Code table:
- Ordering code changed for 32-QFN package: From -32LKXC to -32LTXC
- Added a new package type – “LTXC” for 48-QFN
- Included Tape and Reel ordering code for 32-QFN and 48-QFN packages
Changed active current values at 24, 12 and 6MHz in table “DC Chip-Level Specifications”
- IDD24: 2.15 to 3.1mA
- IDD12: 1.45 to 2.0mA
- IDD6: 1.1 to 1.5mA
Added information on using P1[0] and P1[1] as the I2C interface during POR or reset
events
*F
2583853
TYJ/PYRS/
HMT
10/10/08
Converted from Preliminary to Final
Added operating voltage ranges with USB
ADC resolution changed from 10-bit to 8-bit
Rephrased battery monitoring clause in page 1 to include “with external components”
Included ADC specifications table
Included Voh7, Voh8, Voh9, Voh10 specs
Flash data retention – condition added to Note [11]
Input leakage spec changed to 25 nA max
Under AC Char, Frequency accuracy of ILO corrected
GPIO rise time for ports 0,1 and ports 2,3 made common
AC Programming specifications updated
Included AC Programming cycle timing diagram
AC SPI specification updated
Spec change for 32-QFN package
Input Leakage Current maximum value changed to 1 μA
Updated VOHV parameter in Table 13
Updated thermal impedances for the packages
Update Development Tools, add Designing with PSoC Designer. Edit, fix links and
table format. Update TMs.
Document Number: 001-12394 Rev *I
Page 31 of 32
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CY7C6431x
CY7C6434x, CY7C6435x
Document Title: CY7C6431x, CY7C6434x, CY7C6435x enCoRe™ V Full Speed USB Controller
Document Number: 001-12394
*G
2653717 DVJA/PYRS
02/04/09
Updated Features, Functional Overview, Development Tools, and Designing with
PSoC Designer sections with edits.
Removed ‘GUI - graphical user interface’ from Document Conventions acronym table.
Removed ‘O - Only a read/write register or bits’ in Table 4
Edited Table 8: removed 10-bit resolution information and corrected units column.
Added package handling section
Added 8K part ‘CY7C64343-32LQXC’ to Ordering Information.
*H
2714694 DVJA/AESA
06/04/2009 Updated Block Diagram.
Added Full Speed USB, 10-bit ADC, SPI, and I2C Slave sections.
ADC Resolution changed from 8-bit to 10-bit
Updated Table 9 DC Chip Level Specs
Updated Table10 DC Char - USB Interface
Updated Table 12 DC POR and LDV Specs
Changed operating temperature from Commercial to Industrial
Changed Temperature Range to Industrial: -40 to 85°C
Figure 9: Changed minimum CPU Frequency from 750 kHz to 5.7 MHz
Table 14: Removed “Maximum” from the FCPU description
Ordering Information: Replaced ‘C’ with ‘I’ in all part numbers to denote Industrial
Temp Range
*I
2764460 DVJA/AESA
09/16/2009 Changed Table 12: ADC Specs
Added F32K2 (Untrimmed) spec to Table 16: AC Chip level Specs
Changed TRAMP spec to SRPOWER_UP in Table 16: AC Chip Level Specs
Added Table 27: Typical Package Capacitance on Crystal Pins
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© Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-12394 Rev *I
Revised September 15, 2009
Page 32 of 32
enCoRe™, PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corporation. All other trademarks or registered
trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names
mentioned in this document may be the trademarks of their respective holders.
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