‡
AR0141CS: 1/4-Inch Digital Image Sensor
Features
1/4-Inch Digital Image Sensor
AR0141CS Datasheet, Rev. 6
For the latest datasheet, please visit: www.onsemi.com
Features
Table 1:
• Superior low-light performance
• Latest 3.0 m pixel with ON Semiconductor
DR-Pix technology
• Linear range capture
• 1.0 Mp and 720p (16:9) images
• Support for external mechanical shutter
• Support for external LED or xenon flash
• On-chip phase-locked loop (PLL) oscillator
• Integrated position-based color and lens shading
correction
• Slave mode for precise frame-rate control
• Stereo/3D camera support
• Statistics engine
• Data interfaces: four-lane serial high-speed pixel
interface (HiSPi) differential signaling (SLVS and
HiVCM), or parallel
• Auto black level calibration
• High-speed context switching
• Temperature sensor
Parameter
Typical Value
Optical format
1/4-inch
Active pixels
1280(H) x 800(V) (entire
array)
Pixel size
3.0 m x 3.0 m
Color filter array
RGB Bayer, Monochrome,
RGB-IR
Shutter type
Electronic rolling shutter
and GRR
Input clock range
6 – 50 MHz
Output clock maximum
148.5 Mp/s (4-lane HiSPi)
74.25 Mp/s (Parallel)
Output
Frame rate
Serial
HiSPi, 12-bit
Parallel
10-, 12-bit
720p
60 fps
Responsivity
4.0 V/lux-sec
SNRMAX
41 dB
Max Dynamic range
Applications
•
•
•
•
•
Key Parameters
Video surveillance
Scanning
Industrial
Stereo vision
720p60 video applications
Supply
voltage
Up to 79 dB
I/O
1.8 or 2.8 V
Digital
1.8 V
Analog
2.8 V
HiSPi
0.3 V - 0.6 V, 1.7 V - 1.9 V
326 mW (Linear Mode
1280x720 60 fps)
General Description
Power consumption (typical)
The ON Semiconductor AR0141CS is a 1/4-inch CMOS
digital image sensor with an active-pixel array of
1280Hx800V. It captures images in linear mode, with a
rolling-shutter readout. It includes sophisticated camera functions such as in-pixel binning, windowing and
both video and single frame modes. It is designed for
low light scene performance. It is programmable
through a simple two-wire serial interface. The
AR0141CS produces extraordinarily clear, sharp digital
pictures, and its ability to capture both continuous
video and single frames makes it the perfect choice for
a wide range of applications, including surveillance
and HD video.
Operating temperature (ambient) -TA –30°C to + 70° C
AR0141CS/D Rev. 6, 4/16 EN
Package options
1
9x9mm 63-ball iBGA
©Semiconductor Components Industries, LLC 2016,
AR0141CS: 1/4-Inch Digital Image Sensor
Ordering Information
Ordering Information
Table 2:
Available Part Numbers
Part Number
Product Description
Orderable Product Attribute Description
AR0141CS2C00SUEA0-DP
Color IBGA
Dry Pack with Protective Film
AR0141CS2C00SUEA0-DR
Color IBGA
Dry Pack without Protective Film
AR0141CS2C00SUEAD3-GEVK
Color IBGA Demo3 Kit
AR0141CS2C00SUEAH-GEVB
Color IBGA Headboard
AR0141CS2M00SUEA0 - TPBR
Mono iBGA
Tape and Reel with Protective Film
AR0141CS2M00SUEA0 - DPBR
Mono iBGA
Dry Pack with Protective Film
AR0141CS2M00SUEAD3-GEVK
Mono IBGA Demo3 Kit
AR0141CS2M00SUEAH-GEVB
Mono IBGA Headboard
AR0141IRSH00SUEA0-DR
RGB-IR, iBGA, Production
AR0141IRSH00SUEA0D3-GEVK
RGB-IR, Demo3 Kit
AR0141IRSH00SUEA0H3-GEVB
RGB-IR, Head Board
AR0141CSSM21SUEA0-TPBR
Mono, iBGA, 21 deg shift
Dry Pack without Protective Film
Engineering Sample
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full
description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
AR0141CS/D Rev. 6, 4/16 EN
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©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
.Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pixel Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Differentiation from AR0141CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Pixel Output Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Pixel Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Gain Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Data Pedestals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Sensor PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Sensor Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Subsampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Sensor Frame Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Frame Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Changing Sensor Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Two-Wire Serial Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
AR0141CS/D Rev. 6, 4/16 EN
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©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
General Description
General Description
The ON Semiconductor AR0141CS can be operated in its default mode or programmed
for frame size, exposure, gain, and other parameters. The default mode output is a 720presolution image at 60 frames per second (fps). In linear mode, it outputs 12-bit raw
data, using either the parallel or serial (HiSPi) output ports. The device may be operated
in video (master) mode or in single frame trigger mode.
FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a
synchronized pixel clock in parallel mode.
The AR0141CS includes additional features to allow application-specific tuning:
windowing and offset, auto black level correction, and on-board temperature sensor.
Optional register information and histogram statistic information can be embedded in
the first and last 2 lines of the image frame.
.Functional Overview
The AR0141CS is a progressive-scan sensor that generates a stream of pixel data at a
constant frame rate. It uses an on-chip, phase-locked loop (PLL) that can be optionally
enabled to generate all internal clocks from a single master input clock running between
6 and 50 MHz. The maximum output pixel rate is 148.5 Mp/s, corresponding to a clock
rate of 74.25 MHz. Figure 1 shows a block diagram of the sensor.
Figure 1:
Block Diagram
12
ADC data
Row noise correction
Black level correction
Test pattern generator
12 bits
Pixel defect correction
12 or 10 bits
Adaptive CD filter
HiSPi
12
Parallel
Digital gain and
pedestal
User interaction with the sensor is through the two-wire serial bus, which communicates with the array control, analog signal chain, and digital signal chain. The core of the
sensor is a 1.1 Mp Active- Pixel Sensor array. The timing and control circuitry sequences
through the rows of the array, resetting and then reading each row in turn. In the time
interval between resetting a row and reading that row, the pixels in the row integrate
AR0141CS/D Rev. 6, 4/16 EN
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©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
.Functional Overview
incident light. The exposure is controlled by varying the time interval between reset and
readout. Once a row has been read, the data from the columns is sequenced through an
analog signal chain (providing offset correction and gain), and then through an analogto-digital converter (ADC). The output from the ADC is a 12-bit value for each pixel in
the array. The ADC output passes through a digital processing signal chain (which
provides further data path corrections and applies digital gain).
Typical Configuration: Serial Four-Lane HiSPi Interface
VDD_IO
1.5kΩ2
1.5kΩ2
Digital Digital
I/O
Core
power1 power1
VDD
Master clock
(6–50 MHz)
EXTCLK
From
controller
SADDR
SDATA
SCLK
TRIGGER
OE_BAR
RESET_BAR
HiSPi
power1
VDD_SLVS
Figure 2:
VDD
Notes:
AR0141CS/D Rev. 6, 4/16 EN
VDD_SLVS
VDD_PLL
VAA
VDD_PLL
VAA
VAA_PIX
SLVS0_P
SLVS0_N
SLVS1_P
SLVS1_N
SLVS2_P
SLVS2_N
SLVS3_P
To
controller
SLVS3_N
SLVSC_P
SLVSC_N
FLASH
SHUTTER
TEST
VDD_IO
Analog Analog
PLL
power1 power1 power1
DGND
AGND
Digital
ground
Analog
ground
VAA_PIX
1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for
slower two-wire speed.
3. The parallel interface output pads can be left unconnected if the serial output interface is used.
4. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply
are mounted as close as possible to the pad. Actual values and results may vary depending on layout and design considerations. Check the AR0141CS demo headboard schematics for circuit recommendations.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized.
6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.
5
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
.Functional Overview
Figure 3:
Typical Configuration: Parallel Pixel Data Interface
1.5kΩ2,
1.5kΩ2
Digital Digital
core
I/O
power1 power1
Master clock
(6-50 MHz)
VDD_IO
PLL Analog Analog
power1 power1 power1
VDD
EXTCLK
DOUT [11:0]
PIXCLK
LINE_VALID
FRAME_VALID
SADDR
SDATA
SCLK
TRIGGER
OE_BAR
From
Controller
VAA_PIX
VDD_PLL VAA
To
controller
FLASH
SHUTTER
RESET_BAR
TEST
DGND
VDD_IO
VDD
VDD_PLL
VAA
VAA_PIX
Digital
ground
Notes:
AR0141CS/D Rev. 6, 4/16 EN
AGND
Analog
ground
1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for
slower two-wire speed.
3. The serial interface output pads and VDDSLVS can be left unconnected if the parallel output interface is used.
4. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply
are mounted as close as possible to the pad. Actual values and results may vary depending on layout and design considerations. Check the AR0141CS demo headboard schematics for circuit recommendations.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized.
6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.
7. The EXTCLK input is limited to 6-50 MHz.
6
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
.Functional Overview
Figure 4:
9 x 9 mm 63-Ball IBGA Package
1
A
2
3
4
5
6
7
8
SLVS0_N
SLVS0_P
SLVS1_N
SLVS1_P
VDD
VDD
STANDBY
SLVS2_N
SLVS2_P
VDD
VAA
VAA
SLVS3_P
DGND
VDD
AGND
AGND
SDATA
DGND
DGND
VDD
VAA_PIX
VAA_PIX
NC
B
VDD_PLL
SLVS_CN
SLVSC_P
C
EXTCLK
VDD_
SLVS
SLVS3_N
D
SADDR
E
LINE_
VALID
FRAME_
VALID
PIXCLK
FLASH
DGND
VDD_IO
NC
F
DOUT8
DOUT9
DOUT10
DOUT11
DGND
VDD_IO
TEST
G
DOUT4
DOUT5
DOUT6
DOUT7
DGND
VDD_IO
TRIGGER
OE_BAR
H
DOUT0
DOUT1
DOUT2
DOUT3
DGND
VDD_IO
VDD_IO
RESET_
BAR
SCLK
Reserved
Top View
(Ball Down)
Table 3:
Ball Descriptions, 9 x 9 mm, 63-ball iBGA
Name
iBGA Pin
Type
Description
SLVS0_N
A2
Output
HiSPi serial data, lane 0, differential N.
SLVS0_P
A3
Output
HiSPi serial data, lane 0, differential P.
SLVS1_N
A4
Output
HiSPi serial data, lane 1, differential N.
SLVS1_P
A5
Output
STANDBY
A8
Input
STANDBY (active high)
HiSPi serial data, lane 1, differential P.
VDD_PLL
B1
Power
PLL power.
SLVSC_N
B2
Output
HiSPi serial DDR clock differential N.
SLVSC_P
B3
Output
HiSPi serial DDR clock differential P.
SLVS2_N
B4
Output
HiSPi serial data, lane 2, differential N.
SLVS2_P
B5
Output
HiSPi serial data, lane 2, differential P.
VAA
B7, B8
Power
Analog power.
EXTCLK
C1
Input
External input clock.
VDD_SLVS
C2
Power
0.3V-0.6V or 1.7V - 1.9V port to HiSPi Output Driver. Set the High_VCM
(R0x306E[9]) bit to 1 when configuring VDD_SLVS to 1.7 – 1.9V.
SLVS3_N
C3
Output
HiSPi serial data, lane 3, differential N.
SLVS3_P
C4
Output
HiSPi serial data, lane 3, differential P.
AR0141CS/D Rev. 6, 4/16 EN
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©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
.Functional Overview
Table 3:
Ball Descriptions, 9 x 9 mm, 63-ball iBGA (continued)
Name
iBGA Pin
Type
Description
DGND
Power
VDD
C5, D4, D5, E5, F5, G5,
H5
A6, A7, B6, C6, D6
Power
Digital power.
AGND
C7, C8
Power
Analog ground.
SADDR
D1
Input
Two-Wire Serial address select. 0: 0x20. 1: 0x30
SCLK
D2
Input
SDATA
D3
I/O
Digital ground.
Two-Wire Serial clock input.
Two-Wire Serial data I/O.
VAA_PIX
D7, D8
Power
Pixel power.
LINE_VALID
E1
Output
Asserted when DOUT line data is valid.
FRAME_VALID
E2
Output
Asserted when DOUT frame data is valid.
Output
Pixel clock out. DOUT is valid on rising edge of this clock.
PIXCLK
E3
VDD_IO
E6, F6, G6, H6, H7
Power
I/O supply power.
DOUT8
F1
Output
Parallel pixel data output.
DOUT9
F2
Output
Parallel pixel data output.
DOUT10
F3
Output
Parallel pixel data output.
DOUT11
F4
Output
Parallel pixel data output (MSB)
TEST
F7
Input.
Manufacturing test enable pin (connect to DGND).
DOUT4
G1
Output
Parallel pixel data output.
DOUT5
G2
Output
Parallel pixel data output.
DOUT6
G3
Output
Parallel pixel data output.
DOUT7
G4
Output
TRIGGER
G7
Input
Exposure synchronization input.
OE_BAR
G8
Input
Output enable (active LOW).
DOUT0
H1
Output
Parallel pixel data output (LSB)
DOUT1
H2
Output
Parallel pixel data output.
DOUT2
H3
Output
Parallel pixel data output.
DOUT3
H4
Output
RESET_BAR
H8
Input
NC
E8
FLASH
E4
NC
E7
Reserved
F8
AR0141CS/D Rev. 6, 4/16 EN
Output
Parallel pixel data output.
Parallel pixel data output.
Asynchronous reset (active LOW). All settings are restored to factory
default.
Flash control output.
8
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Pixel Data Format
Pixel Data Format
Pixel Array Structure
The AR0141CS pixel array consists of 1280 columns by 800 rows of optically active
pixels.While the sensor's format is 1344 x 848, additional active columns and active rows
are included for use when horizontal or vertical mirrored readout is enabled, to allow
readout to start on the same pixel. The pixel adjustment is always performed for monochrome or color versions. The active area is surrounded with optically transparent
dummy pixels to improve image uniformity within the active area. Not all dummy pixels
or barrier pixels can be read out.
Figure 5:
Pixel Array Description
8
total = 86 8
1348 ( 2+ 1344 + 2)
86 8 ( 8+ 2+ 4+ 848 +6 )
total = 1348
Active pixels
Transport pixels
NOT TO SCALE
All dimensions in PIXELS
unless otherwise stated
AR0141CS/D Rev. 6, 4/16 EN
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©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Differentiation from AR0141CS
Figure 6:
RGB Pixel Color Pattern Detail (Top Right Corner) - AR0141CS
Column Readout Direction
Row Readout Direction
Active Pixel (0,0)
Array Pixel (0, 0)
Figure 7:
R G
R
G R
G R
G
G B
G
B G
B G
B
R G
R
G R
G R
G
G B
G
B G
B G
B
R G
R
G R
G R
G
G B
G
B G
B G
B
RGB-IR Pixel Color Pattern Detail (Top Right Corner) - ARO141IR
Column Readout Direction
Row Readout Direction
Active Pixel (0,0)
Array Pixel (0, 0)
R
IR
R
IR R
IR
R
IR
G
B
G
B
G
B
G
B
R
IR
R
IR R
IR
R
IR
G
B
G
B
G
B
G
B
R
IR
R
IR R
IR
R
IR
G
B
G
B
B
G
B
G
Differentiation from AR0141CS
The AR0141IR can be electrically differentiated from the AR0141CS by reading bits 11:9
in R0x31FA. The AR0141IR contains a unique value of 4 in these bits. It is necessary to set
R0x301A[5]=1 prior to reading R0x31FA[11:9].
AR0141CS/D Rev. 6, 4/16 EN
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©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Differentiation from AR0141CS
Default Readout Order
By convention, the sensor core pixel array is shown with pixel (0,0) in the top right
corner (see Figure 6). This reflects the actual layout of the array on the die. Also, the first
pixel data read out of the sensor in default condition is that of pixel (0, 0).
When the sensor is imaging, the active surface of the sensor faces the scene as shown in
Figure 8. When the image is read out of the sensor, it is read one row at a time, with the
rows and columns sequenced as shown in Figure 8.
Figure 8:
Imaging a Scene
Lens
Scene
Sensor (rear view)
Row
Readout
Order
Column Readout Order
AR0141CS/D Rev. 6, 4/16 EN
Pixel (0,0)
11
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Pixel Output Interfaces
Pixel Output Interfaces
Parallel Interface
The parallel pixel data interface uses these output-only signals:
• FRAME_VALID
• LINE_VALID
• PIXCLK
• DOUT[11:0]
The parallel pixel data interface is disabled by default at power up and after reset. It can
be enabled by programming R0x301A. Table 5 shows the recommended settings.
When the parallel pixel data interface is in use, the serial data output signals can be left
unconnected. Set reset_register [bit 12 (R0x301A[12] = 1)] to disable the serializer while
in parallel output mode.
Output Enable Control
When the parallel pixel data interface is enabled, its signals can be switched asynchronously between the driven and High-Z under pin or register control, as shown in Table 4.
Table 4:
Output Enable Control
OE_BAR Pin
Drive Pins R0x301A[6]
Description
Disabled
Disabled
1
X
0
0
1
0
1
X
Interface High-Z
Interface driven
Interface High-Z
Interface driven
Interface driven
Configuration of the Pixel Data Interface
Fields in R0x301A are used to configure the operation of the pixel data interface. The
supported combinations are shown in Table 5.
Table 5:
Configuration of the Pixel Data Interface
Serializer Disable
R0x301 A[12]
Parallel Enable
R0x301 A[7]
0
0
Power up default.
Serial pixel data interface and its clocks are enabled. Transitions to soft standby are
synchronized to the end of frames on the serial pixel data interface.
1
1
Parallel pixel data interface, sensor core data output. Serial pixel data interface and its
clocks disabled to save power. Transitions to soft standby are synchronized to the end of
frames in the parallel pixel data interface.
AR0141CS/D Rev. 6, 4/16 EN
Description
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AR0141CS: 1/4-Inch Digital Image Sensor
Pixel Output Interfaces
High Speed Serial Pixel Data Interface
The High Speed Serial Pixel (HiSPi) interface uses four data lanes and one clock as
output.
• SLVSC_P
• SLVSC_N
• SLVS0_P
• SLVS0_N
• SLVS1_P
• SLVS1_N
• SLVS2_P
• SLVS2_N
• SLVS3_P
• SLVS3_N
The HiSPi interface supports three protocols, Streaming-S, Streaming-SP, and Packetized
SP. The streaming protocols conform to a standard video application where each line of
active or intra-frame blanking provided by the sensor is transmitted at the same length.
The Packetized SP protocol will transmit only the active data ignoring line-to-line and
frame-to-frame blanking data.
These protocols are further described in the High-Speed Serial Pixel (HiSPi) Interface
Protocol Specification V1.50.00.
The HiSPi interface building block is a unidirectional differential serial interface with
four data and one double data rate (DDR) clock lanes. One clock for every four serial
data lanes is provided for phase alignment across multiple lanes. Figure 9 shows the
configuration between the HiSPi transmitter and the receiver.
Figure 9:
HiSPi Transmitter and Receiver Interface Block Diagram
A camera containing
the HiSPi transmitter
Tx
PHY0
AR0141CS/D Rev. 6, 4/16 EN
A host (DSP) containing
the HiSPi receiver
Dp0
Dp0
Dn0
Dn0
Dp1
Dp1
Dn1
Dn1
Dp2
Dp2
Dn2
Dn2
Dp3
Dp3
Dn3
Dn3
Cp0
Cp0
Cn0
Cn0
13
Rx
PHY0
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Pixel Output Interfaces
HiSPi Physical Layer
The HiSPi physical layer is partitioned into blocks of four data lanes and an associated
clock lane. Any reference to the PHY in the remainder of this document is referring to
this minimum building block.
The PHY will serialize 12-bit data words and transmit each bit of data centered on a
rising edge of the clock, the second on the falling edge of the clock. Figure 10 shows bit
transmission. In this example, the word is transmitted in order of MSB to LSB. The
receiver latches data at the rising and falling edge of the clock.
Figure 10:
Timing Diagram
TxPost
cp
….
cn
TxPre
dp
….
MSB
dn
LSB
1 UI
DLL Timing Adjustment
The specification includes a DLL to compensate for differences in group delay for each
data lane. The DLL is connected to the clock lane and each data lane, which acts as a
control master for the output delay buffers. Once the DLL has gained phase lock, each
lane can be delayed in 1/8 unit interval (UI) steps. This additional delay allows the user
to increase the setup or hold time at the receiver circuits and can be used to compensate
for skew introduced in PCB design.
Delay compensation may be set for clock and/or data lines in the hispi_timing register
R0x31C0. If the DLL timing adjustment is not required, the data and clock lane delay
settings should be set to a default code of 0x000 to reduce jitter, skew, and power dissipation.
delay
data _lane 0
AR0141CS/D Rev. 6, 4/16 EN
delay
delay
DATA3_DEL[2:0]
DATA2_DEL[2:0]
DATA1_DEL[2:0]
CLOCK_DEL[2:0]
Block Diagram of DLL Timing Adjustment
DATA0_DEL[2:0]
Figure 11:
delay
delay
data _lane 1 clock _lane 0 data _lane 2 data _lane 3
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AR0141CS: 1/4-Inch Digital Image Sensor
Pixel Output Interfaces
Figure 12:
Delaying the Clock with Respect to Data
1 UI
dataN (DATAN_DEL = 000)
cp (CLOCK_DEL = 000)
cp (CLOCK_DEL = 001)
cp (CLOCK_DEL = 010)
cp (CLOCK_DEL = 011)
cp (CLOCK_DEL = 100)
cp (CLOCK_DEL = 101)
c p (CLOCK_DEL = 110)
cp (CLOCK_DEL =111)
increasing CLOCK_DEL[2:0] increases clock delay
Figure 13:
Delaying Data with Respect to the Clock
cp ( CLOCK_DEL = 000)
dataN (DATAN_DEL = 000)
dataN(DATAN_DEL = 001)
dataN(DATAN_DEL = 010)
dataN(DATAN_DEL = 011)
dataN(DATAN_DEL = 100)
dataN(DATAN_DEL = 101)
dataN(DATAN_DEL = 110)
dataN(DATAN_DEL = 111)
increasing DATAN_DEL[2:0] increases data delay
t
DLLSTEP
1 UI
HiSPi Protocol Layer
The HiSPi protocol is described in the HiSPi Protocol Specification document.
AR0141CS/D Rev. 6, 4/16 EN
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AR0141CS: 1/4-Inch Digital Image Sensor
Pixel Sensitivity
Serial Configuration
The serial format should be configured using R0x31AC. Refer to the AR0141CS Register
Reference document for more detail regarding this register.
The serial_format register (R0x31AE) controls which serial format is in use when the
serial interface is enabled (reset_register[12] = 0). The following serial formats are
supported:
• 0x0304 - Sensor supports quad-lane HiSPi operation
• 0x0302 - Sensor supports dual-lane HiSPi operation
Pixel Sensitivity
Figure 14:
Integration Control in ERS Readout
Row Integration
(TINTEGRATION)
Row Reset
(Start of Integration)
Row Readout
A pixel's integration time is defined by the number of clock periods between a row's
reset and read operation. Both the read followed by the reset operations occur within a
row period (TROW) where the read and reset may be applied to different rows. The read
and reset operations will be applied to the rows of the pixel array in a consecutive order.
The coarse integration time is defined by the number of row periods (TROW) between a
row's reset and the row read. The row period is defined as the time between row read
operations (see Sensor Frame Rate).
TCOARSE = TROW * coarse_integration_time
Figure 15:
(EQ 1)
Example of 8.33ms Integration in 16.6ms Frame
TCOARSE = coarse_integration_time x TROW
8.33 ms =563 rows x 22.22 μs/row
Read
Reset
Horizontal Blanking
Vertical Blanking
TFRAME = frame_length_lines x TROW
16.6 ms = 750 rows x 22.22 μs/row
Time
Vertical Blanking
AR0141CS/D Rev. 6, 4/16 EN
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AR0141CS: 1/4-Inch Digital Image Sensor
Pixel Sensitivity
Figure 16:
Row Read and Row Reset Showing Fine Integration
Start of Read Row N + 1
and Reset Row K + 1
Start of Read Row N
and Reset Row K
Read Row N
Reset Row K
T FIN E = fine_integration _time x (1/CLK_PIX)
TROW = line_length _pck x (1/CLK_PIX)
TFINE = fine_integration_time/clk_pix
(EQ 2)
The maximum allowed value for fine_integration_time is
line_length_pck - fine_integration_time_max_margin
Figure 17:
(EQ 3)
Row Integration Time is Greater Than the Frame Readout Time
TCOARSE=coarse_integration_time x TROW
20.7ms = 930 rows x 22.22 μs/row
R ead
P ointer
Horizontal B lank ing
V ertic al B lank ing
Im age
TFRAME = frame_length_lines x TROW
16.6ms = 750 rows x 22.22 μs/row
V ertic al B lank ing
T im e
S hutter
P ointer
Horizontal B lank ing
E x tended V ertic al B lank ing
4.1 m s
Im age
The minimum frame-time is defined by the number of row periods per frame and the
row period. The sensor frame-time will increase if the coarse_integration_time is set to a
value equal to or greater than the frame_length_lines.
AR0141CS/D Rev. 6, 4/16 EN
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AR0141CS: 1/4-Inch Digital Image Sensor
Gain Stages
Gain Stages
The sensor analog gain stage will apply the same analog gain to each color channel.
Digital gain can be configured to separate levels for each color channel.
The level of analog gain applied is controlled by the coarse_gain and fine_gain at
R0x3060 analog gain register. The analog readout circuitry can be configured differently
for each analog gain level. Total analog gain is (2coarse_gain) x(1+fine_gain/16), where
coarse_gain = R0x3060[6:4], fine_gain = R0x3060[3:0]. ON Semiconductor recommends
limiting maximum analog gain up to 12x gain for optimal image quality.
Each digital gain can be configured from a gain of 0 to 15.992 using R0x3056, R0x3058,
R0x305A, R0x305C, and R0x305E digital gain registers. The digital gain supports 128 gain
steps per 6dB of gain. The format of each digital gain register is “xxxx.yyyyyyy” where
“xxxx” refers an integer gain of 1 to 15 and “yyyyyyy” is a fractional gain ranging from 0/
128 to 127/128.
The sensor includes a digital dithering feature to reduce quantization noise resulting
from using digital gain. It can be implemented by setting R0x30BA[5] to 1. The default
value is 0.
AR0141CS/D Rev. 6, 4/16 EN
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AR0141CS: 1/4-Inch Digital Image Sensor
Data Pedestals
Data Pedestals
The data pedestal is a constant offset that is added to pixel values at the end of the datapath. The default offset is 168 and is a 12-bit offset. This offset matches the maximum
range used by the corrections in the digital readout path. The purpose of the data
pedestal is to convert negative values generated by the digital datapath into positive
output data.
Reset
The AR0141CS may be reset by the RESET_BAR pin (active LOW) or the reset register.
Hard Reset of Logic
The host system can reset the image sensor by bringing the RESET_BAR pin to a LOW
state. Alternatively, the RESET_BAR pin can be connected to an external RC circuit for
simplicity. Registers written via the two-wire interface will not be preserved following a
hard reset.
Soft Reset of Logic
Soft reset of logic is controlled by the R0x301A Reset register. Bit 0 is used to reset the
digital logic of the sensor. Furthermore, by asserting the soft reset, the sensor aborts the
current frame it is processing and starts a new frame. This bit is a self-resetting bit and
also returns to “0” during two-wire serial interface reads.
Clocks
The AR0141CS requires one clock input (EXTCLK).
Sensor PLL
VCO
Figure 18:
PLL Dividers Affecting VCO Frequency
EXTCLK
(6-50 MHz)
pre_pll_clk_div
2 (1-64)
pll_multiplier
58 (32-384)
FVCO
The sensor contains a phase-locked loop (PLL) that is used for timing generation and
control. The required VCO clock frequency is attained through the use of a pre-PLL clock
divider followed by a multiplier. The PLL multiplier should be an even integer. If an odd
integer (M) is programmed, the PLL will default to the lower (M-1) value to maintain an
even multiplier value. The multiplier is followed by a set of dividers used to generate the
output clocks required for the sensor array, the pixel analog and digital readout paths,
and the output parallel and serial interfaces.
AR0141CS/D Rev. 6, 4/16 EN
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AR0141CS: 1/4-Inch Digital Image Sensor
Sensor PLL
Parallel PLL Configuration
Figure 19:
PLL for the Parallel Interface
.
F VCO
EXTCLK
(6-50 MHz)
pre_pll_clk_div
2 (1-64)
vt_sys_clk_div
1 (1, 2, 4, 6, 8,
10, 12, 14, 16)
pll_multiplier
58 (32-384)
vt_pix_clk_div
6 (4-16)
CLK_OP
(Max 74.25 Mp/s)
The maximum output of the parallel interface is 74.25 MPixel/s. The sensor will not use
the FSERIAL, FSERIAL_CLK, or CLK_OP when configured to use the parallel interface.
Table 6:
PLL Parameters for the Parallel Interface
Parameter
Symbol
Min
Max
Unit
External Clock
EXTCLK
6
50
MHz
FVCO
384
VCO Clock
Output Clock
Table 7:
CLK_OP
MHz
Mpixel/s
Example PLL Configuration for the Parallel Interface
Parameter
Value
Output
445.5 MHz (Max)
FVCO
vt_sys_clk_div
1
vt_pix_clk_div
6
CLK_OP
74.25 MPixel/s (= 445.5 MHz / 6)
Output pixel rate
AR0141CS/D Rev. 6, 4/16 EN
768
74.25
74.25 MPixel/s
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AR0141CS: 1/4-Inch Digital Image Sensor
Sensor PLL
Serial PLL Configuration
Figure 20:
PLL for the Serial Interface
F V CO
EXTCLK
(6-50 MHz)
vt_sys_clk_div
1 (1, 2, 4, 6, 8,
10, 12, 14, 16)
pll_multiplier
58 (32-384)
pre_pll_clk_div
2 (1-64)
op_sys_clk_div
(default = 1)
vt_pix_clk_div
6 (4-16)
CLK_PIX
op_pix_clk_div
12 (8, 10, 12, 14, 16)
CLK_OP
F V CO
F S E RIA L
1/2
F S E RIA L_CLK
The sensor will use op_sys_clk_div and op_pix_clk_div to configure the output clock per
lane (CLK_OP). The configuration will depend on the number of active lanes (1, 2, or 4)
configured. To configure the sensor protocol and number of lanes, refer to “Serial
Configuration” on page 16.
Table 8:
PLL Parameters for the Serial Interface
Parameter
Symbol
Min
Max
Unit
External Clock
EXTCLK
6
50
MHz
FVCO
384
VCO Clock
Readout Clock
CLK_PIX
Output Serial Data Rate Per Lane
Output Serial Clock Speed Per Lane
768
MHz
74.25
Mpixel/s
FSERIAL
300 (HiSPi)
600 (HiSPi)
Mbps
FSERIAL_CLK
150 (HiSPi)
350(HiSPi)
MHz
Configure the serial output so that it adheres to the following rules:
• The maximum data-rate per lane (FSERIAL) is 600Mbps/lane (HiSPi).
• Configure the output pixel rate per lane (CLK_OP) so that the sensor output pixel rate
matches the peak pixel rate (2 x CLK_PIX).
– 4-lane: 4 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 148.5 Mpixel/s)
– 2-lane: 2 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 74.25 Mpixel/s)
Table 9:
AR0141CS/D Rev. 6, 4/16 EN
Example PLL Configurations for the Serial Interface
4-lane
2-lane
Parameter
12-bit
12-bit
Units
FVCO
445.5
445.5
MHz
vt_sys_clk_div
1
1
vt_pix_clk_div
6
12
op_sys_clk_div
1
1
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©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Sensor PLL
Table 9:
Example PLL Configurations for the Serial Interface
Parameter
op_pix_clk_div
4-lane
2-lane
12-bit
12-bit
12
12
Units
FSERIAL
445.5
445.5
MHz
FSERIAL_CLK
222.75
222.75
MHz
CLK_PIX
74.25
37.125
Mpixel/s
CLK_OP
37.125
37.125
Mpixel/s
Pixel Rate
148.5
74.25
Mpixel/s
Stream/Standby Control
The sensor supports a soft standby mode. In this mode, the external clock can be optionally disabled to further minimize power consumption. If this is done, then the “PowerUp Sequence” on page 59 must be followed.
Soft Standby
Soft Standby is a low-power state that is controlled through register R0x301A[2].
Depending on the value of R0x301A[4], the sensor will go to Standby after completion of
the current frame readout. When the sensor comes back from Soft Standby, previously
written register settings are still maintained. Soft Standby will not occur if the Trigger pin
is held high.
A specific sequence needs to be followed to enter and exit from Soft Standby.
Entering Soft Standby:
1. Set R0x301A[12] = 1 if serial mode was used
2. Set R0x301A[2] = 0 and drive Trigger pin low.
3. Turn off external clock to further minimize power consumption
Exiting Soft Standby:
1. Enable external clock if it was turned off
2. Set R0x301A[2] = 1 or drive Trigger pin high.
3. Set R0x301A[12] = 0 if serial mode is used
AR0141CS/D Rev. 6, 4/16 EN
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AR0141CS: 1/4-Inch Digital Image Sensor
Sensor Readout
Sensor Readout
Image Acquisition Modes
The AR0141CS supports two image acquisition modes:
• Electronic rolling shutter (ERS) mode
This is the normal mode of operation. When the AR0141CS is streaming, it generates
frames at a fixed rate, and each frame is integrated (exposed) using the ERS. When the
ERS is in use, timing and control logic within the sensor sequences through the rows
of the array, resetting and then reading each row in turn. In the time interval between
resetting a row and subsequently reading that row, the pixels in the row integrate incident light. The integration (exposure) time is controlled by varying the time between
row reset and row readout. For each row in a frame, the time between row reset and
row readout is the same, leading to a uniform integration time across the frame. When
the integration time is changed (by using the two-wire serial interface to change register settings), the timing and control logic controls the transition from old to new integration time in such a way that the stream of output frames from the AR0141CS
switches cleanly from the old integration time to the new while only generating
frames with uniform integration. See “Changes to Integration Time” in the AR0141CS
Register Reference.
• Global reset mode
This mode can be used to acquire a single image at the current resolution. In this
mode, the end point of the pixel integration time is controlled by an external electromechanical shutter, and the AR0141CS provides control signals to interface to that
shutter.
The benefit of using an external electromechanical shutter is that it eliminates the visual
artifacts associated with ERS operation. Visual artifacts arise in ERS operation, particularly at low frame rates, because an ERS image effectively integrates each row of the pixel
array at a different point in time.
Window Control
The sequencing of the pixel array is controlled by the x_addr_start, y_addr_start, x_addr_end, and y_addr_end registers.
Readout Modes
Horizontal Mirror
When the horiz_mirror bit (R0x3040[14]) is set in the read_mode register, the order of
pixel readout within a row is reversed, so that readout starts from x_addr_end + 1 and
ends at x_addr_start. Figure 21 on page 24 shows a sequence of 6 pixels being read out
with R0x3040[14] = 0 and R0x3040[14] = 1.
AR0141CS/D Rev. 6, 4/16 EN
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AR0141CS: 1/4-Inch Digital Image Sensor
Sensor Readout
Figure 21:
Effect of Horizontal Mirror on Readout Order
LINE_VALID
horiz_mirror = 0
DOUT[11:0]
G0[11:0] R0[11:0] G1[11:0] R1[11:0] G2[11:0] R2[11:0]
horiz_mirror = 1
DOUT[11:0]
G3[11:0] R2[11:0] G2[11:0] R1[11:0] G1[11:0] R0[11:0]
Vertical Flip
When the vert_flip bit (R0x3040[15]) is set in the read_mode register, the order in which
pixel rows are read out is reversed, so that row readout starts from y_addr_end and ends
at y_addr_start. Figure 30 shows a sequence of 6 rows being read out with R0x3040[15] =
0 and R0x3040[15] = 1.
Figure 22:
Effect of Vertical Flip on Readout Order
FRAME_VALID
AR0141CS/D Rev. 6, 4/16 EN
vert_flip = 0
DOUT[11:0]
Row0[11:0] Row1[11:0] Row2[11:0] Row3[11:0] Row4[11:0] Row5[11:0]
vert_flip = 1
DOUT[11:0]
Row6[11:0] Row5[11:0] Row4[11:0] Row3[11:0] Row2[11:0] Row1[11:0]
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AR0141CS: 1/4-Inch Digital Image Sensor
Subsampling
Subsampling
The AR0141CS supports subsampling. Subsampling allows the sensor to read out a
smaller set of active pixels by either skipping, binning, or summing pixels within the
readout window.
Figure 23:
Horizontal Binning in the AR0141CS Sensor
lsb
lsb
lsb
-
lsb lsb
lsb
Horizontal binning is achieved either in the pixel readout or the digital readout. The
sensor will sample the combined 2x adjacent pixels within the same color plane.
Figure 24:
Vertical Row Binning in the AR0141CS Sensor
e-
e-
e-
e-
Vertical row binning is applied in the pixel readout. Row binning can be configured as 2x
rows within the same color plane.
Pixel skipping can be configured up to 2x in both the x-direction and y-direction. Skipping pixels in the x-direction will not reduce the row time. Skipping pixels in the y-direction will reduce the number of rows from the sensor effectively reducing the frame time.
Skipping will introduce image artifacts from aliasing.
Table 10:
Available Skip and Bin Modes in the AR0141CS Sensor
Subsampling Method
Horizontal
Vertical
Skipping
Binning
2x
2x
2x
2x
The sensor increments its x and y address based on the x_odd_inc and y_odd_inc value.
The value indicates the addresses that are skipped after each pair of pixels or rows has
been read.
AR0141CS/D Rev. 6, 4/16 EN
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AR0141CS: 1/4-Inch Digital Image Sensor
Subsampling
The sensor will increment x and y addresses in multiples of 2. This indicates that a
GreenR and Red pixel pair will be read together. As well, that the sensor will read a Gr-R
row first followed by a B-Gb row.
1 + x_odd_inc
x subsampling factor = ----------------------------------2
(EQ 4)
1 + y_odd_inc
y subsampling factor = ----------------------------------2
(EQ 5)
A value of 1 is used for x_odd_inc and y_odd_inc when no pixel subsampling is indicated.
In this case, the sensor is incrementing x and y addresses by 1 + 1 so that it reads consecutive pixel and row pairs. To implement a 2x skip in the x direction, the x_odd_inc is set
to 3 so that the x address increment is 1+3, meaning that sensor will skip every other GrR pair.
Table 11:
Configuration for Horizontal Subsampling
No subsampling
Skip 2x
Analog Bin 2x
Digital Bin 2x
Table 12:
x_odd_inc
Restrictions
x_odd_inc = 1
skip = (1+1)*0.5 = 1x
x_odd_inc = 3
skip = (1+3)*0.5 = 2x
x_odd_inc = 3
skip = (1+3)*0.5 =2x
col_sf_bin_en = 1
x_odd_inc = 3
skip = (1+3)*0.5 =2x
col_bin =1
The horizontal FOV must be programmed to
meet the following rule:
Configuration for Vertical Subsampling
y_odd_inc
No subsampling
Skip 2x
Analog Bin 2x
Note:
AR0141CS/D Rev. 6, 4/16 EN
x_addr_end
– x_addr_start + 1 = even number
------------------------------------------------------------------------ x_odd_inc + 1 2
Restrictions:
y_odd_inc = 1
skip = (1+1)*0.5 = 1x
row_bin = 0
y_odd_inc = 3
skip = (1+3)*0.5 =2x
row_bin = 0
y_odd_inc = 3
skip = (1+3)*0.5 =2x
row_bin = 1
The vertical FOV must be programmed to meet
the following rule:
y_addr_end
– y_addr_start + 1 = even number
------------------------------------------------------------------------ y_odd_inc + 1 2
In skip2 the window size has to be a multiple of 4.
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AR0141CS: 1/4-Inch Digital Image Sensor
Sensor Frame Rate
Sensor Frame Rate
The time required to read out an image frame (TFRAME) can be derived from the number
of clocks required to output each image and the pixel clock.
The frame-rate is the inverse of the frame period.
fps=1/TFRAME
(EQ 6)
The number of clocks can be simplified further into the following parameters:
• The number of clocks required for each sensor row (line_length_pck)
This parameter also determines the sensor row period when referenced to the sensor
readout clock. (TROW = line_length_pck x 1/CLK_PIX)
• The number of row periods per frame (frame_length_lines)
• An extra delay between frames used to achieve a specific output frame period
(extra_delay)
TFRAME=1/(CLK_PIX) ×[frame_length_lines × line_length_pck + extra_delay]
Figure 25:
(EQ 7)
Frame Period Measured in Clocks
frame_length_lines = active rows + VB
AR0141CS/D Rev. 6, 4/16 EN
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AR0141CS: 1/4-Inch Digital Image Sensor
Slave Mode
Row Period (TROW)
line_length_pck will determine the number of clock periods per row and the row period
(TROW) when combined with the sensor readout clock. line_length_pck includes both
the active pixels and the horizontal blanking time per row. The sensor utilizes two
readout paths, as seen in Figure 1 on page 4, allowing the sensor to output two pixels
during each pixel clock.
Row Periods Per Frame
frame_length_lines determines the number of row periods (TROW) per frame. This
includes both the active and blanking rows. The minimum vertical blanking value is
defined by the number of OB rows read per frame, two embedded data rows, and two
blank rows.
y_addr_end – y_addr_start + 1
Minimum frame_length_lines = --------------------------------------------------------------------------- + min_vertical_blanking
y_odd_inc + 1 2
(EQ 8)
The sensor is configured to output frame information in two embedded data rows by
setting R0x3064[8] to 1 (default). If R0x3064[8] is set to 0, the sensor will instead output
two blank rows. The data configured in the two embedded rows is defined in two
embedded rows of data at the top of the frame by setting R0x3064[7] and two rows of
embedded statistics at the end of the frame by setting R0x3064[7] for exposure calculations. See the section on Embedded Data and Statistics.
Table 13:
Minimum Vertical Blanking Configuration
min_vertical_blanking1
R0x3180[7:4]
OB Rows
0x8 (Default)
8 OB Rows
8 OB + 8 = 16
0x4
4 OB Rows
4 OB + 8 = 12
0x2
2 OB Rows
2 OB + 8 = 10
The locations of the OB rows, embedded rows, and blank rows within the frame readout
are identified in Figure 26: “Slave Mode Active State and Vertical Blanking,” on page 29.
Slave Mode
The slave mode feature of the AR0141CS supports triggering the start of a frame readout
from a VD signal that is supplied from an external device. The slave mode signal allows
for precise control of frame rate and register change updates. The VD signal is an edge
triggered input to the trigger pin and must be at least 3 PIXCLK cycles wide.
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AR0141CS: 1/4-Inch Digital Image Sensor
Slave Mode
Figure 26:
Slave Mode Active State and Vertical Blanking
VD Signal
Start of frame N
Time
Frame Valid
OB Rows (2, 4, or 8 rows)
Embedded Data Row (2 rows)
Active Data Rows
Blank Rows or Embedded stats (2 rows)
Extra Vertical Blanking
(frame_length_lines - min_frame_length_lines)
Extra Delay (clocks)
The period between the
rising edge of the VD signal
and the slave mode ready
state is TFRAME + 16 clocks.
Slave Mode Active State
End of frame N
Start of frame N + 1
If the slave mode is disabled, the new frame will begin after the extra delay period is
finished.
The slave mode will react to the rising edge of the input VD signal if it is in an active state.
When the VD signal is received, the sensor will begin the frame readout and the slave
mode will remain inactive for the period of one frame time plus 16 clock periods
(TFRAME + (16 / CLK_PIX)). After this period, the slave mode will re-enter the active state
and will respond to the VD signal.
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AR0141CS: 1/4-Inch Digital Image Sensor
Slave Mode
Figure 27:
Slave Mode Example with Equal Integration and Frame Readout Periods
The integration of the last row is started before the end of the programmed integration for the first row.
Frame
Valid
Rising
Edge
Rising
Edge
Rising
Edge
VD Signal
Slave Mode
Trigger
Inactive
Active
Rising edge of VD
signal triggers the start
of the frame readout.
Inactive
Row reset and read
operations begin
after the rising edge
of the VD signal.
Row 0
Active
Row Reset
(start of integration)
Row Readout
Programmed Integration
Integration due to
Slave Mode Delay
Row N
The Slave Mode will become
“Active” after the last row period.
Both the row reset and row read
operations will wait until the rising
edge of the VD signal..
The row shutter and read operations will stop when the slave mode becomes active and
is waiting for the VD signal. The following should be considered when configuring the
sensor to use the slave mode:
1. The frame period (TFRAME) should be configured to be less than the period of the
input VD signal. The sensor will disregard the input VD signal if it appears before the
frame readout is finished.
2. If the sensor integration time is configured to be less than the frame period, then the
sensor will not have reset all of the sensor rows before it begins waiting for the input
VD signal. This error can be minimized by configuring the frame period to be as close
as possible to the desired frame rate (period between VD signals).
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AR0141CS: 1/4-Inch Digital Image Sensor
Slave Mode
Figure 28:
Slave Mode Example Where the Integration Period is Half of the Frame Readout Period
The sensor read pointer will have paused at row 0 while the shutter pointer pauses at row N/2. The extra integration
caused by the slave mode delay will only be seen by rows 0 to N/2. The example below is for a frame readout period of
16.6ms while the integration time is configured to 8.33ms.
Frame
Valid
Rising
Edge
Rising
Edge
Rising
Edge
VD Signal
Slave Mode
Trigger
Inactive
8.33 ms 8.33 ms
Active
Inactive
Row reset and read
operations begin after
the rising edge of the
Vd signal.
Row 0
Active
Row Reset
(start of integration)
Row Readout
Programmed Integration
Integration due to
Slave Mode Delay
Row N
Reset operation is
held during slave
mode “Active” state.
When the slave mode becomes active, the sensor will pause both row read and row reset
operations. (Note: The row integration period is defined as the period from row reset to
row read.) The frame-time should therefore be configured so that the slave mode “wait
period” is as short as possible. In the case where the sensor integration time is shorter
than the frame time, the “wait period” will only increase the integration of the rows that
have been reset following the last VD pulse.
The period between slave mode pulses must also be greater than the frame period. If the
rising edge of the VD pulse arrives while the slave mode is inactive, the VD pulse will be
ignored and will wait until the next VD pulse has arrived.
To enter slave mode:
1. While in soft-standby, set R0x30CE[4] = 1 to enter slave mode.
2. Enable the input pins (TRIGGER) by setting R0x301A[8] = 1.
3. Enable streaming by setting R0x301A[2] = 1.
4. Apply sync-pulses to the TRIGGER input.
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AR0141CS: 1/4-Inch Digital Image Sensor
Frame Readout
Frame Readout
The sensor readout begins with vertical blanking rows followed by the active rows. The
frame readout period can be defined by the number of row periods within a frame
(frame_length_lines) and the row period (line_length_pck/clk_pix). The sensor will read
the first vertical blanking row at the beginning of the frame period and the last active row
at the end of the row period.
Figure 29:
Example of the Sensor Output of a 1280 x 720 Frame at 60 fps
The frame valid and line valid signals mentioned in this diagram represent internal signals within the sensor.
The SYNC codes represented in this diagram represent the HiSPi Streaming-SP protocol.
1/60s
1/60s
Row Reset
Row Read
Row Reset
Row Read
Vertical Blanking
Active Rows
Row Reset
Time
Row Read
Row Reset
Row Read
End of Frame
Readout
Start of Frame
Start of Active Row
HB (370 Pixels/Column)
1280 x 720
End of Line
HB (370 Pixels/Column)
VB
(30 Rows)
Serial SYNC Codes
Start of Vertical Blanking
VB
(30 Rows)
End of Frame
Readout
1280 x 720
End of Frame
Frame Valid
Line Valid
Figure 29 aligns the frame integration and readout operation to the sensor output. It also
shows the sensor output using the HiSPi Streaming-SP protocol. Different sensor protocols will list different SYNC codes.
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AR0141CS: 1/4-Inch Digital Image Sensor
Frame Readout
Table 14:
Serial SYNC Codes Included with Each Protocol Included with the AR0141CS Sensor
Start of Vertical
Blanking Row (SOV)
Interface/Protocol
Parallel
Start of Frame
(SOF)
Start of Active Line
(SOL)
End of Line
(EOL)
End of Frame
(EOF)
Parallel interface uses FRAME VALID (FV) and LINE VALID (LV) outputs to denote start and end of line and
frame.
Required
Unsupported
Required
Unsupported
Unsupported
Required
Required
Required
Unsupported
Unsupported
Unsupported
Required
Required
Required
Required
HiSPi Streaming-S
HiSPi Streaming-SP
HiSPi Packetized SP
Figure 30 illustrates how the sensor active readout time can be minimized while
reducing the frame rate. 750 VB rows were added to the output frame to reduce the
1280 x 720 frame rate from 60 fps to 30 fps without increasing the delay between the
readout of the first and last active row.
Figure 30:
Example of the Sensor Output of a 1280 x720 Frame at 30 fps
The frame valid and line valid signals mentioned in this diagram represent internal signals within the sensor.
The SYNC codes represented in this diagram represent the HiSPi Streaming-SP protocol.
1/30s
Row Reset
1/30s
Row Read
Row Reset
Row Read
Vertical Blanking
Active Rows
Row Reset
Time
Row Read
Row Reset
Row Read
End of Frame
Readout
End of Frame
Readout
Serial SYNC Codes
Start of Vertical Blanking
Start of Frame
Start of Active Row
VB
(780 Rows)
1280 x 720
H B (370 P ixels )
End of Line
End of Frame
VB
(780 Rows)
1280 x 720
H B (370 P ixels )
Frame Valid
Line Valid
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AR0141CS: 1/4-Inch Digital Image Sensor
Changing Sensor Modes
Changing Sensor Modes
Register Changes
All register writes are delayed by one frame. A register that is written to during the
readout of frame n will not be updated to the new value until the readout of frame n+2.
This includes writes to the sensor gain and integration registers.
Real-Time Context Switching
In the AR0141CS, the user may switch between two full register sets A and B by writing to
a context switch change bit in R0x30B0[13]. When the context switch is configured to
context A the sensor will reference the context A registers. If the context switch is
changed from A to B during the readout of frame n, the sensor will then reference the
context B coarse_integration_time registers in frame n+1 and all other context B registers
at the beginning of reading frame n+2. The sensor will show the same behavior when
changing from context B to context A.
Table 15:
List of Configurable Registers for Context A and Context B
Context A
Context B
Register Description
Address
Register Description
Address
coarse_integration_time
0x3012
coarse_integration_time_cb
0x3016
line_length_pck
0x300C
line_length_pck_cb
0x303E
frame_length_lines
0x300A
frame_length_lines_cb
0x30AA
row_bin
0x3040[12]
row_bin_cb
0x3040[10]
col_bin
0x3040[13]
col_bin_cb
0x3040[11]
fine_gain
0x3060[3:0]
fine_gain_cb
0x3060[11:8]
coarse_gain
0x3060[5:4]
coarse_gain_cb
0x3060[13:12]
x_addr_start
0x3004
x_addr_start_cb
0x308A
y_addr_start
0x3002
y_addr_start_cb
0x308C
x_addr_end
0x3008
x_addr_end_cb
0x308E
y_addr_end
0x3006
y_addr_end_cb
0x3090
y_odd_inc
0x30A6
y_odd_inc_cb
0x30A8
x_odd_inc
0x30A2
x_odd_inc_cb
0x30AE
green1_gain
0x3056
green1_gain_cb
0x30BC
blue_gain
0x3058
blue_gain_cb
0x30BE
red_gain
0x305A
red_gain_cb
0x30C0
green2_gain
0x305C
green2_gain_cb
0x30C2
global_gain
0x305E
global_gain_cb
0x30C4
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AR0141CS: 1/4-Inch Digital Image Sensor
Changing Sensor Modes
Figure 31:
Example of Changing the Sensor from Context A to Context B
1/6 0s
1/3 0s
1/6 0s
V ertical B lanking
A ctive R ow s
T im e
S ta rt o f A c tiv e R o w
E n d o f F ra m e
H B (370 P ixels/C olum n)
1 280 x 720
F ra m e N
H B (370 P ixels/C olum n)
1 280 x 720
F ra m e N+1
Integration time of context
B mode implemented
during readout of frame
N+1
Write context A to B
during readout of Frame N
H B (370 P ixels/C olum n)
VB
(780 Rows)
VB
(30 R ows)
S ta rt o f F ra m e
VB
(30 R ows)
c
Serial SYNC Codes
S ta rt o f V e rtic a l B la n k in g
End of Fram e
Readout
End of Fram e
Readout
End of Fram e
Readout
1280 x 720
F ra m e N+2
Context B mode is
implemented in frame N+2
Compression
The AR0141CS can optionally compress 12-bit data to 10-bit using A-law compression.
The compression is applied after the data pedestal has been added to the data. See “Data
Pedestals” on page 19.
The A-law compression is disabled by default and can be enabled by setting R0x31D0
from “0” to “1” and 0x31AC needs to be set to 0x0C0A.
Table 16:
A-Law Compression Table for 12-10 bits
Input Values
Compressed Codeword
Input Range
11
10
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
0 to 127
128 to 255
256 to 511
512 to 1023
1024 to 2047
2048 to 4095
0
0
0
0
0
1
0
0
0
0
1
a
0
0
0
1
a
b
0
0
1
a
b
c
0
1
a
b
c
d
a
a
b
c
d
e
b
b
c
d
e
f
c
c
d
e
f
g
d
d
e
f
g
h
e
e
f
g
h
X
f
f
g
X
X
X
g
g
X
X
X
X
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
a
a
a
a
a
a
b
b
b
b
b
b
c
c
c
c
c
c
d
d
d
d
d
d
e
e
e
e
e
e
f
f
f
f
f
f
g
g
g
g
g
g
h
h
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AR0141CS: 1/4-Inch Digital Image Sensor
Changing Sensor Modes
Temperature Sensor
The AR0141CS sensor has a built-in temperature sensor, accessible through registers,
that is capable of measuring die junction temperature.
The temperature sensor can be enabled by writing R0x30B4[0]=1 and R0x30B4[4]=1.
After this, the temperature sensor output value can be read from R0x30B2[9:0].
The value read out from the temperature sensor register is an ADC output value that
needs to be converted downstream to a final temperature value in degrees Celsius. Since
the PTAT device characteristic response is quite linear in the temperature range of operation required, a simple linear function in the format of the equation below can be used
to convert the ADC output value to the final temperature in degrees Celsius.
Temperature = slope R0x30B2 9:0 + T 0
(EQ 9)
For this conversion, a minimum of two known points are needed to construct the line
formula by identifying the slope and y-intercept “T0”. These calibration values can be
read from registers R0x30C6 and R0x30C8, which correspond to value read at 105°C and
55°C respectively. Once read, the slope and y-intercept values can be calculated and
used in Equation 9.
For more information on the temperature sensor registers, refer to the AR0141CS
Register Reference.
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AR0141CS: 1/4-Inch Digital Image Sensor
Changing Sensor Modes
Embedded Data and Statistics
The AR0141CS has the capability to output image data and statistics embedded within
the frame timing. There are two types of information embedded within the frame
readout.
• Embedded Data:
If enabled, these are displayed on the two rows immediately before the first active
pixel row is displayed.
• Embedded Statistics:
If enabled, these are displayed on the two rows immediately after the last active pixel
row is displayed.
Figure 32:
Frame Format with Embedded Data Lines Enabled
Register Data
Image
HBlank
Status & Statistics Data
VBlank
Embedded Data
The embedded data contains the configuration of the image being displayed. This
includes all register settings used to capture the current frame. The registers embedded
in these rows are as follows:
Line 1: Registers R0x3000 to R0x312F
Line 2: Registers R0x3136 to R0x31BF, R0x31D0 to R0x31FF
Note:
All undefined registers will have a value of 0.
In parallel mode, since the pixel word depth is 12 bits/pixel, the sensor 16-bit register
data will be transferred over 2 pixels where the register data will be broken up into 8 MSB
and 8 LSB. The alignment of the 8-bit data will be on the 8 MSB bits of the 12-bit pixel
word. For example, if a register value of 0x1234 is to be transmitted, it will be transmitted
over two, 12-bit pixels as follows: 0x120, 0x340.
Embedded Statistics
The embedded statistics contain frame identifiers and histogram information of the
image in the frame. This can be used by downstream auto-exposure algorithm blocks to
make decisions about exposure adjustment.
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AR0141CS: 1/4-Inch Digital Image Sensor
Changing Sensor Modes
This histogram is divided into 244 bins with a bin spacing of 64 evenly spaced bins for
digital code values 0 to 28, 120 evenly spaced bins for values 28 to 212, 60 evenly spaced
bins for values 212 to 216. It is recommended that auto exposure algorithms be developed
using the histogram statistics on line 1.
The first pixel of each line in the embedded statistics is a tag value of 0x0B0. This signifies that all subsequent statistics data is 10 bit data aligned to the MSB of the 12-bit pixel.
Figure 33 summarizes how the embedded statistics transmission looks like. It should be
noted that data, as shown in Figure 33, is aligned to the MSB of each word:
Figure 33:
Format of Embedded Statistics Output within a Frame
data_format_
code = 8'h0B
# words =
10'h1EC
stats line 1
data_format_
code = 8'h0B
# words =
10'h00C
{2'b00,frame
_count MSB}
{2'b00,frame
_count LSB}
histogram
bin1 [19:0]
histogram
bin1 [9:0]
mean
[19:10]
mean
[9:0]
lowEndMean
[19:10]
lowEndMean
[9:0]
{2'b00,frame
_ID MSB}
{2'b00,frame
_ID LSB}
histogram
bin0 [19:10]
histogram
bin0 [9:0]
histogram
bin243 [19:0]
histogram
bin243 [9:0]
8'h07
histBegin
[19:10]
histBegin
[9:0]
histEnd
[19:10]
histEnd
[9:0]
perc_lowEnd
[19:10]
perc_lowEnd
[9:0]
norm_abs_
dev [19:10]
norm_abs_
dev [9:0]
8'h07
stats line 2
8'h07
The statistics embedded in these rows are as follows:
Line 1:
• 0x0B0 - identifier
• Register 0x303A - frame_count
• Register 0x31D2 - frame ID
• Histogram data - histogram bins 0-243
Line 2:
• 0x0B0 (TAG)
• Mean
• Histogram Begin
• Histogram End
• Low End Histogram Mean
• Percentage of Pixels Below Low End Mean
• Normal Absolute Deviation
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AR0141CS: 1/4-Inch Digital Image Sensor
Changing Sensor Modes
Test Patterns
The AR0141CS has the capability of injecting a number of test patterns into the top of
the datapath to debug the digital logic. With one of the test patterns activated, any of the
datapath functions can be enabled to exercise it in a deterministic fashion. Test patterns
are selected by Test_Pattern_Mode register (R0x3070). Only one of the test patterns can
be enabled at a given point in time by setting the Test_Pattern_Mode register according
to Table 17. When test patterns are enabled the active area will receive the value specified by the selected test pattern and the dark pixels will receive the value in Test_Pattern_Green (R0x3074 and R0x3078) for green pixels, Test_Pattern_Blue (R0x3076) for
blue pixels, and Test_Pattern_Red (R0x3072) for red pixels. The noise pedestal offset at
register 0x30FE impacts on the test pattern output, so the noise_pedestal needs to be set
as 0x0000 for normal test pattern output.
Table 17:
Test Pattern Modes
Test_Pattern_Mode
Test Pattern Output
0
1
2
3
256
No test pattern (normal operation)
Solid color test pattern
100% Vertical Color Bars test pattern
Fade-to-Gray Vertical Color Bars test pattern
Walking 1s test pattern (12-bit)
Solid Color
When the color field mode is selected, the value for each pixel is determined by its color.
Green pixels will receive the value in Test_Pattern_Green, red pixels will receive the value
in Test_Pattern_Red, and blue pixels will receive the value in Test_Pattern_Blue.
Vertical Color Bars
When the vertical color bars mode is selected, a typical color bar pattern will be sent
through the digital pipeline.
Walking 1s
When the walking 1s mode is selected, a walking 1s pattern will be sent through the
digital pipeline. The first value in each row is 1.
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AR0141CS: 1/4-Inch Digital Image Sensor
Two-Wire Serial Register Interface
Two-Wire Serial Register Interface
The two-wire serial interface bus enables read/write access to control and status registers within the AR0141CS.The interface protocol uses a master/slave model in which a
master controls one or more slave devices. The sensor acts as a slave device. The master
generates a clock (SCLK) that is an input to the sensor and is used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal
(SDATA). SDATA is pulled up to VDD_IO off-chip by a 1.5k resistor. Either the slave or
master device can drive SDATA LOW—the interface protocol determines which device is
allowed to drive SDATA at any given time.
The protocols described in the two-wire serial interface specification allow the slave
device to drive SCLKLOW; the AR0141CS uses SCLK as an input only and therefore never
drives it LOW.
Protocol
Data transfers on the two-wire serial interface bus are performed by a sequence of lowlevel protocol elements:
1. a (repeated) start condition
2. a slave address/data direction byte
3. an (a no) acknowledge bit
4. a message byte
5. a stop condition
The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a
start condition, and the bus is released with a stop condition. Only the master can
generate the start and stop conditions.
Start Condition
A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH.
At the end of a transfer, the master can generate a start condition without previously
generating a stop condition; this is known as a “repeated start” or “restart” condition.
Stop Condition
A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH.
Data Transfer
Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of
data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer
mechanism is used for the slave address/data direction byte and for message bytes.
One data bit is transferred during each SCLK clock period. SDATA can change when SCLK
is LOW and must be stable while SCLK is HIGH.
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AR0141CS: 1/4-Inch Digital Image Sensor
Two-Wire Serial Register Interface
Slave Address/Data Direction Byte
Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data
transfer direction. A “0” in bit [0] indicates a WRITE, and a “1” indicates a READ. The
default slave addresses used by the AR0141CS are 0x20 (write address) and 0x21 (read
address) in accordance with the specification. Alternate slave addresses of0x30 (write
address) and0x31 (read address) can be selected by enabling and asserting the SADDR
input.
An alternate slave address can also be programmed through R0x31FC.
Message Byte
Message bytes are used for sending register addresses and register write data to the slave
device and for retrieving register read data.
Acknowledge Bit
Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the
SCLK clock period following the data transfer. The transmitter (which is the master when
writing, or the slave when reading) releases SDATA. The receiver indicates an acknowledge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is
LOW and must be stable while SCLK is HIGH.
No-Acknowledge Bit
The no-acknowledge bit is generated when the receiver does not drive SDATA LOW
during the SCLK clock period following a data transfer. A no-acknowledge bit is used to
terminate a read sequence.
Typical Sequence
A typical READ or WRITE sequence begins by the master generating a start condition on
the bus. After the start condition, the master sends the 8-bit slave address/data direction
byte. The last bit indicates whether the request is for a read or a write, where a “0” indicates a write and a “1” indicates a read. If the address matches the address of the slave
device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus.
If the request was a WRITE, the master then transfers the 16-bit register address to which
the WRITE should take place. This transfer takes place as two 8-bit sequences and the
slave sends an acknowledge bit after each sequence to indicate that the byte has been
received. The master then transfers the data as an 8-bit sequence; the slave sends an
acknowledge bit at the end of the sequence. The master stops writing by generating a
(re)start or stop condition.
If the request was a READ, the master sends the 8-bit write slave address/data direction
byte and 16-bit register address, the same way as with a WRITE request. The master then
generates a (re)start condition and the 8-bit read slave address/data direction byte, and
clocks out the register data, 8 bits at a time. The master generates an acknowledge bit
after each 8-bit transfer. The slave’s internal register address is automatically incremented after every 8 bits are transferred. The data transfer is stopped when the master
sends a no-acknowledge bit.
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AR0141CS: 1/4-Inch Digital Image Sensor
Two-Wire Serial Register Interface
Single READ from Random Location
This sequence (Figure 34) starts with a dummy WRITE to the 16-bit address that is to be
used for the READ. The master terminates the WRITE by generating a restart condition.
The master then sends the 8-bit read slave address/data direction byte and clocks out
one byte of register data. The master terminates the READ by generating a no-acknowledge bit followed by a stop condition. Figure 34 shows how the internal register address
maintained by the AR0141CS is loaded and incremented as the sequence proceeds.
Figure 34:
Single READ from Random Location
Previous Reg Address, N
Slave Address
S
0 A Reg Address[15:8]
S = start condition
P = stop condition
Sr = restart condition
A = acknowledge
A = no-acknowledge
A
Reg Address, M
Reg Address[7:0]
A Sr
Slave Address
1 A
M+1
Read Data
A P
slave to master
master to slave
Single READ from Current Location
This sequence (Figure 35) performs a read using the current value of the AR0141CS
internal register address. The master terminates the READ by generating a no-acknowledge bit followed by a stop condition. The figure shows two independent READ
sequences.
Figure 35:
Single READ from Current Location
Previous Reg Address, N
S
AR0141CS/D Rev. 6, 4/16 EN
Slave Address
1 A
Reg Address, N+1
Read Data
A P
S
42
Slave Address
1 A
N+2
Read Data
A P
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Two-Wire Serial Register Interface
Sequential READ, Start from Random Location
This sequence (Figure 36) starts in the same way as the single READ from random location (Figure 34). Instead of generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge bit and continues to
perform byte READs until “L” bytes have been read.
Figure 36:
Sequential READ, Start from Random Location
Previous Reg Address, N
S
Slave Address
0 A Reg Address[15:8]
M+1
M+2
Read Data
A
Read Data
A
Reg Address, M
Reg Address[7:0] A Sr
Slave Address
M+L-2
M+3
M+L-1
Read Data
A
1 A
Read Data
A
M+1
Read Data
A
M+L
A P
Sequential READ, Start from Current Location
This sequence (Figure 37) starts in the same way as the single READ from current location (Figure 35). Instead of generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge bit and continues to
perform byte READs until “L” bytes have been read.
Figure 37:
Sequential READ, Start from Current Location
Previous Reg Address, N
S
Slave Address
1 A
Read Data
N+1
A
N+2
Read Data
A
N+L-1
Read Data
A
Read Data
N+L
A P
Single WRITE to Random Location
This sequence (Figure 38) begins with the master generating a start condition. The slave
address/data direction byte signals a WRITE and is followed by the HIGH then LOW
bytes of the register address that is to be written. The master follows this with the byte of
write data. The WRITE is terminated by the master generating a stop condition.
Figure 38:
Single WRITE to Random Location
Previous Reg Address, N
S
Slave Address
AR0141CS/D Rev. 6, 4/16 EN
0 A Reg Address[15:8]
A
43
Reg Address, M
Reg Address[7:0]
A
Write Data
M+1
A P
A
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Two-Wire Serial Register Interface
Sequential WRITE, Start at Random Location
This sequence (Figure 39) starts in the same way as the single WRITE to random location
(Figure 38). Instead of generating a no-acknowledge bit after the first byte of data has
been transferred, the master generates an acknowledge bit and continues to perform
byte WRITEs until “L” bytes have been written. The WRITE is terminated by the master
generating a stop condition.
Figure 39:
Sequential WRITE, Start at Random Location
Previous Reg Address, N
S
Slave Address
0 A Reg Address[15:8]
M+1
Write Data
AR0141CS/D Rev. 6, 4/16 EN
M+2
A
Write Data
A
Reg Address, M
Reg Address[7:0]
A
Write Data
M+L-2
M+3
Write Data
A
44
M+1
A
M+L-1
A
Write Data
M+L
A
P
A
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Spectral Characteristics
Spectral Characteristics
Figure 40 specifies the quantum efficiency of the RGB Bayer sensor.
Figure 40:
Quantum Efficiency - Color Sensor
AR0141CS/D Rev. 6, 4/16 EN
45
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Spectral Characteristics
Figure 41 specifies the quantum efficiency of the monochrome sensor.
Figure 41:
Quantum Efficiency - Monochrome Sensor
AR0141CS/D Rev. 6, 4/16 EN
46
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Spectral Characteristics
Figure 42:
RGB-NIR Quantum Efficiency
70
B lu e
60
Q uantum E fficiency (% )
G ree n
N IR
50
Red
40
30
20
10
0
350
450
550
650
750
850
950
1050
1150
W avelength (nm )
AR0141CS/D Rev. 6, 4/16 EN
47
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Spectral Characteristics
Figure 43:
Chief Ray Angle - 21deg
Image Height
AR0141 Mono CRA Characteristic
30
28
26
24
22
20
CRA (deg)
18
16
14
12
10
8
6
4
2
0
0
10
20
30
40
50
60
70
80
Image Height (%)
AR0141CS/D Rev. 6, 4/16 EN
48
90
100
110
CRA
(%)
(mm)
(deg)
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
0
0.113
0.226
0.340
0.453
0.566
0.679
0.792
0.906
1.019
1.132
1.245
1.358
1.472
1.585
1.698
1.811
1.925
2.038
2.151
2.264
0
1.01
2.03
3.07
4.11
5.17
6.23
7.30
8.38
9.46
10.54
11.63
12.73
13.82
14.92
16.01
17.10
18.19
19.28
20.36
21.43
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
Electrical Specifications
Unless otherwise stated, the following specifications apply under the following conditions:
VDD = 1.8V – 0.10/+0.15; VDD_IO = VDD_PLL = VAA = VAA_PIX = 2.8V ± 0.3V;
VDD_SLVS = 0.4V – 0.1/+0.2; TA = -30°C to +85°C; output load = 10pF;
frequency = 74.25 MHz; HiSPi off.
Two-Wire Serial Register Interface
The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are
shown in Figure 44 and Table 18.
Figure 44:
Two-Wire Serial Bus Timing Parameters
SDATA
tLOW
tf
tSU;DAT
tr
tf
tHD;STA
tr
tBUF
SCLK
S
tHD;STA
Note:
Table 18:
tHD;DAT
tHIGH
tSU;STA
tSU;STO
Sr
P
S
Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register
address are issued.
Two-Wire Serial Bus Characteristics
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V; TA = 25°C
Standard Mode
Parameter
Fast Mode
Symbol
Min
Max
Min
Max
Unit
fSCL
0
100
0
400
kHz
tHD;STA
4.0
-
0.6
-
s
LOW period of the SCLK clock
tLOW
4.7
-
1.3
-
s
HIGH period of the SCLK clock
tHIGH
4.0
-
0.6
-
s
Set-up time for a repeated START
condition
tSU;STA
4.7
-
0.6
-
S
Data hold time
tHD;DAT
04
3.455
06
0.95
s
-
ns
SCLK Clock Frequency
Hold time (repeated) START condition
After this period, the first clock pulse is
generated
tSU;DAT
250
-
1006
Rise time of both SDATA and SCLK signals
tr
-
1000
20 + 0.1Cb7
300
ns
Fall time of both SDATA and SCLK signals
tf
-
300
20 + 0.1Cb7
300
ns
tSU;STO
4.0
-
0.6
-
s
tBUF
4.7
-
1.3
-
s
Cb
-
400
-
400
pF
Data set-up time
Set-up time for STOP condition
Bus free time between a STOP and START
condition
Capacitive load for each bus line
AR0141CS/D Rev. 6, 4/16 EN
49
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
Table 18:
Two-Wire Serial Bus Characteristics (continued)
f
EXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V; TA = 25°C
Standard Mode
Parameter
Serial interface input pin capacitance
SDATA max load capacitance
SDATA pull-up resistor
Notes:
Symbol
Min
Max
CIN_SI
-
CLOAD_SD
1.5
RSD
Fast Mode
Min
Max
Unit
3.3
-
3.3
pF
30
-
30
pF
4.7
1.5
4.7
k
2
1.
2.
3.
4.
This table is based on I C standard (v2.1 January 2000). Philips Semiconductor.
Two-wire control is I2C-compatible.
All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz.
A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the
undefined region of the falling edge of SCLK.
5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of
the SCLK signal.
6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch
the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it
must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according
to the Standard-mode I2C-bus specification) before the SCLK line is released.
7. Cb = total capacitance of one bus line in pF.
I/O Timing
By default, the AR0141CS launches pixel data, FV, and LV with the falling edge of PIXCLK.
The expectation is that the user captures DOUT[11:0], FV, and LV using the rising edge of
PIXCLK.
See Figure 45 for I/O timing diagram.
Figure 45:
I/O Timing Diagram
tR
t RP
tF
t FP
90%
90%
10%
10%
t EXTCLK
EXTCLK
PIXCLK
t PD
Data[11:0]
Pxl _0
Pxl _1
Pxl _2
Pxl _n
t PLH
LINE_VALID/
FRAME_VALID
AR0141CS/D Rev. 6, 4/16 EN
t PFL
t PFH
t PLL
FRAME_VALID leads LINE_VALID by 6 PIXCLKs.
50
FRAME_VALID trails
LINE_VALID by 6 PIXCLKs.
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
Table 19:
I/O Timing Characteristics (2.8V VDD_IO)
Conditions: fPIXCLK=37.125 MHz (720P30fps; VDD_IO = 2.8V
Symbol
Definition
Condition
Min
Typ
Max
Unit
fEXTCLK1
Input clock frequency
PLL enabled
6
–
50
MHz
tEXTCLK1
Input clock period
tR
Input clock rise time
PLL enabled
20
–
166
ns
–
3
–
ns
tF
Input clock fall time
–
3
–
ns
tRR
PIXCLK rise time
PCLK slew rate setting= 2
2.0
3.5
6.4
ns
tFP
PIXCLK fall time
PCLK slew rate setting= 2
1.9
3.3
6.2
ns
45
50
55
%
Clock duty cycle
tJITTER2
Input clock jitter at 27 MHz
fPIXCLK
PIXCLK frequency
default PLL configuration
tPD
PIXCLK to Data[11:0]
tPFH
–
–
600
ps
6
37.125
74.25
MHz
PCLK slew rate setting=2
parallel slew rate setting= 4
-2.0
–
5.9
ns
PIXCLK to FV high
PCLK slew rate setting=2
parallel slew rate setting=2
-0.9
–
4.4
ns
tPLH
PIXCLK to LV high
PCLK slew rate setting=2
parallel slew rate setting=2
-0.8
–
4.6
ns
tPFL
PIXCLK to FV low
PCLK slew rate setting=2
parallel slew rate setting=2
-1.5
–
3.1
ns
tPLL
PIXCLK to FV low
PCLK slew rate setting=2
parallel slew rate setting=2
-1.5
–
3.3
ns
CLOAD
Output load capacitance
–
30
–
pF
CIN
Input pin capacitance
–
2.5
–
pF
Note:
AR0141CS/D Rev. 6, 4/16 EN
Slew rate setting = 2 for PIXCLK
Slew rate setting = 2 for parallel ports
51
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
Table 20:
I/O Timing Characteristics (1.8V VDD_IO)
Conditions: fPIXCLK = 37.125 MHz(720P30fps;) VDD_IO = 1.8V
Symbol
Definition C
Condition
Min
Typ
Max
Unit
fEXTCLK1
Input clock frequency
PLL enabled
6
–
50
MHz
tEXTCLK1
Input clock period
tR
Input clock rise time
PLL enabled
20
–
166.6666667
ns
–
3
–
ns
tF
Input clock fall time
–
tRR
PIXCLK rise time
PCLK slew rate setting=2
3.2
3
–
ns
5.6
9.5
ns
tFP
PIXCLK fall time
PCLK slew rate setting=2
2.9
45
5.0
8.8
ns
50
55
%
Clock duty cycle
tJITTER2
Input clock jitter at 27 MHz
fPIXCLK
PIXCLK frequency
Default PLL configuration
tPD
PIXCLK to Data[11:0]
tPFH
–
–
600
ps
6
37.125
74.25
MHz
PCLK slew rate setting=2
Parallel slew rate setting=2
-2.2
–
5.9
ns
PIXCLK to FV high
PCLK slew rate setting=2
Parallel slew rate setting=2
-0.9
–
4.5
ns
tPLH
PIXCLK to LV high
PCLK slew rate setting=2
Parallel slew rate setting=2
-0.9
–
4.6
ns
tPFL
PIXCLK to FV low
PCLK slew rate setting=2
Parallel slew rate setting=2
-1.7
–
3.1
ns
tPLL
PIXCLK to FV low
PCLK slew rate setting=2
Parallel slew rate setting=2
-1.6
–
3.4
ns
CLOAD
Output load capacitance
–
30
–
pF
CIN
Input pin capacitance
–
2.5
–
pF
Note:
Slew rate setting = 2 for PIXCLK
Slew rate setting = 2 for parallel ports
Table 21:
Parallel Slew Rate
(R0x306E[15:13])
Conditions
Min
Typ
Max
Units
7
6
5
4
3
2
1
0
Default
Default
Default
Default
Default
Default
Default
Default
0.83
0.71
0.64
0.56
0.47
0.39
0.29
0.2
1.38
1.2
1.07
0.94
0.79
0.64
0.48
0.32
2.1
1.84
1.65
1.44
1.21
0.98
0.74
0.49
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
Note:
AR0141CS/D Rev. 6, 4/16 EN
I/O Rise Slew Rate (2.8V VDD_IO)
30pf loads at nominal voltages.
52
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
Table 22:
Parallel Slew Rate
(R0x306E[15:13])
Conditions
Min
Typ
Max
Units
7
6
5
4
3
2
1
0
Default
Default
Default
Default
Default
Default
Default
Default
0.76
0.67
0.61
0.55
0.48
0.4
0.31
0.21
1.25
1.12
1.04
0.93
0.81
0.67
0.52
0.35
1.85
1.68
1.56
1.41
1.23
1.03
0.79
0.54
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
Note:
30pf loads at nominal voltages.
Table 23:
I/O Rise Slew Rate (1.8V VDD_IO)
Parallel Slew Rate
(R0x306E[15:13])
Conditions
Min
Typ
Max
Units
7
6
5
4
3
2
1
0
Default
Default
Default
Default
Default
Default
Default
Default
0.32
0.28
0.25
0.23
0.2
0.17
0.13
0.09
0.51
0.44
0.4
0.36
0.31
0.26
0.2
0.13
0.85
0.75
0.68
0.6
0.51
0.41
0.32
0.21
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
Note:
30pf loads at nominal voltages.
Table 24:
I/O Fall Slew Rate (1.8V VDD_IO)
Parallel Slew Rate
(R0x306E[15:13])
Conditions
Min
Typ
Max
Units
7
6
5
4
3
2
1
0
Default
Default
Default
Default
Default
Default
Default
Default
0.32
0.28
0.26
0.24
0.21
0.18
0.14
0.1
0.53
0.47
0.43
0.39
0.34
0.29
0.22
0.16
0.87
0.77
0.71
0.64
0.56
0.47
0.36
0.25
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
Note:
AR0141CS/D Rev. 6, 4/16 EN
I/O Fall Slew Rate (2.8V VDD_IO)
30pf loads at nominal voltages.
53
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
DC Electrical Characteristics
The DC electrical characteristics are shown in the tables below.
Table 25:
DC Electrical Characteristics
Symbol
Definition
Condition
Min
Typ
Max
Unit
VDD
Core digital voltage
1.7
1.8
1.95
V
VDD_IO
I/O digital voltage
1.7/2.5
1.8/2.8
1.9/3.1
V
Analog voltage
2.5
2.8
3.1
V
VAA_PIX
VAA
Pixel supply voltage
2.5
2.8
3.1
V
VDD_PLL
PLL supply voltage
2.5
2.8
3.1
V
VDD_SLVS
HiSPi supply voltage
0.3
0.4
0.6
V
VIH
Input HIGH voltage
VDD_IO*0.7
–
–
V
VIL
Input LOW voltage
–
–
VDD_IO*0.3
V
20
–
–
A
IIN
Input leakage current
No pull-up resistor; VIN = VDD_IO or
DGND
VOH
Output HIGH voltage
VDD_IO-0.3
–
–
V
VOL
Output LOW voltage
–
–
0.4
V
IOH
Output HIGH current
At specified VOH
-22
–
–
mA
IOL
Output LOW current
At specified VOL
–
–
22
mA
Caution
Table 26:
Stresses greater than those listed in Table 26 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Absolute Maximum Ratings
Symbol
Definition
Condition
Min
Max
Unit
VDD_MAX
Core digital voltage
–0.3
2.4
V
VDD_IO_MAX
I/O digital voltage
–0.3
4
V
VAA_MAX
Analog voltage
–0.3
4
V
VAA_PIX
Pixel supply voltage
–0.3
4
V
VDD_PLL
PLL supply voltage
–0.3
4
V
HiSPi I/O digital voltage
–0.3
2.4
V
Storage temperature
–40
150
°C
VDD_SLVS_MAX
tST
Note:
AR0141CS/D Rev. 6, 4/16 EN
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
54
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
Table 27:
Operating Current Consumption in Parallel Output and Linear Mode
Definition
Condition
Symbol
Min
Typ
Max
Unit
Digital operating current
Streaming,1280x720 60 fps
IDD1
–
137
160
mA
I/O digital operating current
Streaming,1280x720 60 fps
IDD_IO
–
15
25
mA
Analog operating current
Streaming,1280x720 60 fps
IAA
–
20
30
mA
Pixel supply current
Streaming,1280x720 60 fps
IAA_PIX
–
1.5
3
mA
PLL supply current
Streaming,1280x720 60 fps
IDD_PLL
–
4
8
mA
Note:
Table 28:
Operating currents are measured at the following conditions:
VAA = VAA_PIX = VDD_PLL = 2.8V
VDD = VDD_IO = 1.8V; CLOAD = 68pF
PLL Enabled and PIXCLK = 74.25 MHz
1x analog gain, 0.36 ms integration time, 60 fps, dark conditions
TJ = 25°C
Operating Currents in HiSPi Output and Linear Mode
Definition
Condition
Symbol
Min
Typ
Max
Unit
Digital Operating Current
Analog operating current
Streaming,1280x720 60 fps
IDD
–
147
170
mA
Streaming,1280x720 60 fps
IAA
–
20
30
mA
Pixel Supply Current
Streaming,1280x720 60 fps
IAA_PIX
–
1.5
3
mA
PLL Supply Current
Streaming,1280x720 60 fps
IDD_PLL
–
5
9
mA
SLVS Supply Current
Streaming,1280x720 60 fps
IDD_SLVS
–
8
15
mA
HiVCM Supply Current
Streaming,1280x720 60 fps
IDD
–
22
25
mA
Note:
Table 29:
VAA = VAA_PIX = VDD_PLL = 2.8V
VDD = VDD_IO = 1.8V
VDD_SLVS=1.8V for HiVCM and =0.4V for SLVS
PLL Enabled and PIXCLK = 74.25 MHz
1x analog gain, 0.36 ms integration time, 60 fps, dark conditions
TJ = 25°C
Standby Current Consumption
Definition
Condition
Soft standby (clock off)
Soft standby (clock on)
Notes:
AR0141CS/D Rev. 6, 4/16 EN
Symbol
Min
Typ
Max
Unit
Analog, 2.8V
-
–
0
0.1
mA
Digital, 1.8V
-
–
0.1
0.25
mA
Analog, 2.8V
-
–
0.01
0.2
mA
Digital, 1.8V
-
–
26
30
mA
1. Analog = VAA + VAA_PIX + VDD_PLL
2. Digital = VDD_IO + VDD_SLVS
55
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
HiSPi Electrical Specifications
Note:
Table 30:
Refer to “High-Speed Serial Pixel Interface Physical Layer Specification v2.00.00” for
further explanation of the HiSPi transmitter specification. The electrical specifications below supersede those given in the HiSPi Physical Layer Specification.
SLVS Power Supply and Operating Temperature
Parameter
Symbol
SLVS Current Consumption1, 2
IDD_TX
HiSPi PHY Current Consumption1,2
Table 31:
Typ
IDD_HiSPi
Operating temperature3
Notes:
Min
TA
-30
Max
Unit
18
mA
45
mA
70
°C
1. Temperature of 25°C
2. Up to 600 Mbps
SLVS Electrical DC Specification
Parameter
Symbol
Min
Typ
Max
Unit
SLVS DC mean common mode voltage
VCM
0.45*VDD_TX
0.5*VDD_TX
0.55*VDD_TX
V
SLVS DC mean differential output voltage
|VOD|
0.36*VDD_TX
0.5*VDD_TX
0.64*VDD_TX
V
Change in VCM between logic 1 and 0
VCM
25
mV
Change in |VOD| between logic 1 and 0
|VOD|
25
mV
VOD noise margin
NM
±30
%
|VCM|
50
mV
Difference in VOD between any two channels
|VOD|
100
mV
Common-mode AC Voltage (pk) without VCM cap
termination
VCM_AC
50
mV
Common-mode AC Voltage (pk) with VCM cap
termination
VCM_AC
30
mV
Maximum overshoot peak |VOD|
VOD_AC
1.3*|VOD|
V
Maximum overshoot Vdiff pk-pk
Vdiff_pkpk
Single-ended output impedance
RO
Difference in VCM between any two channels
Output Impedance Mismatch
AR0141CS/D Rev. 6, 4/16 EN
35
RO
56
50
2.6*VOD
V
70
20
%
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
Table 32:
SLVS Electrical Timing Specification
Parameter
Symbol
Min
Max
Unit
Notes
Data Rate
1/UI
280
600
Mbps
1
Bitrate Period
tPW
1.43
3.57
ns
1
Max setup time from transmitter
tPRE
0.3
UI
1, 2
Max hold time from transmitter
tPOST
0.3
UI
1, 2
Eye Width
tEYE
0.6
UI
1, 2
tTOTALJIT
0.2
UI
1, 2
Data Total Jitter (pk-pk) @1e-9
Clock Period Jitter (RMS)
tCKJIT
50
ps
2
Clock Cycle-to-Cycle Jitter (RMS)
tCYCJIT
100
ps
2
Rise time (20% - 80%)
Fall time (20% - 80%)
Clock duty cycle
Mean Clock to Data Skew
tR
150ps
0.25
UI
3
tF
150ps
0.25
UI
3
DCYC
45
55
%
2
tCHSKEW
-0.1
0.1
UI
1, 4
2.1
UI
1, 5
-100
100
ps
6
PHY-to-PHY Skew
tPHYSKEW
Mean differential skew
tDIFFSKEW
Notes:
Figure 46:
1. One UI is defined as the normalized mean time between one edge and the following edge of the
clock.
2. Taken from the 0V crossing point with the DLL off.
3. Also defined with a maximum loading capacitance of 10 pF on any pin. The loading capacitance
may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum
0.3 UI.
4. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any
edges.
5. The absolute skew between any Clock in one PHY and any Data lane in any other PHY between any
edges.
6. Differential skew is defined as the skew between complementary outputs. It is measured as the
absolute time between the two complementary edges at mean VCM point. Note that differential
skew also is related to the VCM_AC spec, which also must not be exceeded.
Differential Output Voltage for Clock or Data Pairs
VDIFFmax
VDIFFmin
0V Diff)
Output Signal is 'Cp - Cn' or 'Dp - Dn'
AR0141CS/D Rev. 6, 4/16 EN
57
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
Figure 47:
Eye Diagram for Clock and Data Signals
RISE
80%
D A T A M A SK
V d i ff
20%
T x Pr e
T x Po s t
FALL
UI/ 2
UI/ 2
V d i ff
M a x V d i ff
C L O C K M A SK
T r i g ge r/ R efe re nce
C L K JIT T ER
Figure 48:
HiSPi Skew Between Data Signals Within the PHY
t C HSKEW1 PHY
Table 33:
Channel, PHY, and Intra-PHY Skew
Measurement Conditions: VDD_HiSPi = 1.8V;VDD_HiSPi_TX = 0.8V; Data Rate =480 Mbps; DLL set to 0
Data Lane Skew in Reference to Clock
AR0141CS/D Rev. 6, 4/16 EN
tCHSKEW1PHY
58
-150
ps
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
Table 34:
Clock DLL Steps
Measurement Conditions: VDD_HiSPi = 1.8V;VDD_HiSPi_TX = 0.8V; Data DLL set to 0
Clock DLL Step
1
2
3
4
5
Step
Delay at 660 Mbps
Eye_opening at 660 Mbps
0.25
0.85
0.375
0.78
0.5
0.71
0.625
0.71
0.75
0.69
UI
UI
Note:
Table 35:
The Clock DLL Steps 6 and 7 are not recommended by ON Semiconductor for the AR0141CS.
Data DLL Steps
Measurement Conditions: VDD_HiSPi = 1.8V;VDD_HiSPi_TX = 0.8V; Clock DLL set to 0
Data DLL Step
1
2
4
6
Step
Delay at 660 Mbps
Eye opening at 660 Mbps
0.25
0.79
0.375
0.84
0.625
0.71
0.875
0.61
UI
UI
Note:
The Data DLL Steps 3, 5, and 7 are not recommended by ON Semiconductor for the AR0141CS.
Power-Up Sequence
The recommended power-up sequence for the AR0141CS is shown in Figure 49. The
available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have
the separation specified below.
1. Turn on VDD_PLL power supply.
2. After 100s, turn on VAA and VAA_PIX power supply.
3. After 100s, turn on VDD_IO power supply.
4. After 100s, turn on VDD power supply.
5. After 100s, turn on VDD_SLVS power supply.
6. After the last power supply is stable, enable EXTCLK.
7. Assert RESET_BAR for at least 1ms. The parallel interface will be tri-stated during this
time.
8. Wait 1800 EXTCLKs for internal initialization into software standby.
9. Initiate load of OTPM data by setting R0x304A=0x0010.
10. Wait for 185135 EXTCLKs for a full OTPM loading.
11. Configure PLL, output, and image settings to desired values.
12. Wait 1ms for the PLL to lock.
13. Set streaming mode (R0x301A[2] = 1).
AR0141CS/D Rev. 6, 4/16 EN
59
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
Figure 49:
Power Up
V D D_P LL (2.8)
t0
V A A_P IX
VA A(2.8)
t1
V D D_IO(1.8/2.8)
t2
t3
V D D(1.8)
V D D_S LV S (0.4)
E X T C LK
tx
t4
R E S E T _B A R
H ard
reset
Table 36:
t7
t6
t5
Internal
S oftw are
initialization
S tandby
R0 x304 A
=0x0010
OT P M
loading
Initialization
S etting
loading
P LL
Lock
S tream ing
Power-Up Sequence
Definition
Symbol
Minimum
Typical
Maximum
Unit
VDD_PLL to VAA/VAA_PIX3
VAA/VAA_PIX to VDD_IO
VDD_IO to VDD
VDD to VDD_SLVS
Xtal settle time
Hard Reset
Internal Initialization
OTPM loading
PLL Lock Time
t0
t1
t2
t3
tx
t4
t5
t6
t7
0
0
0
0
–
12
1800
185135
1
100
100
100
100
301
–
–
–
–
–
–
–
–
–
–
–
–
–
s
s
s
s
ms
ms
EXTCLK
EXTCLK
ms
Notes:
AR0141CS/D Rev. 6, 4/16 EN
1. Xtal settling time is component-dependent, usually taking about 10 – 100 ms.
2. Hard reset time is the minimum time required after power rails are settled. In a circuit where Hard
reset is held down by RC circuit, then the RC time must include the all power rail settle time and
Xtal settle time.
3. It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered
before or at least at the same time as the others. If the case happens that VDD_PLL is powered after
other supplies then sensor may have functionality issues and will experience high current draw on
this supply.
60
©Semiconductor Components Industries, LLC, 2016.
AR0141CS/D Rev. 6, 4/16 EN
Power-Down Sequence
The recommended power-down sequence for the AR0141CS is shown in Figure 50. The available power supplies
(VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have the separation specified below.
1. Disable streaming if output is active by setting standby R0x301a[2] = 0
2. The soft standby state is reached after the current row or frame, depending on configuration, has ended.
3. Turn off VDD_SLVS.
4. Turn off VDD.
5. Turn off VDD_IO
6. Turn off VAA/VAA_PIX.
7. Turn off VDD_PLL.
Figure 50:
Power Down
VDD_SLVS (0.4)
t0
VDD (1.8)
t1
61
V DD_IO (1.8/2.8)
t2
VAA_PIX
VAA (2.8)
VDD_PLL (2.8)
EXTCLK
©Semiconductor Components Industries, LLC, 2016
t4
Power Down until next Power up cycle
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
t3
AR0141CS: 1/4-Inch Digital Image Sensor
Electrical Specifications
Table 37:
Power-Down Sequence
Definition
VDD_SLVS to VDD
Note:
AR0141CS/D Rev. 6, 4/16 EN
Symbol
Minimum
Typical
Maximum
Unit
t0
0
–
–
s
VDD to VDD_IO
t1
0
–
–
s
VDD_IO to VAA/VAA_PIX
t2
0
–
–
s
VAA/VAA_PIX to VDD_PLL
t3
0
–
–
s
PwrDn until Next PwrUp Time
t4
100
–
–
ms
t4 is required between power down and next power up time; all decoupling caps from regulators
must be completely discharged.
62
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Package Drawings
Package Drawings
Figure 51:
63-Ball iBGA Package (Case 503AH)
IBGA63 9x9
CASE 503AH
ISSUE O
DATE 30 DEC 2014
Notes:
AR0141CS/D Rev. 6, 4/16 EN
1.
2.
3.
4.
Dimensions are in mm. Dimensions in () are for reference only.
Encapsulant: Epoxy.
Substrate material: Epoxy laminate 0.25 thickness. Double AR glass.
LID MATERIAL: BOROSILICATE GLASS 0.4±0.4MM thickness
Refractive Index at 20C = 1.5255 @ 546 nm and 1.5231 @ 588 nm.
Double Side AR Coating: 530-570nm R<1%; 420-700nm R<2%.
5. Image sensor die: 0.2 thickness.
6. Solder ball material: SAC 305 (95% Sn, 3% Ag, 0.5% Cu).
Dimensions apply to solder balls post reflow.
Pre-reflow ball is 0.5 on a 0.4 SMD ball pad.
63
©Semiconductor Components Industries, LLC, 2016.
AR0141CS: 1/4-Inch Digital Image Sensor
Package Drawings
7. Maximum rotation of optical area relative to package edges: 0.75°.
Maximum tilt of optical area relative to substrate plane D: 25 microns.
Maximum tilt of cover glass relative to optical area plane E: 5 microns.
A-Pix is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the
rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/
Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its
products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey
any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
This literature is subject to all applicable copyright laws and is not for resale in any manner.
AR0141CS/D Rev. 6, 4/16 EN
64
©Semiconductor Components Industries, LLC, 2016 .