AD AD8008ARZ-REEL71 Ultralow distortion,high speed amplifier Datasheet

Ultralow Distortion,
High Speed Amplifiers
AD8007/AD8008
CONNECTION DIAGRAMS
Extremely low distortion
Second harmonic
−88 dBc @ 5 MHz
−83 dBc @ 20 MHz (AD8007)
−77 dBc @ 20 MHz (AD8008)
Third harmonic
−101 dBc @ 5 MHz
−92 dBc @ 20 MHz (AD8007)
−98 dBc @ 20 MHz (AD8008)
High speed
650 MHz, −3 dB bandwidth (G = +1)
1000 V/μs slew rate
Low noise
2.7 nV/√Hz input voltage noise
22.5 pA/√Hz input inverting current noise
Low power: 9 mA/amplifier typical supply current
Wide supply voltage range: 5 V to 12 V
0.5 mV typical input offset voltage
Small packaging: 8-lead SOIC, 8-lead MSOP, and 5-lead SC70
NC 1
7
+VS
6
VOUT
–VS 4
5
NC
AD8007
(Top View)
5
+VS
4
–IN
+IN 3
02866-002
–VS 2
Figure 2. 5-Lead SC70 (KS)
(Top View)
8
+VS
7
VOUT2
+IN1 3
6
–IN2
–VS 4
5
+IN2
–IN1 2
02866-003
AD8008
VOUT1 1
Figure 3. 8-Lead SOIC (R) and 8-Lead MSOP (RM)
The AD8007 is available in a tiny SC70 package as well as a
standard 8-lead SOIC. The dual AD8008 is available in both an
8-lead SOIC and an 8-lead MSOP. These amplifiers are rated to
work over the industrial temperature range of −40°C to +85°C.
–30
G = +2
RL = 150Ω
VS = ±5V
VOUT = 2V p-p
–40
–50
–60
–70
SECOND
–80
–90
THIRD
–100
–110
1
10
FREQUENCY (MHz)
100
02866-004
With the wide supply voltage range (5 V to 12 V) and wide
bandwidth, the AD8007/AD8008 are designed to work in a
variety of applications. The AD8007/AD8008 amplifiers have
a low power supply current of 9 mA/amplifier.
–IN 2
+IN 3
VOUT 1
DISTORTION (dBc)
The AD8007/AD8008 have 650 MHz bandwidth, 2.7 nV/√Hz
voltage noise, −83 dB SFDR at 20 MHz (AD8007), and −77 dBc
SFDR at 20 MHz (AD8008).
NC
NC = NO CONNECT
Instrumentation
IF and baseband amplifiers
Filters
A/D drivers
DAC buffers
The AD8007 (single) and AD8008 (dual) are high performance
current feedback amplifiers with ultralow distortion and noise.
Unlike other high performance amplifiers, the low price and
low quiescent current allow these amplifiers to be used in a
wide range of applications. Analog Devices, Inc., proprietary
second-generation eXtra-Fast Complementary Bipolar (XFCB)
process enables such high performance amplifiers with low power
consumption.
8
Figure 1. 8-Lead SOIC (R)
APPLICATIONS
GENERAL DESCRIPTION
AD8007
(Top View)
02866-001
FEATURES
Figure 4. AD8007 Second and Third Harmonic Distortion vs. Frequency
Rev. E
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IMPORTANT LINKS for the AD8007_8008*
Last content update 08/18/2013 06:08 pm
PARAMETRIC SELECTION TABLES
DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE
Find Similar Products By Operating Parameters
High Speed Amplifiers Selection Table
Analog Filter Wizard 2.0
AD8007/AD8008 SPICE Macro-Model
DOCUMENTATION
DESIGN COLLABORATION COMMUNITY
AN-692: Universal Precision Op Amp Evaluation Board
AN-649: Using the Analog Devices Active Filter Design Tool
MT-057: High Speed Current Feedback Op Amps
MT-051: Current Feedback Op Amp Noise Considerations
MT-034: Current Feedback (CFB) Op Amps
MT-059: Compensating for the Effects of Input Capacitance on VFB
and CFB Op Amps Used in Current-to-Voltage Converters
A Stress-Free Method for Choosing High-Speed Op Amps
Current Feedback Amplifiers Part 1: Ask The Applications Engineer-22
Current Feedback Amplifiers Part 2: Ask The Applications Engineer-23
Two-Stage Current-Feedback Amplifier
FOR THE AD8007
AN-358: Noise and Operational Amplifier Circuits
AN-356: User's Guide to Applying and Measuring Operational
Amplifier Specifications
AN-257: Careful Design Tames High Speed Op Amps
AN-253: Find Op Amp Noise with Spreadsheet
UG-112: Universal Evaluation Board for Single, High Speed Op Amps
Offered in SC-70 Packages
UG-101: Evaluation Board User Guide
FOR THE AD8008
UG-129: Evaluation Board User Guide
UG-128: Universal Evaluation Board for Dual High Speed Op Amps in
SOIC Packages
EVALUATION KITS & SYMBOLS & FOOTPRINTS
View the Evaluation Boards and Kits page for the AD8007
View the Evaluation Boards and Kits page for the AD8008
Symbols and Footprints for the AD8007
Symbols and Footprints for the AD8008
Collaborate Online with the ADI support team and other designers
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Quality and Reliability
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SAMPLE & BUY
AD8007
AD8008
View Price & Packaging
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This content may be frequently modified.
AD8007/AD8008
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Applications ....................................................................................... 1
Theory of Operation ...................................................................... 15
Connection Diagrams ...................................................................... 1
Using the AD8007/AD8008 ...................................................... 15
General Description ......................................................................... 1
Layout Considerations ............................................................... 16
Revision History ............................................................................... 2
Layout And Grounding Considerations ...................................... 17
Specifications..................................................................................... 3
Grounding ................................................................................... 17
VS = ±5 V ....................................................................................... 3
Input Capacitance ...................................................................... 17
VS = 5 V.......................................................................................... 4
Output Capacitance ................................................................... 17
Absolute Maximum Ratings............................................................ 6
Input-to-Output Coupling ........................................................ 17
Maximum Power Dissipation ......................................................... 6
External Components and Stability ......................................... 17
Output Short Circuit ........................................................................ 6
Outline Dimensions ....................................................................... 18
ESD Caution .................................................................................. 6
Ordering Guide .......................................................................... 19
REVISION HISTORY
11/09—Rev. D to Rev. E
Change to Output Capacitance Section....................................... 17
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 19
6/03—Rev. C to Rev. D
Change to Layout Considerations Section .................................. 15
Deleted Figure 7 .............................................................................. 16
Deleted Evaluation Board Section ................................................ 16
Updated Outline Dimensions ....................................................... 16
10/02—Rev. B to Rev. C
Connection Diagrams Captions Updated .................................... 1
Ordering Guide Updated ................................................................ 5
Figure 5 Edited ............................................................................... 14
Updated Outline Dimensions ....................................................... 19
9/02—Rev. A to Rev. B
Updated Outline Dimensions ....................................................... 19
8/02—Rev. 0 to Rev. A
Added AD8008 .................................................................. Universal
Added SOIC-8 (RN) and MSOP-8 (RM) ......................................1
Changes to Features ..........................................................................1
Changes to General Description ....................................................1
Changes to Specifications ................................................................2
Edits to Maximum Power Dissipation Section .............................4
New Figure 2 .....................................................................................4
Changes to Ordering Guide ............................................................5
New TPCs 19 to 24 and TPCs 27, 29, 30, and 35 ..........................9
Changes to Evaluation Board Section ......................................... 16
MSOP-8 (RM) Added ................................................................... 19
Rev. E | Page 2 of 20
AD8007/AD8008
SPECIFICATIONS
VS = ±5 V
TA = 25°C, RS = 200 Ω, RL = 150 Ω, RF = 499 Ω, Gain = +2, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Overdrive Recovery Time
Slew Rate
Settling Time to 0.1%
Settling Time to 0.01%
NOISE/HARMONIC PERFORMANCE
Second Harmonic
Third Harmonic
IMD
Third-Order Intercept
Crosstalk (AD8008)
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Transimpedance
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Saturation Voltage
Short-Circuit Current, Source
Short-Circuit Current, Sink
Capacitive Load Drive
Conditions
Min
G = +1, VO = 0.2 V p-p, RL = 1 kΩ
G = +1, VO = 0.2 V p-p, RL = 150 Ω
G = +2, VO = 0.2 V p-p, RL = 150 Ω
G = +1, VO = 2 V p-p, RL = 1 kΩ
VO = 0.2 V p-p, G = +2, RL = 150 Ω
±2.5 V input step, G = +2, RL = 1 kΩ
G = +1, VO = 2 V step
G = +2, VO = 2 V step
G = +2, VO = 2 V step
540
250
180
200
50
AD8007/AD8008
Typ
Max
Unit
650
500
230
235
90
30
1000
18
35
MHz
MHz
MHz
MHz
MHz
ns
V/μs
ns
ns
fC = 5 MHz, VO = 2 V p-p
fC = 20 MHz, VO = 2 V p-p
fC = 5 MHz, VO = 2 V p-p
fC = 20 MHz, VO = 2 V p-p
fC = 19.5 MHz to 20.5 MHz, RL = 1 kΩ, VO = 2 V p-p
fC = 5 MHz, RL = 1 kΩ
fC = 20 MHz, RL = 1 kΩ
f = 5 MHz, G = +2
f = 100 kHz
−Input, f = 100 kHz
+Input, f = 100 kHz
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
−88
−83/−77
−101
−92/−98
−77
43.0/42.5
42.5
−68
2.7
22.5
2
0.015
0.010
dBc
dBc
dBc
dBc
dBc
dBm
dBm
dB
nV/√Hz
pA/√Hz
pA/√Hz
%
Degree
+Input
−Input
+Input
−Input
VO = ±2.5 V, RL = 1 kΩ
RL = 150 Ω
1.0
0.4
0.5
3
4
0.4
16
9
1.5
0.8
56
4
1
−3.9 to +3.9
59
900
+Input
+Input
VCM = ±2.5 V
VCC − VOH, VOL − VEE, RL = 1 kΩ
30% overshoot
Rev. E | Page 3 of 20
1.1
130
90
8
4
8
6
mV
μV/°C
μA
μA
nA/°C
nA/°C
MΩ
MΩ
MΩ
pF
V
dB
1.2
V
mA
mA
pF
AD8007/AD8008
Parameter
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio
+PSRR
−PSRR
Conditions
Min
AD8007/AD8008
Typ
Max
5
12
10.2
9
59
59
64
65
Unit
V
mA
dB
dB
VS = 5 V
TA = 25°C, RS = 200 Ω, RL = 150 Ω, RF = 499 Ω, Gain = +2, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Overdrive Recovery Time
Slew Rate
Settling Time to 0.1%
Settling Time to 0.01%
NOISE/HARMONIC PERFORMANCE
Second Harmonic
Third Harmonic
IMD
Third-Order Intercept
Crosstalk (AD8008)
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Transimpedance
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
Conditions
G = +1, VO = 0.2 V p-p, RL = 1 kΩ
G = +1, VO = 0.2 V p-p, RL = 150 Ω
G = +2, VO = 0.2 V p-p, RL = 150 Ω
G = +1, VO = 1 V p-p, RL = 1 kΩ
VO = 0.2 V p-p, G = +2, RL = 150 Ω
2.5 V input step, G = +2, RL = 1 kΩ
G = +1, VO = 2 V step
G = +2, VO = 2 V step
G = +2, VO = 2 V step
AD8007/AD8008
Min Typ
Max
Unit
520
350
190
270
72
580
490
260
320
120
30
740
18
35
MHz
MHz
MHz
MHz
MHz
ns
V/μs
ns
ns
665
fC = 5 MHz, VO = 1 V p-p
fC = 20 MHz, VO = 1 V p-p
fC = 5 MHz, VO = 1 V p-p
fC = 20 MHz, VO = 1 V p-p
fC = 19.5 MHz to 20.5 MHz, RL = 1 kΩ,
VO = 1 V p-p
fC = 5 MHz, RL = 1 kΩ
fC = 20 MHz, RL = 1 kΩ
Output-to-output, f = 5 MHz, G = +2
f = 100 kHz
−Input, f = 100 kHz
+Input, f = 100 kHz
−96/−95
−83/−80
−100
−85/−88
−89/−87
dBc
dBc
dBc
dBc
dBc
43.0
42.5/41.5
−68
2.7
22.5
2
dBm
dBm
dB
nV/√Hz
pA/√Hz
pA/√Hz
+Input
−Input
+Input
−Input
VO = 1.5 V to 3.5 V, RL = 1 kΩ
RL = 150 Ω
0.5
0.4
0.5
3
4
0.7
15
8
1.3
0.6
54
4
1
1.1 to 3.9
56
+Input
+Input
VCM = 1.75 V to 3.25 V
Rev. E | Page 4 of 20
4
8
6
mV
μV/°C
μA
μA
nA/°C
nA/°C
MΩ
MΩ
MΩ
pF
V
dB
AD8007/AD8008
Parameter
OUTPUT CHARACTERISTICS
Output Saturation Voltage
Short-Circuit Current, Source
Short-Circuit Current, Sink
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio
+PSRR
−PSRR
Conditions
AD8007/AD8008
Min Typ
Max
VCC − VOH, VOL − VEE, RL = 1 kΩ
1.05
70
50
8
30% overshoot
5
8.1
59
59
Rev. E | Page 5 of 20
62
63
Unit
1.15
V
mA
mA
pF
12
9
V
mA
dB
dB
AD8007/AD8008
ABSOLUTE MAXIMUM RATINGS
Rating
12.6 V
See Figure 5
±VS
±1.0 V
See Figure 5
−65°C to +125°C
−40°C to +85°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8007/AD8008
packages is limited by the associated rise in junction temperature
(TJ) on the die. The plastic encapsulating the die locally reaches
the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8007/AD8008.
Exceeding a junction temperature of 175°C for an extended
time can result in changes in the silicon devices, potentially
causing failure.
The still-air thermal properties of the package and PCB (θJA),
ambient temperature (TA), and the total power dissipated in the
package (PD) determine the junction temperature of the die.
The junction temperature can be calculated as
If the rms signal levels are indeterminate, then consider the
worst case, when VOUT = VS/4 for RL to midsupply
⎛ VS ⎞
⎜
⎟
⎝ 4 ⎠
PD = (VS × I S ) +
RL
In single-supply operation, with RL referenced to VS, worst case is
VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through-holes, ground, and power planes
reduces the θJA. Care must be taken to minimize parasitic
capacitances at the input leads of high speed op amps, see the
Layout Considerations section.
Figure 5 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the SOIC-8 (125°C/W),
MSOP-8 (150°C/W), and SC70-5 (210°C/W) packages on a
JEDEC standard 4-layer board. θJA values are approximations.
2.0
1.5
MSOP-8
SOIC-8
1.0
SC70-5
0.5
0
–60
–40
TJ = TA + (PD × θJA)
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL ) is referenced to
midsupply, the total drive power is VS/2 × IOUT, some of which is
dissipated in the package and some in the load (VOUT × IOUT).
The difference between the total drive power and the load
power is the drive power dissipated in the package.
–20
0
20
40
60
AMBIENT TEMPERATURE (°C)
80
100
Figure 5. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
OUTPUT SHORT CIRCUIT
Shorting the output to ground or drawing excessive current for
the AD8007/AD8008 will likely cause catastrophic failure.
ESD CAUTION
PD = Quiescent Power + (Total Drive Power − Load Power)
⎛V
V
PD = (VS × I S ) + ⎜⎜ S × OUT
RL
⎝ 2
2
02866-005
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Output Short-Circuit Duration
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
RMS output voltages should be considered. If RL is referenced to
VS, as in single-supply operation, then the total drive power is
VS × IOUT.
MAXIMUM POWER DISSIPATION (W)
Table 3.
⎞ VOUT 2
⎟−
⎟
RL
⎠
Rev. E | Page 6 of 20
AD8007/AD8008
TYPICAL PERFORMANCE CHARACTERISTICS
VS = ±5 V, RL = 150 Ω, RS = 200 Ω, RF = 499 Ω, unless otherwise noted.
3
6.4
2
6.3
G = +1
6.2
0
6.1
G = +2
GAIN (dB)
–1
–2
–3
–4
G = +10
VS = +5V
5.9
5.8
VS = ±5V
5.6
G = –1
–6
1
5.5
1000
10
100
FREQUENCY (MHz)
5.4
10
Figure 6. Small Signal Frequency Response for Various Gains
3
Figure 9. 0.1 dB Gain Flatness; VS = +5, VS = ±5 V
9
G = +1
2
8
1
–1
RL = 150kΩ, VS = ±5V
–3
–4
5
RL = 150kΩ,
VS = +5V
4
3
RL = 150kΩ, VS = ±5V
2
RL = 150kΩ, VS = 5V
–5
RL = 1kΩ, VS = ±5V
1
–6
1000
–1
10
Figure 10. Small Signal Frequency Response for VS and RL
9
3
2
G = +1
RL = 1kΩ
8
1
–1
5
GAIN (dB)
6
–2
RS = 301Ω
RS = 249Ω
–4
3
RF = RG = 249Ω
RF = RG = 499Ω
2
1
–6
0
1000
Figure 8. Small Signal Frequency Response for Various RS Values
–1
10
02866-008
100
FREQUENCY (MHz)
RF = RG = 324Ω
4
–5
–7
10
G = +2
7
RS = 200Ω
0
–3
1000
100
FREQUENCY (MHz)
RF = RG = 649Ω
100
FREQUENCY (MHz)
1000
02866-011
100
FREQUENCY (MHz)
02866-007
10
02866-010
0
Figure 7. Small Signal Frequency Response for VS and RL
GAIN (dB)
RL = 1kΩ, VS = +5V
6
GAIN (dB)
GAIN (dB)
0
–7
G = +2
7
RL = 1kΩ, VS = ±5V
–2
1000
100
FREQUENCY (MHz)
02866-009
–5
–7
6.0
5.7
02866-006
NORMALIZED GAIN (dB)
1
G = +2
Figure 11. Small Signal Frequency Response for Various Feedback Resistors,
RF = RG
Rev. E | Page 7 of 20
AD8007/AD8008
10M
20pF AND
20Ω SNUB
8
20pF AND
10Ω SNUB
1M
TRANSIMPEDANCE (Ω)
6
5
499Ω
499Ω
3
RSNUB
0pF
200Ω
2
49.9Ω
1
1
PHASE
10k
1000
–90
1k
–150
–180
100
–210
10
–270
CLOAD
10
100
FREQUENCY (MHz)
1
10k
100k
Figure 12. Small Signal Frequency Response for
Capacitive Load and Snub Resistor
3
–1
5
GAIN (dB)
6
VS = +5V, –40°C
VS = ±5V, –40°C
2
1
–6
0
–7
–1
1000
Figure 13. Small Signal Frequency Response over Temperature,
VS = +5 V, VS = ±5 V
3
10
100
FREQUENCY (MHz)
1000
G = +2
8
G = +1 G = +2
7
0
6
GAIN (dB)
–1
G = +10
–2
G = –1
–3
5
4
2
–5
1
–6
0
1
10
100
FREQUENCY (MHz)
1000
–1
Figure 14. Large Signal Frequency Response for Various Gains
RL = 150Ω, VS = ±5V, VO = 2V p-p
3
–4
02866-014
NORMALIZED GAIN (dB)
VS = ±5V, –40°C
9
1
–7
VS = +5V, –40°C
Figure 16. Small Signal Frequency Response over Temperature,
VS = +5 V, VS = ±5 V
VOUT = 2V p-p
2
VS = ±5V, +85°C
3
–5
100
FREQUENCY (MHz)
VS = +5V, +85°C
4
–4
02866-013
GAIN (dB)
7
0
10
–330
1G 2G
G = +2
8
1
–3
100M
9
VS = ±5V, +85°C
–2
1M
10M
FREQUENCY (Hz)
Figure 15. Transimpedance and Phase vs. Frequency
VS = +5V, +85°C
G = +1
2
0
–30
RL = 1kΩ, VS = ±5V, VO = 2V p-p
RL = 150Ω, VS = +5V, VO = 1V p-p
RL = 1kΩ, VS = +5V, VO = 1V p-p
10
100
FREQUENCY (MHz)
1000
Figure 17. Large Signal Frequency Response for VS and RL
Rev. E | Page 8 of 20
02866-017
0
30
TRANSIMPEDANCE
100k
02866-012
GAIN (dB)
7
4
90
PHASE (Degrees)
9
20pF
02866-016
G = +2
02866-015
10
AD8007/AD8008
–40
–40
G = +1
VS = 5V
VO = 1V p-p
–50
HD2, RL = 150Ω
G = +2
VS = 5V
VO = 1V p-p
–50
HD3, RL = 150Ω
DISTORTION (dBc)
–70
HD3, RL = 1kΩ
–80
–70
–80
–90
–90
–100
–100
100
–110
–40
100
G = +2
VS = ±5V
VO = 2V p-p
–50
–60
DISTORTION (dBc)
HD2, RL = 150Ω
–70
HD2, RL = 1kΩ
–80
HD3, RL = 150Ω
HD2, RL = 1kΩ
–70
HD2, RL = 150Ω
–80
–90
–90
HD3, RL = 1kΩ
1
10
FREQUENCY (MHz)
–100
100
–110
02866-019
–100
Figure 19. AD8007 Second and Third Harmonic Distortion vs. Frequency and RL
–30
–70
–80
HD3, G = +1
–90
10
FREQUENCY (MHz)
–70
HD2, VO = 2V p-p
–80
HD3, VO = 2V p-p
–100
100
–110
02866-020
1
HD2, VO = 4V p-p
–60
–90
HD2, G = +1
–100
100
HD3, VO = 4V p-p
–50
HD3, G = +10
10
FREQUENCY (MHz)
G = +2
VS = ±5V
RL = 150Ω
–40
DISTORTION (dBc)
–60
1
–30
HD2, G = +10
–50
HD3, RL = 1kΩ
Figure 22. AD8007 Second and Third Harmonic Distortion vs. Frequency and RL
VS = ±5V
VO = 2V p-p
RL = 150Ω
–40
HD3, RL = 150Ω
02866-022
–60
DISTORTION (dBc)
10
FREQUENCY (MHz)
Figure 21. AD8007 Second and Third Harmonic Distortion vs. Frequency and RL
G = +1
VS = ±5V
VO = 2V p-p
–50
DISTORTION (dBc)
1
02866-021
10
FREQUENCY (MHz)
02866-018
1
–40
–110
HD3, RL = 150Ω
HD3, RL = 1kΩ
Figure 18. AD8007 Second and Third Harmonic Distortion vs. Frequency and RL
–110
HD2, RL = 150Ω
1
10
FREQUENCY (MHz)
100
02866-023
DISTORTION (dBc)
HD2, RL = 1kΩ
–110
HD2, RL = 1kΩ
–60
–60
Figure 20. AD8007 Second and Third Harmonic Distortion vs. Frequency and Gain
Figure 23. AD8007 Second and Third Harmonic Distortion vs. Frequency and VO
Rev. E | Page 9 of 20
AD8007/AD8008
VS = ±5 V, RS = 200 Ω, RF = 499 Ω, RL = 150 Ω, @ 25°C, unless otherwise noted.
–40
–40
G=1
VS = 5V
VO = 1V p-p
–50
–60
–60
DISTORTION (dBc)
HD2, RL = 150Ω
–70
HD2, RL = 1kΩ
–80
–90
HD2, RL = 150Ω
–70
HD2, RL = 1kΩ
–80
–90
HD3, RL = 1kΩ
HD3, RL = 1kΩ
–100
–100
HD3, RL = 150Ω
1
10
HD3, RL = 150Ω
100
FREQUENCY (MHz)
–110
02866-024
–110
Figure 24. AD8008 Second and Third Harmonic Distortion vs. Frequency and RL
10
FREQUENCY (MHz)
100
Figure 27. AD8008 Second and Third Harmonic Distortion vs. Frequency and RL
–40
–40
G=2
VS = ±5V
–50 VO = 2V p-p
G=1
VS = 5V
VO = 1V p-p
–50
–60
DISTORTION (dBc)
–60
DISTORTION (dBc)
1
02866-027
DISTORTION (dBc)
G=2
VS = 5V
VO = 1V p-p
–50
–70
HD2, RL = 150Ω
–80
HD2, RL = 1kΩ
HD2, RL = 1kΩ
–70
HD2, RL = 150Ω
–80
–90
–90
–100
–100
HD3, RL = 1kΩ
HD3, RL = 150Ω
HD3, RL = 150Ω
10
FREQUENCY (MHz)
100
02866-025
1
–110
Figure 25. AD8008 Second and Third Harmonic Distortion vs. Frequency and RL
100
Figure 28. AD8008 Second and Third Harmonic Distortion vs. Frequency and RL
VS = ±5V
VO = 2V p-p
RL = 150Ω
–40
G=2
RL = 150Ω
VS = ±5V
–40
–50
–50
HD2, G = 10
DISTORTION (dBc)
–60
–70
–80
HD2, G = 1
–60
HD2, VO = 4V p-p
–70
HD2, VO = 2V p-p
–80
–90
–90
HD3, VO = 4V p-p
–100
–100
1
HD3, VO = 2V p-p
HD3, G = 1
10
FREQUENCY (MHz)
100
–110
02866-026
HD3, G = 10
Figure 26. AD8008 Second and Third Harmonic Distortion vs. Frequency and Gain
1
10
FREQUENCY (MHz)
100
02866-029
DISTORTION (dBc)
10
FREQUENCY (MHz)
–30
–30
–110
1
02866-028
HD3, RL = 1kΩ
–110
Figure 29. AD8008 Second and Third Harmonic Distortion vs. Frequency and VO
Rev. E | Page 10 of 20
AD8007/AD8008
–60
–65
G = +2
VS = 5V
FO = 20MHz
–65
HD3, RL = 1kΩ
–75
HD2, RL = 1kΩ
–70
DISTORTION (dBc)
DISTORTION (dBc)
G = +2
VS = ±5V
FO = 20MHz
–70
HD3, RL = 150Ω
–75
–80
HD2, RL = 150Ω
HD3, RL = 1kΩ
HD2, RL = 150Ω
–80
–85
HD2, RL = 1kΩ
–90
HD3, RL = 150Ω
–95
–100
–85
2.0
1.5
2.5
VOUT (V p-p)
Figure 30. AD8007 Second and Third Harmonic Distortion vs. VOUT and RL
44
40
39
38
37
36
5
4
VOUT (V p-p)
6
G = +2
VS = ±5V
VO = 2V p-p
RL = 1kΩ
42
41
40
39
38
37
20
25
30 35 40 45 50
FREQUENCY (MHz)
55
60
65
70
35
5
Figure 31. AD8007 Third-Order Intercept vs. Frequency
15
20
25
30 35 40 45 50
FREQUENCY (MHz)
60
65
70
Figure 34. AD8008 Third-Order Intercept vs. Frequency
HD2, RL = 1kΩ
–70
HD2, RL = 150Ω
HD2, RL = 150Ω
–75
DISTORTION (dBc)
HD2, RL = 1kΩ
–75
–80
HD3, RL = 150Ω
HD3, RL = 1kΩ
–80
HD3, RL = 150Ω
–85
HD3, RL = 1kΩ
–90
–95
–100
–85
G = +2
VS = 5V
FO = 20MHz
–105
1.5
2.0
VOUT (V p-p)
2.5
–110
02866-032
–90
1.0
55
–65
G = +2
VS = 5V
FO = 20MHz
–70
10
Figure 32. AD8008 Second and Third Harmonic Distortion vs. VOUT and RL
1
2
3
4
VOUT (V p-p)
5
6
02866-035
15
02866-031
10
5
02866-034
36
35
DISTORTION (dBc)
3
43
41
–65
2
44
THIRD-ORDER INTERCEPT (dBm)
42
1
Figure 33. AD8007 Second and Third Harmonic Distortion vs. VOUT and RL
G = +2
VS = ±5V
VO = 2V p-p
RL = 1kΩ
43
THIRD ORDER INTERCEPT (dBm)
–110
02866-030
–90
1.0
02866-033
–105
Figure 35. AD8008 Second and Third Harmonic Distortion vs. VOUT and RL
Rev. E | Page 11 of 20
AD8007/AD8008
VS = ±5 V, RL = 150 Ω, RS = 200 Ω, RF = 499 Ω, unless otherwise noted.
1000
2.7nV/ Hz
1
10
10k
1k
FREQUENCY (Hz)
100
100k
1M
100
INVERTING CURRENT NOISE 22.5pA / Hz
10
1
10
NONINVERTING CURRENT NOISE 2.0pA/ Hz
Figure 36. Input Voltage Noise vs. Frequency
1k
1M
10k
100k
FREQUENCY (Hz)
10M
Figure 39. Input Current Noise vs. Frequency
–20
G = +2
R = 150Ω
–30 V = ±5V
S
VM = 1V p-p
–40
G = +2
CROSSTALK (dB)
100
OUTPUT IMPEDANCE (Ω)
1k
100
02866-039
CURRENT NOISE (pA/ Hz)
10
02866-036
VOLTAGE NOISE (nV/ Hz)
100
10
1
SIDE B DRIVEN
–50
–60
SIDE A DRIVEN
–70
–80
0.1
1M
10M
FREQUENCY (Hz)
100M
1G
–100
100k
02866-037
0.01
100k
Figure 37. Output Impedance vs. Frequency
1M
10M
FREQUENCY (Hz)
100M
1G
02866-040
–90
Figure 40. AD8008 Crosstalk vs. Frequency (Output to Output)
0
20
VS = ±5V, +5V
10
–10
0
PSRR (dB)
–10
–30
–40
–20
–30
+PSRR
–40
–50
–50
–60
–60
1M
10M
FREQUENCY (Hz)
100M
1G
–80
10k
Figure 38. CMRR vs. Frequency
100k
10M
1M
FREQUENCY (Hz)
Figure 41. PSRR vs. Frequency
Rev. E | Page 12 of 20
100M
1G
02866-041
–70
100k
–PSRR
–70
02866-038
CMRR (dB)
–20
AD8007/AD8008
G = +2
RL = 150Ω, VS = +5V AND ±5V
RL = 150Ω, VS = +5V AND ±5V
RL = 1kΩ, VS = +5V AND ±5V
RL = 150Ω, VS = +5V AND ±5V
50mV/DIV
20
30
TIME (ns)
10
40
50
02866-042
0
50mV/DIV
0
20
30
TIME (ns)
40
50
Figure 45. Small Signal Transient Response for
RL = 150 Ω, RL = 1 kΩ and VS = +5 V, VS = ±5 V
Figure 42. Small Signal Transient Response for
RL = 150 Ω, RL = 1 kΩ and VS = +5 V, VS = ±5 V
G = +1
10
02866-045
G = +1
G = –1
RL = 150Ω
INPUT
RL = 1kΩ
OUTPUT
0
10
20
30
TIME (ns)
40
50
02866-043
1V/DIV
0
20
30
TIME (ns)
40
50
Figure 46. Large Signal Transient Response, G = −1, RL = 150 Ω
Figure 43. Large Signal Transient Response for RL = 150 Ω, RL = 1 kΩ
G = +2
10
02866-046
1V/DIV
G = +2
CLOAD = 0pF
CL = 0pF
CL = 20pF
CLOAD = 10pF
CLOAD = 20pF
CL = 20pF
RSNUB = 10Ω
499Ω
499Ω
200Ω
RSNUB
–
+
CLOAD
49.9Ω
10
20
30
TIME (ns)
40
Figure 44. Large Signal Transient Response for
CLOAD = 0 pF, CLOAD = 10 pF, and CLOAD = 20 pF
50
02866-044
0
0
10
20
30
TIME (ns)
40
50
02866-047
50mV/DIV
1V/DIV
Figure 47. Small Signal Transient Response, Effect of Series Snub Resistor
when Driving Capacitive Load
Rev. E | Page 13 of 20
AD8007/AD8008
4
G = +2
G = +10
VS = ±5V
VIN = ±0.75V
3
+VS
RL = 1kΩ
2
RL = 150Ω
VOUT ( V)
1
0
–1
OUTPUT (2V/DIV)
INPUT (1V/DIV)
–VS
–2
400
500
–3
–4
0
Figure 48. Output Overdrive Recovery, RL = 1 kΩ, 150 Ω, VIN = ±2.5 V
200
400
600
800
1000
RL (Ω)
Figure 50. VOUT Swing vs. RL, VS = ±5 V, G = +10, VIN = ±0.75 V
0.5
G = +2
0.4
0.2
0.1
0
–0.1
18ns
–0.2
–0.3
–0.4
–0.5
0
5
10
15
20
25
TIME (ns)
30
35
40
45
02866-049
SETTLING TIME (%)
0.3
Figure 49. 0.1% Settling Time, 2 V Step
Rev. E | Page 14 of 20
02866-050
300
200
TIME (ns)
100
02866-048
0
AD8007/AD8008
THEORY OF OPERATION
The AD8007 (single) and AD8008 (dual) are current feedback
amplifiers optimized for low distortion performance. A simplified
conceptual diagram of the AD8007 is shown in Figure 51. It
closely resembles a classic current feedback amplifier comprised
of a complementary emitter-follower input stage, a pair of signal
mirrors, and a diamond output stage. However, in the case of
the AD8007/AD8008, several modifications were made to improve
the distortion performance over that of a classic current feedback
topology.
+VS
M1
USING THE AD8007/AD8008
Supply Decoupling for Low Distortion
Decoupling for low distortion performance requires careful
consideration. The commonly adopted practice of returning the
high frequency supply decoupling capacitors to physically separate
(and possibly distant) grounds can lead to degraded even-order
harmonic performance. This situation is shown in Figure 52 using
the AD8007 as an example; however, it is not recommended. For a
sinusoidal input, each decoupling capacitor returns to its ground a
quasi-rectified current carrying high even-order harmonics.
RF
499Ω
– I3
I1 –
GND 1
CJ1
+VS
Q1
D1
IDI
IN+
Q5
RG
499Ω
IDO
HIGH-Z
IN–
OUT
D2
Q2
Q4
–VS
10µF
+
0.1µF
Q3
CJ2
IN
Q6
+VS
RS
200Ω
AD8007
OUT
–VS
–VS
02866-052
M2
10µF
+
0.1µF
– I4
GND 2
RF
02866-051
RG
Figure 51. Simplified Schematic of AD8007
The signal mirrors were replaced with low distortion, high
precision mirrors. In Figure 51, they are shown as M1 and M2.
Their primary function from a distortion standpoint is to reduce
the effect of highly nonlinear distortion caused by capacitances,
CJ1 and CJ2. These capacitors represent the collector-to-base
capacitances of the output devices of the mirrors.
Figure 52. High Frequency Capacitors Returned to Physically Separate
Grounds (Not Recommended)
The decoupling scheme shown in Figure 53 is recommended.
In Figure 53, the two high frequency decoupling capacitors are
first tied together at a common node and are then returned to
the ground plane through a single connection. By first adding
the two currents flowing through each high frequency decoupling
capacitor, this ensures that the current returned into the ground
plane is only at the fundamental frequency.
RF
499Ω
A voltage imbalance arises across the output stage, as measured
from the high impedance node, high-Z, to the output node, OUT.
This imbalance is a result of delivering high output currents and
is the primary cause of output distortion. Circuitry is included
to sense this output voltage imbalance and generate a compensating
current, IDO. When injected into the circuit, IDO reduces the
distortion that could be generated at the output stage. Similarly, the
nonlinear voltage imbalance across the input stage (measured from
the noninverting to the inverting input) is sensed, and a current,
IDI, is injected to compensate for input-generated distortion.
The design and layout are strictly top-to-bottom symmetric to
minimize the presence of even-order harmonics.
10µF
+
RG
499Ω
IN
+VS
0.1µF
RS
200Ω
AD8007
OUT
0.1µF
–VS
10µF
+
02866-053
I2 –
Figure 53. High Frequency Capacitors Returned to Ground at a Single Point
(Recommended)
Rev. E | Page 15 of 20
AD8007/AD8008
Whenever physical layout considerations prevent the decoupling
scheme shown in Figure 53, the user can connect one of the
high frequency decoupling capacitors directly across the supplies
and connect the other high frequency decoupling capacitor to
ground (see Figure 54).
RF
499Ω
C1
0.1µF
RG
499Ω
IN
RS
200Ω
AD8007
The standard noninverting configuration with recommended
power supply bypassing is shown in Figure 54. The 0.1 μF high
frequency decoupling capacitors should be X7R or NPO chip
components. Connect C2 from the +VS pin to the −VS pin.
Connect C1 from the +VS pin to signal ground.
The length of the high frequency bypass capacitor leads is critical.
Parasitic inductance due to long leads works against the low
impedance created by the bypass capacitor. The ground for the
load impedance should be at the same physical location as the
bypass capacitor grounds. For larger value capacitors, which are
intended to be effective at lower frequencies, the current return
path distance is less critical.
10µF
+
+VS
LAYOUT CONSIDERATIONS
OUT
C2
0.1µF
10µF
+
02866-054
–VS
Figure 54. High Frequency Capacitors Connected Across the Supplies
(Recommended)
Rev. E | Page 16 of 20
AD8007/AD8008
LAYOUT AND GROUNDING CONSIDERATIONS
GROUNDING
EXTERNAL COMPONENTS AND STABILITY
A ground plane layer is important in densely packed printed
circuit boards (PCB) to minimize parasitic inductances. However,
an understanding of where the current flows in a circuit is critical
to implementing effective high speed circuit design. The length
of the current path is directly proportional to the magnitude of
parasitic inductances and thus the high frequency impedance of
the path. High speed currents in an inductive ground return
create unwanted voltage noise. Broad ground plane areas reduce
parasitic inductance.
The AD8007/AD8008 are current feedback amplifiers and, to a
first order, the feedback resistor determines the bandwidth and
stability. The gain, load impedance, supply voltage, and input
impedances also have an effect.
INPUT CAPACITANCE
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground.
Even 1 pF or 2 pF of capacitance reduces the input impedance at
high frequencies, in turn increasing the gain of the amplifier, which
causes peaking of the frequency response or even oscillations if
severe enough. Place the external passive components that are
connected to the input pins as close as possible to the inputs to
avoid parasitic capacitance. The ground and power planes must
be kept at a distance of at least 0.05 mm from the input pins on
all layers of the board.
OUTPUT CAPACITANCE
To a lesser extent, parasitic capacitances on the output can cause
peaking of the frequency response. The following two methods
minimize its effect:
•
•
Put a small value resistor in series with the output to isolate
the load capacitance from the output stage of the amplifier
(see Figure 12).
Increase the phase margin by increasing the gain of the
amplifier or by increasing the value of the feedback resistor.
Figure 11 shows the effect of changing RF on the bandwidth and
peaking for a gain of 2. Increasing RF reduces peaking but also
reduces bandwidth. Figure 6 shows that for a given RF increasing
the gain also reduces peaking and bandwidth. Table 4 shows the
recommended RF and RG values that optimize bandwidth with
minimal peaking.
Table 4. Recommended Component Values
Gain
−1
+1
+2
+5
+10
RF (Ω)
499
499
499
499
499
RG (Ω)
499
Not applicable
499
124
54.9
RS (Ω)
200
200
200
200
200
The load resistor also affects bandwidth, as shown in Figure 7 and
Figure 10. A comparison between Figure 7 and Figure 10 also
demonstrates the effect of gain and supply voltage.
When driving loads with a capacitive component, stability
improves by using a series snub resistor, RSNUB, at the output.
The frequency and pulse responses for various capacitive
loads are illustrated in Figure 12 and Figure 47, respectively.
For noninverting configurations, a resistor in series with the
input, RS, is needed to optimize stability for a gain of 1, as
illustrated in Figure 8. For larger noninverting gains, the effect
of a series resistor is reduced.
INPUT-TO-OUTPUT COUPLING
To minimize capacitive coupling, the input and output signal
traces should not be parallel. When they are not parallel, they
help reduce unwanted positive feedback.
Rev. E | Page 17 of 20
AD8007/AD8008
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
4.00 (0.1574)
3.80 (0.1497)
5
1
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
SEATING
PLANE
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
012407-A
COMPLIANT TO JEDEC STANDARDS MS-012-A A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 55. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
3.20
3.00
2.80
3.20
3.00
2.80
8
1
5.15
4.90
4.65
5
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.40
0.25
6°
0°
0.23
0.13
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 56. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. E | Page 18 of 20
0.70
0.55
0.40
091709-A
0.15
0.05
COPLANARITY
0.10
AD8007/AD8008
2.20
2.00
1.80
1.35
1.25
1.15
5
4
1
2
3
2.40
2.10
1.80
0.65 BSC
0.10 MAX
COPLANARITY
0.10
0.40
0.10
1.10
0.80
0.30
0.15
SEATING
PLANE
0.22
0.08
0.46
0.36
0.26
072809-A
1.00
0.90
0.70
COMPLIANT TO JEDEC STANDARDS MO-203-AA
Figure 57. 5-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8007AKS-R2
AD8007AKSZ-R2 1
AD8007AKSZ-REEL1
AD8007AKSZ-REEL71
AD8007AR
AD8007AR-REEL
AD8007AR-REEL7
AD8007ARZ1
AD8007ARZ-REEL1
AD8007ARZ-REEL71
AD8008AR
AD8008AR-REEL7
AD8008AR-REEL
AD8008ARZ1
AD8008ARZ-REEL71
AD8008ARZ-REEL1
AD8008ARM
AD8008ARM-REEL
AD8008ARM-REEL7
AD8008ARMZ1
AD8008ARMZ-REEL1
AD8008ARMZ-REEL71
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
5-Lead SC70
5-Lead SC70
5-Lead SC70
5-Lead SC70
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
Z = RoHS Compliant Part, # denotes RoHS compliant part may be top or bottom marked.
Rev. E | Page 19 of 20
Package Outline
KS-5
KS-5
KS-5
KS-5
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
Branding
HTA
HTC
HTC
HTC
H2B
H2B
H2B
H2B#
H2B#
H2B#
AD8007/AD8008
NOTES
©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02866-0-11/09(E)
Rev. E | Page 20 of 20