MP2624 2 The Future of Analog IC Technology I C Controlled 4.5A Single Cell USB / Adaptor Charger with Narrow VDC Power Path Management USB OTG and Shipping Mode DESCRIPTION FEATURES The MP2624 is a 4.5A, highly integrated, switching-mode battery charger IC for singlecell Li-ion or Li-polymer batteries. This device supports NVDC architecture with power path management suitable for different portable applications, such as tablets, MID, and smart phones. Its low impedance power path optimizes efficiency, reduces battery charging time, and extends battery life. The I2C serial interface with charging and system settings allows the device to be controlled flexibly. The MP2624 supports a wide range of input sources, including standard USB host ports and wall adapters. The MP2624 detects the input source type according to the USB Battery Charging Spec 1.2 (BC1.2) and then informs the host to set the proper input current limit. Also, this device is compliant with USB2.0 and USB3.0 power specifications by adopting a proper input current and voltage regulation scheme. In addition, the MP2624 supports USB On-The-Go operation by supplying 5V with current up to 1.3A. The power path management regulates the system voltage slightly above the set maximum voltage between the battery voltage and the I2C programmable lowest voltage level (e.g. 3.6V). With this feature, the system is able to operate even when the battery is depleted completely or removed. When the input source current or voltage limit is reached, the power path management reduces automatically the charge current to meet the priority of the system power requirement. If the system current continues increasing, even when the charge current is reduced to zero, the supplement mode allows the battery to power both the system and the input power supply at the same time. The MP2624 is available 3mm x 4mm package. MP2624 Rev.1.05 4/9/2018 in a QFN-22 High Efficiency 4.5A 1.5MHz Buck Charger and 1.5MHz 1.3A Boost Mode to Support OTG o 94% Efficiency @ 2A o Fast Charge Time by Battery Path Impedance Compensation o USB OTG o 94% Efficiency @ 5V, 1.2A OTG o Selectable OTG Current Outputs 3.9V to 7.0V Operating Input Voltage Range Highest Battery Discharge Efficiency with 10mΩ Battery Discharge MOSFET up to 9A Single Input USB Compliant Charge Narrow System Bus Voltage Power Path Management o Instant On Works with No Battery or Deeply Discharged Battery o Ideal Diode Operation in Battery Supplemental Mode Constant-Off-Time Control to Reduce Charging Time under Lower Input Voltages High Accuracy of Charging Parameter I2C Port for Flexible System Parameter Setting and Status Reporting Full DISC Control to Support Shipping Mode High Integration o Fully Integrated Power Switches and No External Blocking Diode and Sense Resistor Required o Built-In Robust Charging Protection including Battery Temperature Monitor and Programmable Timer o Built-In Battery Disconnection Function High Accuracy o ±0.5% Charge Voltage Regulation o ±5% Charge Current Regulation o ±5% Input Current Regulation o ±2% Output Regulation in Boost Mode Safety o Battery Temperature Sensing for Charge Mode o Battery Charging Safety Timer www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 1 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG Thermal Regulation and Thermal Shutdown o Battery/System Over-Voltage Protection o MOSFET Over-Current Protection Charging Operation Indicator Thermal Limiting Regulation on Chip Tiny QFN-22 3mm x 4mm Package o APPLICATIONS Tablet PCs Smart Phones Mobile Internet Devices All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION MP2624 Rev.1.05 4/9/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 2 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG ORDERING INFORMATION Part Number* Package Top Marking MP2624GL EVKT-2624 QFN-22 (3mm x 4mm) Evaluation Kit See Below * For Tape & Reel, add suffix –Z (e.g. MP2624GL–Z) TOP MARKING MP: MPS prefix Y: Year code W: Week code 2624: First four digits of the part number LLL: Lot number EVALUATION KIT EVKT-2624 EVKT-2624 Kit contents: (Items can be ordered separately). # Part Number Item 1 EV2624-L-00A EVKT-USBI2C-02BAG MP2624 Evaluation Board Includes one USB to I2C Dongle, one USB Cable, and one Ribbon Cable USB Flash drive that stores the GUI installation file and supplemental documents 2 3 Tdrive-2624 Quantity 1 1 1 Order direct from MonolithicPower.com or our distributors EVKT-2624 Evaluation Kit Set-Up MP2624 Rev.1.05 4/9/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 3 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG PACKAGE REFERENCE DM INT STAT NTC CE 22 21 20 19 18 TOP VIEW DP 1 17 DISC IN 2 16 BATT PMID 3 15 SYS SW 4 14 SW PGND 5 13 BST VNTC 6 12 OTG 9 SDA VREF 11 AGND 8 SCL 10 ILIM 7 QFN-22 (3mm x 4mm) MP2624 Rev.1.05 4/9/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 4 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG PIN FUNCTIONS Package Name Pin # Type Description 1 DP I 2 IN Power 3 PMID Power 4, 14 5 SW PGND Power Power 6 VNTC O 7 SCL I/O Positive pin of the USB data line pair. DP and DM achieve USB host/charging port detection automatically. Power input of the IC from the adapter or USB. Place a 1μF ceramic capacitor from IN to PGND as close as possible to the IC. Internal Power Pin. Connect to the drain of the reverse-blocking MOSFET and the drain of the high-side MOSFET. Bypass with a 4.7μF capacitor from PMID to PGND as close as possible to the IC. Switching node. Power ground. Pull-up voltage bias of the NTC comparator resistive divider for both the feedback and the reference. I2C interface clock. Connect SCL to the logic rail through a 10kΩ resistor. 8 SDA I/O I2C interface data. Connect SDA to the logic rail through a 10kΩ resistor. 9 VREF P 10 ILIM I 11 AGND I/O 12 OTG I 13 BST P 15 SYS P 16 BATT P 17 DISC I 18 CE ------- I 19 NTC I 20 STAT -------------- O 21 INT O 22 DM I MP2624 Rev.1.05 4/9/2018 PWM low-side driver output. Connect a 10μF ceramic capacitor from VREF to AGND as close as possible to the IC. Programmable input current limit. A resistor is connected from ILIM to ground to set the minimum input current limit. The actual input current limit is the lowest setting by ILIM and I2C. Analog ground. Boost mode enable control or input current limiting selection pin. The On-TheGo is enabled through I2C. During boost operation, OTG low suspends boost operation. If the input is detected as the USB host, OTG is used as the input current limiting selection pin. When OTG = high, IIN_LMT = 500mA. When OTG = low, IIN_LMT = 100mA. Bootstrap. Connect a 470nF bootstrap capacitor between BST and SW to form a floating supply across the power switch driver to drive the power switch’s gate above the supply voltage. System output. Connect a 2x22μF ceramic capacitor from SYS to PGND as close as possible to the IC. Battery positive terminal. Connect a 2x22μF ceramic capacitor from BATT to PGND as close as possible to the IC. Battery disconnection control. Active low charge enable. Battery charging is enabled when the corresponding ------- register is set to active, and CE is low. Temperature sense input. Connect a negative temperature coefficient thermistor. Program the hot and cold temperature window with a resistor divider from VNTC to NTC to AGND. The charge is suspended when NTC is out of range. Indicator for charging operation. Open-drain interrupt output. INT sends the charging status, and the fault interrupts the host. Negative pin of the USB date line pair. DM and DP achieve USB host/charging port detection automatically. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 5 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG ABSOLUTE MAXIMUM RATINGS (1) IN, PMID, STAT to GND ...............-0.3V to +20V SW to GND ............-0.3V (-2V for 20ns) to +20V BST to GND…………........................ SW to +6V BATT, SYS to GND………………. ..-0.3V to +6V All other pins to GND ......................-0.3V to +6V STAT, INT sink current ............................. 10mA (2) Continuous power dissipation (TA = +25C) ................................................................... 2.6W Junction temperature ............................150C Lead temperature (solder) ........................260C Storage temperature…. .......... -65°C to +150C Recommended Operating Conditions (3) VIN to GND .............................. .....3.9V to 7.0V(4) IIN........................................................... Up to 3A ISYS ..................................................... Up to 4.5A ICHG ..................................................... Up to 4.5A VBATT ............................................... Up to 4.425V IDCHG ................................. (Continuous) up to 6A IDCHG .......................................... (Pulse) up to 9A Operating junction temp. (TJ) ... -40C to +125C MP2624 Rev.1.05 4/9/2018 Thermal Resistance (5) θJA θJC QFN-22 (3mm x 4mm) ............ 48 ...... 11.... °C/W NOTES: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation will produce an excessive die temperature, causing the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) The inherent switching noise voltage should not exceed the absolute maximum rating on either BST or SW. A tight layout minimizes switching loss. 5) Measured on JESD51-7, 4-layer PCB. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 6 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG ELECTRICAL CHARACTERISTICS VIN = 5V, TA = 25°C, unless otherwise noted. Parameter Symbol Condition Step-Down Converter Input voltage range VIN Min Typ Max Units 7.0 V 65 μA 3.9 VIN = 5V, both DC/DC and battery FET are disabled Input shutdown current VIN > VIN_UVLO, VIN > VBATT, charge disabled, switching, SYS float VIN > VIN_UVLO, VIN > VBATT, charge enabled, switching BATT and SYS float VIN rising 3 5 3.45 3.6 VIN_UVLO hysteresis VIN falling 200 VIN vs. VBATT headroom VIN rising VIN falling Input quiescent current Input under-voltage lockout VIN UVLO Internal reverse-blocking RIN to PMID MOSFET on resistance High-side NMOS on RH_DS resistance Low-side NMOS on resistance RL DS High-side NMOS peak current limit Low-side NMOS peak current limit Switching frequency SYS Output Minimum system regulation VSYS_MIN voltage [I2C] System regulation voltage Ideal diode forward voltage in supplement mode MP2624 Rev.1.05 4/9/2018 VSYS_MAX VF_IDD 3 5 mA mV 250 90 300 115 mV mV Measure from IN to PMID 25 35 mΩ Measure from PMID to SW 25 35 mΩ Measure from SW to PGND 28 35 mΩ VBATT = 4.2V, ICHG = 2A ISYS = 0, VBATT = 3.4V, POR default, REG01[2:0] = 110 50mV or 100mV (REG01[0]) higher than VBATT_FULL depends on the I2C setting 50mA discharge current 200 65 V 1.4 7.5 A 7 A 1.7 2.0 3.6 3.53 MHz V 4.525 24 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. V mV 7 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG ELECTRICAL CHARACTERISTICS (continued) VIN = 5V, TA = 25°C, unless otherwise noted. Parameter SYS/BAT comparator Symbol Battery good comparator (Threshold compared with VSYS_MIN) Condition VSYS falling VBATT rising to the battery FET being turned on fully VBATT falling Min Typ 40 Max Units mV 60 mV -40 mV Battery Charger Battery charge full voltage [I2C] VBATT_FULL Charge voltage regulation accuracy Constant current charge current [I2C] Charge current regulation accuracy Battery pre-charge threshold VBATT_PRE [I2C] Battery pre-charge hysteresis Battery short threshold VBATT SHORT Battery short threshold hysteresis Trickle-charge current ITC 2 Pre-charge current [I C] IPRE Pre-charge current accuracy Termination current [I2C] IBF Termination current accuracy Recharge threshold below VBATT FULL Recharge threshold delay BATT to SYS FET on resistance Battery discharge current limit Battery discharge controlled by DISC MP2624 Rev.1.05 4/9/2018 peak function VRECH Depends on the I2C setting default (REG04[7:2] = 110000): 4.2V 3.48 4.425 V VBATT_FULL = 4.2V -0.5 0.5 % 0.512 4.544 A ICHG = 2A -5 5 % REG04[4]=1, VBATT rising 2.8 3.0 3.1 V 2.0 220 2.1 2.2 mV V Depends on the I2C setting VBATT falling VBATT rising VBATT falling 130 mV VBATT = 1.8V Depends on the I2C setting VBATT = 2.6V, IPRE = 256mA Depends on the l2C setting VBATT_FULL = 4.2V, IBF = 512mA VBATT_FULL = 4.2V, IBF = 128mA 128 REG04[0] = 1 64 -25 128 1024 25 1024 mA mA % mA -30 30 % 250 mA 15 98 180 mV 20 ms RBATFET VBATT = 3.8V 10 IDSG_LMT VIN = 0V, VBATT = 3.8V, OTG disabled, ISYS rising 11 tDISC DISC pulled low time period to turn off the battery discharge function DISC pulled high and low time period to turn on the battery discharge function 15 mΩ A 6.6 s 0.5 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 8 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG ELECTRICAL CHARACTERISTICS (continued) VIN = 5V, TA = 25°C, unless otherwise noted. Parameter Symbol Condition Input Voltage and Input Current Based Power Path Input voltage regulation VIN_REG threshold [I2C] REG00[6:3] = 1011, Input voltage regulation VIN REG = 4.76V accuracy USB100 USB150 Input current limit IIN_LMT USB500 Input current limit accuracy Min Typ Max Units 5.1 V 4 % 3.9 -4 70 120 400 100 150 500 USB900 750 900 IIN_LMT = 1.8A, REG00[2:0] = 101 1450 1800 mA mA Protection Battery over-voltage protection VBATT_OVP Battery over-voltage protection hysteresis Thermal shutdown rising threshold(6) Thermal shutdown hysteresis TJ_SHDN Rising. Compared to VBATT FULL 200 mV Compared to VBATT_FULL 68 mV TJ rising 184 ºC 20 ºC (6) NTC low temp rising threshold NTC low temp rising threshold hysteresis NTC cool temp rising threshold VCOLD VCOOL NTC hot temp falling threshold hysteresis As percentage of VVNTC VWARM As percentage of VVNTC 68.6 As percentage of VVNTC As percentage of VVNTC 72.1 69.2 55.9 56.5 69.8 48.5 % % 57.1 1.4 47.9 % % 1.3 As percentage of VVNTC VHOT 71.5 1.4 As percentage of VVNTC NTC warm temp falling threshold hysteresis NTC hot temp falling threshold 70.9 As percentage of VVNTC NTC cool temp rising threshold hysteresis NTC warm temp falling threshold As percentage of VVNTC % % 49.1 1.3 % % NOTE: 6) Guaranteed by design. MP2624 Rev.1.05 4/9/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 9 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG ELECTRICAL CHARACTERISTICS (continued) VIN = 5V, TA = 25°C, unless otherwise noted. Parameter VREF LDO Symbol VREF LDO output voltage VREF LDO current limit OTG Boost Mode Battery operating range VBATT Battery discharge current VIN OTG OTG output voltage accuracy Battery operation UVLO Battery operation UVLO hysteresis VBATT OTG output voltage protection threshold Min Typ VIN = 10V, IVREF = 40mA VIN = 5V, IVREF = 20mA VVREF = 4V 4.82 5 4.8 UVLO OTG output current limit [I C] DP/DM USB Detection DP voltage source Data connect detect current source DM sink current Leakage current input DP/DM Data detect voltage Logic low Session valid to connect time for powered up peripheral MP2624 Rev.1.05 4/9/2018 VDP SRC REG02[1:0] = 00, VBATT = 3.7V REG02[1:0] = 01, VBATT = 3.7V 4.5 V 20 μA 35 μA 5.15 V -2 VBATT = 3.7V, OTG is VOTG_OVP enabled, force a voltage at IN until switching is off IOLIM mA VIN < VIN_UVLO, VBATT_OTG = 4.2V, battery FET is off VIN < VIN_UVLO, VBATT_OTG = 4.2V, battery FET is on IOTG = 0A As percentage of VIN_OTG, IOTG = 0A. VBATT falling Units V 50 OTG output voltage protection threshold hysteresis 2 Max 2.5 OTG IBATT_OTG OTG output voltage Condition 2 % 2.5 V 200 mV 5.75 V 175 mV 0.5 0.6 0.7 1.3 1.5 1.7 0.5 0.6 0.7 V 13 μA 150 1 1 0.4 0.8 μA μA μA V V 45 mins A IDP_SRC 7 IDM SINK IDP LKG IDM LKG VDAT REF VLGC LOW 50 -1 -1 0.25 100 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 10 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG ELECTRICAL CHARACTERISTICS (continued) VIN = 5V, TA = 25°C, unless otherwise noted. Parameter Logic I/O Characteristics Low logic voltage threshold High logic voltage threshold I2C Interface (SDA, SCL) Symbol Condition VL VH Input high threshold level Input low threshold level Output low threshold level I2C clock frequency FSCL Digital Clock and Watchdog Timer Digital clock 1 FDIG1 Digital clock 2 FDIG2 Watchdog timer tWDT MP2624 Rev.1.05 4/9/2018 VPULL UP = 1.8V, SDA and SCL VPULL_UP = 1.8V, SDA and SCL ISINK = 5mA VREF LDO enabled REG05 [5:4] = 11 Min Max Units 0.4 1.3 V V 1.3 V 1400 Typ 1700 39 160 0.4 V 0.4 400 V kHz 2000 kHz kHz s www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 11 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG TYPICAL PERFORMANCE CHARACTERISTICS VIN = 5.0V, VBATT = full range, I2C controlled, ICHG = 4.5A, IIN_LMT = 3.0A, VIN_REG = 4.36V, L = 2.2μH, TA = 25°C, unless otherwise noted. Battery Charge Curve Auto Recharge VIN=5V, ISYS=0A VIN=5V, ISYS=0A Trickle Charge Steady State VIN=5V, VBATT=2.8V VBATT 1V/div. VSYS 1V/div. VBATT 1V/div. CHGOK 2V/div. VSYS 1V/div. CHGOK 2V/div. VSW 1V/div. VSYS 1V/div. IL 1A/div. IBATT 2A/div. IBATT 2A/div. IBATT 200mA /div. Constant Current Charge Steady State Constant Voltage Charge Steady State VIN=5V, VBATT=3.6V VIN=5V, VBATT=4.2V COT Operation VIN=4.5V VIN 2V/div. VSW 2V/div. VSYS 1V/div. VSW 2V/div. VSYS 1V/div. IL 2A/div. IBATT 2A/div. IL 1A/div. IBATT 1A/div. VSW 2V/div. VBATT 1V/div. IL 1A/div. Input Current Limit Input Voltage Limit Power On VIN=5V, VBATT=4.2V, ICHG=3.5A VIN=5V/1.0A, VBATT=2.8V, ICHG=2A VIN=5V, VBATT=3.7V VSYS 1V/div. ISYS 2A/div. IIN 2A/div. IBATT 2A/div. VIN 1V/div. ISYS 2A/div. IIN 1A/div. IBATT 500mA/div. VIN 2V/div. IL 1A/div. VSYS 1V/div. IBATT 200mA/div. MP2624 Rev.1.05 4/9/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 12 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 5.0V, VBATT = full range, I2C controlled, ICHG = 4.5A, IIN_LMT = 3.0A, VIN_REG = 4.36V, L = 2.2μH, TA = 25°C, unless otherwise noted. Power Off EN On OTG Mode Start-Up VIN=5V, VBATT=3.7V VIN=5V, VBATT=3.7V VIN_OTG=5V,VBATT_OTG=3.6V, IOTG=1.3A VSW 5V/div. VPMID 1V/div. VIN 2V/div. VSW 2V/div. IL 2A/div. IL 1A/div. VSYS 1V/div. VSYS 1V/div. VIN 1V/div. IBATT 200mA/div. IBATT 2A/div. IL 1A/div. OTG Output CC Mode Battery Discharge Current DISC Function VIN_OTG=5V,VBATT_OTG=3.6V, IOTG=1.3A VIN=Float, ISYS=9A,VBATT=4.0V VIN=Float, ISYS=1A,VBATT=4.2V VDISC 2V/div. VIN 1V/div. VPMID 1V/div. VBATT 1V/div. VBATT 1V/div. VSYS 1V/div. VSW 2V/div. VSYS 1V/div. VIN 1V/div. IBATT 1A/div. IOTG 1A/div. ISYS 2A/div. NTC Function NTC Function Battery Charge Curve VIN=5V,VBATT=3.8V, ICHG=2A VIN=5V,VBATT=3.8V, ICHG=2A VIN=9V, ISYS=0A VSYS 1V/div. VNTC 1V/div. VNTC 1V/div. IL 1A/div. VSYS 1V/div. IBATT 1A/div. IL 1A/div. VSYS 1V/div. IBATT 1A/div. MP2624 Rev.1.05 4/9/2018 VBATT 1V/div. CHGOK 2V/div. IBATT 2A/div. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 13 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG FUNCTIONAL BLOCK DIAGRAM IN PMID 25mΩ DP USB Port OTG VREF LD O DM Power Control BST 25mΩ SW PWM Driver SDA Syste m Output SCL CE ILIM INT DISC VSYS I2C + Logic Control + NonVolatile Memory 28mΩ PGND SYS Linear Charge& Ideal Diode Control 10mΩ BATT STAT NTC NTC Protectio n Li-ion Battery Pack VNTC AGNG Figure 1: Functional Block Diagram MP2624 Rev.1.05 4/9/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 14 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG OPERATION Introduction The MP2624 is a highly integrated I2C controlled switching-mode battery charger IC with NVDC power path management for single-cell lithiumion or lithium-polymer battery applications. The MP2624 integrates a reverse blocking FET, a high-side switching FET, a low-side switching FET, and a battery FET between SYS and BATT. Its low impedance and high efficiency allows higher current (4.5A) capacity for a given package size. Power Supply The internal bias circuit of the MP2624 is powered from the higher voltage of VIN and VBATT. When VIN or VBATT rises above the respective UVLO threshold, the sleep comparator, battery depletion comparator, and the battery FET driver are active; the I2C interface is ready for communication and all the registers are reset to the default value. The host can access all the registers. Input Power Status Indication The MP2624 qualifies the voltage and current of the input source before start-up. The input source has to meet the following requirements: 1. VIN > VBATT + 250mV 2. VIN_UVLO < VIN 3. OTG is not enabled by host Once the input power source meets the conditions above, the system status register REG08 Bit [2] asserts that the input power is good, and the DP/DM detection starts (if enabled). Then the step-down converter is ready to operate. The conditions above are monitored continuously, and the charge cycle is suspended if a condition is outside one of the limits (see Figure 2). Charger IC or DC/DC DC/DC Rails Backlighting Battery FET 3G Module Narrow VDC Power Structure The MP2624 employs a narrow VDC (NVDC) power structure with the battery FET decoupling the system from the battery, thus allowing separate control between the system and the battery. The system is always given priority to start-up even with a deeply-discharged or missing battery. When the input power is available (even with a depleted battery), the system voltage is always above the preset minimum system voltage (VSYS_MIN) set by the I2C register REG01 Bit [3:1]. As depicted in Figure 2, the NVDC power structure is composed of a front-end, step-down DC/DC converter and a battery FET between SYS and BATT. The DC/DC converter is a 1.5MHz step-down switching regulator adopting constant-off-time (COT) control to provide power to the system, which drives the system load directly and charges the battery through the battery FET. For system voltage control: (1) A minimum system voltage (VSYS_MIN) can be set via the register REG01 Bit [3:1]. When the battery voltage is lower than VSYS_MIN + 60mV, the system voltage is regulated at Max (VSYS_MIN, VBATT) + ∆V, and the battery FET works linearly to charge the battery with trickle-charge, pre-charge, or fast-charge current through the battery FET, depending on the battery voltage. ∆V can be set to 50mV or 100mV via the I2C register REG01 Bit [0]. (2) When the battery voltage exceeds VSYS_MIN + 60mV, the system voltage tracks the battery voltage with a voltage differential of ICHGRBATFET, where the RBATFET is the on resistance of the battery FET. (3) When the charging is suspended or completed, the system voltage is regulated at ∆V higher than Max (VSYS_MIN, VBATT). ∆V can be set to 50mV or 100mV via the I2C register REG01 Bit [0]. Figure 2: NVDC Power Path Management Structure MP2624 Rev.1.05 4/9/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 15 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG VSYS regulation is shown in Figure 3. V SYS_MIN + 110mV vSYS 60mV 50mV V SYS_MIN vBATT V SYS_MIN + 160mV vSYS 100mV 60mV V SYS_MIN vBATT Figure 3: VSYS Variation with VBATT The MP2624 monitors continuously the voltage at SYS. Once the system voltage is 100mV over VBATT_FULL + ∆V, it is detected as a VSYS OVP condition. The MP2624 will turn off the DC/DC converter, and then the system will be powered by the battery. Battery Charge Profile The MP2624 provides four main charging phases: trickle charge, pre-charge, constant-current charge, and constant-voltage charge. MP2624 Rev.1.05 4/9/2018 Phase 1 (Trickle Charge): When the input power is qualified as a good power supply, the MP2624 checks the battery voltage to decide if trickle charge is required. If the battery voltage is lower than VBATT_SHORT (2.1V), a charging current of 128mA is applied on the battery, which helps reset the protection circuit in the battery pack. Phase 2 (Pre-Charge): When the battery voltage exceeds the VBATT_SHORT, the MP2624 starts to pre-charge safely the deeply depleted battery until the battery voltage reaches the “pre-charge to fast-charge threshold” (VBATT_PRE). If VBATT_PRE is not reached before the pre-charge timer expires, the charge cycle ends, and a corresponding timeout fault signal is asserted. The pre-charge current can be programmed via the I2C register REG03 Bit [7:4]. Phase 3 (Constant-Current Charge) When the battery voltage exceeds VBATT_PRE set via the REG04 Bit [1], the MP2624 enters a constant-current charge (fast charge) phase. The fast-charge current can be programmed as high as 4.5A via the REG02 Bit [7:2]. Phase 4 (Constant-Voltage Charge) When the battery voltage rises to the preprogrammable charge full voltage (VBATT_FULL) set via the REG04 Bit [7:2], the charge current begins to taper off. The charge cycle is considered complete when the charge current reaches the battery full termination threshold (IBF) set via the REG03 Bit [3:0], assuming the termination function is enabled by REG05[7] = 1. If IBF is not reached before the safety charge timer expires (see “Safety Timer” section), the charge cycle ends, and the corresponding timeout fault signal is asserted. Figure 4 shows the battery charge profile. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 16 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG VBATT_FULL ICHG System Voltage VSYS_MIN Charge Current VBATT_PRE VBATT_SHORT IPRE IBF ITC Trickle charge Pre-charge CC Fast Charge Constant Voltage Charge Charge Full Figure 4: Battery Charge Profile During the entire charging process, the actual charge current may be less than the register setting due to other loop regulations like dynamic power management (DPM) regulation (input current limit or input voltage regulation loop), or thermal regulation. Thermal regulation reduces the charge current, so the IC junction temperature does not exceed the pre-set limit. The multiple thermal regulation thresholds (from 60ºC to 120ºC) help system design meet thermal requirements for different applications. The junction temperature regulation threshold can be set via the REG06 Bit [1:0]. A new charge cycle starts when the following conditions are valid: The input power is re-plugged. Battery charging is enabled by I2C, and -------- CE is forced to a low logic. No thermistor fault. No safety timer fault. No battery over voltage. The BATT FET is not forced to turn off. Automatic Recharge When the battery is charged full or the charging is terminated, the battery may be discharged because of the system consumption or selfdischarge. When the battery voltage is discharged below the recharge threshold, automatically the MP2624 starts a new charging cycle. MP2624 Rev.1.05 4/9/2018 -------- CE Control -------- CE is a logic input pin for enabling or disabling battery charging by turning on/off the DC/DC or restarting a new charging cycle. The battery charging is enabled when the REG01 Bit [5:4] is -------- set to 01, and CE is pulled to low logic. Indication Apart from multiple status bits designed in the I2C registers, the MP2624 also has a hardware ---------------- status output pin (STAT ). The status STAT in different states is shown in Table 1. Table 1: Operation Indications Charging State Charging Charging complete, sleep mode, charge disable Charging suspended STAT Low High Blinking at 1Hz Battery Over-Voltage Protection The MP2624 is designed with built-in battery over-voltage protection. When the battery voltage exceeds VBATT_FULL + 160mV, the MP2624 suspends immediately the charging and asserts a fault. When battery over-voltage protection occurs, only the charging is disabled, and the DC/DC will keep operating. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 17 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG Battery Floating Detection The MP2624 is capable of detecting whether a battery is connected or not. The following conditions initiate battery float detection: Charging is enabled. Auto-recharge is triggered. Battery OVP recovery. Battery Always Present VSYS VBATT 1.5s Before a charging cycle is initiated, the MP2624 will implement battery floating detection (see Figure 5). Under this condition, the detection block sinks a 3mA current for 1.5 seconds to check if VBATT is lower than 2.1V. If VBATT is higher than 2.1V, the battery present will be detected. Otherwise, the MP2624 will continue to source a 3mA current and start a 1 second timer to check when VBATT exceeds 3.6V. If VBATT is still lower than 3.6V when the 1 second timer expires, the battery present is asserted. The system regulation voltage is set to Max (VSYS_MIN, VBATT) + ∆V, and the charging begins to soft start. Before the 1 second timer expires (as soon as VBATT rises up to 3.6V), the 3mA sink current source will be disabled, and the battery absent is detected. In this case, the charging is disabled, and the system regulation voltage is set to VBATT_FULL + ∆V. Battery floating detection flow is shown in Figure 6. Battery Always Absent 4.2V 3.6V 2.1V 4.2V 3.6V (a) Charging Start-Up with Battery Absent VSYS 2.1V 1s (b) Charging Start-Up with Battery Present (c) Remove Battery during Charging Figure 5: Battery Float Detection Examples System Over-Voltage Protection The MP2624 always monitors the voltage at SYS. When system over-voltage is detected (VSYS > VBATT_FULL+ ∆V +100mV), the DC/DC converter is turned off, and the system is powered by the battery via the battery FET. ∆V can be set to 50mV or 100mV via the I2C register REG01 Bit[0]. During heavy system load transient, System OVP often happens when load transient from heavy to light. The timer is suspend when system OVP, so the timer may transfer between normal and suspend frequently, the timer counter will receive a fault timer clock signal, then fault timer out may happen under this condition. VBATT 1.5s MP2624 Rev.1.05 4/9/2018 1s www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 18 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG Battery Dectection 1. EnChg 2. Auto-recharge 3. Battery OVP Recover Battery Present As Default Sink 3mA for 1.5s VBATT < 2.1V? No Battery Present Source 3mA for 1s Yes Source 3mA, Start 1s Timer Yes VBATT > 3.6V? 1s Timer Expired? No 1s Timer Expired ? Yes Yes Disable 3mA Source Current Battery Present No Set the V SYS to Max (V SYS_MIN , V BATT) + 50mV or 100mV No Battery Absent Charge Start Set the V SYS to V BATT_FULL + 50mV or 100mV Disable Charge Figure 6: Battery Float Detection Flow MP2624 Rev.1.05 4/9/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 19 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG Input Voltage Based and Input Current Based Power Management To meet the maximum current limit for the USB specification and avoid overloading the adapter, the MP2624 features both input current and input voltage power management by continuously monitoring the input current and input voltage. The total input current limit is programmable to prevent the input source from being overloaded. When the input current hits the limit, the charge current tapers off to keep the input current from increasing further. If the pre-set input current limit is higher than the rating of the adapter, the back-up input voltage based power management works to prevent the input source from being overloaded. When the input voltage falls below the input voltage regulation threshold, due to the heavy load, the charge current is reduced to keep the input voltage from dropping further. During CV mode, while battery voltage has been charged to the value only 100mV lower than the battery full threshold, if the power path management happens and charge current drops be lower than IBF, the charge full will be fault detected. The operation of the power path management is applied in the following two cases: As mentioned in the “NVDC Power Structure” section, a) When VBATT < VSYS_MIN + 60mV, the system voltage is regulated at Max (VSYS_MIN, VBATT) + ∆V. If the input current or voltage regulation threshold is reached, the system voltage loop will lose the control of the DC/DC converter, which will cause system voltage drops. Once the system voltage drops by 2%VSYS_MIN, the charge current will be decreased to keep the system voltage from dropping further. b) When VBATT > VSYS_MIN + 60mV (since the battery is connected to the system directly due to the free transition between each control loop), the charge current will decrease automatically when the input current limit or the voltage regulation threshold is reached. Battery Supplement Mode During battery supplement mode, the charge current is reduced to keep the input current or MP2624 Rev.1.05 4/9/2018 input voltage from dropping when DPM occurs. If the input source is still overloaded, even when the charge current has decreased to zero, the system voltage starts to fall off. Once the system voltage falls below the battery voltage, the MP2624 enters battery supplement mode. The battery will power both the system and the DC/DC converter simultaneously. An ideal diode mode is designed in the MP2624 to optimize the control transition between the battery FET and DC/DC converter. The battery FET will enter ideal diode mode under the following conditions: a) Charging start-up when VBATT > VSYS_MIN + ∆V. b) When VBATT < VSYS_MIN +∆V, if the system voltage drops below the battery voltage, the battery FET will enter ideal diode mode. During ideal diode mode, the battery FET operates as an ideal diode. When the system voltage is 40mV below the battery voltage, the battery FET turns on and regulates the gate drive of the battery FET; the VDS of the battery FET remains around 20mV. As the discharge current increases, the battery FET obtains a stronger gate drive and a smaller RDS until the battery FET is fully on. NTC (Negative Thermistor Temperature Coefficient) “Thermistor” is the generic name given to a thermally sensitive resistor. Generally, a negative temperature coefficient thermistor is called a thermistor. Depending on the manufacturing method and the structure, there are many thermistor shapes and characteristics for various applications. The thermistor resistance values, unless otherwise specified, are classified at a standard temperature of 25ºC. The resistance of a temperature is solely a function of its absolute temperature. Refer to the thermistor datasheet. The mathematical expression, which relates to the resistance and the absolute temperature of a thermistor, is shown in Equation (1): R1 R2 e 1 1 T1 T2 (1) Where R1 is the resistance at the absolute temperature T1, R2 is the resistance at the www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 20 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG absolute temperature T2, and β is a constant, which depends on the material of the thermistor. In charge mode, the MP2624 monitors continuously the battery’s temperature by measuring the voltage at NTC. This voltage is determined by the resistive divider whose ratio is produced by the different resistances of the NTC thermistor under the different ambient temperatures of the battery. Maximum Charge Current 1C 0.5C Maximum Charge Voltage : 4.25V (4.2V Typical) 4.15V Maximum 4.10V Maximum Cold Cool T1 (0DegC) Normal T2 (10DegC) Warm Hot threshold (45ºC<TNTC<60ºC), and the hot battery threshold (TNTC>60ºC). For a given NTC thermistor, these temperatures correspond to the VCOLD, VCOOL, VWARM, and VHOT. When VNTC < VHOT or VNTC > VCOLD, the charging is suspended, and the timers are suspended. When VHOT < VNTC < VWARM, the charge-full voltage (VBATT_FULL) is reduced by 150mV compared to the programmable threshold. When VCOOL < VNTC < VCOLD, the charging current is reduced to half of the programmable charge current. Figure 7 shows the JEITA control. Separate Pull-Up Pin VNTC for NTC Protection As shown in Figure 8, a separate pull-up VNTC is designed as the internal pull-up terminal of the resistive divider for the NTC comparator. Both the reference divider and the feedback divider are connected together to VNTC. The VNTC is connected to VREF via an internal switch (in charge mode only). T3 T4 T5 (45DegC) (50DegC) (60DegC) VREF Charge/ Discharge? Figure 7: NTC Window MP2624 sets internally a pre-determined upper and lower bound of the range. If the voltage at NTC goes out of this range, which means the temperature is outside the safe operating limit, the charging is ceased unless the operating temperature returns to a safe range. To satisfy the JEITA requirement, the MP2624 monitors four temperature thresholds: the cold battery threshold (TNTC<0ºC), the cool battery threshold (0ºC<TNTC<10ºC), the warm battery MP2624 Rev.1.0 4/9/2018 VNTC RT1 NTC Cold RT2 RNTC Hot Cool NTC Protection Warm Figure 8: NTC Protection Circuit www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 21 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG Check VBUS No VBUS>3.8V? Yes DCD Start 500ms Timer Enable IDP_SRC (10µA) Connect RDM_PULL_DOWN (20kΩ) No DP< VDAT_REF(0.325V) for 40ms? Yes No 500ms Timer Expires? Release DP, DM Yes DM/DP Floating Primary Detection Release DP/DM, set IIN_LMT at 100mA Enable VDP_SRC (0.6V) Enable IDM_SINK (50µA) DM< VDAT_REF(0.325V) after 56ms? Yes Release DP/DM, set IIN_LMT at 100mA (OTG=Low) 500mA(OTG=High) No Release DP/DM, set IIN_LMT at 1800mA Figure 9: USB Detection Flow Chart MP2624 Rev.1.05 4/9/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 22 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG DM/DP USB Detection The USB ports in personal computers are convenient places for portable devices (PDs) to draw current for charging batteries. If the portable device is attached to a USB host of hub, then the USB specification requires the portable device to draw a limited current (100mA/500mA in USB2.0, and 150mA/ 900mA in USB3.0). When the device is attached to a charging port, it is allowed to draw more than 1.5A. The MP2624 features input source detection compatible with the Battery Charging Specification Revision 1.2 (BC1.2) to program the input current limit during default mode. The user can force DP/DM detection in the host mode by writing 1 to REG07 Bit [7]. When the input source is first applied, the input current limit begins with 100mA by default. If the input source passes the input source qualification, the MP2624 starts DP/DM detection. The DP/DM detection circuit is shown in Figure 10. The DP/DM detection has two steps: 1. Data Contact Detection (DCD) 2. Primary Detection. DCD detection uses a current source to detect when the data pins have made contact during an attach event. The protocol for data contact detect is as follows: The power device (PD) detects VIN asserted. The PD turns on DP IDP_SRC and the DM pull-down resistor for 40ms. The PD waits for the DP line to be low. The PD turns off IDP_SRC and the DM pulldown resistor when the DP line is detected as low or the 40ms timer is expired. DCD allows the PD to start primary detection as soon as the data pins have made contact. Once the data contact is detected, the MP2624 will jump to the primary detection immediately. If the data contact is not detected, the MP2624 will jump automatically to the primary detection after 300ms from the beginning of the DCD. MP2624 Rev.1.05 4/9/2018 Primary detection is used to distinguish between the USB host (or SDP) and different types of charging ports. During primary detection, the PD turns on the VDP_SRC on DP and the IDM_SINK on DM. If the portable device is attached to a USB host, the DM is low. Figure 9 shows the USB detection flow chart. To be compatible with the USB specification and BC1.2, set the input current limit according to the values listed in Table 2. Table 2: Input Current Limit vs. USB Type DP/DM Detection Floating SDP SDP DCP OTG IIN_LMT REG08 [7:6] X LOW HIGH X 100mA 100mA 500mA 1.8A 00 10 10 01 The USB detection runs as soon as the VIN is detected and is independent of the charge enable status. After the DP/DM detection is complete, the MP2624 will set the input current limit according to Table 2 and assert the USB port type in REG08 Bit [7-6]. The host is able to revise the input current limit as well according to the USB port type asserted in the REG08 Bit [7:6]. DP VDP_SRC VLGC_HI IDP_SRC CHG_DET VDAT _REF IDM_SINK DM RDM_DWN Figure 10: DP/DM Detection Circuit www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 23 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG When the detection algorithm is complete, the DP and DM signal lines enter a high-Z (HZ) state with an approximate 4pF capacitive load. Input Current Limit Setting via ILIM For safe operation, the MP2624 has an additional hardware pin (ILIM) to adjust the maximum input current limit. It can be set by a resistor connected from ILIM to GND. The actual input current limit is the lower value between the ILIM setting and the register setting value via I2C. via I2C. The safety timer does not operate in USB OTG mode. The safety timer is reset at the beginning of a new charging cycle. Also, it can be reset by -------- toggling CE or write 00 and 01 sequentially to the REG01 Bit [5:4]. The following actions restart the safety timer: Interrupt to Host (INT) The MP2624 has an alert mechanism, which can output an interrupt signal via INT to notify the system of the operation by outputting a 256μs low state INT pulse. All of the events below trigger the INT output: Good input source detected USB detection completed UVLO Charge completed Any fault in REG09 (Watchdog timer fault, OTG fault, thermal fault, safety timer fault, battery OVP fault, and NTC fault) When a fault occurs, the charger device sends out an INT signal and latches the fault state in REG09 until the host reads the fault register. Before the host reads REG09, the charger device will not send a new INT signal upon new faults except for NTC faults. The NTC fault is not latched and always reports the current thermistor conditions. In order to read the current fault status, the host has to read REG09 two times consecutively. The 1st reads the fault register status from the last INT, and the 2nd reads the current fault register status. Safety Timer The MP2624 provides both a pre-charge and complete charge safety timer to prevent an extended charging cycle due to abnormal battery conditions. The total safety timer for both trickle charge and pre-charge is 1 hour when the battery voltage is lower than VBATT_PRE. The complete charge safety timer starts when the battery enters constant-current charge. The constantcurrent charge safety timer can be programmed by I2C. The safety timer feature can be disabled MP2624 Rev.1.05 4/9/2018 A new charge cycle has begun. Toggling CE from low to high to low (charge enable) Write REG01 Bit [5:4] from 00 to 01 (charge enable) Write REG05 Bit [3] from 0 to 1 (safety timer enable) Write REG01 Bit [7] from 0 to 1 (software reset) -------- The timer can be refreshed after timer out when one of the following thing happens: The input power reset. Toggling CE from low to high to low (charge enable). Writing REG01 Bit[5:4] from 00 to 01 (charge enable). -------- MP2624 adjusts automatically or suspends the timer when a fault occurs. The timer is suspended during the conditions below: The battery is discharging System OVP occurs NTC hot or cold fault If the input current limit, input voltage regulation, or thermal regulation threshold is reached, the rest of the timer is doubled by enable the 2X timer in PPM function (REG07H Bit[6]=1). Once the PPM operation is removed, the rest of the timer returns to the original setting. This setting may cause an application issue, if the IC operates in and out of PPM frequently, the single timer period will be divided, which causes false timer out termination. The solution is to disable the 2X timer function by set REG07H Bit[6] to 0. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 24 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG USB Timer The total charging timer in default mode from the 100mA USB source is limited by a 45 minute timer. When this timer expires, the MP2624 stops the converter and goes into high-Z mode. Once the device enters the HIZ state in host mode, it stays in HIZ until the host writes REG00 [7] to 0. When the processor starts-up, it is recommended to first check if the charger is in HIZ mode or not. In default mode, the charger will reset REG00 [7] back to 0 when the input source is removed. When another power source is plugged in, the charger will run detection again and update the current limit. Host Mode and Default Mode The MP2624 is a host-controlled device. After the power-on reset, the MP2624 starts in the watchdog timer expiration state or default mode. All the registers are in the default settings. Any write to the MP2624 makes it transition into host mode. All the device parameters are programmable by the host. To keep the device in host mode, the host has to reset the watchdog timer regularly by writing 1 to REG01 Bit [6] before the watchdog timer expires. Once the watchdog timer expires, the MP2624 returns to default mode. VREF LDO Output The VREF LDO supplies the internal bias circuits as well as the high-side and low-side FET gate drive. The pull-up rail of STAT can be connected to VREF as well. The VREF LDO will be enabled once OTG is enabled. In non-OTG mode, the internal VREF LDO is enabled when the following conditions are valid: VIN > 3.3V No thermal shutdown Both the internal LDO output and VBATT will be passed to VREF via a PMOS. Only when VIN > VBATT +250mV, the internal LDO output will be delivered to VREF. Figure 12 shows the host mode and default mode change flow chart. S1 IN VREF LDO Control BATT S2 Figure 11: VREF Power Supply Circuit Thermal Regulation and Thermal Shutdown The MP2624 monitors continuously the internal junction temperature to maximize power delivery and avoid overheating the chip. When the internal junction temperature reaches the preset threshold, the MP2624 starts to reduce the charge current to prevent higher power dissipation. When the junction temperature reaches 150°C, the PWM step-down converter goes into shutdown mode. Battery Discharge Function If only the battery is connected and the input source is absent (but the OTG function is disabled), the battery FET is turned on completely when VBATT is above the VBATT_UVLO threshold. The 10mΩ battery FET minimizes the conduction loss during discharge and VREF LDO stays off. The quiescent current of the MP2624 is as low as 20μA. The low on resistance and low quiescent current help extend the running time of the battery. There is an over-current limit designed in the MP2624 to avoid system over current when the battery is discharging. Once the discharged current exceeds this limit (IDSG_LMT in EC Table) for a 20μs blanking time, the discharge FET is turned off. After a one second recovery time, the discharge FET is turned on again. The VREF power supply circuit is shown in Figure 11. MP2624 Rev.1.05 4/9/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 25 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG POR V IN >V IN_U VLO or V BAT T>V BATT_U VLO No Yes S leep C om parator A c tiv e , B attery F E T driv er pow er up 2 I C W rite? Yes No D efau lt M o d e H o st M o d e R eset w atchdog tim e r R eset R egister Sta rt w atchdo g tim er H ost Program s R egisters R e se t R E G0 1 B it [ 6] ? Yes Yes No W a tch d o g Tim e r E xp ire d? No Figure 12: Host Mode and Default Mode Battery Shipping Mode Write 1 to REG07 Bit[5] turns off the battery FET immediately when in battery discharge mode. Write 0 to REG07 Bit[5] turns on the battery FET again. In applications where the battery is not removable, it’s essential to disconnect the battery from the system to allow the system power reset. The MP2624 has a dedicated DISC pin to cut off the path from the battery to the system when the host has lost control. Once the logic at DISC is set to low for more than 8 seconds, the battery is disconnected from the system by turning off the battery FET as the battery shipping mode. When the DISC is pulled to logic high and logic low ang keeps the low period over 0.5s, the IC exit the MP2624 Rev.1.05 4/9/2018 shipping mode and the BATT FET is turned on again. This control is shown in Figure 13. Figure 13: DISC Control Function www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 26 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG Boost Start -Up Power the PMID Pin to 5V Regulate the current at IIN _LMT + 300mA Start the 3ms and 30ms Timer Yes No No V BUS > 4.6V? 3ms timer expires ? 5ms timer expires ? No Yes Yes 30ms timer expires? No Turn off block switch Start 5ms timer Yes Turn on the block switch Latch Off the block switch Figure 14: OTG Boost Start-Up Flow OTG Boost Function The MP2624 is able to supply a regulated 5V output at IN for powering the peripherals compliant with the USB On-The-Go specification. The MP2624 will not enter the OTG mode if the battery is below the battery UVLO threshold to ensure that the battery is not drained. In order to enable the OTG mode, the input voltage at IN must be below 1.0V. Boost operation can be enabled when REG01 Bit [5:4] = 10/11 and OTG is high. The OTG output current can be selected as 500mA or 1.3A via I2C (REG02 Bit [1:0]). During boost mode, the status register REG08 Bit [7:6] is set to 11. Boost operation is enabled only when the following conditions are met: VBATT > VBATT_UVLO (rising 2.7V) OTG is Bit [5:4] =10/11 After a 200ms delay, boost mode is enabled VIN < 1V high, and REG01 30ms, the OTG fault will be asserted, and OTG will be disabled until the host command is executed, or OTG is toggled. Also, the MP2624 provides output short-circuit protection and output over-voltage protection. In OTG mode, if VIN falls below USB UVLO for more than 30ms, an OTG fault will be asserted, and OTG will be disabled until the host command is executed, or OTG is toggled. Any fault during boost operation sets the fault register REG09 Bit [6] to 1. When both charging and OTG are enabled, the OTG operation takes priority. Figure 14 shows the OTG boost start-up time sequence. Once OTG is enabled, the MP2624 will boost the PMID to 5.0V first. Then the block FET is regulated linearly with the current limit of IOLIM + 300mA. When the VIN_OTG is charged higher than 4.6V within 6ms, the block FET is turned on fully. Otherwise, PMID tries to charge IN again after a 8ms off period. When the total time hits 56ms, the OTG is turned off and will not start again until the OTG mode is reset. When the OTG output is in an OCP condition or short condition, the output works the same process. Once OTG is enabled, if the voltage at VIN does not go above the USB UVLO (4.65V) level within MP2624 Rev.1.05 4/9/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 27 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG The MP2624 monitors continuously the voltage at VIN_OTG in OTG boost mode. Once the VIN exceeds VOTG_OVP, the MP2624 stops switching, and a corresponding fault register is set high to indicate the fault. In boost mode, the MP2624 employs a fixed 1.5MHz PWM step-up switching regulator. It switches from PWM operation to pulse-skipping operation at light load. OTG Output CC Mode When in the OTG mode, the load at the VIN has current limit, which could be set via the I2C REG02H Bit[1:0], high to 2A. MP2624 could operates in CC mode when the current limit is reached while the VIN voltage does not drop to the over load or short circuit threshold (<VBATT+100mV) as shown in Figure 15. Therefore, MP2624 not only has the CC mode during the charging process, but also has CC mode operation in OTG mode for various applications. Figure 15. OTG Output U-I Curve Impedance Compensation to Accelerate Charging Throughout the charging cycle, the constantvoltage charging stage occupies larger ratios. To accelerate the charging cycle, it is better to have the charging remain in the constant-current charge stage as long as possible. MP2624 allows the user to compensate the intrinsic resistance of the battery by adjusting the charge full voltage threshold, according to the charge current and internal resistance. In addition, a maximum allowed regulated voltage is set for the sake of the safety condition. See Equation (2): VBATT _ REG VBATT _ FULL Min ICHG _ ACT R BAT _ CMP , VCLAMP (2) Where VBATT_REG is the battery regulation voltage, VBATT_FULL is the charge full voltage set via the I2C MP2624 Rev.1.05 4/9/2018 REG04 Bit [7:2]; ICHG_ACT is the real-time charge current during the operation; RBAT_CMP is the compensated resistor to simulate the resistor of the connection wire of the battery (it is selected through the REG06 Bit[7:5]), and VCLAMP is the battery compensation voltage clamp (above VBATT_FULL); it is selected via the REG06 Bit[4:2]. Sleep Mode When the input power source is missing and OTG is disabled, the MP2624 will transition into sleep mode. During sleep mode, the battery powers the internal circuit, and the internal VREF LDO is turned off. The system is connected to the battery through the battery FET, and IN is bridged off from SYS by the reverse blocking FET. In order to extend the battery life during shipping and storage, the MP2624 can turn off the battery FET to minimize leakage. Series Interface The MP2624 family uses an I2C compatible interface for flexible charging parameters setting and instantaneous device status reporting. I2CTM is a bidirectional 2-wire serial interface developed by Philips Semiconductor (now NXP Semiconductors). Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). The device can be considered a master or a slave when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit the transfer. At that time, any device addressed is considered a slave. The device operates as a slave device with the address 4BH, receiving control inputs from the master device, like a micro controller or a digital signal processor. The I2C interface supports both standard mode (up to 100k bits), and fast mode (up to 400k bits). Both SDA and SCL are bi-direction lines, connecting to the positive supply voltage via a current source or pull-up resistor. When the bus is free, both lines are high. SDA and SCL are open drains. The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can change only when the clock signal on the SCL line is low. One clock pulse is generated for each data bit transferred (see Figure 16). www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 28 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG SDA Data line stable; data valid SCL Change of data allowed Figure 16: Bit Transfer on the I2C Bus All the transactions begin with a START (S) and can be terminated by a STOP (P). A high to low transition on the SDA line while the SCL line is high defines a START condition. A low to high transition on the SDA line when the SCL line is high defines a STOP condition. START and STOP conditions are always generated by the master. The bus is considered busy after the START condition; it is considered free after the STOP condition (see Figure 17). SDA SCL START (S) STOP (P) Figure 17: START and STOP Conditions Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other function, it can hold the SCL line low to force the master into a wait state (clock stretching). Data transfer then continues when the slave is ready for another byte of data and releases the SCL line (see Figure 18). Figure 18: Data Transfer on the I2C BUS MP2624 Rev.1.05 4/9/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 29 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received, so another byte may be sent. All clock pulses, including the acknowledge 9th clock pulse, are generated by the master. The transmitter releases the SDA line during the acknowledge clock pulse, so the receiver can pull the SDA line low. It remains high during the 9th clock pulse; this is the “not acknowledge” signal. The master can then generate either a STOP to abort the transfer or a repeated START to start a new transfer. After the START, a slave address is sent. This address is 7 bits long followed by the 8th bit a data direction bit (bit R/W). A zero indicates a transmission (WRITE), and a one indicates a request for data (READ). The complete data transfer is shown in Figure 19. Figure 19: Complete Data Transfer Figure 20: Single Write Figure 21: Single Read Figure 22: Multi Write MP2624 Rev.1.05 4/9/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 30 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG Figure 23: Multi Read If the register address is not defined, the charger IC sends back NACK and returns to an idle state. real condition. In addition, the fault register REG09 does not support multi-read or multi-write. The charger device supports multi-read and multi-write on REG00 through REG08. REG09 is a fault register. It keeps all the fault information from the last read until the host issues a new read. For example, if there is a TS fault but it is recovered immediately, the host still sees the TS fault during the first read. In order to get the present fault information, the host has to read REG09 for the second time. REG09 does not support multi-read and multi-write. The fault register REG09 locks the previous fault and only clears it after the register is read. For example, if the charge safety timer expiration fault occurs but recovers later, the fault register REG09 reports the fault when it is read the first time; it returns to normal when it is read the second time. To verify a real time fault, the fault register REG09 should be read twice to get the MP2624 Rev.1.05 4/9/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 31 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG I2C REGISTER MAP IC Address: 4BH Input Source Control Register/ Address: 00H (Default: 0011 0000) Bit Symbol Description Read/ Write Default Bit 7 EN_HIZ(7) 0 – Disable, 1 – Enable Read/ Write Default: Disable (0) Read/ Write Offset: 3.88V Range:3.88V – 5.08V Default: 4.36V (0110) Input Voltage Regulation Bit 6 VIN_REG [3] 640mV Bit 5 VIN_REG [2] 320mV Bit 4 VIN_REG [1] 160mV Bit 3 VIN_REG [0] 80mV Input Current Limit Bit 2 IIN_LMT [2] Bit 1 IIN_LMT [1] Bit 0 IIN_LMT [0] 000 – 100mA 001 – 150mA 010 – 500mA 011 – 900mA 100 – 1200mA 101 – 1800mA 110 – 2000mA 111 – 3000mA Default: SDP: 100mA (000) or 500mA (010) Read/ Write Default: DCP/CDP: 1.8A (101) Power-On Configuration Register / Address: 01H (Default: 0001 1011) Bit Symbol Description Bit 7 Register reset 0 – Keep current setting 1 - Reset 0 – Normal 1 – Reset I2C watchdog timer reset Charger Configuration Bit 5 Mode [1] Bit 6 Bit 4 Mode [0] 00 – Charge disable 01 – Charge battery 10/11 – OTG, Minimum System Voltage Bit 3 VSYS_MIN [2] 0.4V Bit 2 VSYS_MIN [1] 0.2V Bit 1 VSYS MIN [0] 0.1V System Regulation Voltage Higher than Full Battery Voltage 0 – 50mV Bit 0 VSYS_MAX [0] 1 – 100mV NOTE: Read/ Write Default Read/ Write Keep current register setting (0) Read/ Write Normal (0) Read/ Write Charge battery (01) Read/ Write Offset: 3V Range: 3V – 3.7V Default: 3.6V (110) Read/ Write Default: 100mV (1) 7) This is used to turn off the DC/DC only. At this time, the system is powered by the battery. MP2624 Rev.1.05 4/9/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 32 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG Charge Current Control Register/ Address: 02H (Default: 0010 0001) Bit Symbol Description Bit 7 ICHG [5] 2048mA Bit 6 ICHG [4] 1024mA Bit 5 ICHG [3] 512mA Bit 4 ICHG [2] 256mA Bit 3 ICHG [1] 128mA Bit 2 ICHG [0] 64mA Read/ Write Default Offset: 512mA Range: 512mA – 4544mA Read/ Write Default: 1024mA (001000) USB OTG Current Limit Bit 1 IOLIM[1] Bit 0 IOLIM[0] 00 – 500mA 01 – 1.3A Read/ Write 1.3A (01) Pre-Charge/ Termination Current/ Address: 03H (Default: 0011 0011) Bit Symbol Description Read/ Write Default Read/ Write Offset: 64mA Range: 64mA – 1024mA Default: 256mA (0011) Read/ Write Offset: 64mA Range: 64mA – 1024mA Default: 256mA (0011) Pre-Charge Current Bit 7 IPRE [3] 512mA Bit 6 IPRE [2] 256mA Bit 5 IPRE [1] 128mA Bit 4 IPRE [0] 64mA Termination Current Bit 3 IBF [3] 512mA Bit 2 IBF [2] 256mA Bit 1 IBF [1] 128mA Bit 0 IBF [0] 64mA MP2624 Rev.1.05 4/9/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 33 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG Charge Voltage Control Register/ Address: 04H (Default 1100 0011) Bit Symbol Description Read/ Write Default Read/ Write Offset: 3.48V Range: 3.48V – 4.425V Default: 4.2V (110000) Read/ Write 3.0V (1) Read/ Write 100mV (1) Charge Full Voltage Bit 7 VBATT_FULL [5] 480mV Bit 6 VBATT [4] 240mV Bit 5 VBATT_FULL [3] 120mV Bit 4 VBATT_FULL [2] 60mV Bit 3 VBATT_FULL [1] 30mV Bit 2 VBATT_FULL [0] 15mV FULL Pre-Charge Threshold Bit 1 VBATT_PRE 0 – 2.8V 1 – 3.0V Battery Recharge Threshold (below VBATT_FULL) Bit 0 VRECH 0 – 200mV 1 – 100mV Charge Termination/Timer Control Register / Address: 05H (default: 1001 1000) Bit Symbol Description Read/ Write Default 0 – Disable 1 – Enable Read/ Write Enable (1) 0 – Match IBF 1 – Indicate before the actual termination on START Read/ Write Match IBF (0) 00 – Disable timer 01 – 40s 10 – 80s 11 – 160s Read/ Write 40s (01) Read/ Write Enable timer (1) Termination Setting Bit 7 EN_BF Termination Indicator Threshold Bit 6 BF_STAT I2C Watchdog Timer Limit Bit 5 WATCHDOG [1] Bit 4 WATCHDOG [0] Safety Timer Setting Bit 3 EN_TIMER 0 – Disable 1 – Enable Constant-Current Charge Timer (2x during PPM) Bit 2 CHG _TMR [1] Bit 1 CHG _TMR [2] Bit 0 Reserved MP2624 Rev.1.05 4/9/2018 00 – 5hrs 01 – 8hrs 10 – 12hrs 11 – 20hrs 5hrs (00) Read/ Write Read/ Write (0) www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 34 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG Compensation/ Thermal Regulation Control Register / Address: 06H (Default: 0000 0011) Bit Symbol Description Bit 7 RBAT_CMP [2] 40mΩ Bit 6 RBAT_CMP [1] 20mΩ Bit 5 RBAT 10mΩ CMP [0] Read/ Write Read/ Write Default Range: 0 – 70mΩ Default: 0mΩ (000) Battery Compensation Voltage Clamp (above VBATT_FULL) Bit 4 VCLAMP [2] 64mV Bit 3 VCLAMP [1] 32mV Bit 2 VCLAMP [0] 16mV Read/ Write Range: 0 – 112mV Default: 0mV (000) Thermal Regulation Threshold Bit 1 Bit 0 TREG [1] TREG [0] 00 – 60ºC 01 – 80 ºC 10 – 100 ºC 11 – 120ºC Default: 120ºC (11) Read/ Write Miscellaneous Operation Control Register/ Address: 07H (Default: 0101 1011) Bit Symbol Description Read/ Write Default Bit 7 USB_DET_EN 0 – Not in DP/DM detection 1 – Force DP/DM detection Read/ Write Not in DP/DM detection (0) Bit 6 TMR2X_EN 0 – Disable 2x extended safety timer 1 – Enable 2x extended safety timer Bit 5 BATFET_DIS Bit 4 Reserved Bit 3 EN_NTC Bit 2 Read/ Write Read/ Write Enable (0) Read/ Write (0) 0 – Disable 1 – Enable Read/ Write Enable (1) BATUVLO_DIS 0 – Enable 1 – Disable Read/ Write (0) Bit 1 INT_MASK [1] 0 – No INT during CHG_FAULT 1 – INT in CHG_FAULT Read/ Write INT in CHG_FAULT (1) Bit 0 INT_MAST [0] 0 – No INT during BAT_FAULT 1 – INT in BAT_FAULT Read/ Write INT in BAT_FAULT (1) MP2624 Rev.1.05 4/9/2018 0 – Enable 1 – Turn off Enable (1) www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 35 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG System Status Register/ Address: 08H (Default: 0000 0001) Bit Symbol Description Bit 7 VBUS_STAT [1] 00 – Unknown 01 – Adaptor port 10 – USB host 11 – OTG Bit 6 VBUS_STAT [0] Bit 5 CHG_STAT [1] Bit 4 CHG_STAT [0] Bit 3 PPM_STAT Read/ Write Default Read only (Including no input or DPDM detection incomplete) Unknown (00) Not charging (00) 00 – Not charging 01 – Trickle charge 10 – Constant-current charge 11 – Charge done Read only 0 – No PPM 1 – VINPPM or IINPPM Read only Read only Bit 2 PG_STAT 0 – No power good 1 – Power good Bit 1 THERM_STAT 0 – Normal 1 – Thermal regulation Bit 0 VSYS_STAT 0 – In VSYSMIN regulation 1 – Not in VSYSMIN regulation No PPM (0) (No power path management occurs) No power good (0) Read only Normal (0) Read only Not in VSYSMIN regulation (1) Fault Register/ Address: 09H (Default: 0000 0000) Bit Symbol Description Read/ Write Default Bit 7 WATCHDOG_F AULT 0 – Normal 1 – Watchdog timer expiration Read only Normal (0) Read only Normal (0) OTG_FAULT 0 – Normal 1 – VBUS overloaded, VBUS OVP, or battery under voltage 00 – Normal 01 – Input fault (bad source) 00 – Thermal shutdown 11 – Safety timer expiration Read only Normal (00) Normal (0) Bit 6 Bit 5 CHG_FAULT [1] Bit 4 CHG_FAULT [0] Bit 3 BAT_FAULT 0 – Normal 1 – Battery OVP Read only Bit 2 NTC_FAULT [2] Read only Bit 1 NTC_FAULT [1] Bit 0 NTC_FAULT [0] 000 – Normal 001 – NTC cold 010 – NTC cool 011 – NTC warm 100 – NTC hot MP2624 Rev.1.05 4/9/2018 Normal (000) www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 36 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG Vender/ Part/ Reversion Status Register/ Address: 0AH (Default: 0000 0100) Bit Symbol Bit 7 Bit 6 Description Read/ Write Default Reserved Read only (0) Reserved Read only (0) MP2624 (000) Read only (000) 0 – Standard 1 – JEITA Read only (1) Read only (00) Part Number Bit 5 PN [2] Bit 4 PN [1] Bit 3 PN [0] Bit 2 NTC_TYPE Revision Bit 1 Rev [1] Bit 0 Rev [0] MP2624 Rev.1.05 4/9/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 37 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG CONTROL FLOW CHART Different Operations in Host Mode MP2624 Rev.1.05 4/9/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 38 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG CONTROL FLOW CHART (continued) Charging Process vSYS= Max (VSYS_MIN, vBATT) + ∆V No ∆V=50mV or 100mV depending on I2C Setting Done? Yes Charger Enabled by Host? No Yes Charger Enabled by /CE? No Yes vSYS= VBATT_FULL + ∆V No Battery Present or Not? vSYS= Max (VSYS_MIN, vBATT) + ∆V Yes MP2624 Rev.1.05 4/9/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 39 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG CONTROL FLOW CHART (continued) Charging Process Charging Start Charge Mode? VBATT = VBATT_FULL VBATT_GD < VBATT < VBATT_FULL CV Charge CC Charge Battery FET On vSYS=VBATT_FULL+ ICHG*RBATFET Battery FET On vSYS=vBATT + ICHG*RBATFET No VBATT_TC < VBATT < VBATT_GD VBATT <VBATT_SC VBATT < VBATT_TC CC Charge TC Charge Wake Up vSYS=VSYS_MIN + ∆V vSYS=VSYS_MIN + ∆V vSYS=VSYS_MIN + ∆V No No No No ICHG<IBF ? VBATT=VBATT_FULL? VBATT>VBATT_GD VBATT>VBATT_TC ? VBATT>VBATT_SC ? Yes Yes Yes Yes Yes Charger “Off”, Indicate battery full vSYS = vBATT + ∆V Yes ∆V=50mV or 100mV depending on I2C Setting No vBATT< VRECH ? MP2624 Rev.1.05 4/9/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 40 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG ripple current, which is usually 30% of the CC charge current. APPLICATION INFORMATION Component Selection Setting the Input Current Limit The input current limit setting is set according to the input power source. For an adapter input, the input current limit can be set through I2C by the GUI. To set a value that is not provided by the I2C, the input current limit can be set through ILIM. Connect a resistor from ILIM to AGND to program the input current limit. The relationship is calculated using Equation (3): IIN_LMT 48.48 （A） R ILIM（k） (3) 2 The MP2624 selects the lower one of the I C and resistor setting for its input current limit setting. For resistor setting, use 1% accuracy resistor. For a USB input, the input current limit is set according to Table 2. Selecting the Inductor Inductor selection is a trade off between cost, size, and efficiency. A lower inductance value corresponds to a smaller size, but it results in a higher ripple current, a higher magnetic hysteretic loss, and a higher output capacitance. Choosing a higher inductance value gives the benefit of a lower ripple current and smaller output filter capacitors, but it may result in higher inductor DC resistance (DCR) loss and larger size. From a practical standpoint, the inductor ripple current should not exceed 30% of the maximum load current under worst-case conditions. When operating with a typical 5V input voltage, the maximum inductor current ripple occurs at the corner point between the trickle charge and the CC charge (VBATT = 3V). Estimate the required inductance with Equation (4) and Equation (5): L VIN VBATT VBATT (H) IL _ MAX VIN fS (MHz) (4) %ripple ) (A) 2 (5) IPEAK ILOAD(MAX ) (1 Where, VIN, VBATT, and fS are the typical input voltage, battery voltage, and switching frequency, respectively. ∆IL_MAX is the maximum inductor MP2624 Rev.1.05 4/9/2018 Although the maximum charge current can be set to a high 4.5A, the real charge current cannot reach this value as the input current limit. For most applications, allow a large enough margin to avoid hitting the peak current limit of the highside switch (7A, typically). The maximum inductor current ripple is set to 1.0A with 5Vin (30% of the max load- about 3.5A considering the input current limit); the inductor is 0.75µH. Select 1.0µH in the application with the saturation current over 4.5A Select 1.0µH in the application with the saturation current over 4.5A Choose a larger inductance such as 2.2uH is good for the EMI consideration with smaller current ripple, while the size may be larger. Selecting the Input Capacitor The input current to the step-down converter is discontinuous, therefore a capacitor is required to supply the AC current to the step-down converter while maintaining the DC input voltage. Use low ESR capacitors for the best performance. Ceramic capacitors are preferred, but tantalum or low ESR electrolytic capacitors will suffice. Choose X5R or X7R dielectrics when using ceramic capacitors. Since the input capacitor (CIN) absorbs the input switching current, it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated with Equation (6): ICIN ILOAD VOUT VOUT 1 VIN VIN (6) Where, VOUT is VSYS. The worst-case condition occurs at VIN = 2VOUT, where ICIN = ILOAD/2. For simplification, choose the input capacitor with a RMS current rating greater than half of the maximum load current. For the MP2624, the RMS current in the input capacitor comes from PMID to GND, so a small, high-quality ceramic capacitor (e.g., 4.7μF), should be placed as close to the IC as possible from VPMID to PGND. The remaining capacitor should be placed from VIN to GND. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 41 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG When using ceramic capacitors, make sure they have enough capacitance to provide sufficient charge to prevent excessive voltage ripple at the input. Selecting the Output Capacitor The output capacitor CSYS from the typical application circuit is in parallel with the SYS load. CSYS absorbs the high-frequency switching ripple current and smoothes the output voltage. Its impedance must be much less than the system load to ensure it properly absorbs the ripple current. Use a ceramic capacitor because it has a lower ESR and a smaller size. This allows the ESR of the output capacitor to be ignored. Thus, the output voltage ripple is given with Equation (7): VSYS r VSYS VSYS VIN % 8 CSYS fS 2 L 1 (7) In order to guarantee ±0.5% system voltage accuracy, the maximum output voltage ripple must not exceed 0.5% (e.g. 0.1%). The maximum output voltage ripple occurs at the minimum system voltage and the maximum input voltage. For VIN = 7V, VSYS_MIN = 3.6V, L = 2.2µH, fS = 1.6MHz, and r =0.1%. The output capacitor can be calculated as 11µF using Equation (8): V 1 SYS _ MIN VIN (8) CSYS 2 8 fS L r Then, choose a 22µF ceramic capacitor. MP2624 Rev.1.05 4/9/2018 Resistor Selection for the NTC Sensor Figure 9 shows an internal resistor divider reference circuit that limits both the high and low temperature thresholds at VTH_High and VTH_Low, respectively. For a given NTC thermistor, select an appropriate RT1 and RT2 to set the NTC window using Equation (9) and Equation (10): RT2//RNTC_Cold RT1 RT2//RNTC_Cold RT2 //RNTC_Hot RT1 RT2 //RNTC_Hot VTH_Low VNTC VTH_High VCC (9) (10) RNTC_Hot is the value of the NTC resistor at a high temperature (within the required temperature operating range), and RNTC_Cold is the value of the NTC resistor at a low temperature. The two resistors (RT1 and RT2) allow the high and low temperature limits to be programmed independently. With this feature, the MP2624 can fit most types of NTC resistors and different temperature operating range requirements. RT1 and RT2 values depend on the type of the NTC resistor selected. For example, for a 103AT thermistor, the thermistor has the following electrical characteristics: At 0°C, RNTC_Cold = 27.28kΩ; at 60°C, RNTC_Hot = 3.02kΩ. The following equation calculations are derived assuming that the NTC window is between 0°C and 50°C. According to Equation (9) and V V Equation (10), use TH_Low and TH_High from the VNTC VNTC EC table to calculate RT1 = 2.27kΩ and RT2 = 6.86kΩ. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 42 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG PCB Layout Guidelines Efficient PCB layout is critical to meet specified noise rejection requirements and improve efficiency. For best results follow the guidelines below: 1) Route the power stage adjacent to the grounds. Aim to minimize the high-side switching node (SW, inductor) trace lengths in the highcurrent paths and the current sense resistor trace. 2) Keep the switching node short and away from all small control signals, especially the feedback network. 3) Place the input capacitor as close as possible to PMID and PGND. 4) Place the output inductor close to the IC and connect the output capacitor between the inductor and PGND of the IC. 5) For high-current applications, the pins for the power pads (IN, SW, SYS, BATT, and PGND) MP2624 Rev.1.05 4/9/2018 should be connected to as much copper on the board as possible. This improves thermal performance because the board conducts heat away from the IC. 6) Connect the PCB ground plane directly to the return of all components via holes. Also, it is recommended to place it, via holes, inside the PGND pads for the IC, if possible. Typically, a star ground design approach is used to keep circuit block currents isolated (high-power/lowpower small signals), which reduces noise coupling and ground-bounce issues. A single ground plane for this design gives good results. With this small layout and a single ground plane, there is no ground-bounce issue; segregating the components minimizes coupling between the signals and stability requirements. 4) Pull the connection wire from the MCU (I2C) far away from the SW mode and cooper regions. SCL and SDA should be closely in parallel. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 43 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG TYPICAL APPLICATION CIRCUITS PMID VBUS 1uF C2 PGND DM DP MP2624 RT1 VNTC 10k C4 1uF GND RT2 15k MPS I2C Connector RNTC 10k R6 VREF 1k BATT C7 22uF SYS 1.0uH SW L1 BST AGND Load 22uF 470nF DISC SCL SDA R1 30.9k Battery C8 SW NTC OTG VREF 4.7uF C1 2k STAT ILIM USB/ Adaptor Port IN 4.7uF C3 R5 INT /EN C6 100k R2 VREF 100k R3 100k R4 C5 10uF Figure 24: Typical Application Circuit of MP2624 with 5VIN Table 3. The BOM of the Key Components MP2624 Rev.1.05 4/9/2018 Qty Ref Value Description 1 C1 4.7μF 1 C2 1 Package Manufacture Ceramic Capacitor;10V; X5R or X7R 1206 Any 1μF Ceramic Capacitor;10V; X5R or X7R 0603 Any C3 4.7uF Ceramic Capacitor;10V; X5R or X7R 0805 Any 1 C4 1uF Ceramic Capacitor;6.3V; X5R or X7R 0603 Any 1 C5 10uF Ceramic Capacitor;6.3V; X5R or X7R 0603 Any 1 C6 470nF 0603 Any 2 C7,C8 22uF Ceramic Capacitor;16V; X5R or X7R Ceramic Capacitor;10V; X5R or X7R 1206 Any 1 RT1 10k 0603 Any 1 RT2 15k 0603 Any 1 L1 1.0μH SMD Any Film Resistor;1% Film Resistor;1%; Inductor;1.0uH;Low DCR;ISAT>5A www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 44 MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG PACKAGE INFORMATION QFN-22 (3mm X 4mm) PIN 1 ID MARKING PIN 1 ID 0.20X0.10 PIN 1 ID INDEX AREA TOP VIEW BOTTOM VIEW SIDE VIEW 0.20x0.10 0.10x45 ? NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX. 4) JEDEC REFERENCE IS MO-220. 5) DRAWING IS NOT TO SCALE. RECOMMENDED LAND PATTERN NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP2624 Rev.1.05 4/9/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 45