AD AD8553ARMZ 1.8 v to 5 v auto-zero, in-amp with shutdown Datasheet

1.8 V to 5 V Auto-Zero, In-Amp
with Shutdown
AD8553
Low offset voltage: 20 μV max
Low input offset drift: 0.1 μV/°C max
High CMR: 120 dB min @ G = 100
Low noise: 0.7 μV p-p from 0.01 Hz to 10 Hz
Wide gain range: 0.1 to 10,000
Single-supply operation: 1.8 V to 5.5 V
Rail-to-rail output
Shutdown capability
PIN CONFIGURATION
RGA 1
10
RGB
VINP 2
AD8553
9
VINN
VCC 3
TOP VIEW
(Not to Scale)
8
GND
7
VREF
6
ENABLE
VO 4
VFB 5
05474-001
FEATURES
Figure 1. 10-Lead MSOP
APPLICATIONS
Strain gauge
Weigh scales
Pressure sensors
Laser diode control loops
Portable medical instruments
Thermocouple amplifiers
GENERAL DESCRIPTION
The AD8553 is a precision instrumentation amplifier featuring
low noise, rail-to-rail output and a power-saving shutdown
mode. The AD8553 also features low offset voltage and drift
coupled with high common-mode rejection. In shutdown
mode, the total supply current is reduced to less than 4 μA.
The AD8553 is capable of operating from 1.8 V to 5.5 V.
The small package and low power consumption allow
maximum channel density and minimum board size for
space-critical equipment and portable systems.
The AD8553 is specified over the industrial temperature range
from −40°C to +85°C. The AD8553 is available in a Pb-free,
10-lead MSOP.
With a low offset voltage of 20 μV, an offset voltage drift of
0.1 μV/°C, and a voltage noise of only 0.7 μV p-p (0.01 Hz to
10 Hz), the AD8553 is ideal for applications where error sources
cannot be tolerated. Precision instrumentation, position and
pressure sensors, medical instrumentation, and strain gauge
amplifiers benefit from the low noise, low input bias current,
and high common-mode rejection. The small footprint and low
cost are ideal for high volume applications.
Rev. A
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AD8553
TABLE OF CONTENTS
Features .............................................................................................. 1
Gain Selection (Gain-Setting Resistors).................................. 12
Applications....................................................................................... 1
Reference Connection ............................................................... 12
Pin Configuration............................................................................. 1
Disable Function ........................................................................ 12
General Description ......................................................................... 1
Output Filtering.......................................................................... 12
Revision History ............................................................................... 2
Clock Feedthrough..................................................................... 12
Specifications..................................................................................... 3
Low Impedance Output............................................................. 12
Electrical Characteristics............................................................. 3
Maximizing Performance Through Proper Layout ............... 13
Absolute Maximum Ratings............................................................ 5
Power Supply Bypassing ............................................................ 13
Thermal Resistance ...................................................................... 5
Input Overvoltage Protection ................................................... 13
ESD Caution.................................................................................. 5
Capacitive Load Drive ............................................................... 13
Typical Performance Characteristics ............................................. 6
Circuit Diagrams/Connections ................................................ 14
Theory of Operation ...................................................................... 11
Outline Dimensions ....................................................................... 18
High PSR and CMR ................................................................... 11
Ordering Guide............................................................................... 18
1/f Noise Correction .................................................................. 11
Applications..................................................................................... 12
REVISION HISTORY
8/10—Rev. 0 to Rev. A
Changes to Figure 30...................................................................... 13
10/05—Revision 0: Initial Version
Rev. A | Page 2 of 20
AD8553
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCC = 5.0 V, VCM = 2.5 V, VREF = VCC/2, VIN = VINP − VINN, RLOAD = 10 kΩ, TA = 25°C, G = 100, unless specified. See Table 5 for gain setting
resistor values. Temperature specifications guaranteed by characterization.
Table 1.
Parameter
INPUT CHARACTERISTICS
Input Offset Voltage
Symbol
Conditions
VOS
G = 1000
G = 100
G = 10
G=1
G = 1000, −40°C ≤ TA ≤ +85°C
G = 100, −40°C ≤ TA ≤ +85°C
G = 10, −40°C ≤ TA ≤ +85°C
G = 1, −40°C ≤ TA ≤ +85°C
vs. Temperature
ΔVOS/ΔT
Input Bias Current
IB
Input Offset Current
VREF Pin Current
Input Operating Impedance
Differential
Common Mode
Input Voltage Range
Common-Mode Rejection
IOS
IREF
Min
Typ
Max
Unit
4
4
15
120
0.02
0.02
0.1
1
0.4
20
20
50
375
0.1
0.1
0.3
3
1
2
2
1
μV
μV
μV
μV
μV/°C
μV/°C
μV/°C
μV/°C
nA
nA
nA
nA
−40°C ≤ TA ≤ +85°C
50||1
10||10
CMR
Gain Error
Gain Drift
Nonlinearity
VREF Range
OUTPUT CHARACTERISITICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
POWER SUPPLY
Power Supply Rejection
Supply Current
Supply Current Shutdown Mode
ENABLE INPUTS
Logic High Voltage
Logic Low Voltage
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Internal Clock Frequency
Signal Bandwidth 1
1
0.01
G = 100, VCM = 0 V to 3.3 V, −40°C ≤ TA ≤ +85°C
G = 10, VCM = 0 V to 3.3 V, −40°C ≤ TA ≤ +85°C
G = 100, VCM = 12.125 mV, VO = 0.075 V to 4.925 V
G = 10, VCM = 121.25 mV , VO = 0.075 V to 4.925 V
G = 10, 100, 1000, −40°C ≤ TA ≤ +85°C
G = 1, −40°C ≤ TA ≤ +85°C
G = 100, VCM = 12.125 mV, VO = 0.075 V to 4.925 V
G = 10, VCM = 121.25 mV, VO = 0.075 V to 4.925 V
0
120
100
3.3
140
120
0.10
0.15
5
30
0.001
0.040
0.8
VOH
VOL
ISC
PSR
ISY
0.3
0.4
25
50
0.003
0.060
4.2
4.925
0.075
±35
G = 100, VS = 1.8 V to 5.5 V, VCM = 0 V
G = 10, VS = 1.8 V to 5.5 V, VCM = 0 V
IO = 0 mA, VIN = 0 V
−40°C ≤ TA ≤ +85°C
100
90
ISD
120
110
1.1
2
f = 0.01 Hz to 10 Hz
G = 100, f = 1 kHz
G = 10, f = 1 kHz
G = 1 to 1000
Higher bandwidths result in higher noise.
Rev. A | Page 3 of 20
0.7
30
150
60
1
V
V
mA
1.3
1.5
4
dB
dB
mA
mA
μA
0.80
V
V
2.40
en p-p
en
MΩ||pF
GΩ||pF
V
dB
dB
%
%
ppm/°C
ppm/°C
% FS
% FS
V
μV p-p
nV/√Hz
nV/√Hz
kHz
kHz
AD8553
VS = 1.8 V, VCM = -0 V, VREF = VS/2, VIN = VINP − VINN, RLOAD = 10 kΩ, TA = 25°C, G = 100, unless specified. See Table 5 for gain setting
resistor values. Temperature specifications guaranteed by characterization.
Table 2.
Parameter
INPUT CHARACTERISTICS
Input Offset Voltage
Symbol
Conditions
VOS
G = 1000
G = 100
G = 10
G=1
G = 1000, −40°C ≤ TA ≤ +85°C
G = 100, −40°C ≤ TA ≤ +85°C
G = 10, −40°C ≤ TA ≤ +85°C
G = 1, −40°C ≤ TA ≤ +85°C
Vs. Temperature
ΔVOS/ΔT
Input Bias Current
IB
Input Offset Current
VREF Pin Current
Input Operating Impedance
Differential
Common Mode
Input Voltage Range
Common-Mode Rejection
IOS
IREF
Min
Typ
Max
Unit
3
3
14
130
0.02
0.02
0.1
1
0.05
20
20
50
375
0.25
0.25
3
10
1
2
2
1
μV
μV
μV
μV
μV/°C
μV/°C
μV/°C
μV/°C
nA
nA
nA
nA
−40°C ≤ TA ≤ +85°C
50||1
10||10
CMR
Gain Error
Gain Drift
Nonlinearity
VREF Range
OUTPUT CHARACTERISITICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
POWER SUPPLY
Power Supply Rejection
Supply Current
Supply Current Shutdown Mode
ENABLE INPUTS
Logic High Voltage
Logic Low Voltage
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Internal Clock Frequency
Signal Bandwidth 1
1
0.02
G = 100, VCM = 0 V to 0.15 V, −40°C ≤ TA ≤ +85°C
G = 10, VCM = 0 V to 0.15 V, −40°C ≤ TA ≤ +85°C
G = 100, VCM =4.125 mV, VO = 0.075 V to 1.725 V
G = 10, VCM = 41.25 mV, VO = 0.075 V to 1.725 V
G = 10, 100, 1000, −40°C ≤ TA ≤ +85°C
G = 1, −40°C ≤ TA ≤ +85°C
G = 100, VCM = 4.125 mV, VO = 0.075 V to 1.725 V
G = 10, VCM = 41.25 mV, VO = 0.075 V to 1.725 V
0
100
90
0.15
110
110
0.2
0.2
0.003
0.010
0.8
VOH
VOL
ISC
PSR
ISY
0.4
0.4
25
50
1.0
1.725
0.075
±5
G = 100, VS = 1.8 V to 5.5 V, VCM = 0 V
IO = 0 mA, VIN = 0 V
−40°C ≤ TA ≤ +85°C
100
ISD
120
0.8
2
f = 0.01 Hz to 10 Hz
G = 100, f = 1 kHz
G = 10, f = 1 kHz
G = 1 to 1000
Higher bandwidths result in higher noise.
Rev. A | Page 4 of 20
0.7
30
150
60
1
V
V
mA
1.2
1.4
4
dB
mA
mA
μA
0.5
V
V
1.4
en p-p
en
MΩ||pF
GΩ||pF
V
dB
dB
%
%
ppm/°C
ppm/°C
% FS
% FS
V
μV p-p
nV/√Hz
nV/√Hz
kHz
kHz
AD8553
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
Input Voltage
Differential Input Voltage 1
Output Short-Circuit Duration to GND
Storage Temperature Range (RM Package)
Operating Temperature Range
Junction Temperature Range (RM Package)
Lead Temperature Range (Soldering, 10 sec)
1
Ratings
6V
+VSUPPLY
±VSUPPLY
Indefinite
−65°C to +150°C
−40°C to +85°C
−65°C to +150°C
300°C
Differential input voltage is limited to ±5.0 V, the supply voltage, or
whichever is less.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ JA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4.
Package Type
θJA 1
θJC
Unit
10-Lead MSOP (RM)
110
32.2
°C/W
1
θJA is specified for the nominal conditions, that is, θJA is specified for the
device soldered on a circuit board.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 20
AD8553
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, G = 100, unless specified, see Table 5 for gain setting resistor values. Filters as noted are the combination of R2/C2 and R3/C3
as in Figure 31.
80
VCC = 1.8V AND 5V
FILTER = 1kHz
GAIN = 1000
60
60
GAIN = 100
40
GAIN (dB)
GAIN (dB)
40
GAIN = 10
20
GAIN = 1
20
0
–20
–20
05474-002
0
–40
10
100
1k
10k
VCC = 1.8V AND 5V
FILTER = 10kHz
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
05474-003
80
–40
10
100k
100
180
VCC = 5V
FILTER = 1kHz
140
CMR (dB)
120
GAIN = 1
100
60
60
40
40
10k
10k
100k
GAIN = 10
GAIN = 1
80
1k
GAIN = 100
100
80
05474-004
CMR (dB)
GAIN = 10
100
VCC = 5V
FILTER = 10kHz
05474-005
GAIN = 100
140
20
10
100k
160
160
120
10k
Figure 5. Gain vs. Frequency
Figure 2. Gain vs. Frequency
180
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
20
10
100k
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 6. Common-Mode Rejection (CMR) vs. Frequency
Figure 3. Common-Mode Rejection (CMR) vs. Frequency
10k
160
GAIN = 100
140
1k
NOISE (nV/√Hz)
GAIN = 1
80
60
20
FILTER = 10kHz
FILTER = 1kHz
10
10
GAIN = 10
100
GAIN = 100, 1000
10
40
100
VCC = 5V AND 1.8V
1k
10k
05474-006
PSR (dB)
100
1
0.01
100k
05474-007
120
GAIN = 1
GAIN = 10
0.1
1
10
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 7. Voltage Noise Density
Figure 4. Power Supply Rejection vs. Frequency
Rev. A | Page 6 of 20
10k
100k
AD8553
80
GAIN = 100
FILTER = 1kHz
VCC = 5V
05474-008
VCC = 1.8V
TURN ON TIME = 15µs
VCC = 1.8V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
60
50
40
30
FILTER SETTLING
20
VCC = 5V
10
0
VCC = 1.8V
–10
05474-009
FILTER SETTLING
–0.1
GAIN = 100
FILTER = 10kHz
70
INPUT OFFSET VOLTAGE (µV)
20µV/DIV
VCC = 5V
TURN ON TIME = 10µs
–20
0.9
0
50
100
TIME (ms)
150
200
250
300
350
TIME (µs)
Figure 11. Input Offset Voltage vs. Turn-On Time
Figure 8. Input Offset Voltage vs. Turn-On Time
VCC = 5V, G = 1, 10, 100, 1000
VCC = 5V, G = 1, 10, 100, 1000
VCC = 1.8V, G = 1, 10, 100, 1000
1V/DIV
10kHz FILTER
1kHz FILTER
1kHz FILTER
05474-011
05474-010
50mV/DIV
10kHz FILTER
500µs/DIV
500µs/DIV
Figure 9. Small Signal Step Response
Figure 12. Large Signal Step Response
VCC = 5V
GAIN = 100, 1000
0
2
4
6
8
10
12
14
16
18
05474-014
05474-017
POPULATION
POPULATION
VCC = 5V
GAIN = 100, 1000
20
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
Figure 13. Input Offset Voltage Drift (μV/°C)
Figure 10. Input Offset Voltage (μV)
Rev. A | Page 7 of 20
0.09
0.10
AD8553
VCC = 5V
GAIN = 10
0
5.0
05474-013
05474-016
POPULATION
POPULATION
VCC = 5V
GAIN = 10
0
10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 50.0
0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 0.30
Figure 17. Input Offset Voltage Drift (μV/°C)
Figure 14. Input Offset Voltage (μV)
VCC = 5V
GAIN = 1
05474-012
05474-015
POPULATION
POPULATION
VCC = 5V
GAIN = 1
–50
–10
30
70
110
150
190
230
270
310
0
350
0.30 0.60 0.90 1.20 1.50 1.80 2.10 2.40 2.70 3.00
Figure 18. Input Offset Voltage Drift (μV/°C)
Figure 15. Input Offset Voltage (μV)
VCC = 5V
GAIN = 100
VCM = 12.125mV
–250 –225 –200 –175 –150 –125 –100 –75
–50
–25
05474-019
05474-020
POPULATION
POPULATION
VCC = 5V
GAIN = 100
VCM = 12.125mV
0
0
Figure 16. Gain Error (m%)
0.3
0.6
0.9
1.2
1.5
1.8
2.1
Figure 19. Nonlinearity (m%)
Rev. A | Page 8 of 20
2.4
2.7
3.0
AD8553
180
VCC = 1.8V
FILTER = 1kHz
160
160
GAIN = 100
GAIN = 100
140
140
GAIN = 10
GAIN = 10
120
CMR (dB)
120
GAIN = 1
100
GAIN = 1
100
80
80
60
60
40
40
05474-021
CMR (dB)
VCC = 1.8V
FILTER = 10kHz
20
10
100
1k
10k
20
10
100k
FREQUENCY (Hz)
05474-022
180
100
1k
10k
100k
FREQUENCY (Hz)
Figure 23. Common-Mode Rejection (CMR) vs. Frequency
Figure 20. Common-Mode Rejection (CMR) vs. Frequency
VCC = 1.8V
GAIN = 100, 1000
–2
0
2
4
6
8
10
12
14
16
18
05474-028
05474-025
POPULATION
POPULATION
VCC = 1.8V
GAIN = 100, 1000
20
0
Figure 21. Input Offset Voltage (μV)
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
Figure 24. Input Offset Voltage Drift (μV/°C)
VCC = 1.8V
GAIN = 10
05474-027
05474-024
POPULATION
POPULATION
VCC = 1.8V
GAIN = 10
0
0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60
Figure 22. Input Offset Voltage (μV)
0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 0.30
Figure 25. Input Offset Voltage Drift (μV/°C)
Rev. A | Page 9 of 20
AD8553
VCC = 1.8V
GAIN = 1
05474-033
05474-023
POPULATION
POPULATION
VCC = 1.8V
GAIN = 1
0
40
80
120
160
200
240
280
320
360
0
Figure 26. Input Offset Voltage (μV)
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8
Figure 28. Input Offset Voltage Drift (μV/°C)
VCC = 5.0V
GAIN = 100
VCC = 1.8V,
G = 10, 100, 1000
1kHz FILTER
05474-036
05474-029
200nV/DIV
500mV/DIV
10kHz FILTER
10SEC/DIV
500µs/DIV
Figure 27. 0.01 Hz to 10 Hz Voltage Noise
Figure 29. Large Signal Step Response
Rev. A | Page 10 of 20
AD8553
THEORY OF OPERATION
The AD8553 is a precision current-mode correction
instrumentation amplifier capable of single-supply operation.
The current-mode correction topology results in excellent
accuracy without the need for trimmed resistors on the die.
Figure 30 shows a simplified diagram illustrating the basic
operation of the AD8553 (without correction). The circuit
consists of a voltage-to-current amplifier (M1 to M6), followed
by a current-to-voltage amplifier (R2 and A1). Application of a
differential input voltage forces a current through External
Resistor R1, resulting in conversion of the input voltage to a
signal current. Transistor M3 to Transistor M6 transfer twice
this signal current to the inverting input of the op amp A1.
Amplifier A1 and External Resistor R2 form a current-tovoltage converter to produce a rail-to-rail output voltage at
VOUT.
Op amp A1 is a high precision auto-zero amplifier. This
amplifier preserves the performance of the autocorrecting,
current-mode amplifier topology while offering the user a true
voltage-in, voltage-out instrumentation amplifier. Offset errors
are corrected internally.
An external reference voltage is applied to the noninverting
input of A1 to set the output reference level. External Capacitor
C2 is used to filter out correction noise.
The pinout of the AD8553 allows the user to access the signal
current from the output of the voltage-to-current converter
(Pin 5). The user can choose to use the AD8553 as a currentoutput device instead of a voltage-output device. See Figure 35
for circuit connections.
HIGH PSR AND CMR
Common-mode rejection and power supply rejection indicate
the amount that the offset voltage of an amplifier changes when
its common-mode input voltage or power supply voltage changes.
The autocorrection architecture of the AD8553 continuously
corrects for offset errors, including those induced by changes in
input or supply voltage, resulting in exceptional rejection
performance. The continuous autocorrection provides great
CMR and PSR performances over the entire operating
temperature range (−40°C to +85°C).
The parasitic resistance in series with R2 does not degrade
CMR but causes a small gain error and a very small offset error.
Therefore, an external buffer amplifier is not required to drive
the VREF pin to maintain excellent CMR performance. This
helps reduce system costs over conventional instrumentation
amplifiers.
1/f NOISE CORRECTION
Flicker noise, also known as 1/f noise, is noise inherent in the
physics of semiconductor devices and decreases 10 dB per
decade. The 1/f corner frequency of an amplifier is the frequency
at which the flicker noise is equal to the broadband noise of the
amplifier. At lower frequencies, flicker noise dominates causing
large errors in low frequency or dc applications.
Flicker noise is seen effectively as a slowly varying offset error,
which is reduced by the autocorrection topology of the AD8553.
This allows the AD8553 to have lower noise near dc than
standard low noise instrumentation amplifiers.
Rev. A | Page 11 of 20
AD8553
APPLICATIONS
GAIN SELECTION (GAIN-SETTING RESISTORS)
DISABLE FUNCTION
The gain of the AD8553 is set according to
The AD8553 provides a shutdown function to conserve power
when the device is not needed. Although there is a 1 μA pull-up
current on the ENABLE pin, Pin 6 should be connected to the
positive supply for normal operation and to the negative supply
to turn the device off. It is not recommended to leave Pin 6
floating.
G = 2 × (R2/R1)
(1)
Table 5 lists the recommended resistor values. Resistor R1 must
be at least 3.92 kΩ for proper operation. Use of resistors larger
than the recommended values results in higher offset and
higher noise.
Gain accuracy depends on the matching of R1 and R2. Any
mismatch in resistor values results in a gain error. Resistor
value errors due to drift affect gain by the amount indicated by
Equation 1. However, due to the current-mode operation of the
AD8553, a mismatch in R1 and R2 does not degrade the CMR.
Care should be taken when selecting and positioning the gain
setting resistors. The resistors should be made of the same
material and package style. Surface-mount resistors are
recommended. They should be positioned as close together
as possible to minimize TC errors.
To maintain good CMR vs. frequency, the parasitic capacitance
on the R1 gain setting pins should be minimized and matched.
This also helps maintain a low gain error at G < 10.
If resistor trimming is required to set a precise gain, trim
Resistor R2 only. Using a potentiometer for R1 degrades the
amplifier’s performance.
REFERENCE CONNECTION
Unlike traditional three op amp instrumentation amplifiers,
parasitic resistance in series with VREF (Pin 7) does not degrade
CMR performance. This allows the AD8553 to attain its extremely
high CMR performance without the use of an external buffer
amplifier to drive the VREF pin, which is required by industrystandard instrumentation amplifiers. This helps save valuable
printed circuit board space and minimizes system costs.
For optimal performance in single-supply applications, VREF
should be set with a low noise precision voltage reference.
However, for a lower system cost, the reference voltage can be
set with a simple resistor voltage divider between the supply and
ground (see Figure 31). This configuration results in degraded
output offset performance if the resistors deviate from their
ideal values. In dual-supply applications, VREF can simply be
connected to ground.
The VREF pin current is approximately 20 pA, and as a result, an
external buffer is not required.
Turn-on time upon switching Pin 6 high is dominated by the
output filters. When the device is disabled, the output becomes
high impedance enabling muxing application of multiple
AD8553 instrumentation amplifiers.
OUTPUT FILTERING
Filter Capacitor C2 is required to limit the amount of switching
noise present at the output. The recommended bandwidth of
the filter created by C2 and R2 is 1.4 kHz. The user should first
select R1 and R2 based on the desired gain, then select C2 based on
C2 = 1/(1400 × 2 × π × R2)
(2)
Addition of another single-pole RC filter of 1.4 kHz on the
output (R3 and C3 in Figure 31 to Figure 33) is required for
bandwidths greater than 10 Hz. These two filters produce an
overall bandwidth of 1 kHz.
When driving an ADC, the recommended values for the second
filter are R3 = 100 Ω and C3 = 1 μF. This filter is required to
achieve the specified performance. It also acts as an antialiasing
filter for the ADC. If a sampling ADC is not being driven, the
value of the capacitor can be reduced, but the filter frequency
should remain unchanged.
For applications with low bandwidths (<10 Hz), only the first
filter is required. In this case, the high frequency noise from the
auto-zero amplifier (output amplifier) is not filtered before the
following stage.
CLOCK FEEDTHROUGH
The AD8553 uses two synchronized clocks to perform the
autocorrection. The input voltage-to-current amplifiers are
corrected at 60 kHz.
Trace amounts of these clock frequencies can be observed at the
output. The amount of feedthrough is dependent upon the gain,
because the autocorrection noise has an input and output
referred term. The correction feedthrough is also dependent
upon the values of the external filters R2/C2, and R3/C3.
LOW IMPEDANCE OUTPUT
For applications where a low output impedance is required, the
circuit in Figure 33 should be used. This provides the same
filtering performance as shown in the configuration in Figure 34.
Rev. A | Page 12 of 20
AD8553
MAXIMIZING PERFORMANCE THROUGH PROPER
LAYOUT
For single-supply operation, a 0.1 μF surface-mount capacitor
should be connected from the supply line to ground.
To achieve the maximum performance of the AD8553, care
should be taken in the circuit board layout. The PC board
surface must remain clean and free of moisture to avoid leakage
currents between adjacent traces. Surface coating of the circuit
board reduces surface moisture and provides a humidity barrier,
reducing parasitic resistance on the board.
All bypass capacitors should be positioned as close to the DUT
supply pins as possible, especially the bypass capacitor between
the supplies. Placement of the bypass capacitor on the back of
the board directly under the DUT is preferred.
INPUT OVERVOLTAGE PROTECTION
All terminals of the AD8553 are protected against ESD. In the
case of a dc overload voltage beyond either supply, a large
current would flow directly through the ESD protection diodes.
If such a condition should occur, an external resistor should be
used in series with the inputs to limit current for voltages
beyond the supply rails. The AD8553 can safely handle 5 mA of
continuous current, resulting in an external resistor selection of
REXT = (VIN − VS)/5 mA.
Care must be taken to minimize parasitic capacitance on Pin 1
and Pin 10 (Resistor R1 connections). Traces from Pin 1 and
Pin 10 to R1 should be kept short and symmetric. Excessive
capacitance on these pins will result in a gain error. This effect
is most prominent at low gains (G < 10).
For high impedance sources, the PC board traces from the
AD8553 inputs should be kept to a minimum to reduce input
bias current errors.
CAPACITIVE LOAD DRIVE
POWER SUPPLY BYPASSING
The output buffer, Pin 4, can drive capacitive loads up to 100 pF.
The AD8553 uses internally generated clock signals to perform
the autocorrection. As a result, proper bypassing is necessary to
achieve optimum performance. Inadequate or improper bypassing
of the supply lines can lead to excessive noise and offset voltage.
A 0.1 μF surface-mount capacitor should be connected between
the supply lines. This capacitor is necessary to minimize ripple
from the correction clocks inside the IC. For dual-supply
operation (see Figure 33), a 0.1 μF (ceramic) surface-mount
capacitor should be connected from each supply pin to ground.
VCC
C2
I
I
M5
M6
R1
I – IR1
IR1 =
R1
2I
VOUT = VREF +
I + IR1
(VINP – VINN )
M1
2IR1
M2
M4
R1
VINP – VINN
A1
VBIAS
VINN M3
2R2
VREF
2I
05474-030
VINP
R2
I – IR1
EXTERNAL
Figure 30. Simplified AD8553 Schematic
Rev. A | Page 13 of 20
AD8553
CIRCUIT DIAGRAMS/CONNECTIONS
VS+
0.1µF
GND
2
VIN+
3
+
6
1
R1
4
AD8553
10
VIN–
9
R3
100Ω
5
–
7
8
VOUT
C3
1µF
R2
GND
C2
R3 AND C3 VALUES ARE
RECOMMENDED TO DRIVE
AN A/D CONVERTER
GND
100kΩ
05474-032
0.1µF
VS+ 100kΩ
GND
Figure 31. Single-Supply Connection Diagram Using Voltage Divider Reference
VS+
0.1µF
0.1µF
2
VIN+
+
3
6
1
R1
AD8553
10
VIN–
4
9
R3
100Ω
5
–
7
8
GND
R2
C2
0.1µF
VOUT
C3
1µF
R3 AND C3 VALUES ARE
RECOMMENDED TO DRIVE
AN A/D CONVERTER
VS–
GND
Figure 32. Dual-Supply Connection Diagram
Rev. A | Page 14 of 20
05474-031
GND
VS–
AD8553
VS+
0.1µF
0.1µF
VS–
2
VIN+
3
+
6
1
R1
4
AD8553
10
VIN–
9
5
R2
8
GND
0.1µF
VOUT
C3
1µF
C2
7
–
R3
100Ω
GND
R3 AND C3 VALUES ARE
RECOMMENDED TO DRIVE
AN A/D CONVERTER
VS–
GND
05474-034
GND
Figure 33. Dual-Supply Connection Diagram with Low Impedance Output
VS+
0.1µF
GND
2
VIN+
3
+
6
1
R1
4
AD8553
10
VIN–
9
8
VOUT
C3
1µF
5
7
–
R3
100Ω
R2
C2
GND
R3 AND C3 VALUES ARE
RECOMMENDED TO DRIVE
AN A/D CONVERTER
VS–
1.0µF
VCC
0.1µF
VOUT
GND
Figure 34. Dual-Supply Connection Diagram Using IC Voltage Reference
Rev. A | Page 15 of 20
05474-035
VIN
AD8553
VS+
6
3
+
7
4
NC (NO CONNECT)
AD8553
R1
V
IO = IN
R1
5
10kΩ
10
9 _
A
8
0.1µF
VS–
05474-037
2
1
VIN
AMMETER
Figure 35. Voltage-to-Current Converter, 0 μA to 30 μA Source
VS+
2
+
1
6
3
VREF = 2.5V
7
100Ω
4
R1
AD8553
C2
A/D
A/D
CONVERTER
1µF
R2
8
Figure 36. Example of an AD8553 Driving a Converter at VS+ = 5 V
Rev. A | Page 16 of 20
05474-038
5
10
9 _
AD8553
VS+
LOGIC
2
+
1
6
3
VREF
7
R3
4
AD8553
R1
C2
100Ω
5
10
9 _
8
R2
VS–
VS+
2
+
1
6
3
VREF
7
R8
4
AD8553
R6
C3
100Ω
VOUT
1µF
5
10
9 _
8
R7
VS+
6
3
VREF
7
R13
4
R11
AD8553
C4
5
10
9 _
8
R12
100Ω
05474-039
2
+
1
Figure 37. Multiplexed Output
Table 5. Recommended External Component Values for Selected Gains
Desired Gain (V/V)
1
2
5
10
50
100
500
1000
R1 (Ω)
200 k
100 k
40.2 k
20 k
4.02 k
3.92 k
3.92 k
3.92 k
R2 || C2 (Ω || F)
100 k || 1200p
100 k || 1200p
100 k || 1200p
100 k || 1200p
100 k || 1200p
196 k || 560p
976 k || 120p
1.96 M || 56p
Rev. A | Page 17 of 20
Calculated Gain
1
2
4.975
10
49.75
100
497.95
1000
AD8553
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
1
5.15
4.90
4.65
6
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.30
0.15
6°
0°
0.23
0.13
COMPLIANT TO JEDEC STANDARDS MO-187-BA
0.70
0.55
0.40
091709-A
0.15
0.05
COPLANARITY
0.10
Figure 38. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD8553ARMZ
AD8553ARMZ-REEL
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
10-Lead MSOP
10-Lead MSOP
Z = RoHS Compliant Part.
Rev. A | Page 18 of 20
Package Option
RM-10
RM-10
Branding
A09
A09
AD8553
NOTES
Rev. A | Page 19 of 20
AD8553
NOTES
©2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05474-0-8/10(A)
Rev. A | Page 20 of 20