Rohm BD9300FV Single-output step-up, negative voltage, step-down switching regulators (controller type) Datasheet

TECHNICAL NOTE
Large Current External FET Controller Type Switching Regulators
Single-output Step-up, Negative Voltage,
Step-down Switching Regulators (Controller type)
BD9300F/BD9300FV
Description
The BD9300F/FV 1-channel DC/DC Step-up, step-down, and inverting converter controller.
This IC has a wide input voltage range of 3.6 to 35 V, providing for a variety of applications. The pin assignment is similar to
that of the BA9700, facilitating a space-saving application.
Features
1) 1-channel PWM control DC/DC converter controller
2) High voltage input of 3.6 to 35 V
3) Reference voltage accuracy of ±1%
4) Oscillation frequency variable in the range of 20 to 800 kHz
5) Built-in UVLO (Under Voltage Lock Out) circuit and SCP (Short Circuit Prevention) circuit
6) Current in standby mode: 0 μA (typ.)
7) Switching external synchronization available (Slave operation)
8) SSOP-B14 Package (for BD9300FV) or SOP14 Package (for BD9300F)
Applications
. TV, power supply for liquid crystal display TV, and backlight
. DSC, DVD, printer, DVD/DVD recorder, and other consumer products
Input
Input
Input
Step-up
voltage
output
Step-up voltage application
Inverting
voltage
output
Inverting voltage application
Step-down
voltage
output
Step-down voltage application
Sep. 2008
Absolute maximum ratings(Ta=25˚C)
Item
Symbol
Rating
Unit
Power supply voltage
Vcc
36
Power dissipation
Pd
400
Operating temperature
Topr
–40 to +85
Storage temperature
Tstg
–55 to +125
Output current
Io
Output voltage
Maximum junction temperature
V
*
mW
˚C
˚C
**
100
mA
Vo
36
V
Tjmax
125
˚C
* Reduce by 4 mW/ ˚C over 25˚C, when mounted on a glass epoxy PCB of 70mmX70mmX1.6mm)
** Should not exceed Pd-value.
Recommended operating range (Ta=25˚C)
Min
Limits
Typ
Max
Vcc
3.6
12
35
V
IO
–
–
30
mA
Item
Symbol
Power supply voltage
Output sink current
Unit
Output voltage
VO
–
–
35
V
Timing capacitance
CT
33
–
1000
pF
Timing resistance
RT
5
–
100
kΩ
Fosc
20
–
800
kHz
Oscillation frequency
Electrical characteristics (Unless otherwise specified, Ta=25˚C, VCC=12V, CT=200pF, RT=20kΩ)
Item
Symbol
Min
Limits
Typ
Max
Unit
Conditions
[Reference voltage block]
Reference voltage
VREF
Input stability
VDLI
–
Load stability
VDLD
2.525
V
1.5
20
mV
Vcc=3.6 to 35V
IREF=1mA
–
0.5
20
mV
IREF=0 ~ 1mA
1/2VREF
1.212
1.25
1.288
V
Oscillation frequency
FOSC
165
220
275
kHz
Charge mode threshold voltage
VOSC+
–
1.95
–
V
Discharge mode threshold voltage
VOSC–
–
1.45
–
V
Frequency variation
FDVO
–
1
–
%
Threshold voltage
VIT
1.5
1.8
2.1
V
Charge current
Iscp
–
7
11
μA
Upper limit threshold voltage
VtH
2.05
–
–
V
Duty Cycle=0%
Lower limit threshold voltage
VtL
–
–
1.35
V
Duty Cycle=100%
Input bias current
Ibd
–
0.1
1
μA
DTC=1.5V
Latch mode charge current
Idtc
200
500
–
μA
DTC=0V
VUT
–
2.8
–
V
1/2 reference voltage
2.475 2.500
IREF=1mA
[Triangular wave oscillator block]
Vcc=3.6 to 35V
[Protection circuit block]
[Rest period adjustment circuit block]
[Under voltage lock out block]
Threshold voltage
Not designed to be radiation-resistant.
2/16
Electrical characteristics (Unless otherwise specified, Ta=25˚C, Vcc=12 V, CT=200pF, RT=20 kΩ)
Item
Symbol
Min
Limits
Typ
Max
Unit
Conditions
[Error amplifier block]
Input bias current
IIB
–
0.1
1
μA
Open loop gain
AV
–
85
–
dB
Maximum output voltage
VOH
2.3
2.5
–
V
Minimum output voltage
VOL
–
0.7
0.9
V
Output sink current
IOI
0.1
1
–
mA
VFB=1.25V
Output source current
IOO
40
70
–
μA
VFB=1.25V
Saturation voltage
VSAT
–
1.0
1.4
V
Io=30mA
Leak current
ILEAK
–
–
10
μA
OUT=35V
CTL ON voltage
VON
2
–
–
V
CTL OFF voltage
VOFF
–
–
0.7
V
CTL sink current
ICTL
–
57
90
μA
VCTL=5V
Standby current
ISTB
–
0
10
μA
VCTL=0V
Average supply current
ICC
–
1.2
2.4
mA
RT=VREF
Null AMP
[Output block]
[Control block]
[Whole device]
Not designed to be radiation-resistant.
Measurement circuit diagram
VCC
1kΩ
FM
A
VCC
V
V
SCP
V IREF
OUT
A
+
A
-
Null
CTL
V
200pF
VREF
1kΩ
1kΩ
A
V
FB
NON
A
A
20kΩ
DTC
V
100kΩ
100kΩ
470pF
Fig. 1 Typical measurement circuit
3/16
Reference characteristics data (Unless otherwise specified, Ta=25˚C)
REFERENCE VOLTAGE VREF [V]
2.55
2.54
2.53
2.52
2.51
2.50
2.49
2.48
2.47
2.46
2.45
-40
-20
0
20
40
60
218
0.10
216
0.09
STAND-BY CURRENT Istby [μA]
SWITCHING FREQUENCY FSW [KHz]
2.56
214
212
210
208
206
204
202
-20
0
20
40
60
0.06
0.05
0.04
0.03
0.02
0.00
80
AMBIENT TEMPERATURE Ta [˚C ]
AMBIENT TEMPERATURE Ta [˚C ]
Fig.2 Reference voltage vs.
Ambient temperature
Fig.3 Switching frequency vs.
Ambient temperature
1.75
85˚C
25˚C
1.50
-40˚C
1.25
85˚C
1.00
0.75
0.50
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
85˚C
0.50
25˚C
-40˚C
0.25
0.25
0.00
0.00
0
4
8
12
16
20
24
28
INPUT VOLTAGE Vcc [V]
32
36
0
Fig.5 Circuit current
OUTPUT VOLTAGE VOUT [V]
25˚C
2.50
85˚C
2.25
2.00
1.75
-40˚C
1.50
1.25
1.00
0.75
0.50
0.25
0.00
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
4.00
3.75
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
8
12
16
20
24
28
32
INPUT VOLTAGE Vcc [V]
36
-40˚C
25˚C
85˚C
0
10
0
4
8
12
16
20
24
28
INPUT VOLTAGE Vcc [V]
32
36
2.25
85˚C
2.00
25˚C
1.75
1.50
-40˚C
1.25
1.00
0.75
0.50
0.25
Fig.6 Reference voltage
3.00
2.75
4
-40˚C
2.50
20
30
40
50
60
70
80
90 100
CONTROL VOLTAGE CTL [V]
OUTPUT CURRENT OUT [mA]
Fig.8 Control threshold voltage
Fig.9 Output current capacitance
4/16
0.00
0
2
4
6
8
10
12
14
REFERENCE CURRENT IREF [mA]
Fig.7 Reference voltage vs. Output current
CONTROL CURRENT ICTL [μA]
-40˚C
2.00
REFERENCE VOLTAGE VREF [V]
2.75
REFERENCE VOLTAGE VREF [V]
3.00
2.75
CIRCUIT CURRENT Icc [mA]
3.00
2.75
2.25 25˚C
85˚C 25˚C
Fig.4 Standby current
3.00
2.50
REFERENCE VOLTAGE VREF [V]
0.07
0.01
200
-40
80
0.08
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
85˚C
25˚C
-40˚C
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2 3.5
CONTROL VOLTAGE VCTL [V]
Fig.10 Control sink current
NON
1/2VREF
INV
VREF
CTL
SCP
Vcc
14
13
12
11
10
9
8
Vcc
CTL
SCP
Block diagram
VREF
INV
1/2VREF
NON
Pin assignment
2.5V
VREF
–
ERR
1.25V
+
N.C.
–
– PWM
+
GND
OUT
FB
CT
RT
DTC
TIMER
LATCH
OSC
1
2
3
4
5
6
7
DTC
RT
CT
FB
OUT
N.C.
GND
Fig. 11 Pin assignment / Block diagram
Pin assignment and function
Pin No.
Pin name
Function
1
DTC
2
RT
External timing resistance
3
CT
External timing capacitance
4
FB
Error amplifier output
5
OUT
PWM output (open collector)
6
N.C.
–
7
GND
Ground
8
Vcc
Power supply
9
SCP
External timer latch setting capacitance (Ground if not used)
10
CTL
Control input
11
VREF
12
INV
13
1/2VREF
14
NON
Rest period setting voltage input
Reference voltage output
Inverting input for error amplifier
1/2 reference voltage output
Non-inverting input for error amplifier
5/16
Description of operations
30kΩ
VCC
100μF
500Ω
33μH
100pF
0.1μF
33kΩ
1/2
VREF INV
NON
20kΩ
14
13
12
VREF
CTL
10
11
SCP
Vcc
9
500Ω
8
100μF
Vo
90kΩ
0.1μF
51kΩ
VREF
100pF
–
+
30kΩ
2.5V
ERR
1.25V
TIMER
LATCH
1000pF
–
– PWM
+
OSC
1
DTC
20kΩ
2
RT
3
4
CT
FB
220pF
5
OUT
6
N.C.
7
GND
Fig. 12 Typical application circuit
VREF block
The VREF block is a block to output a reference voltage of 2.5 V (TYP), which is used as the operating power supply for all the
Internal. The CTL pin is used to turn ON/OFF the reference voltage. Furthermore, this reference voltage has a current
capacitance of 1 mA (MIN) or more, from which a high-accuracy reference voltage can be generated through dividing
resistance.
ERRAMP block
The ERRAMP block is an error amplifier to amplify potential between the NON and the INV pins and then output a voltage.
The FB pin output voltage determines the output pulse Duty. When the FB voltage reaches 1.95 V (TYP) or more, switching
will be OFF (Duty=0%). When the FB voltage reaches 1.45 V (TYP) or less, the output NPN Tr will be FULL ON (Duty=100%).
OSC block
The OSC block is a block to determine the switching frequency through the RT and the CT pins. RT and CT voltages determine
the triangular waveform.
TIMER LATCH block
The TIMER LATCH block is an output short circuit protection circuit to detect output short circuit when the output voltage from
the FB pin of the error amplifier reaches 1 V (TYP) or less. When the FB voltage reaches 1 V (TYP) or less, the TIMER will
starts operating to charge the SCP pin at a current capacitance of 7 μA (TYP). When the SCP voltage reaches 1.8 V (TYP),
the LATCH will be activated to shut down the circuit.
PWM/Driver block
The PWM/Driver block is a PWM comparator to determine Duty value differences between output from the error amplifier
and the oscillator triangular wave. The DTC voltage determines the maximum duty ratio. When the DTC voltage reaches
1.95 V (TYP), the switching OFF is activated. FULL ON will be activated when the DTC voltage reaches 1.45 V (TYP).
The DTC voltage setting should be made through dividing resistance with the VREF block.
6/16
Timing chart
. Basic operation
OSC
[V]
2
1
DT
FB
0
VCC
[V]
5
0
VREF
[V] 2.5
0
5
0
OUT 5
[V]
0
NON 2.5
[V]
0
CTL
[V]
Fig. 13 Basic operation
. When the short circuit protection is activated
5
VO
[V]
0
2.5
NON 1.25
[V]
0
FB
[V]
2.5
FB
DTC
1.5
DTC
[V]
0
1.8
SCP
[V]
0
Fig. 14 Timing when the short circuit protection is activated
7/16
External component setting procedure
(1) Design of feedback resistance constant
Set step-down, step-up, and inverting feedback resistance as shown below. Set resistance in the range of 1 kΩ to
330 kΩ. Setting the resistance to 1 kΩ or less will result in degraded power efficiency, while setting it to 330 kΩ or
more will increase the offset voltage due to the input bias current of 0.1μA (TYP) of the error amplifier.
. Step-down voltage
.
. Step-up voltage
Vo
Vo
Reference voltage: 1.25 V
Inverting voltage
Vo (Negative)
Reference voltage: 1.25 V
R8
Reference voltage: 1.25 V
R8
12
R8
12
–
–
ERR
14
12
+
14
–
ERR
+
14
R9
ERR
+
R9
R9
11 VREF
Fig. 15 Step-down voltage
Fig.16 Step-up voltage
R8+R9
Vo =
X 1.25 [V]
R9
R8+R9
Vo =
X 1.25 [V]
R9
Fig. 17 Inverting voltage
R8
Vo = 1.25 ( 1–
[V ]
R9 )
(2) Setting of oscillation frequency
Connecting a resistor and capacitor to the RT pin (pin 2) and the CT pin (pin 3) will set the triangular wave oscillation
frequency. The RT determines the charge/discharge current to the capacitor. Referring to Fig. 18, set RT resistor and
the CT capacitor. Recommended setting ranges are 5 to 100 kΩ for the CT resistor, 33 to 1000 pF for the CT capacitor,
and 20 kHz to 800 kHz for the oscillation frequency. Any setting outside of these ranges may turn OFF switching,
thus impairing the operation guarantee.
10000
Ta=25˚C
Vcc=12V
FREQ [kHz]
1000
100
CT=33pF
CT=100pF
CT=200pF
CT=470pF
CT=1000pF
10
1
2
10
100
200
RT [kΩ]
Fig. 18 RT/CT vs. Frequency
(3) Setting of DTC voltage
Applying the VDTC voltage to the DTC pin (pin 1) will fix the maximum duty ratio.This will serve to prevent the power
transistor (FET) from being FULL ON. Fig. 19 shows the relationship between the DTC voltage and the maximum duty
ratio. Referring to this Figure, set the DTC voltage.Next, generate the VDTC by dividing the VREF voltage with resistance
and then input the VDTC in the DTC pin.
120
Ta=25˚C
Vcc=12V
Fosc=220kHz
ON DUTY [%]
100
80
60
40
20
0
-20
1.4
1.5
1.6
1.7
1.8
VDTC [V]
1.9
2
Fig. 19 DTC voltage vs. Maximum duty
Furthermore, the maximum duty ratio should be designed so as not to become a maximum duty for the normal use. The
following section shows ranges for the normal use.
. Step-down voltage
ONDutyMAX =
VOMAX
VCCMIN
. Step-up voltage
ONDutyMAX =
VOMAX – VOMIN
8/16
VOMAX
. nverting voltage
ONDutyMAX =
VOMAX
VOMAX – VCCMIN
(4) Setting of soft start time
Adding a capacitor to the DTC resistance divider will enable the soft start function activation.
The soft start function will be required to prevent an excessive increase in the coil current and overshoot of the output voltage,
while in startup operation. Fig. 20 shows the relationship between the capacitor and the soft start time. Referring to this Figure,
set the capacitor. It is recommended to set the capacitance value in the range of 0.01 to 10 μF. Setting the capacitance value to
0.01 μF or less, may cause overshoot to the output voltage, while setting it to 10 μF or more may cause an inverse current
in the internal parasitic diode when the power supply is grounded, thus resulting in damage to the internal element.
the internal element.
tsoft [Msec]
1.00E+02
Ta=25˚C
Vcc=12V
Vo=5V
Fosc=220kHz
L=33 μH
1.00E+01 COUT=100μF
R1=20k
R2=33k
1.00E+00
1.00E–01
1.00E–09
1.00E–08
1.00E–07
CDTC [F]
1.00E–06
1.00E–05
Fig. 20 Soft start capacitance vs. Delay time
Vcc
C5
Q1
R6
Q2
D1
L
R7
C6
D2
C7
OUT
Fig. 21 ON/OFF peak circuit
Since the PNP Tr is generally slow in switching, in terms of the sat characteristics , the ON/OFF peak circuit is used as
an acceleration circuit. The D1 and the C7 generate an ON peak current, while the Q1 and the C7 forms an OFF peak
circuit.Set pull-up resistance to 510 Ω as a guide at VCC=12 V. It is recommended to set this resistance in the range of
100 kΩ to 10 kΩ. In order to make adjustment of the R6 and R7, however, pay attention of the points listed in table below.
NO.
1
2
3
4
Item
Efficiency
Tr Turn ON / Turn OFF
Switching frequency
Load current capacitance
To reduce R6
Degraded
Faster Turn OFF
Increasable
Degraded
To reduce R7
Degraded
Faster Turn OFF
Increasable
Degraded
Take 1000 pF as a guide for the C7 setting. If the ON/OFF peak currents are inadequate, increase the C7 capacitance
value. It is recommended to set capacitance values in the range of 100 pF to 10000 pF. Setting the capacitance value
to 10000 pF or more may increase the peak current and degrade the power efficiency.
9/16
(6) Phase compensation
Phase compensation setting procedure
The phase compensation setting procedure varies with the selection of output capacitors used for DC/DC converter
application. In this connection, the following section describes the procedure by classifying into the two types.
Furthermore, the application stability conditions are described in the Description section.
1. Application stability conditions
2. For output capacitors having high ESR, such as electrolytic capacitor
3. For output capacitors having low ESR, such as ceramic capacitor or OS-CON
1. Application stability conditions
The following section shows the stability conditions of negative feedback system.
. DSC, DVD, printer, DVD/DVD recorder, and other consumer productsAt a 1 (0-dB) gain,
the phase delay is 150˚ or less (i.e., the phase margin is 30˚ or more).
Furthermore, since the DC/DC converter application is sampled according to the switching frequency, GBW of the overall
system should be set to 1/10 or less of the switching frequency. The following section summarizes the targeted
characteristics of this application.
. DSC, DVD, printer, DVD/DVD recorder, and other consumer productsAt a 1 (0-dB) gain, the phase delay is 150˚ or
less (i.e., the phase margin is 30˚ or more).
. DSC, DVD, printer, DVD/DVD recorder, and other consumer productsThe GBW (i.e., frequency at 0-dB gain) for this
occasion is 1/10 or less of the switching frequency.
In other words, the responsiveness is determined with restrictions on the GBW. Consequently, in order to upgrade
the responsiveness, higher switching frequency should be provided.
In order to ensure the stability through the phase compensation, a secondary phase delay (–180˚) resulting from LC
resonance should be canceled with a secondary phase lead (i.e., through inserting two phase leads).
Furthermore, the GBW (i.e., frequency at 1-dB gain) is determined according to phase compensation capacitance to be
provided for the error amplifier. Consequently, in order to reduce the GBW, increase the capacitance value.
(1) Typical (sun) integrator (Low pass filter)
A
+
Feedback R
(2) Open loop characteristics of (mon) integrator
A
–
FB
(a)
–20dB/decade
Gain
[dB]
GBW(b)
0
C
f
Phase 0
[˚]
–90
–90˚
Phase margin
–180˚
–180
f
(a) point
fa=
(b) point
fb=GBW=
[Hz]
[Hz]
Fig. 22 Typical integrator characteristics
Since the error amplifier is provided with (sun) or (mon) phase compensation, the low pass filter is applied. In the case of
the DC/DC converter application, the R becomes a parallel resistance of the feedback resistance.
10/16
2. For output capacitors having high ESR, such as aluminum electrolytic capacitor
For output capacitors having high ESR (i.e., several ohms), the phase compensation setting procedure becomes
comparatively simple. Since the DC/DC converter application has a LC resonant circuit attached to the output,
a –180˚ phase-delay occurs in that area. If ESR component is present there, however, a +90˚ phase-lead occurs to shift
the phase delay to –90˚. Since the phase delay is desired to set within 150˚, this is a very effective method but has
a demerit to increase the ripple component of the output voltage.
(3) LC resonant circuit
(4) With ESR provided
Vcc
Vcc
L
L
Vo
Vo
RESR
C
C
fz=
[Hz]
fz=
At this resonance point, a -180˚
phase-delay occurs.
[Hz] : Resonance point
fESR=
[Hz] : Phase lead
A – 90˚ phase-delay occurs.
* Same for the phase compensation of inverting and step-up voltages
Fig. 23 DC/DC converter output application
According to changes in phase characteristics due to the ESR, only one phase lead should be inserted. For this phase
lead, select either of the methods shown below:
(5) Insert feedback resistance in the C.
(6) Insert the R3 in integrator.
Vo
Vo
C1
R3
C2
R1
C2
R1
–
+
A
–
FB
+
FB
A
R2
Phase lead: fz=
Phase lead: fz=
[Hz]
[Hz]
Fig. 24 Typical phase compensation circuit
To cancel the LC resonance, phase lead frequency should be set close to the LC resonant frequency.
y.
11/16
3. For output capacitors having low ESR, such as a ceramic capacitor or OS-CON
In order to use capacitors having low ESR (i.e., several tens of mW), two phase-leads should be inserted so that a
– 180˚ phase-dela y, due to LC resonance, will be compensated. The following section shows a typical phase
compensation procedure.
. Phase compensation with secondary phase lead
Vo
R3
R1
C2
Phase lead: fz1=
[Hz]
Phase lead: fz2=
[Hz]
C1
INV
–
+
FB
A
R2
LC resonant frequency: fr=
[Hz]
Fig. 25 Typical circuit after secondary compensation circuit
For the settings of phase lead frequency, insert both of the phase leads close to the LC resonant frequency.
Phase compensation on the BD9300F/FV
For BD9300F/FV, since the error amplifier input is inverted to the normal input, the phase compensation procedure is
slightly different. (The BD9300F/FV returns feedback to the NON pin.)
Vo
Internal REG
2.5V
R1
+
–
R2
The BD9300 returns feedback to the +
side of the error amplifier.
100kΩ
100
kΩ
FB
A
C
Fig. 26 Typical circuit after phase compensation on BD9300F/FV
The BD9300F/FV feeds back on the + side input and returns the phase compensation on the - side input. Consequently,
resistance of the resistance divider being used to determine the reference voltage has influence on the frequency
characteristics. (The BD9300F/FV has a 1/2 VREF pin to divide resistance by 100 kΩ.)
The following section shows the phase characteristics.
Primary phase delay: fp =
Phase lead:
fz =
1
[Hz], where A is approximately 80 dB.
100kΩ
2
1
[Hz]
100kΩ
2
As a result, inserting a phase compensation capacitor will cause phase lead component. If any further phase lead is
required, add a capacitor in parallel with the R1.
12/16
Equivalent circuit
(1) DTC
VREF
VREF
VREF
1kΩ
100Ω
DTC
RT
(3) CT
(4) FB
VREF
VREF
VREF
VREF
17.8kΩ
100Ω
500Ω
FB
CT
100kΩ
(5) OUT
(9) SCP
VREF
VREF
OUT
500Ω
SCP
2kΩ
(10) CTL
(12) INV
VREF
VREF
VCC
1kΩ
CTL
INV
75kΩ
50kΩ
(13) 1/2VREF
(14) NON
VREF
VREF
VREF
VREF
100kΩ
1kΩ
1/2VREF
NON
100kΩ
13/16
Cautions on use
1) Absolute maximum ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the
devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to
exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses.
2) GND potential
Ground-GND potential should maintain at the minimum ground voltage level. Furthermore, no terminals should be lower than the GND
potential voltage including an electric transients.
3) Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
4) Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any connection error or if
positive and ground power supply terminals are reversed. The IC may also be damaged if pins are shorted together or are shorted to other
circuitís power lines.
5) Operation in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction.
6) Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always
discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to, or removing it from a jig or
fixture, during the inspection process. Ground the IC during assembly steps as an antistatic measure. Use similar precaution when
transporting and storing the IC.
7) IC pin input
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements to keep them isolated. PñN junctions are
formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode or transistor. For example, the
relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the PñN junction operates as a parasitic diode.
When Pin B > GND > Pin A, the PñN junction operates as a parasitic transisto r.
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among
circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate, such as applying a voltage that is
lower than the GND (P substrate) voltage to an input pin, should not be used.
Transistor (NPN)
Resistor
B
(Pin A)
(Pin B)
C
E
GND
N
P
P+
P+
P
P+
N
N
N
N
Player
P+
N
N
Parasitic element
Player
GND
Parasitic element
GND
(Pin B)
(Pin A)
B
Parasitic element
C
E
GND
GND
Fig. 28 Typical simple construction of monolithic IC
Parasitic element
8) Ground wiring pattern
The power supply and ground lines must be as short and thick as possible to reduce line impedance. Fluctuating voltage
on the power ground line may damage the device.
14/16
Derating curve
BD9300FV
BD9300F
PD
[mW]
PD
[mW]
(1) IC Only
(2) On 70 X 70 X 1.6mm Board
400 (2)
350
(1)
300
300
(1) IC Only
(2) On 70 X 70 X 1.6mm Board
(2)
400
(1)
200
100
0
100
25
50
75
100
125
0
25
50
Ta [˚C ]
75
100
Ta [˚C ]
Fig. 29 Thermal derating characteristics
Selection of order type
B
D
9
Product name
3
0
0
F
Package
FV:SSOP-B14
F :SOP14
V
–
E
2
Package/Forming specifications
E2 : Embossed carrier tape
Package specifications
SOP14
<Outline dimensions>
<Package specifications>
Package style
Embossed carrier tape
Q’ty per package
2500pcs
Packaging direction E2
(When holding a reel by left hand and pulling out the tape by
right hand, No. 1 pin appears in the upper left of the reel.)
No. 1 pin
Pulling-out side
Reel
*Orders are available in complete units only.
SSOP-B14
<Outline dimensions>
<Package specifications>
Package style
Embossed carrier tape
Q’ty per package
2500pcs
Packaging direction E2
(When holding a reel by left hand and pulling out the tape by
right hand, No. 1 pin appears in the upper left of the reel.)
No. 1 pin
Reel
*Orders are available in complete units only.
15/16
Pulling-out side
125
Catalog No.08T677A '08.9 ROHM ©
Appendix
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM
CO.,LTD.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you
wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM
upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account
when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples
of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to
use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information.
The Products specified in this document are intended to be used with general-use electronic equipment
or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or
malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as
derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your
use of any Product outside of the prescribed scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or system
which requires an extremely high level of reliability the failure or malfunction of which may result in a direct
threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment,
aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear
no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may be controlled under
the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact your nearest sales office.
ROHM Customer Support System
www.rohm.com
Copyright © 2009 ROHM CO.,LTD.
THE AMERICAS / EUROPE / ASIA / JAPAN
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Appendix-Rev4.0