AMIC A25QFM080QL 8mbit, 3v suspend/resume, dual/quad-i/o serial flash memory Datasheet

A25LQ080 Series
8Mbit, 3V Suspend/Resume, Dual/Quad-I/O Serial Flash Memory
with 100MHz Uniform 4KB Sectors
Document Title
8Mbit, 3V Suspend/Resume, Dual/Quad-I/O Serial Flash Memory with 100MHz Uniform 4KB
Sectors
Revision History
Rev. No.
1.0
History
Issue Date
Remark
Final version issue
April 1, 2016
Final
(April, 2016, Version 1.0)
AMIC Technology Corp.
AMIC reserves the right to change products and specifications discussed herein without notice.
A25LQ080 Series
8Mbit, 3V Suspend/Resume, Dual/Quad-I/O Serial Flash Memory
with 100MHz Uniform 4KB Sectors
FEATURES
„ Family of Serial Flash Memories
- A25LQ080: 8M-bit /2M-byte
„ Flexible Sector Architecture with 4KB sectors
- Sector Erase (4K-bytes) in 70ms (typical)
- Block Erase (64K-bytes) in 0.5s (typical)
- Program/Erase Suspend & Resume
„ Page Program (up to 256 Bytes) in 1.5ms (typical)
„ 2.7 to 3.6V Single Supply Voltage
„ Dual input / output instructions resulting in an equivalent
clock frequency of 200MHz:
- FAST_READ_DUAL_OUTPUT Instruction
- FAST_READ_DUAL_INPUT_OUTPUT Instruction
- Dual Input Fast Program (DIFP) Instruction
„ Quad input / output instructions resulting in an equivalent
clock frequency of 400MHz:
- FAST_READ_QUAD_ OUTPUT Instruction
- FAST_READ_QUAD_INPUT_OUTPUT Instruction
- Quad Input Fast Program (QIFP) Instruction
„ SPI Bus Compatible Serial Interface
„ 100MHz Clock Rate (maximum)
„ Deep Power-down Mode 15µA (Max.)
„ Advanced Protection Features
- Software and Hardware Write-Protect
- Top/Bottom, 4KB Complement Array Protection
„ Additional 64-byte user-lockable, one-time programmable
(OTP) area
„ 8Mbit Flash memory
- Uniform 4-Kbyte Sectors
- Uniform 64-Kbyte Blocks
„ Electronic Signatures
- JEDEC Standard Two-Byte Signature
A25LQ080: (4014h)
- RES Instruction, One-Byte, Signature, for backward
compatibility
A25LQ080: (13h)
„ Package options
- 8-pin SOP (150/209mil), 8-pin DIP (300mil) or 8-pin WSON
(6*5mm)
- All Pb-free (Lead-free) products are RoHS compliant
GENERAL DESCRIPTION
The A25LQ080 is 8M bit Serial Flash Memory, with advanced
write protection mechanisms, accessed by a high speed
SPI-compatible bus.
sectors. Each sector is composed of 16 pages. Each page is
256 bytes wide. Thus, the whole memory can be viewed as
consisting of 4,096 pages, or 1,048,576 bytes.
The whole memory can be erased using the Chip Erase
instruction, a block at a time, using Block Erase instruction, or a
sector at a time, using the Sector Erase instruction.
The memory can be programmed 1 to 256 bytes at a time,
using the Page Program instruction.
The memory is organized as 16 blocks, each containing 16
Pin Configurations
„ SOP8 Connections
„ DIP8 Connections
A25LQ080
S
DO (IO1)
W (IO2)
VSS
1
2
3
4
8 VCC
7 HOLD (IO3)
6 C
5 DI (IO0)
(April, 2016, Version 1.0)
„ WSON8 Connections
A25LQ080
S
DO (IO1)
W (IO2)
VSS
1
2
3
4
8 VCC
7 HOLD (IO3)
6 C
5 DI (IO0)
1
A25LQ080
S
DO (IO1)
W (IO2)
VSS
1
2
3
4
8
7
6
5
VCC
HOLD (IO3)
C
DI (IO0)
AMIC Technology Corp.
A25LQ080 Series
Pin Descriptions
Pin No.
Pin Name
I/O
I
Description
Chip Select Input
1
S
2
DO (IO1)
I/O
Data Output (Data Input Output 1)(1)
3
W (IO2)
I/O
Write Protect Input (Data Input Output 2)
4
VSS
5
DI (IO0)
6
C
7
HOLD (IO3)
8
VCC
(2)
Ground
I/O
I
Data Input (Data Input Output 0) (1)
Serial Clock Input
I/O
Hold Input (Data Input Output 3) (2)
Power Supply
Notes:
(1) IO0 and IO1 are used for Dual and Quad Instructions
(2) IO0 ~ IO3 are used for Quad Instructions
Block Diagram
HOLD (IO3)
W (IO2)
High Voltage
Generator
Control Logic
S
64 OTP bytes
C
I/O Shift Register
DI (IO0)
DO (IO1)
Address register
and Counter
256 Byte
Data Buffer
Status
Register
FFFFFh (8M)
Y Decoder
Size of the
memory area
0000FFh
000000h
256 Byte (Page Size)
X Decoder
(April, 2016, Version 1.0)
2
AMIC Technology Corp.
A25LQ080 Series
PIN DESCRIPTION
Write Protect ( W )
The Write Protect ( W ) pin can be used to prevent the Status
Register from being written. Used in conjunction with the
Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1
and BP0) bits and Status Register Protect (SRP0) bit, a
portion or the entire memory array can be hardware
protected. The Write Protect ( W ) pin is active low.
When the QE bit of Status Register-2 is set for Quad I/O, the
Write Protect ( W ) pin (Hardware Write Protect) function is
not available since this pin is used for IO2. See the Pin
Configuration for Quad I/O operation.
Chip Select ( S )
The SPI Chip Select ( S ) pin enables and disables device
operation. When Chip Select ( S ) is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2,
IO3) pins are at high impedance. When deselected, the
devices power consumption will be at standby levels unless
an internal erase, program or write status register cycle is in
progress.
When Chip Select ( S ) is brought low the device will be
selected, power consumption will increase to active levels
and instructions can be written to and data read from the
device. After power-up, Chip Select ( S ) must transition from
high to low before a new instruction will be accepted.
Hold ( HOLD )
The Hold ( HOLD ) pin allows the device to be paused while
Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2,
IO3)
The A25LQ080 support standard SPI, Dual SPI and Quad
SPI operation. Standard SPI instructions use the
unidirectional DI (input) pin to serially write instructions,
addresses or data to the device on the rising edge of the
Serial Clock (C) input pin. Standard SPI also uses the
unidirectional DO (output) to read data or status from the
device on the falling edge of Serial Clock (C).
Dual and Quad SPI instruction use the bidirectional IO pins
to serially write instructions, addresses or data to the device
on the rising edge of Serial clock (C) and read data or status
from the device on the falling edge of Serial Clock (C).
Quad SPI instructions require the non-volatile Quad Enable
bit (QE) in Status Register-2 to be set. When QE=1 the Write
Protect ( W ) pin becomes IO2 and Hold ( HOLD ) pin
becomes IO3.
(April, 2016, Version 1.0)
it is actively selected. When Hold ( HOLD ) pin is brought low,
while Chip Select ( S ) pin is low, the DO pin will be at high
impedance and signals on the DI and Serial Clock (C) pins
will be ignored (don’t care). When Hold ( HOLD ) pin is
brought high, device operation can resume. The Hold
function can be useful when multiple devices are sharing the
same SPI signals. The Hold ( HOLD ) pin is active low.
When the QE bit of Status Register-2 is set for Quad I/O. the
Hold ( HOLD ) pin function is not available since this pin is
used for IO3. See the Pin Configuration for Quad I/O
operation.
Serial Clock (C)
The SPI Serial Clock Input (C) pin provides the timing for
serial input and output operations.
3
AMIC Technology Corp.
A25LQ080 Series
SPI MODES
falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 1,
is the clock polarity when the bus master is in Stand-by mode
and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0) Æ Mode 0
– C remains at 1 for (CPOL=1, CPHA=1) Æ Mode 3
These devices can be driven by a microcontroller with its SPI
peripheral running in either of the two following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising
edge of Serial Clock (C), and output data is available from the
Figure 1. SPI Modes Supported
CPOL
CPHA
Mode 0 0
0 C
Mode 3 1
1 C
DIO
MSB
DO
(April, 2016, Version 1.0)
MSB
4
AMIC Technology Corp.
A25LQ080 Series
SPI OPERATIONS
Standard SPI Instructions
Hold Condition
The A25LQ080 is accessed through an SPI compatible bus
consisting of four signals: Serial Clock (C), Chip Select ( S ),
Serial Data Input (DI), and Serial Data Output (DO). Standard
SPI instructions use the DI input pin to serially write
instructions, addresses or data to the device on the rising
edge of Serial Clock (C). The DO output pin is used to read
data or status from the device on the falling edge of Serial
Clock (C).
The Hold ( HOLD ) signal is used to pause any serial
communications with the device without resetting the clocking
sequence. However, taking this signal Low does not
terminate any Write Status Register, Program or Erase cycle
that is currently in progress. The HOLD function is only
available for standard SPI and Dual SPI operation, not during
Quad SPI.
To enter the Hold condition, the device must be selected, with
Chip Select ( S ) Low.
The Hold condition starts on the falling edge of the Hold
Dual SPI Instructions
The A25LQ080 supports Dual SPI operation when using the
“FAST_READ_DUAL_OUTPUT and FAST_READ_DUAL_
INPUT_OUTPUT” (3B and BB hex) instructions. These
instructions allow data to be transferred to or from the device
at two to three times the rate of ordinary Serial Flash devices.
The Dual Read instructions are ideal for quickly downloading
code to RAM upon power-up (code-shadowing) or for
executing non-speed-critical code directly from the SPI bus
(XIP). When using Dual SPI instructions the DI and DO pins
become bidirectional I/O pins; IO0 and IO1.
( HOLD ) signal, provided that this coincides with Serial Clock
(C) being Low (as shown in Figure 2.).
The Hold condition ends on the rising edge of the Hold
( HOLD ) signal, provided that this coincides with Serial Clock
(C) being Low.
If the falling edge does not coincide with Serial Clock (C)
being Low, the Hold condition starts after Serial Clock (C)
next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after
Serial Clock (C) next goes Low. This is shown in Figure 2.
During the Hold condition, the Serial Data Output (DO) is high
impedance, and Serial Data Input (DI) and Serial Clock (C)
are Don’t Care.
Quad SPI Instructions
The A25LQ080 supports Quad SPI operation when using the
“FAST_READ_QUAD_OUTPUT”
(6B
hex)
and
“FAST_READ_QUAD_INPUT_OUTPUT”
(EB
hex)
instructions. This instruction allows data to be transferred to
or from the device four to six times the rate of ordinary Serial
Flash. These 2 instructions offer a significant improvement in
continuous and random access transfer rates allowing fast
code-shadowing to RAM or execution directly from the SPI
bus (XIP). When using Quad SPI instructions the DI and DO
pins become bi-directional IO0 and IO1, and the W and
HOLD pins become IO2 and IO3 respectively. Quad SPI
instructions require the non-volatile Quad Enable bit (QE) in
Status Register-2 to be set.
Normally, the device is kept selected, with Chip Select ( S )
driven Low, for the whole duration of the Hold condition. This
is to ensure that the state of the internal logic remains
unchanged from the moment of entering the Hold condition.
If Chip Select ( S ) goes High while the device is in the Hold
condition, this has the effect of resetting the internal logic of
the device. To restart communication with the device, it is
necessary to drive Hold ( HOLD ) High, and then to drive Chip
Select ( S ) Low. This prevents the device from going back to
the Hold condition.
Figure 2. Hold Condition Activation
C
HOLD
Hold
Condition
(standard use)
(April, 2016, Version 1.0)
5
Hold
Condition
(non-standard use)
AMIC Technology Corp.
A25LQ080 Series
OPERATING FEATURES
device then goes in to the Stand-by Power mode. The device
consumption drops to ICC1.
The Deep Power-down mode is entered when the specific
instruction (the Deep Power-down Mode (DP) instruction) is
executed. The device consumption drops further to ICC2. The
device remains in this mode until another specific instruction
(the Release from Deep Power-down Mode and Read
Electronic Signature (RES) instruction) is executed.
All other instructions are ignored while the device is in the
Deep Power-down mode. This can be used as an extra
software protection mechanism, when the device is not in
active use, to protect the device from inadvertent Write,
Program or Erase instructions.
Page Programming
To program one data byte, two instructions are required: Write
Enable (WREN), which is one byte, and a Page Program (PP)
sequence, which consists of four bytes plus data. This is
followed by the internal Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction
allows up to 256 bytes to be programmed at a time (changing
bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.
Dual Input Fast Program
The Dual Input Fast Program (DIFP) instruction makes it
possible to program up to 256 bytes using two input pins at
the same time (by changing bits from 1 to 0).
For optimized timings, it is recommended to use the Dual
Input Fast Program (DIFP) instruction to program all
consecutive targeted bytes in a single sequence rather to
using several Dual Input Fast Program (DIFP) sequences
each containing only a few bytes.
Status Register
The Status Register contains a number of status and control
bits that can be read or set (as appropriate) by specific
instructions. See Read Status Register (RDSR) for a detailed
description of the Status Register bits.
Protection Modes
Quad Input Fast Program
The environments where non-volatile memory devices are
used can be very noisy. No SPI device can operate correctly
in the presence of excessive noise. To help combat this, the
A25LQ080 boasts the following data protection mechanisms:
„ Power-On Reset and an internal timer (tPUW) can provide
protection against inadvertent changes while the power
supply is outside the operating specification.
„ Program, Erase and Write Status Register instructions are
checked that they consist of a number of clock pulses that
is a multiple of eight, before they are accepted for
execution.
„ All instructions that modify data must be preceded by a
Write Enable (WREN) instruction to set the Write Enable
Latch (WEL) bit. This bit is returned to its reset state by
the following events:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Program OTP (POTP) instruction completion
- Page Program (PP) instruction completion
- Dual Input Fast Program (DIFP) instruction completion
- Quad input Fast Program (QIFP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
„ The Block Protect (BP2, BP1, BP0) bits conjunction with
Sector Protect (SEC) bit , Top/Bottom (TB) bit and
Complement Protect (CMP) bit allow part of the memory to
be configured as read-only. This is the Software Protected
Mode (SPM).
„ The Write Protect ( W ) signal allows the Block Protect
(BP2, BP1, BP0) bits, Sector Protect (SEC) bit,
Top/Bottom (TB) bit, All Protect (APT), Complement
Protect (CMP) bit and Status Register Protect (SRP0) bit
to be protected. This is the Hardware Protected Mode
(HPM).
„ In addition to the low power consumption feature, the
Deep Power-down mode offers extra software protection
from inadvertent Write, Program and Erase instructions, as
all instructions are ignored except one particular instruction
(the Release from Deep Power-down instruction).
The Quad Input Fast Program (QIFP) instruction makes it
possible to program up to 256 bytes using four input pins (IO3,
IO2, IO1, and IO0) at the same time (by changing bits from 1 to
0).
For optimized timings, it is recommended to use the Quad
Input Fast Program (QIFP) instruction to program all
consecutive targeted bytes in a single sequence rather to
using several Quad Input Fast Program (QIFP) sequences
each containing only a few bytes.
Sector Erase, Block Erase, and Chip Erase
The Page Program (PP) instruction, Dual Input Fast Program
(DIFP) instruction, and Quad Input Fast Program (QIFP)
instruction allow bits to be reset from 1 to 0. Before this can
be applied, the bytes of memory need to have been erased to
all 1s (FFh). This can be achieved, a sector at a time, using
the Sector Erase (SE) instruction, a block at a time, using the
Block Erase (BE) instruction, or throughout the entire memory,
using the Chip Erase (CE) instruction. This starts an internal
Erase cycle (of duration tSE, tBE, or tCE).
The Erase instruction must be preceded by a Write Enable
(WREN) instruction.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register
(WRSR), Program OTP (POTP), Program (PP, DIFP, QIFP),
or Erase (SE, BE, or CE) can be achieved by not waiting for
the worst case delay (tW, tPP, tSE, tBE, tCE). The Write In
Progress (WIP) bit is provided in the Status Register so that
the application program can monitor its value, polling it to
establish when the previous Write cycle, Program cycle or
Erase cycle is complete.
Active Power, Stand-by Power and Deep Power-Down
Modes
When Chip Select ( S ) is Low, the device is enabled, and in
the Active Power mode.
When Chip Select ( S ) is High, the device is disabled, but
could remain in the Active Power mode until all internal cycles
have completed (Program, Erase, Write Status Register). The
(April, 2016, Version 1.0)
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AMIC Technology Corp.
A25LQ080 Series
Table 1-1. Protected Area Sizes (CMP=0)
A25LQ080
Status Register Content
(8M-Bit) Memory Protection
SEC
TB
BP2
BP1
BP0
Block(s)
Addresses
Density(Byte)
Portion
X
X
0
0
0
None
None
None
None
0
0
0
0
1
15
F0000h – FFFFFh
64KB
Upper 1/16
0
0
0
1
0
14 – 15
E0000h – FFFFFh
128KB
Upper 1/8
0
0
0
1
1
12 – 15
C0000h – FFFFFh
256KB
Upper 1/4
0
0
1
0
0
8 – 15
80000h – FFFFFh
512KB
Upper 1/2
0
0
1
0
1
0 – 15
00000h – FFFFFh
1MB
ALL
0
1
0
0
1
0
000000h – 0FFFFh
64KB
Lower 1/16
0
1
0
1
0
0–1
000000h – 1FFFFh
128KB
Lower 1/8
0
1
0
1
1
0–3
000000h – 3FFFFh
256KB
Lower 1/4
0
1
1
0
0
0–7
000000h – 7FFFFh
512KB
Lower 1/2
0
1
1
0
1
0 – 15
000000h – FFFFFh
1MB
ALL
X
X
1
1
X
0 – 15
000000h – FFFFFh
1MB
ALL
1
0
0
0
1
15
FF000h – FFFFFh
4KB
Top Block
1
0
0
1
0
15
FE000h – FFFFFh
8KB
Top Block
1
0
0
1
1
15
FC000h – FFFFFh
16KB
Top Block
1
0
1
0
X
15
F8000h – FFFFFh
32KB
Top Block
1
1
0
0
1
0
000000h – 00FFFh
4KB
Bottom Block
1
1
0
1
0
0
000000h – 01FFFh
8KB
Bottom Block
1
1
0
1
1
0
000000h – 03FFFh
16KB
Bottom Block
1
1
1
0
X
0
000000h – 07FFFh
32KB
Bottom Block
Note:
1. X = don’t care
2.
If any Erase or Program command specifies a memory region that contains protected data portion, this command will be
ignored.
(April, 2016, Version 1.0)
7
AMIC Technology Corp.
A25LQ080 Series
Table 1-2. Protected Area Sizes (CMP=1)
A25LQ080
Status Register Content
(8M-Bit) Memory Protection
SEC
TB
BP2
BP1
BP0
Block(s)
Addresses
Density(Byte)
Portion
X
X
0
0
0
0 – 15
000000h – FFFFFh
1MB
ALL
0
0
0
0
1
0 – 14
000000h – EFFFFh
960KB
Lower 15/16
0
0
0
1
0
0 – 13
000000h – DFFFFh
896KB
Lower 7/8
0
0
0
1
1
0 – 11
000000h – BFFFFh
768KB
Lower 3/4
0
0
1
0
0
0–7
000000h – 7FFFFh
512KB
Lower 1/2
0
0
1
0
1
0–7
000000h – 7FFFFh
512KB
Lower 1/2
0
0
1
1
0
0–7
000000h – 7FFFFh
512KB
Lower 1/2
0
0
1
1
1
None
None
None
None
0
1
0
0
1
1 – 15
010000h – FFFFFh
960KB
Upper 15/16
0
1
0
1
0
2 – 15
020000h – FFFFFh
896KB
Upper 7/8
0
1
0
1
1
4 – 15
040000h – FFFFFh
768KB
Upper 3/4
0
1
1
0
0
8 – 15
080000h – FFFFFh
512KB
Lower 1/2
0
1
1
0
1
8 – 15
080000h – FFFFFh
512KB
Lower 1/2
0
1
1
1
0
8 – 15
080000h – FFFFFh
512KB
Lower 1/2
0
1
1
1
1
None
None
None
None
1
0
0
0
1
0 – 15
000000h – FEFFFh
1020KB
Lower 255/256
1
0
0
1
0
0 – 15
000000h – FDFFFh
1016KB
Lower 127/128
1
0
0
1
1
0 – 15
000000h – FBFFFh
1008KB
Lower 63/64
1
0
1
1
0
0 – 15
000000h – F7FFFh
992KB
Lower 31/32
1
0
1
1
1
None
None
None
None
1
1
0
0
1
0 – 15
001000h – FFFFFh
1020KB
Upper 255/256
1
1
0
1
0
0 – 15
002000h – FFFFFh
1016KB
Upper 127/128
1
1
0
1
1
0 – 15
004000h – FFFFFh
1008KB
Upper 63/64
1
1
1
1
0
0 – 15
008000h – FFFFFh
992KB
Upper 31/32
1
1
1
1
1
None
None
None
None
Note:
1. X = don’t care
2.
If any Erase or Program command specifies a memory region that contains protected data portion, this command will be
ignored.
(April, 2016, Version 1.0)
8
AMIC Technology Corp.
A25LQ080 Series
MEMORY ORGANIZATION
Each page can be individually programmed (bits are
programmed from 1 to 0). The device is Sector, Block, or Chip
Erasable (bits are erased from 0 to 1) but not Page Erasable.
The memory is organized as:
„ 1,048,576 bytes (8 bits each)
„ 16 blocks (64 Kbytes each)
„ 256 sectors (4 Kbytes each)
„ 4096 pages (256 bytes each)
„ 64 bytes OTP located outside the main memory array
Table 2. Memory Organization
A25LQ080 Address Table
Block
Sector
255
...
...
...
...
...
96
60000h
60FFFh
239
EF000h
EFFFFh
95
5F000h
5FFFFh
50FFFh
DFFFFh
4F000h
4FFFFh
CF000h
CFFFFh
191
BF000h
BFFFFh
63
3F000h
3FFFFh
48
30000h
30FFFh
47
2F000h
2FFFFh
...
...
...
...
...
2
40FFFh
...
C0FFFh
40000h
...
...
C0000h
64
...
...
192
3
...
207
...
...
D0FFFh
...
...
D0000h
4
176
B0000h
B0FFFh
32
20000h
20FFFh
175
AF000h
AFFFFh
31
1F000h
1FFFFh
...
...
...
...
...
1
160
A0000h
A0FFFh
16
10000h
10FFFh
159
9F000h
9FFFFh
15
0F000h
0FFFFh
...
...
...
...
...
...
144
90000h
90FFFh
4
04000h
04FFFh
8F000h
03FFFh
2
02000h
02FFFh
1
01000h
01FFFh
0
00000h
00FFFh
...
03000h
...
8FFFFh
3
...
128
80000h
80FFFh
127
7F000h
7FFFFh
...
...
...
7
50000h
79
208
143
8
80
...
9
DF000h
...
E0FFFh
...
...
E0000h
...
...
224
5
...
10
6FFFFh
F0FFFh
...
11
6F000h
F0000h
...
12
6
Address range
240
223
13
111
FFFFFh
...
14
FF000h
Sector
...
15
Block
Address range
112
70000h
70FFFh
(April, 2016, Version 1.0)
0
9
AMIC Technology Corp.
A25LQ080 Series
INSTRUCTIONS
Read Status Register (RDSR) or Release from Deep
Power-down, Read Device Identification and Read Electronic
Signature (RES) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select ( S )
can be driven High after any bit of the data-out sequence is
being shifted out.
In the case of a Page Program (PP), Program OTP (POTP),
Dual Input Fast Program (DIFP), Quad Input Fast Program
(QIFP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE),
Write Status Register (WRSR), Write Enable (WREN), Write
Disable (WRDI) or Deep Power-down (DP) instruction, Chip
Select ( S ) must be driven High exactly at a byte boundary,
otherwise the instruction is rejected, and is not executed. That
is, Chip Select ( S ) must driven High when the number of
All instructions, addresses and data are shifted in and out of
the device, most significant bit first.
Serial Data Input(s) IO0 (IO1, IO2, IO3) is (are) sampled on the
first rising edge of Serial Clock (C) after Chip Select ( S ) is
driven Low. Then, the one-byte instruction code must be
shifted in to the device, most significant bit first, on Serial Data
Input(s) IO0 (IO1, IO2, IO3), each bit being latched on the rising
edges of Serial Clock (C).
The instruction set is listed in Table 3.
Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by
address bytes, or by data bytes, or by dummy bytes (don’t
care), or by a combination or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at
Higher Speed (Fast_Read), Read Data Bytes at Higher Speed
by Dual Output (FAST_READ_DUAL_OUTPUT), Read Data
Bytes at Higher Speed by Dual Input and Dual Output
(FAST_READ_DUAL_INPUT_OUTPUT) , Read Data Bytes at
Higher Speed by Quad Output (FAST_READ_QUAD
_OUTPUT), Read Data Bytes at Higher Speed by Quad Input
and Quad Output (FAST_READ_QUAD_INPUT_OUTPUT),
Read OTP (ROTP), Read Identification (RDID), Read
Electronic Manufacturer and Device Identification (REMS),
(April, 2016, Version 1.0)
clock pulses after Chip Select ( S ) being driven Low is an
exact multiple of eight.
All attempts to access the memory array during a Write Status
Register cycle, Program cycle or Erase cycle are ignored, and
the internal Write Status Register cycle, Program cycle or
Erase cycle continues unaffected.
10
AMIC Technology Corp.
A25LQ080 Series
Table 3. Instruction Set
Instruction
One-byte
Instruction Code
Description
Address
Bytes
Dummy
Bytes
Data
Bytes
WREN
Write Enable
0000 0110
06h
0
0
0
WRDI
Write Disable
0000 0100
04h
0
0
0
RDSR-1
Read Status Register-1
0000 0101
05h
0
0
1 to ∞
RDSR-2
Read Status Register-2
0011 0101
35h
0
0
1 to ∞
WRSR
Write Status Register
0000 0001
01h
0
0
2
READ
Read Data Bytes
0000 0011
03h
3
0
1 to ∞
FAST_READ
Read Data Bytes at Higher Speed
0000 1011
0Bh
3
1
1 to ∞
FAST_READ_DUAL
_OUTPUT
Read Data Bytes at Higher Speed
by Dual Output (1)
0011 1011
3Bh
3
1
1 to ∞(1)
FAST_READ_DUAL
_INPUT_OUTPUT
Read Data Bytes at Higher Speed
by Dual Input and Dual Output (1)(2)
1011 1011
BBh
3(2)
1(2)
1 to ∞(1)
FAST_READ_QUAD
_OUTPUT
Read Data Bytes at Higher Speed
by Quad Output (4)
0110 1011
6Bh
3
1
1 to ∞(4)
FAST_READ_QUAD
_INPUT_OUTPUT
Read Data Bytes at Higher Speed
by Quad Input and Quad Output (3)(4)
1110 1011
EBh
3(3)
1(3)
1 to ∞(4)
ROTP
Read OTP (Read 64 bytes of OTP
area)
0100 1011
4Bh or 48h
3
1
1 to ∞
POTP
Program OTP (Program 64 bytes of
OTP area)
0100 0010
42h
3
0
1 to 64
PP
Page Program
0000 0010
02h
3
0
1 to 256
DIFP
Dual Input Fast Program
1010 0010
A2h
3
0
1 to 256(5)
QIFP
Quad Input Fast Program
0011 0010
32h
3
0
1 to 256(6)
SE
Sector Erase
0010 0000
20h
3
0
0
BE
Block Erase
1101 1000
D8h or 52h
3
0
0
CE
Chip Erase
1100 0111
C7h or 60h
0
0
0
DP
Deep Power-down
1011 1001
B9h
0
0
0
RDID
Read Device Identification
1001 1111
9Fh
0
0
1 to ∞
REMS
Read Electronic Manufacturer &
Device Identification
1001 0000
90h
1(7)
2
1 to ∞
1010 1011
ABh
0
3
1 to ∞
0
0
0
0
3
0
0
0
0
0
0
0
3
1
1 to 64
RES
Release from Deep Power-down,
and Read Electronic Signature
Release from Deep Power-down
HPM
High Performance Mode
SUSPEND
Program / Erase Suspend
RESUME
Program / Erase Resume
SFDP
Read SFDP
(April, 2016, Version 1.0)
1010 0011
A3h
0111 0101
75h
1011 0000
B0h
0111 1010
7Ah
0011 0000
30h
0101 1010
5Ah
11
AMIC Technology Corp.
A25LQ080 Series
Note: (1) Dual Output Data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
(2) Dual Input Address
IO0 = (A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0, M6, M4, M2, M0)
IO1 = (A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1, M7, M5, M3, M1)
(3) Quad Input Address
IO0 = (A20, A16, A12, A8, A4, A0, M4, M0)
IO1 = (A21, A17, A13, A9, A5, A1, M5, M1)
IO2 = (A22, A18, A14, A10, A6, A2, M6, M2)
IO3 = (A23, A19, A15, A11, A7, A3, M7, M3)
(4) Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
(5) Dual Input Fast Program Input Data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
(6) Quad Input Fast Program Input Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
(7) ADD= (00h) will output manufacturer’s ID first and ADD=(01h) will output device ID first
(April, 2016, Version 1.0)
12
AMIC Technology Corp.
A25LQ080 Series
Write Enable (WREN)
Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving
Chip Select ( S ) Low, sending the instruction code, and then
The Write Enable (WREN) instruction (Figure 3.) sets the
Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every
Page Program (PP), Dual Input Fast Program (DIFP), Quad
Input Fast Program (QIFP), Program OTP (POTP), Sector
Erase (SE), Block Erase (BE), and Chip Erase (CE) and Write
driving Chip Select ( S ) High.
Figure 3. Write Enable (WREN) Instruction Sequence
S
0
1
2 3
4 5
6
7
C
Instruction (06h)
DI
DO
High Impedance
Write Disable (WRDI)
﹣ Power-up
The Write Disable (WRDI) instruction (Figure 4.) resets the
﹣
﹣
﹣
﹣
﹣
﹣
﹣
﹣
﹣
Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving Chip
Select ( S ) Low, sending the instruction code, and then driving
Chip The Write Enable Latch (WEL) bit is reset under the
following conditions:
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Dual Input Fast Program (DIFP) instruction completion
Quad Input Fast Program (QIFP) instruction completion
Program OTP (POTP) instruction completion
Sector Erase (SE) instruction completion
Block Erase (BE) instruction completion
Chip Erase (CE) instruction completion
Figure 4. Write Disable (WRDI) Instruction Sequence
S
0
1
2 3
4 5
6
7
C
Instruction (04h)
DI
DO
(April, 2016, Version 1.0)
High Impedance
13
AMIC Technology Corp.
A25LQ080 Series
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the
Status Register to be read. The instruction code of “05h” is
for Status Register-1 and “35h” is for Status Register-2. The
Status Register may be read at any time, even while a
Program, Erase or Write Status Register cycle is in progress.
When one of these cycles is in progress, it is recommended
to check the Write In Progress (WIP) bit before sending a
new instruction to the device. It is also possible to read the
Status Register continuously, as shown in Figure 5.
Table 4-a Status Register-1 Format
b7
SRP0
b6
SEC
b5
TB
b4
BP2
b3
BP1
b2
BP0
b1
WEL
b0
WIP
Status Register Protect 0
(Non-volatile)
Sector Protect
(Non-volatile)
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, and BP0)
bits are non-volatile read/write bits in the status register (b4,
b3, and b2) that provide Write Protection control and status.
Block Protect bits can be set using the Write Status Register
Instruction (see tW in AC characteristics). All, none or a
portion of the memory array can be protected from Program
and Erase instructions (see Table 1. Protected Area Sizes).
These bits can be set with the Write Status Register
Instruction depending on the state of SRP0 and WEL bit. The
factory default setting for the Block Protect Bits is 0 which
means none of the array protected. For value of BP2, BP1,
BP0 after power-on, see note please.
TB bit. The non-volatile Top/Bottom (TB) bit controls if the
Block Protect Bits (BP2, BP1, BP0) protect from the Top
(TB=0) or the Bottom (TB=1) of the array as shown in Table 1.
Protected Area Sizes. The factory default setting is TB=0.
The TB bit can be set with the Write Status Register
Instruction depending on the state of SRP0 and WEL bit.
Top/Bottom Bit
(Non-volatile)
Block Protect Bits
(Non-volatile)
Write Enable Latch Bit
Write In Progress Bit
Table 4-b Status Register-2 Format
b15
SUS
Program, Dual Input Fast Program, Quad Input Fast Program,
Sector Erase, Block Erase, Chip Erase, and Write Status
Register.
b14
CMP
b13
0
b12
0
b11
0
b10
APT
b9
QE
b8
0
Suspend Status
(Volatile)
Complement Protect
(Non-volatile)
Reserved
All Protect
(Auto Write Protect)
Quad Enable
(Non-volatile)
Reserved
The status and control bits of the Status Register are as
follows:
WIP bit. The Write In Progress (WIP) bit is a read only bit in
the status register (b0) that is set to a 1 state when the
device is busy with a Write Status Register, Program or
Erase cycle. During this time the device will ignore further
instructions except for the Read Status Register, Suspend
and Resume instructions (see tW, tPP, tSE, tBE, and tCE in AC
Characteristics). When the program, erase, write status
register instruction has completed or Program/Erase
Suspend instruction is executed, the WIP bit will be cleared
to a 0 state indicating the device is ready for further
instructions.
WEL bit. The Write Enable Latch (WEL) bit is a read only bit
in the status register (b1) that is set to a 1 after executing a
Write Enable Instruction. The WEL status bit is cleared to a 0
when the device is write disabled or Program/Erase
suspended. A write disable state occurs upon power-up or
after any of the following instructions: Write Disable, Page
(April, 2016, Version 1.0)
SEC bit. The non-volatile Sector Protect (SEC) bit in the
status register (b6) controls if the Block Protect Bits (BP2,
BP1, BP0) protect 4KB Sectors (SEC=1) or 64KB Blocks
(SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array
as shown in Table 1. Protected Area Sizes. This bit can be
set with the Write Status Register Instruction depending on
the state of the SRP0, and WEL bit. The factory default
setting for SEC is 0.
SRP0 bit. The Status Register Protect bit (SRP0) is a
non-volatile read/write bit in the status register (b7). The
SRP0 bit controls the method of write protection: software
protection, hardware protection, or one time programmable
protection.
QE bit. The Quad Enable (QE) bit is a non-volatile read/write
bit in the status register (b9) that allows Quad SPI operation.
When QE is set to 0(factory default), the W pin and
HOLD pin are enabled. When QE is set to 1, the W pin
and HOLD pin become IO2 and IO3. This bit can be set with
the Write Status Register Instruction depending on the state
of the SRP0 and WEL bit. The factory default setting for QE
is 0.
APT bit. The All Protect (APT) bit is a non-volatile read/write
bit in the status register (b10). Whole chip will be kept in
write-protect state after power-on if this bit is set to 1. This bit
can be set with the Write Status Register Instruction
depending on the state of SRP0 and WEL bit. The factory
default setting for APT is 0.
CMP bit. The Complement Protect (CMP) bit is a non-volatile
read/write bit in the status register (b14). It’s used in
conjunction with SEC, TB, BP2, BP1, BP0 bits to provide
more flexibility for the array protection. Once CMP is set to 1,
previous array protection set by SEC, TB, BP2, BP1 and BP0
will be reversed. Please refer to table 1 for more details. The
factory default setting for CMP is 0.
14
AMIC Technology Corp.
A25LQ080 Series
SUS bit. The Suspend Status (SUS) bit is a volatile read only
bit in the status register (b15) which is set to 1 after executing
a Program/Erase Suspend instruction. The SUS bit is cleared
to 0 by Program/Erase Resume instruction as well as a
power-down, power-up cycle.
Note:
1. When APT is 0, BP2, BP1, BP0 won’t be changed after
power-on.
2. When APT is 1 and CMP is 0, all BP2, BP1, BP0 will be
set to 1 after power-on.
3. When APT is 1 and CMP is 1, all BP2, BP1, BP0 will be
set to 0 after power-on.
Figure 5. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
S
0
1
2 3 4
5 6
7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
Instruction (05h or 35h)
DI
Status Register 1 or 2 Out
DO
High Impedance
(April, 2016, Version 1.0)
7 6 5
MSB
3 2 1
4
15
Status Register 1 or 2 Out
0
7 6
MSB
5
4
3
2 1
0
7
AMIC Technology Corp.
A25LQ080 Series
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new
values to be written to the Status Register. Before it can be
accepted, a Write Enable (WREN) instruction must
previously have been executed. After the Write Enable
(WREN) instruction has been decoded and executed, the
device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by
driving Chip Select ( S ) Low, followed by the instruction
code and the data byte on Serial Data Input (DI).
The instruction sequence is shown in Figure 6. Only
non-volatile Status Register bits SRP0, SEC, TB, BP2, BP1,
BP0 (bits 7, 6, 5, 4, 3, 2 of Status Register-1) and CMP,
APT, QE (bits 14, 10 and 9 of Status Register-2) can be
written. All other Status Register bits are always read as ‘0’
and will not be affected by the Write Status Register
instruction.
Chip Select ( S ) must be driven High after the eighth or
sixteenth bit of the data byte has been latched in. If not, the
Write Status Register (WRSR) instruction is not executed.
If Chip Select ( S ) is driven high after the eighth clock the
CMP and QE bits will be cleared to 0.
As soon as Chip Select ( S ) is driven High, the self-timed
Write Status Register cycle (whose duration is tW) is initiated.
While the Write Status Register cycle is in progress, the
Status Register may still be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit
is 1 during the self-timed Write Status Register cycle, and is
0 when it is completed. When the cycle is completed, the
Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the
user to change the values of the Block Protect (APT, CMP,
SEC, TB, BP2, BP1, BP0) bits, to define the size of the area
that is to be treated as read-only, as defined in Table 1. The
Write Status Register (WRSR) instruction also allows the
user to set the Status Register Protect (SRP0) bit. Those
bits are used in conjunction with the Write Protect ( W ) pin
to disable writes to the Status Register. Factory default for
all Status Register bits are 0.
Figure 6. Write Status Register (WRSR) Instruction Sequence
S
0
C
1
2 3 4
5 6
7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction (01h)
Status Register In
DI
7
6 5
4
3 2 1
0 15 14 13 12 11 10 9
8
MSB
High Impedance
DO
Table 5. Protection Modes
SRP0
W
Status Register
Description
0
X
Software Protection
Status Register is Writable (if the WREN instruction has set the WEL
bit). The values in the CMP, APT, SRP0, SEC, TB, BP2, BP1, BP0
bits can be changed.
1
0
Hardware Protection
Status Register is hardware write protected. The values in the CMP,
APT, SRP0, SEC, TB, BP2, BP1, BP0 bits cannot be changed.
1
1
Software Protection
When W pin is high. Status Register is Writable (if the WREN
instruction has set the WEL bit). The values in the CMP, APT,
SRP0, SEC, TB, BP2, BP1, BP0 bits can be changed.
(April, 2016, Version 1.0)
16
AMIC Technology Corp.
A25LQ080 Series
Read Data Bytes (READ)
The device is first selected by driving Chip Select ( S ) Low.
The instruction code for the Read Data Bytes (READ)
instruction is followed by a 3-byte address (A23-A0), each bit
being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, is shifted out on
Serial Data Output (DO), each bit being shifted out, at a
maximum frequency fR, during the falling edge of Serial Clock
(C).
The instruction sequence is shown in Figure 7. The first byte
addressed can be at any location. The address is
automatically incremented to the next higher address after
each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ)
instruction. When the highest address is reached, the
address counter rolls over to 000000h, allowing the read
sequence to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by
driving Chip Select ( S ) High. Chip Select ( S ) can be driven
High at any time during data output. Any Read Data Bytes
(READ) instruction, while an Erase, Program or Write cycle is
in progress, is rejected without having any effects on the
cycle that is in progress.
Figure 7. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
S
0
1
2 3 4
5 6
7 8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction (03h)
24-Bit Address
23 22 21
DI
3
2
1
0
MSB
High Impedance
DO
7 6
Data Out 1
5 4 3 2
Data Out 2
1
0
7
MSB
Note: Address bits A23 to A20 are Don’t Care, for A25LQ080.
(April, 2016, Version 1.0)
17
AMIC Technology Corp.
A25LQ080 Series
Read Data Bytes at Higher Speed (FAST_READ)
Speed (FAST_READ) instruction. When the highest address
is reached, the address counter rolls over to 000000h,
allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select ( S ) Low.
The instruction code for the Read Data Bytes at Higher
Speed (FAST_READ) instruction is followed by a 3-byte
address (A23-A0) and a dummy byte, each bit being
latched-in during the rising edge of Serial Clock (C). Then the
memory contents, at that address, is shifted out on Serial
Data Output (DO), each bit being shifted out, at a maximum
frequency fC, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 8. The first byte
addressed can be at any location. The address is
automatically incremented to the next higher address after
each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher
instruction is terminated by driving Chip Select ( S ) High.
Chip Select ( S ) can be driven High at any time during data
output. Any Read Data Bytes at Higher Speed (FAST_READ)
instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle
that is in progress.
Figure 8. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence
S
0
1
2 3 4
5 6
7 8
9 10
28 29 30 31
C
Instruction (0Bh)
24-Bit Address
23 22 21
DI
2
3
1
0
MSB
High Impedance
DO
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy Byte
7 6
DI
5
4
3
2 1
0
Data Out 2
Data Out 1
7 6
DO
5
4
MSB
3
2
1
0
7 6
MSB
5
4
3
2
1
0
7
MSB
Note: Address bits A23 to A20 are Don’t Care, for A25LQ080.
(April, 2016, Version 1.0)
18
AMIC Technology Corp.
A25LQ080 Series
Read Data Bytes at Higher Speed by Dual Output (FAST_READ_DUAL_OUTPUT)
The FAST_READ_DUAL_OUTPUT (3Bh) instruction is
similar to the FAST_READ (0Bh) instruction except the data
is output on two pins, IO0 and IO1, instead of just DO. This
allows data to be transferred from the A25LQ080 at twice the
rate of standard SPI devices.
Similar
to
the
FAST_READ
instruction,
the
FAST_READ_DUAL_OUTPUT instruction can operate at the
highest possible frequency of fC (See AC Characteristics).
This is accomplished by adding eight “dummy” clocks after
the 24-bit address as shown in figure 9. The dummy clocks
allow the device’s internal circuits additional time for setting
up the initial address. The input data during the dummy
clocks is “don’t care”. However, the IO0 and IO1 pins should
be high-impedance prior to the falling edge of the first data
out clock.
Figure 9. FAST_READ_DUAL_OUTPUT Instruction Sequence and Data-Out Sequence
S
0
1
2 3 4
5 6
7 8
9 10
28 29 30 31
C
Instruction (3Bh)
24-Bit Address
23 22 21
IO0
2
3
1
0
MSB
High Impedance
IO1
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
DIO switches from input to output
Dummy Byte
IO0
7 6
IO1
5
4
3
2 1
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
7 5
3
1
7
5
3
1
7 5
3
1
7
5
3
1
MSB
Data Out 1
Data Out 2
Data Out 3
7
MSB
MSB
Data Out 4
Note: Address bits A23 to A20 are Don’t Care, for A25LQ080.
(April, 2016, Version 1.0)
19
AMIC Technology Corp.
A25LQ080 Series
Read Data Bytes at Higher Speed by Dual Input and Dual Output (FAST_READ_DUAL_INPUT_OUTPUT)
The FAST_READ_DUAL_INPUT_OUTPUT (BBh) instruction
is similar to the FAST_READ (0Bh) instruction except the
data is input and output on two pins, IO0 and IO1, instead of
just DO. This allows data to be transferred from the
A25LQ080 at twice the rate of standard SPI devices.
Similar
to
the
FAST_READ
instruction,
the
FAST_READ_DUAL_INPUT_OUTPUT
instruction
can
operate at the highest possible frequency of fC (See AC
Characteristics).
Figure 10. FAST_READ_DUAL_INPUT_OUTPUT Instruction Sequence and Data-Out Sequence
S
0
1
2 3 4
5 6
7 8
9 10
16 17 18 19
C
Instruction (BBh)
24-Bit Address
22 20 18
IO0
6
4
2
0
7
5
3
1
MSB
High Impedance
IO1
23 21 19
S
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
C
Dummy
Byte
DIO switches from input to output
6
4
2
IO0
6
4
2
0
IO1
7
5
3
1 7 5 3
MSB
0 6
1
Data Out 1
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
7 5
3
1
7
5
3
1
7 5
3
1
7
5
3
1
MSB
MSB
Data Out 2
Data Out 3
Data Out 4
7
MSB
Data Out 5
Note: Address bits A23 to A20 are Don’t Care, for A25LQ080.
(April, 2016, Version 1.0)
20
AMIC Technology Corp.
A25LQ080 Series
Read Data Bytes at Higher Speed by Quad Output (FAST_READ_QUAD_OUTPUT)
This is accomplished by adding eight “dummy” clocks after
the 24-bit address as shown in figure 11. The dummy clocks
allow the device’s internal circuits additional time for setting
up the initial address. The input data during the dummy
clocks is “don’t care”. However, the IO pins should be
high-impedance prior to the falling edge of the first data out
clock.
The FAST_READ_QUAD_OUTPUT (6Bh) instruction is
similar to the FAST_READ (0Bh) instruction except the data
is output on four pins (IO0, IO1, IO2, IO3), instead of just DO.
This allows data to be transferred from the A25LQ080 at
quadruple the rate of standard SPI devices.
Similar
to
the
FAST_READ
instruction,
the
FAST_READ_QUAD_OUTPUT instruction can operate at
the highest possible frequency of fC (See AC Characteristics).
Figure 11. FAST_READ_QUAD_OUTPUT Instruction Sequence and Data-Out Sequence
S
0
1
2 3 4
5 6
7 8
9 10
28 29 30 31
C
Instruction (6Bh)
24-Bit Address
23 22 21
IO0
2
3
1
0
MSB
High Impedance
IO1,2,3
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
IO switches from input to output
Dummy Byte
IO0
7 6
5
4
3
2 1
0
4
0
4
0
4
0
4
0
4
IO1
5 1
5
1
5
1
5
1
5
IO2
6 2
6
2
6
2
6
2
6
IO3
7 3
7
3
7
3
7
3
7
Data Out 1Data Out 2Data Out 3Data Out 4
Note: Address bits A23 to A20 are Don’t Care, for A25LQ080.
(April, 2016, Version 1.0)
21
AMIC Technology Corp.
A25LQ080 Series
Read Data Bytes at Higher Speed by Quad Input and Quad Output (FAST_READ_QUAD_INPUT_OUTPUT)
Instruction.
Similar
to
the
FAST_READ
instruction,
the
FAST_READ_QUAD_INPUT_OUTPUT
instruction
can
operate at the highest possible frequency of fC (See AC
Characteristics).
The
FAST_READ_QUAD_INPUT_OUTPUT
(EBh)
instruction is similar to the FAST_READ (0Bh) instruction
except the data is input and output on four pins (IO3, IO2, IO1,
IO0) instead of just DO. This allows data to be transferred
from the A25LQ080 at quadruple the rate of standard SPI
devices. The Quad Enable bit (QE) of Status Register-2 must
be set to enable the FAST_READ_QUAD_INPUT_OUTPUT
Figure 12. FAST_READ_QUAD_INPUT_OUTPUT Instruction and Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
IO Switches from
Input to Output
Instruction (EBh)
IO0
20 16 12 8
4
0
4
0
4
0
4
IO1
21 17 13 9
5
1
5
1
5
1
5
IO2
22 18 14 10 6
2
6
2
6
2
6
23 19 15 11 7
3
7
3
7
3
7
IO3
A23-16 A15-8
A7-0
Dummy Dummy Dummy
Data out 1 Data out 2
Note: Address bits A23 to A20 are Don’t Care, for A25LQ080.
(April, 2016, Version 1.0)
22
AMIC Technology Corp.
A25LQ080 Series
Read OTP (ROTP)
000000h, allowing the read sequence to be continued
indefinitely.
The Read OTP (ROTP) instruction is terminated by driving
The device is first selected by driving Chip Select ( S ) Low.
The instruction code for the Read OTP (ROTP) instruction is
followed by a 3-byte address (A23- A0) and a dummy byte.
Each bit is latched in on the rising edge of Serial Clock (C).
Then the memory contents at that address are shifted out on
Serial Data output (DO).
Each bit is shifted out at the maximum frequency, fC(Max.) on
the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 13.
The address is automatically incremented to the next higher
address after each byte of data is shifted out. When the
highest address is reached, the address counter rolls over to
Chip Select ( S ) High. Chip Select ( S ) can be driven High at
any time during data output. Any Read OTP (ROTP)
instruction issued while an Erase, Program or Write Status
Register cycle is in progress, is rejected without having any
effect on the cycle that is in progress.
Figure 13. Read OTP (ROTP) instruction and data-out sequence
S
0
1
2 3 4
5 6
7 8
28 29 30 31
9 10
C
Instruction
(4Bh or 48h)
24-Bit Address
DI
23 22 21
2
3
1
0
MSB
High Impedance
DO
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy Byte
DI
7 6
5
4
DO
3
2 1
0
7 6
5
4
3
2
1 0
MSB
7 6
5
4
3
2
MSB
Data Out 1
1
0
7
MSB
Data Out n
Note: A23 to A6 are don’t care. (1 ≤ n ≤ 64)
(April, 2016, Version 1.0)
23
AMIC Technology Corp.
A25LQ080 Series
Program OTP (POTP)
completed. At some unspecified time before the cycle is
complete, the Write Enable Latch (WEL) bit is reset.
The Program OTP instruction (POTP) is used to program at
most 64 bytes to the OTP memory area (by changing bits
from 1 to 0, only). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded,
the device sets the Write Enable Latch (WEL) bit.
The Program OTP instruction is entered by driving Chip
To lock the OTP memory:
Bit 0 of the OTP control byte, that is byte 63, (see Figure 14)
is used to permanently lock the OTP memory array.
• When bit 0 of byte 63 = ’1’, the OTP memory array can be
programmed.
• When bit 0 of byte 63 = ‘0’, the OTP memory array are
read-only and cannot be programmed anymore.
Once a bit of the OTP memory has been programmed to ‘0’,
it can no longer be set to ‘1’.
Therefore, as soon as bit 0 of address 63h (control byte) is
set to ‘0’, the 64 bytes of the OTP memory array become
read-only in a permanent way.
Any Program OTP (POTP) instruction issued while an Erase,
Program or Write Status Register cycle is in progress is
rejected without having any effect on the cycle that is in
progress.
Select ( S ) Low, followed by the instruction code, three
address bytes and at least one data byte on Serial Data input
(DI).
Chip Select ( S ) must be driven High after the eighth bit of
the last data byte has been latched in, otherwise the
Program OTP instruction is not executed.
The instruction sequence is shown in Figure 14.
As soon as Chip Select ( S ) is driven High, the self-timed
Page Program cycle (whose duration is tPP) is initiated. While
the Program OTP cycle is in progress, the Status Register
may be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Program OTP cycle, and it is 0 when it is
Figure 14. Program OTP (POTP) instruction sequence
S
0
1
2 3 4
5 6
7 8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction (42h)
24-Bit Address
23 22 21
DI
2
3
Data Byte 1
1
0
MSB
7 6
5
0
4
3 2
1
0
MSB
S
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
C
Data Byte 2
DI
7 6
5
4
3
2 1
Data Byte 3
0
7 6
5
4
3
2
MSB
Data Byte n
1 0
7 6
5
MSB
4
3
2
1
0
7
MSB
Note: A23 to A6 are don’t care. (1 ≤ n ≤ 64)
(April, 2016, Version 1.0)
24
AMIC Technology Corp.
A25LQ080 Series
Figure 15. How to permanently lock the 64 OTP bytes
64 Data Byte
OTP Control Byte
Byte Byte Byte
0
1
2
Byte Byte
62
63
Bit
7
(April, 2016, Version 1.0)
Bit
6
Bit
5
Bit
4
25
Bit
3
Bit
2
Bit
1
Bit
0
When bit 0 =0
the OTP bytes
become READ only
AMIC Technology Corp.
A25LQ080 Series
Page Program (PP)
The Page Program (PP) instruction allows bytes to be
programmed in the memory (changing bits from 1 to 0).
Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL).
programmed correctly within the same page. If less than 256
Data bytes are sent to device, they are correctly programmed
at the requested addresses without having any effects on the
other bytes of the same page.
Chip Select ( S ) must be driven High after the eighth bit of the
last data byte has been latched in, otherwise the Page
Program (PP) instruction is not executed.
The Page Program (PP) instruction is entered by driving Chip
Select ( S ) Low, followed by the instruction code, three
address bytes and at least one data byte on Serial Data Input
(DI). If the 8 least significant address bits (A7-A0) are not all
zero, all transmitted data that goes beyond the end of the
current page are programmed from the start address of the
same page (from the address whose 8 least significant bits
As soon as Chip Select ( S ) is driven High, the self-timed
Page Program cycle (whose duration is tPP) is initiated. While
the Page Program cycle is in progress, the Status Register
may be read to check the value of the Write In Progress (WIP)
bit. The Write In Progress (WIP) bit is 1 during the self-timed
Page Program cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write
Enable Latch (WEL) bit is reset.
(A7-A0) are all zero). Chip Select ( S ) must be driven Low for
the entire duration of the sequence.
The instruction sequence is shown in Figure 16. If more than
256 bytes are sent to the device, previously latched data are
discarded and the last 256 data bytes are guaranteed to be
A Page Program (PP) instruction applied to a page which is
protected by the Block Protect (CMP, SEC, TB, BP2, BP1,
BP0) bits (see table 1) is not executed.
Figure 16. Page Program (PP) Instruction Sequence
S
0
1
2 3 4
5 6
7 8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction (02h)
23 22 21
3
2
1
MSB
0
5
7 6
4
3
1
2
0
S
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2073
2074
2075
2076
2077
2078
2079
MSB
2072
DI
Data Byte 1
24-Bit Address
C
Data Byte 2
DI
7 6
MSB
5
4
3
2
Data Byte 3
1
0
7 6
5
4
MSB
3
2
Data Byte 256
1
0
7 6
5
4
3
2
1
0
MSB
Note: Address bits A23 to A20 are Don’t Care, for A25LQ080.
(April, 2016, Version 1.0)
26
AMIC Technology Corp.
A25LQ080 Series
Dual Input Fast Program (DIFP)
The Dual Input Fast Program (DIFP) instruction is very
similar to the Page Program (PP) instruction, except that the
data are entered on two pins IO0 and IO1 instead of only one.
Inputting the data on two pins instead of one doubles the
data transfer bandwidth compared to the Page Program (PP)
instruction.
The Dual Input Fast Program (DIFP) instruction is entered by
correctly programmed at the requested addresses without
having any effects on the other bytes in the same page.
For optimized timings, it is recommended to use the Dual
Input Fast Program (DIFP) instruction to program all
consecutive targeted bytes in a single sequence rather to
using several Dual Input Fast Program (DIFP) sequences
each containing only a few bytes.
driving Chip Select ( S ) Low, followed by the instruction code,
three address bytes and at least one data byte on Serial
Data Output (IO0 and IO1).
If the 8 least significant address bits (A7-A0) are not all zero,
all transmitted data that goes beyond the end of the current
page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0)
Chip Select ( S ) must be driven High after the eighth bit of
the last data byte has been latched in, otherwise the Dual
Input Fast Program (DIFP) instruction is not executed.
As soon as Chip Select ( S ) is driven High, the self-timed
Page Program cycle (whose duration is tPP) is initiated. While
the Dual Input Fast Program (DIFP) cycle is in progress, the
Status Register may be read to check the value of the Write
In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Page Program cycle, and 0 when it is
completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
A Dual Input Fast Program (DIFP) instruction applied to a
page that is protected by the Block Protect (CMP, SEC, TB,
BP2, BP1, BP0) bits (see Table 1) is not executed.
are all zero). Chip Select ( S ) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 17.
If more than 256 bytes are sent to the device, previously
latched data are discarded and the last 256 data bytes are
guaranteed to be programmed correctly within the same
page. If less than 256 data bytes are sent to device, they are
Figure 17. Dual Input Fast Program (DIFP) instruction sequence
S
0
1
2 3 4
5 6
7 8
9 10
28 29 30 31
C
Instruction (A2h)
24-Bit Address
23 22 21
IO0
2
3
1
0
MSB
High Impedance
IO1
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
IO0
6 4
2
0
6
Data In 1
IO1
7 5
MSB
3
4 2
0
6
Data In 2
1
7
5 3
MSB
4
2
0
6
Data In 3
1
7
5
MSB
3
4
2
0
6
4
Data In 4
1
7
5
MSB
3
2
0
6
Data In 5
1
7
5
MSB
3
1
4
2
0
Data In 256
7
5
3
1
MSB
Note: Address bits A23 to A20 are Don’t Care, for A25LQ080.
(April, 2016, Version 1.0)
27
AMIC Technology Corp.
A25LQ080 Series
Quad Input Fast Program (QIFP)
page. If less than 256 data bytes are sent to device, they are
correctly programmed at the requested addresses without
having any effects on the other bytes in the same page.
For optimized timings, it is recommended to use the Quad
Input Fast Program (QIFP) instruction to program all
consecutive targeted bytes in a single sequence rather to
using several Quad Input Fast Program (QIFP) sequences
each containing only a few bytes.
The Quad Input Fast Program (QIFP) instruction is very
similar to the Page Program (PP) instruction, except that the
data are entered on four pins (IO3, IO2, IO1, IO0) instead of
only one. Inputting the data on four pins instead of one
quadruples the data transfer bandwidth compared to the
Page Program (PP) instruction. To use Quad Input Fast
Program the Quad Enable bit (QE) of Status Register-2 must
be set.
The Quad Input Fast Program (QIFP) instruction is entered
Chip Select ( S ) must be driven High after the eighth bit of
the last data byte has been latched in, otherwise the Quad
Input Fast Program (QIFP) instruction is not executed.
by driving Chip Select ( S ) Low, followed by the instruction
code, three address bytes and at least one data byte on Data
Input Output (IO3, IO2, IO1, IO0).
If the 8 least significant address bits (A7-A0) are not all zero,
all transmitted data that goes beyond the end of the current
page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0)
As soon as Chip Select ( S ) is driven High, the self-timed
Page Program cycle (whose duration is tPP) is initiated. While
the Quad Input Fast Program (QIFP) cycle is in progress, the
Status Register may be read to check the value of the Write
In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Page Program cycle, and 0 when it is
completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
A Quad Input Fast Program (QIFP) instruction applied to a
page that is protected by the Block Protect (CMP, SEC, TB,
BP2, BP1, BP0) bits (see Table 1) is not executed.
are all zero). Chip Select ( S ) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 18.
If more than 256 bytes are sent to the device, previously
latched data are discarded and the last 256 data bytes are
guaranteed to be programmed correctly within the same
Figure 18. Quad Input Fast Program (QIFP) instruction sequence
S
0
1
2 3 4
5 6
7 8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction (32h)
24-Bit Address
23 22 21
3
2
Byte 1 Byte 2 Byte 3 Byte 4
1
0
4
0
4
0
4
0
4
0
IO1
5
1
5
1
5
1
5
1
IO2
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
3
IO0
MSB
IO3
MSB
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
536
537
538
539
540
541
542
543
S
C
Byte 5 Byte 6 Byte 7 Byte 8 Byte 9 Byte 10Byte 11 Byte 12 Byte 253 Byte 254Byte 255 Byte 256
IO0
4 0
4
0
4
0
4
0
4 0
4
0
4
0
4
0
4 0
4
0
4
0
4
0
IO1
5 1
5
1
5
1
5
1
5 1
5
1
5
1
5
1
5 1
5
1
5
1
5
1
IO2
6 2
6
2
6
2
6
2
6 2
6
2
6
2
6
2
6 2
6
2
6
2
6
2
IO3
7 3
7
3
7
3
7
3
7 3
7
3
7
3
7
3
7 3
7
3
7
3
7
3
Note: Address bits A23 to A20 are Don’t Care, for A25LQ080
(April, 2016, Version 1.0)
28
AMIC Technology Corp.
A25LQ080 Series
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits
inside the chosen sector. Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip
instruction is not executed. As soon as Chip Select ( S ) is
driven High, the self-timed Sector Erase cycle (whose
duration is tSE) is initiated. While the Sector Erase cycle is in
progress, the Status Register may be read to check the value
of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Sector Erase cycle, and is
0 when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is
protected by the Block Protect (CMP, SEC, TB, BP2, BP1,
BP0) bits (see table 1) is not executed.
Select ( S ) Low, followed by the instruction code on Serial
Data Input (DI). Chip Select ( S ) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 19. Chip Select
( S ) must be driven High after the eighth bit of the instruction
code has been latched in, otherwise the Sector Erase
Figure 19. Sector Erase (SE) Instruction Sequence
S
0
1
2 3 4
5 6
7 8
9 10
28 29 30 31
C
Instruction (20h)
DI
24-Bit Address
23 22 21
3
2
1
0
MSB
Note: Address bits A23 to A20 are Don’t Care, for A25LQ080.
(April, 2016, Version 1.0)
29
AMIC Technology Corp.
A25LQ080 Series
Block Erase (BE)
The Block Erase (BE) instruction sets to 1 (FFh) all bits inside
the chosen block. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded,
the device sets the Write Enable Latch (WEL).
The Block Erase (BE) instruction is entered by driving Chip
instruction is not executed. As soon as Chip Select ( S ) is
driven High, the self-timed Block Erase cycle (whose duration
is tBE) is initiated. While the Block Erase cycle is in progress,
the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit
is 1 during the self-timed Block Erase cycle, and is 0 when it
is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
A Block Erase (BE) instruction applied to a page which is
protected by the Block Protect (CMP, SEC, TB, BP2, BP1,
BP0) bits (see table 1) is not executed.
Select ( S ) Low, followed by the instruction code on Serial
Data Input (DI). Chip Select ( S ) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 20. Chip Select
( S ) must be driven High after the eighth bit of the instruction
code has been latched in, otherwise the Block Erase
Figure 20. Block Erase (BE) Instruction Sequence
S
0
1
2 3 4
5 6
7 8
9 10
28 29 30 31
C
24-Bit Address
Instruction (D8h or 52h)
DI
23 22 21
3
2
1
0
MSB
Note: Address bits A23 to A20 are Don’t Care, for A25LQ080.
(April, 2016, Version 1.0)
30
AMIC Technology Corp.
A25LQ080 Series
Chip Erase (CE)
The Chip Erase (CE) instruction sets all bits to 1 (FFh). Before
it can be accepted, a Write Enable (WREN) instruction must
previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL).
The Chip Erase (CE) instruction is entered by driving Chip
code has been latched in, otherwise the Chip Erase
instruction is not executed. As soon as Chip Select ( S ) is
driven High, the self-timed Chip Erase cycle (whose duration
is tCE) is initiated. While the Chip Erase cycle is in progress,
the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is
1 during the self-timed Chip Erase cycle, and is 0 when it is
completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Chip Erase (CE) instruction is ignored if one, or more,
sectors/blocks are protected.
Select ( S ) Low, followed by the instruction code on Serial
Data Input (DI). Chip Select ( S ) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 21. Chip Select
( S ) must be driven High after the eighth bit of the instruction
Figure 21. Chip Erase (CE) Instruction Sequence
S
0
1
2
3
4 5
6
7
C
Instruction
(C7h or 60h)
DI
(April, 2016, Version 1.0)
31
AMIC Technology Corp.
A25LQ080 Series
Deep Power-down (DP)
The Deep Power-down mode automatically stops at
Power-down, and the device always Powers-up in the
Standby mode.
The Deep Power-down (DP) instruction is entered by driving
Executing the Deep Power-down (DP) instruction is the only
way to put the device in the lowest consumption mode (the
Deep Power-down mode). It can also be used as an extra
software protection mechanism, while the device is not in
active use, since in this mode, the device ignores all Write,
Program and Erase instructions.
Chip Select ( S ) Low, followed by the instruction code on
Serial Data Input (DI). Chip Select ( S ) must be driven Low for
the entire duration of the sequence. The instruction sequence
is shown in Figure 22.
Driving Chip Select ( S ) High deselects the device, and puts
the device in the Standby mode (if there is no internal cycle
currently in progress). But this mode is not the Deep
Power-down mode. The Deep Power-down mode can only be
entered by executing the Deep Power-down (DP) instruction,
to reduce the standby current (from ICC1 to ICC2, as specified in
DC Characteristics Table.).
Chip Select ( S ) must be driven High after the eighth bit of the
instruction code has been latched in, otherwise the Deep
Power-down (DP) instruction is not executed. As soon as
Chip Select ( S ) is driven High, it requires a delay of tDP
before the supply current is reduced to ICC2 and the Deep
Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an Erase,
Program or Write Status Register cycle is in progress, is
rejected without having any effects on the cycle that is in
progress.
Once the device has entered the Deep Power-down mode, all
instructions are ignored except the Release from Deep
Power-down and Read Electronic Signature (RES) instruction.
This releases the device from this mode. The Release from
Deep Power-down and Read Electronic Signature (RES)
instruction also allows the Electronic Signature of the device
to be output on Serial Data Output (DO).
Figure 22. Deep Power-down (DP) Instruction Sequence
S
0
1
2
3
4 5
6
tDP
7
C
Instruction (B9h)
DI
Stand-by Mode
(April, 2016, Version 1.0)
32
Deep Power-down Mode
AMIC Technology Corp.
A25LQ080 Series
Read Device Identification (RDID)
The Read Identification (RDID) instruction allows the 8-bit
manufacturer identification code to be read, followed by two
bytes of device identification. The manufacturer identification
is assigned by JEDEC, and has the value 37h. The device
identification is assigned by the device manufacturer, and
indicates the memory in the first byte (40h), and the memory
capacity of the device in the second byte (14h for
A25LQ080).
Any Read Identification (RDID) instruction while an Erase, or
Program cycle is in progress, is not decoded, and has no
effect on the cycle that is in progress.
This is followed by the 24-bit device identification, stored in
the memory, being shifted out on Serial Data Output (DO),
each bit being shifted out during the falling edge of Serial
Clock (C).
The instruction sequence is shown in Figure 23. The Read
Identification (RDID) instruction is terminated by driving Chip
Select ( S ) High at any time during data output.
When Chip Select ( S ) is driven High, the device is put in the
Stand-by Power mode. Once in the Stand-by Power mode,
the device waits to be selected, so that it can receive, decode
and execute instructions.
The device is first selected by driving Chip Select ( S ) Low.
Then, the 8-bit instruction code for the instruction is shifted in.
Table 6. Read Identification (READ_ID) Data-Out Sequence
Manufacture Identification
Device Identification
Manufacture ID
Memory Type
Memory Capacity
37h
40h
14h (A25LQ080)
Figure 23. Read Identification (RDID) Instruction Sequence and Data-Out Sequence
S
0 1
2
3
4
5
6
7
8
9 10
13 14 15 16 17 18
21 22 23 24 25 26
29 30 31
10
2
C
Instruction (9Fh)
IO0
IO1
23
High Impedance
(April, 2016, Version 1.0)
22 21
18
17 16 15
Manufacture ID
33
14 13
9
Memory Type
8
7
6
5
1
0
Memory Capacity
AMIC Technology Corp.
A25LQ080 Series
Read Electronic Manufacturer ID & Device ID (REMS)
The Read Electronic Manufacturer ID & Device ID (REMS)
instruction allows the 8-bit manufacturer identification code to
be read, followed by one byte of device identification. The
manufacturer identification is assigned by JEDEC, and has
the value 37h for AMIC. The device identification is assigned
by the device manufacturer, and has the value 13h for
A25LQ080.
Any Read Electronic Manufacturer ID & Device ID (REMS)
instruction while an Erase, or Program cycle is in progress, is
not decoded, and has no effect on the cycle that is in
progress.
If the one-byte address is set to 01h, then the device ID
be read first and then followed by the Manufacturer ID.
the other hand, if the one-byte address is set to 00h, then
Manufacturer ID will be read first and then followed by
device ID.
will
On
the
the
The instruction sequence is shown in Figure 24. The Read
Electronic Manufacturer ID & Device ID (REMS) instruction is
terminated by driving Chip Select ( S ) High at any time during
data output.
When Chip Select ( S ) is driven High, the device is put in the
Stand-by Power mode. Once in the Stand-by Power mode,
the device waits to be selected, so that it can receive, decode
and execute instructions.
The device is first selected by driving Chip Select ( S ) Low.
The 8-bit instruction code is followed by 2 dummy bytes and
one byte address (A7~A0), each bit being latched-in on Serial
Data Input (DI) during the rising edge of Serial Clock (C).
Table 7. Read Electronic Manufacturer ID & Device ID (REMS) Data-Out Sequence
Manufacture Identification
Device Identification
37h
13h (A25LQ080)
Figure 24. Read Electronic Manufacturer ID & Device ID (REMS) Instruction Sequence and Data-Out Sequence
S
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23
C
Instruction (90h)
2 Dummy Bytes
15 14 13
DI
3 2 1 0
MSB
DO
High Impedance
S
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
ADD(1)
DI
7 6 5 4 3 2 1 0
Manufacturer ID
Device ID
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
DO
MSB
MSB
MSB
Notes:
(1) ADD=00h will output the manufacturer ID first and ADD=01h will output device ID first
(April, 2016, Version 1.0)
34
AMIC Technology Corp.
A25LQ080 Series
Release from Deep Power-down and Read Electronic Signature (RES)
stored in the memory, is shifted out on Serial Data Output
(DO), each bit being shifted out during the falling edge of
Serial Clock (C).
The instruction sequence is shown in Figure 25.
The Release from Deep Power-down and Read Electronic
Signature (RES) instruction is terminated by driving Chip
Once the device has entered the Deep Power-down mode,
all instructions are ignored except the Release from Deep
Power-down and Read Electronic Signature (RES)
instruction. Executing this instruction takes the device out of
the Deep Power-down mode.
The instruction can also be used to read, on Serial Data
Output (DO), the 8-bit Electronic Signature, whose value for
A25LQ080 is 13h.
Select ( S ) High after the Electronic Signature has been read
at least once. Sending additional clock cycles on Serial Clock
Except while an Erase, Program or Write Status Register
cycle is in progress, the Release from Deep Power-down and
Read Electronic Signature (RES) instruction always provides
access to the 8-bit Electronic Signature of the device, and
can be applied even if the Deep Power-down mode has not
been entered.
(C), while Chip Select ( S ) is driven Low, cause the
Electronic Signature to be output repeatedly.
When Chip Select ( S ) is driven High, the device is put in the
Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by
Power mode is immediate. If the device was previously in the
Deep Power-down mode, though, the transition to the Stand-
Any Release from Deep Power-down and Read Electronic
Signature (RES) instruction while an Erase, Program or Write
Status Register cycle is in progress, is not decoded, and has
no effect on the cycle that is in progress.
by Power mode is delayed by tRES2, and Chip Select ( S )
must remain High for at least tRES2 (max), as specified in AC
Characteristics Table . Once in the Stand-by Power mode,
the device waits to be selected, so that it can receive, decode
and execute instructions.
The device is first selected by driving Chip Select ( S ) Low.
The instruction code is followed by 3 dummy bytes, each bit
being latched-in on Serial Data Input (DI) during the rising
edge of Serial Clock (C). Then, the 8-bit Electronic Signature,
Figure 25. Release from Deep Power-down and Read Electronic Signature (RES) Instruction Sequence and
Data-Out Sequence
S
0
1
2 3 4
5 6
7 8
9 10
28 29 30 31 32 33 34 35 36 37 38
C
Instruction (ABh)
23 22 21
DI
tRES2
3 Dummy Bytes
3
2
1
0
MSB
DO
High Impedance
7 6
5
4
3
2
1
0
MSB
Deep Power-down Mode
Stand-by Mode
Note: The value of the 8-bit Electronic Signature, for A25LQ080 is 13h.
(April, 2016, Version 1.0)
35
AMIC Technology Corp.
A25LQ080 Series
Figure 26. Release from Deep Power-down (RES) Instruction Sequence
S
C
0
1
2
3
4 5
6
tRES1
7
Instruction (ABh)
DI
DO
High Impedance
Deep Power-down Mode
Driving Chip Select ( S ) High after the 8-bit instruction byte
has been received by the device, but before the whole of the
8-bit Electronic Signature has been transmitted for the first
time (as shown in Figure 26.), still insures that the device is
put into Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the
Stand-by Power mode is immediate. If the device was
(April, 2016, Version 1.0)
Stand-by Mode
previously in the Deep Power-down mode, though, the
transition to the Stand-by Power mode is delayed by tRES1,
and Chip Select ( S ) must remain High for at least tRES1 (max),
as specified in AC Characteristics Table. Once in the
Stand-by Power mode, the device waits to be selected, so
that it can receive, decode and execute instructions.
36
AMIC Technology Corp.
A25LQ080 Series
High Performance Mode (A3h)
The High Performance Mode (HPM) instruction can be
executed prior to Dual or Quad I/O instructions if chip is
operated at high frequencies. This instruction allows
pre-charging of internal charge pumps so the voltages
required for accessing the Flash memory array are readily
available. The instruction sequence includes the A3h
instruction code followed by three dummy byte clocks shown
in Fig.28. After the HPM instruction is executed, the device
will maintain a slightly higher standby current than standard
SPI operation. The Release from Power-down (ABh) can be
used to return to standard SPI standby current (ICC1). In
addition, Write Enable instruction (06h) and Power Down
instruction (B9h) will also release the device from HPM mode
back to standard SPI standby state.
Figure 27. High Performance Mode Instruction Sequence
S
0
1
2 3 4
5 6
7 8
9 10
28 29 30 31
C
Instruction (A3)
DI
23 22 21
3
MSB
2
1
0
High Performance
Current
DO
(April, 2016, Version 1.0)
tRES2
3 Dummy Bytes
37
AMIC Technology Corp.
A25LQ080 Series
Program / Erase Suspend
The Suspend instruction allows the system to interrupt a
Sector or Block Erase operation or a Page Program
operation and then read from or program data to, any other
sectors or blocks. The Suspend instruction sequence is
shown in figure 29.
The Write Status Register instruction (01h) and Erase
instructions (20h, 52h, D8h, C7h, 60h) are not allowed during
Erase Suspend. Erase Suspend is valid only during the
Sector or Block erase operation. If written during the Chip
Erase operation, the Erase Suspend instruction is ignored.
The Write Status Register instruction (01h) and Page
Program instructions (02h) are not allowed during Program
Suspend. Program Suspend is valid only during the Page
Program operation.
The Suspend instruction will be accepted by the device only
if the SUS bit in the Status Register equals to 0 and the WIP
bit equals to 1 while a Sector or Block Erase or a Page
Program operation is on-going. If the SUS bit equals to 1 or
the BUSY bit equals to 0, the Suspend instruction will be
ignored by the device. A maximum of time of “tSUS” (See AC
Characteristics) is required to suspend the erase or program
operation. The WIP bit in the Status Register will be cleared
from 1 to 0 within “tSUS” and the SUS bit in the Status
Register will be set from 0 to 1 immediately after
Program/Erase Suspend. For a previously resumed
Program/Erase operation, it is also required that the Suspend
instruction is not issued earlier than a minimum of time of
“tSUS” following the preceding Resume instruction.
Unexpected power off during the Program/Erase suspend
state will reset the device and release the suspend state.
SUS bit in the Status Register will also reset to 0. The data
within the page, sector or block that was being suspended
may become corrupted. It is recommended for the user to
implement system design techniques against the accidental
power interruption and preserve data integrity during
Program/Erase suspend state.
Figure 28. Suspend Instruction Sequence
S
0
1
2
3
4 5
6
tSUS
7
C
Instruction (75h or B0h)
DIO
High Impedance
DO
Accept Read or Program
Instruction
Table 8. Operations Allowed and Not Allowed During a Program or Erase Suspend
Command
Operation During Program Suspend
Operation During Erase Suspend
Allowed
Allowed
Read Commands
Read Data
Program and Erase Commands
PP
Not Allowed
Allowed
SE/ BE/ CE
Not Allowed
Not Allowed
Allowed
Allowed
Not Allowed
Not Allowed
SUSPEND
Not Allowed
Not Allowed
RESUME
Allowed
Allowed
HPM
Allowed
Allowed
Status Register Commands
RDSR-1/ RDSR-2
WRSR
Other Commands
WREN
Allowed
Allowed
WRDI
Allowed
Allowed
RDID/ REMS/ RES/ SFDP
Allowed
Allowed
Not Allowed
Not Allowed
DP
(April, 2016, Version 1.0)
38
AMIC Technology Corp.
A25LQ080 Series
Program / Erase Resume
The Resume instruction must be written to resume the Sector
or Block Erase operation or the Page Program operation
after a Program/Erase Suspend. The Resume instruction will
be accepted by the device only if the SUS bit in the Status
Register equals to 1 and the WIP bit equals to 0. After issued
the SUS bit will be cleared from 1 to 0 immediately, the WIP
bit will be set from 0 to 1 within 200ns and the Sector or
Block will complete the erase operation or the page will
complete the program operation. If the SUS bit equals to 0 or
the WIP bit equals to 1, the Resume instruction will be
ignored by the device. The Resume instruction sequence is
shown in figure 30.
Resume instruction is ignored if the previous Program/Erase
Suspend operation was interrupted by unexpected power off.
It is also required that a subsequent Program/Erase Suspend
instruction not to be issued within a minimum of time of “tSUS”
following a previous Resume instruction.
Figure 29. Resume Instruction Sequence
S
0
1
2
3
4 5
6
7
C
Instruction (7Ah or 30h)
DIO
DO
High Impedance
Resume Sector or Block Erase
(April, 2016, Version 1.0)
39
AMIC Technology Corp.
A25LQ080 Series
Read SFDP Register (5Ah)
The A25LQ080 features a 64-Byte Serial Flash Discoverable
Parameter (SFDP) register that contains information about
devices operational capability such as available commands,
timing and other features.
The SFDP parameters are stored in one or more Parameter
Identification (PID) tables. Currently only one PID table is
specified but more may be added in the future. The Read
SFDP Register instruction is compatible with the JEDEC
SFDP standard (JESD216) established in 2011.
The Read SFDP instruction is initiated by driving Chip Select
( S ) Low and shifting the instruction code “5Ah” followed by a
24-bit address (A23-A0)(1) into the DIO pin. Eight “dummy”
clocks are also required before the SFDP register contents
are shifted out on the falling edge of the 40th Serial Clock (C)
with most significant bit (MSB) first as shown in figure 31. For
SFDP register values and descriptions, refer to the following
SFDP Definition table.
Note: 1. A23-A6 = 0; A5-A0 are used to define the starting
byte address for the 64-Byte SFDP Register.
Figure 30. Read SFDP Register Instruction Sequence Diagram
S
0
1
2 3 4
5 6
7 8
9 10
28 29 30 31
C
Instruction (5Ah)
24-Bit Address
23 22 21
DIO
2
3
1
0
High Impedance
DO
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy Byte
DIO
7 6
5
4
3
2 1
0
Data Out 2
Data Out 1
DO
7 6
5
4
3
MSB
(April, 2016, Version 1.0)
2
1
0
7 6
MSB
40
5
4
3
2
1
0
7
MSB
AMIC Technology Corp.
A25LQ080 Series
Table 9. SFDP Definition table
Description
Address(h)
Address (Bit)
Data
00h
7:0
53h
01h
15:8
46h
02h
23:16
44h
03h
31:24
50h
Minor Revision
04h
7:0
00h
Start from 0x00
Major Revision
05h
15:8
01h
Start from 0x01
Number of Parameter Header
06h
23:16
00h
Reserved
07h
31:24
FFh
Parameter ID(0)
08h
7:0
00h
Parameter Minor Revision
09h
15:8
00h
Start from 0x00
Parameter Major Revision
0Ah
23:16
01h
Start from 0x01
Parameter Length (in DW)
0Bh
31:24
09h
0Eh:0Ch
23:00
000010h
0Fh
31:24
FFh
SPI Flash Discoverability Parameters (SFDP)
Signature
SFDP
Revision
Parameter Table Pointer
Reserved
(April, 2016, Version 1.0)
(Byte Mode)
41
Comment
Hex: 50444653
Reserved
Reserved
AMIC Technology Corp.
A25LQ080 Series
Parameter ID (0)
Description
Address(h)
(Byte Mode)
Address (Bit)
Data
Comment
00= reserved
Block/Sector Erase Sizes
01:00
01
01=4KB erase
10= reserved
11=64KB erase
Write Granularity
02
1
Write Enable Command Required for
Writing to Volatile Status Register
03
0
Write Enable Opcode Select for Writing
to Volatile Status Register
04
0
07:05
7h
15:08
20h
16
1
10h
Unused
4Kilo Byte Erase Opcode
11h
Supports Single Input Address Dual
Output Fast read
0=1Byte 1=64Byte
Reserved
4KB Erase Support
(FFh=not supported)
0=not supported
1=support
00=3 byte
Number of bytes used in addressing for
flash array read, write and erase
18:17
00
01=3 byte or 4byte
10= 4-byte only
11= reserved
Supports Dual Transfer Rate Clocking
0=not supported
19
0
Supports Dual Input Address Dual
Output Fast read
20
1
Supports Quad Input Address Quad
Output Fast read
21
1
Supports Single Input Address Quad
Output Fast read
22
1
23
1
13h
31:24
FFh
17h to 14h
31:00
007FFFFFh
Unused
Flash Size in bits
(April, 2016, Version 1.0)
12h
42
1=support
0=not supported
1=support
0=not supported
1=support
0=not supported
1=support
Reserved
8Mb
AMIC Technology Corp.
A25LQ080 Series
Parameter ID (0) (Continued)
Address(h)
Description
Address (Bit)
Data
04:00
00110
Comment
(Byte Mode)
Quad Input Address Quad Output Fast
Read Number of Wait States(dummy
bits) needed before valid output
This filed should be
counted in clocks.
18h
Quad Input Address Quad Output Fast
Read Number of Mode Bits
Quad Input Address Quad Output Fast
Read Opcode
Single Input Address Quad Output Fast
Read Number of Wait States(dummy
bits) needed before valid output
19h
Single Input Address Dual Output Fast
Read Number of Wait States(dummy
bits) needed before valid output
Dual Input Address Dual Output Fast
Read Number of Wait States(dummy
bits) needed before valid output
1Bh
(April, 2016, Version 1.0)
EBh
20:16
01000
23:21
000
31:24
6Bh
04:00
01000
This filed should be
counted in clocks.
1Ch
1Dh
07:05
000
15:08
3Bh
20:16
00100
This filed should be
counted in clocks.
1Eh
Dual Input Address Dual Output Fast
Read Number of Mode Bits
Dual Input Address Dual Output Fast
Read Opcode
15:08
This filed should be
counted in clocks.
Single Input Address Dual Output Fast
Read Number of Mode Bits
Single Input Address Dual Output Fast
Read Opcode
000
1Ah
Single Input Address Quad Output Fast
Read Number of Mode Bits
Single Input Address Quad Output Fast
Read Opcode
07:05
1Fh
43
23:21
000
31:24
BBh
AMIC Technology Corp.
A25LQ080 Series
Parameter ID (0) (Continued)
Description
Address(h)
(Byte Mode)
Address (Bit)
Data
Comment
0
0
not supported
03:01
7h
04
0
07:05
7h
Supports (2-2-2) Fast Read
Reserved
Supports (4-4-4) Fast Read
20h
Reserved
not supported
Reserved
23h to 21h
31:08
FFFFFFh
Reserved
25h to 24h
15:0
FFFFh
20:16
00000
23:21
000
27h
31:24
00h
29h to 28h
15:0
FFFFh
20:16
00000
23:21
000
(2-2-2) Fast Read Number of Wait States
(2-2-2) Fast Read Number of Mode Bits
(2-2-2) Fast Read Opcode
Reserved
(4-4-4) Fast Read Number of Wait States
(4-4-4) Fast Read Number of Mode Bits
26h
2Ah
(4-4-4) Fast Read Opcode
2Bh
31:24
00h
Sector Type 1 Size (4KB)
2Ch
07:00
0Ch
Sector Type 1 Opcode
2Dh
15:08
20h
Sector Type 2 Size (32KB)
2Eh
23:16
00h
Sector Type 2 Opcode
2Fh
31:24
00h
Sector Type 3 Size (64KB)
30h
07:00
10h
Sector Type 3 Opcode
31h
15:08
D8h
Sector Type 4 Size (256KB)
32h
23:16
00h
Sector Type 4 Opcode
33h
31:24
00h
not supported
not supported
not supported
not supported
Notes:
1. Data stored in Byte Address 34h to 3Fh are Reserved, the value is FFh.
(April, 2016, Version 1.0)
44
AMIC Technology Corp.
A25LQ080 Series
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must not be
selected (that is Chip Select ( S ) must follow the voltage
applied on VCC) until VCC reaches the correct value:
­
­
VCC (min) at Power-up, and then for a further delay of tVSL
VSS at Power-down
Usually a simple pull-up resistor on Chip Select ( S ) can be
used to insure safe and proper Power-up and Power-down.
To avoid data corruption and inadvertent write operations
during power up, a Power On Reset (POR) circuit is included.
The logic inside the device is held reset while VCC is less than
the POR threshold value, VWI – all operations are disabled,
and the device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN),
Program OTP (POTP), Page Program (PP), Dual Input Fast
Program (DIFP), Quad Input Fast Program (QIFP), Sector
Erase (SE), Block Erase (BE), Chip Erase (CE) and Write
Status Register (WRSR) instructions until a time delay of tPUW
has elapsed after the moment that VCC rises above the VWI
threshold. However, the correct operation of the device is not
guaranteed if, by this time, VCC is still below VCC(min). No
Write Status Register, Program or Erase instructions should
be sent until the later of:
­ tPUW after VCC passed the VWI threshold
- tVSL afterVCC passed the VCC(min) level
These values are specified in Table 9.
If the delay, tVSL, has elapsed, after VCC has risen above
VCC(min), the device can be selected for Read instructions
even if the tPUW delay is not yet fully elapsed.
At Power-up, the device is in the following state:
The device is in the Standby mode (not the Deep
Power-down mode).
­ The Write Enable Latch (WEL) bit is reset.
Normal precautions must be taken for supply rail decoupling,
to stabilize the VCC feed. Each device in a system should
have the VCC rail decoupled by a suitable capacitor close to
the package pins. (Generally, this capacitor is of the order of
0.1µF).
At Power-down, when VCC drops from the operating voltage,
to below the POR threshold value, VWI, all operations are
disabled and the device does not respond to any instruction.
(The designer needs to be aware that if a Power-down occurs
while a Write, Program or Erase cycle is in progress, some
data corruption can result.)
­
Figure 31. Power-up Timing
VCC
VCC(max)
VCC(min)
Reset
State
tVSL
VWI
Read
Access
allowed
Full Device Access
tPUW
time
(April, 2016, Version 1.0)
45
AMIC Technology Corp.
A25LQ080 Series
Table 9. Power-Up Timing
Symbol
Parameter
Min.
Max.
Unit
tVSL
VCC(min) to S Low
10
μs
tPUW
Time Delay Before Write Instruction
3
ms
VWI
Write Inhibit Threshold Voltage
2.3
2.5
V
Note: These parameters are characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains
00h (all Status Register bits are 0).
(April, 2016, Version 1.0)
46
AMIC Technology Corp.
A25LQ080 Series
Absolute Maximum Ratings*
*Comments
Storage Temperature (TSTG) . . . . . . . . . . -65°C to + 150°C
Lead Temperature during Soldering (Note 1)
D.C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6V to VCC+0.6V
Transient Voltage (<20ns) on Any Pin to Ground Potential . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VCC+2.0V
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . -0.6V to +4.0V
Electrostatic Discharge Voltage (Human Body model)
(VESD) (Note 2) . . . . . . . . . . . . . . . . . . . -2000V to 2000V
Stressing the device above the rating listed in the Absolute
Maximum Ratings" table may cause permanent damage to
the device. These are stress ratings only and operation of
the device at these or any other conditions above those
indicated in the Operating sections of this specification is not
implied. Exposure to Absolute Maximum Rating conditions
for extended periods may affect device reliability. Refer also
to the AMIC SURE Program and other relevant quality
documents.
Notes:
1. Compliant with JEDEC Std J-STD-020B (for small body,
Sn-Pb or Pb assembly).
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω ,
R2=500Ω)
DC AND AC PARAMETERS
This section summarizes the operating and measurement
conditions, and the DC and AC characteristics of the device.
The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the
Measurement Conditions summarized in the relevant tables.
Designers should check that the operating conditions in their
circuit match the measurement conditions when relying on
the quoted parameters.
Table 10. Operating Conditions
Symbol
Parameter
Min.
Max.
Unit
VCC
Supply Voltage
2.7
3.6
V
TA
Ambient Operating Temperature
–40
85
°C
Table 11. Data Retention and Endurance
Parameter
Condition
Min.
Max.
Unit
Erase/Program Cycles
At 85°C
100,000
Cycles
Data Retention
At 85°C
20
Years
Table 12. Capacitance
Symbol
Parameter
COUT
Output Capacitance (DO)
CIN
Input Capacitance (other pins)
Test Condition
Min.
Max.
Unit
VOUT = 0V
8
pF
VIN = 0V
6
pF
Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 33 MHz.
(April, 2016, Version 1.0)
47
AMIC Technology Corp.
A25LQ080 Series
Table 13. DC Characteristics
Symbol
Parameter
Test Condition
Min.
Max.
Unit
ILI
Input Leakage Current
±2
µA
ILO
Output Leakage Current
±2
µA
ICC1
Standby Current
1
15
µA
ICC2
Deep Power-down Current
1
15
µA
C= 0.1VCC / 0.9.VCC at 100MHz, DO = open
24
mA
C= 0.1VCC / 0.9.VCC at 50MHz, DO = open
21
mA
C= 0.1VCC / 0.9.VCC at 33MHz, DO = open
17
mA
Operating Current (Dual Read)
C= 0.1VCC / 0.9.VCC at 100MHz, IO0, IO1 = open
26
mA
Operating Current (Quad Read)
C= 0.1VCC / 0.9.VCC at 100MHz, IO0 ~ IO3 = open
28
mA
S = VCC
S = VCC
15
mA
12
mA
S = VCC
S = VCC
25
mA
25
mA
S = VCC, VIN = VSS or VCC
S = VCC, VIN = VSS or VCC
Operating Current (Read)
ICC3
ICC4
Operating Current (PP)
ICC5
Operating Current (WRSR)
ICC6
Operating Current (SE)
ICC7
Operating Current (BE)
VIL
Input Low Voltage
–0.5
0.3VCC
V
VIH
Input High Voltage
0.7VCC
VCC+0.4
V
VOL
Output Low Voltage
IOL = 1.6mA
0.4
V
VOH
Output High Voltage
IOH = –100µA
VCC–0.2
V
Note: 1. This is preliminary data at 85°C
Table 14. AC Measurement Conditions
Symbol
CL
Parameter
Min.
Load Capacitance
Max.
30
Input Rise and Fall Times
Unit
pF
5
ns
Input Pulse Voltages
0.2VCC to 0.8VCC
V
Input Timing Reference Voltages
0.3VCC to 0.7VCC
V
VCC / 2
V
Output Timing Reference Voltages
Note: Output Hi-Z is defined as the point where data out is no longer driven.
Figure 32. AC Measurement I/O Waveform
Input Levels
Input and Output
Timing Reference Levels
0.8VCC
0.7VCC
0.5VCC
0.3VCC
0.2VCC
(April, 2016, Version 1.0)
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AMIC Technology Corp.
A25LQ080 Series
Table 15. AC Characteristics
Symbol
Alt.
fC
fC
fR
tCH
1
tCLH
tCL
1
tCLL
Parameter
Min.
Typ.
Max.
Unit
Clock Frequency for all instructions, except READ (03h)
D.C.
100
MHz
Clock Frequency for READ (03h) instruction
D.C.
50
MHz
Clock High Time
5
5
ns
tCLCH 2
Clock Rise Time3 (peak to peak)
0.1
V/ns
tCHCL 2
Clock Fall Time3 (peak to peak)
0.1
V/ns
S Active Setup Time (relative to C)
5
ns
S Not Active Hold Time (relative to C)
5
ns
tSLCH
Clock Low Time
ns
tCSS
tCHSL
tDVCH
tDSU
Data In Setup Time
3
ns
tCHDX
tDH
Data In Hold Time
3
ns
tCHSH
S Active Hold Time (relative to C)
5
ns
tSHCH
S Not Active Setup Time (relative to C)
5
ns
30
ns
tSHSL
tCSH
S Deselect Time
tSHQZ 2
tDIS
Output Disable Time
7
ns
tCLQV
tV
Clock Low to Output Valid
7
ns
tCLQX
tHO
Output Hold Time
0
ns
tHLCH
HOLD Setup Time (relative to C)
5
ns
tCHHH
HOLD Hold Time (relative to C)
5
ns
tHHCH
HOLD Setup Time (relative to C)
5
ns
tCHHL
HOLD Hold Time (relative to C)
5
ns
tHHQX
2
tLZ
HOLD to Output Low-Z
7
ns
tHLQZ
2
tHZ
HOLD to Output High-Z
7
ns
tWHSL
4
tSHWL 4
tDP
Write Protect Setup Time
20
ns
Write Protect Hold Time
100
ns
2
S High to Deep Power-down Mode
3
µs
tRES1 2
S High to Standby Mode without Electronic Signature Read
1
µs
tRES2 2
S High to Standby Mode with Electronic Signature Read
1
µs
tW
Write Status Register Cycle Time
5
20
ms
Page Program Cycle Time
2
6
ms
Program OTP Cycle Time
2
3
ms
tSE
Sector Erase Cycle Time
0.08
0.2
s
tBE
Block Erase Cycle Time
0.5
2
s
tCE
Chip Erase Cycle Time of A25LQ080
8
20
s
tpp
Note: 1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for WRSR instruction when Status Register Protect bit (SRP0) = 1
(April, 2016, Version 1.0)
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AMIC Technology Corp.
A25LQ080 Series
Figure 33. Serial Input Timing
tSHSL
S
tCHSL
tSLCH
tCHSH
C
tCHCL
tDVCH
tCLCH
tCHDX
DI
DO
tSHCH
MSB IN
LSB IN
High Impedance
Figure 34. Write Protect Setup and Hold Timing during WRSR
W
tSHWL
tWHSL
S
C
DI
DO
(April, 2016, Version 1.0)
High Impedance
50
AMIC Technology Corp.
A25LQ080 Series
Figure 35. Hold Timing
S
tHLCH
tHHCH
tCHHL
C
tCHHH
DI
tHLQZ
tHHQX
DO
HOLD
Figure 36. Output Timing
S
tCH
C
DI
ADDR.LSB IN
tCLQV
tCLQX
tCL
tCLQV
tSHQZ
tCLQX
DO
LSB OUT
tQLQH
tQHQL
(April, 2016, Version 1.0)
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AMIC Technology Corp.
A25LQ080 Series
Part Numbering Scheme
A25 X X X X X X / X
Packing
Blank: for DIP8
G: for SOP8 In Tube
Q: for Tape & Reel
Package Material
Blank: normal
F: PB free
Package Type
Blank = DIP 8
M = 209 mil SOP 8
O = 150 mil SOP 8
Q4 = WSON 8 (6*5mm)
Device Density
080 = 8 Mbit (4KB uniform sectors)
Quad SPI Operation
Q = Support Quad SPI Operation
Blank = Do not support Quad SPI Operation
Device Voltage
L = 2.7-3.6V
Device Type
A25 = AMIC Serial Flash
(April, 2016, Version 1.0)
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AMIC Technology Corp.
A25LQ080 Series
Ordering Information
Part No.
Speed (MHz)
Active Read
Current
Max. (mA)
Program/Erase
Current
Max. (mA)
Standby
Current
Max. (μA)
A25LQ080-F
8 Pin Pb-Free DIP (300 mil)
A25LQ080O-F
A25LQ080M-F
Package
8 Pin Pb-Free SOP (150 mil)
100
24
15
15
8 Pin Pb-Free SOP (209mil)
8 Pin Pb-Free WSON (6*5mm)
A25LQ080Q4-F
Operating temperature range: -40°C ~ +85°C
(April, 2016, Version 1.0)
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AMIC Technology Corp.
A25LQ080 Series
Package Information
unit: inches/mm
P-DIP 8L Outline Dimensions
Dimensions in inches
Dimensions in mm
Symbol
Min
Nom
Max
Min
Nom
Max
A
-
-
0.180
-
-
4.57
A1
0.015
-
-
0.38
-
-
A2
0.128
0.130
0.136
3.25
3.30
3.45
B
0.014
0.018
0.022
0.36
0.46
0.56
B1
0.050
0.060
0.070
1.27
1.52
1.78
B2
0.032
0.039
0.046
0.81
0.99
1.17
C
D
0.008
0.350
0.010
0.360
0.013
0.370
0.20
8.89
0.25
9.14
0.33
9.40
E
0.290
0.300
0.315
7.37
7.62
8.00
E1
0.254
0.260
0.266
6.45
6.60
6.76
e1
-
0.100
-
-
2.54
-
L
0.125
-
-
3.18
-
-
EA
0.345
-
0.385
8.76
-
9.78
S
0.016
0.021
0.026
0.41
0.53
0.66
Notes:
1. Dimension D and E1 do not include mold flash or protrusions.
2. Dimension B1 does not include dambar protrusion.
3. Tolerance: ±0.010” (0.25mm) unless otherwise specified.
(April, 2016, Version 1.0)
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AMIC Technology Corp.
A25LQ080 Series
Package Information
unit: mm
E
e
HE
SOP 8L (150mil) Outline Dimensions
A1
A
b
0° ~ 8°
D
L
Symbol
Dimensions in mm
A
1.35~1.75
A1
0.10~0.25
b
0.33~0.51
D
4.7~5.0
E
3.80~4.00
e
1.27 BSC
HE
5.80~6.20
L
0.40~1.27
Notes:
1. Maximum allowable mold flash is 0.15mm.
2. Complies with JEDEC publication 95 MS –012 AA.
3. All linear dimensions are in millimeters (max/min).
4. Coplanarity: Max. 0.1mm
(April, 2016, Version 1.0)
55
AMIC Technology Corp.
A25LQ080 Series
Package Information
unit: mm
5
1
4
E
8
E1
SOP 8L (209mil) Outline Dimensions
C
A2
A
D
GAGE PLANE
SEATING PLANE
A1
b
θ
0.25
e
L
Dimensions in mm
Symbol
Min
Nom
Max
A
1.75
1.95
2.16
A1
0.05
0.15
0.25
A2
1.70
1.80
1.91
0.48
b
0.35
0.42
C
0.19
0.20
0.25
D
5.13
5.23
5.33
E
7.70
7.90
8.10
E1
5.18
5.28
5.38
e
1.27 BSC
L
0.50
0.65
0.80
θ
0°
-
8°
Notes:
Maximum allowable mold flash is 0.15mm at the package
ends and 0.25mm between leads
(April, 2016, Version 1.0)
56
AMIC Technology Corp.
A25LQ080 Series
Package Information
unit: mm/mil
0.25 C
WSON 8L (6 X 5 X 0.8mm) Outline Dimensions
1
0.25 C
b
2
3
4
6
5
L
4
e
1
D2
D
C0.30
Pin1 ID Area
5
8
8
E
7
E2
A3
A1
A
// 0.10 C
Seating Plane
Symbol
y C
Dimensions in mm
Dimensions in mil
Min
Nom
Max
Min
Nom
Max
A
0.700
0.750
0.800
27.6
29.5
31.5
A1
0.000
0.020
0.050
0.0
0.8
2.0
A3
0.203 REF
8.0 REF
b
0.350
0.400
0.480
13.8
15.8
18.9
D
5.900
6.000
6.100
232.3
236.2
240.2
141.7
D2
3.200
3.400
3.600
126.0
133.9
E
4.900
5.000
5.100
192.9
196.9
200.8
E2
3.800
4.000
4.200
149.6
157.5
165.4
L
0.500
0.600
0.750
19.7
23.6
29.5
0.080
0
1.270 BSC
e
y
0
-
50.0 BSC
-
3.2
Note:
1. Controlling dimension: millimeters
2. Leadframe thickness is 0.203mm (8mil)
(April, 2016, Version 1.0)
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AMIC Technology Corp.