Rev 1; 6/04 2-Wire, 5-Bit DAC with Three Digital Outputs The DS4302 is a 5-bit digital-to-analog converter (DAC) with three programmable digital outputs. The DS4302 communicates through a 2-wire, SMBus™-compatible, serial interface. The tiny 8-pin µSOP package is ideal for use in space-constrained applications. Features DS4302 General Description ♦ SO Package is a Drop-In Replacement for the MPS1251 and MPS1252 ♦ Single 5-Bit DAC (32 Steps) ♦ 0V to 2V and 0V to 1.9V Versions ♦ Three Programmable Digital Outputs ♦ SMBus-Compatible Serial Interface ♦ 4.5V to 5.5V Supply Voltage Range ♦ 8-Pin SO and 8-Pin µSOP Packages ♦ Industrial Temperature Range: -40°C to +85°C Applications CCFL Backlight Brightness Control Power-Supply Calibration Ordering Information VOUT RANGE TOP BRAND DS4302Z-020 0V to 2.0V 4302B 8 SO DS4302Z-019* 0V to 1.9V 4302A 8 SO DS4302U-020 0V to 2.0V 4302B 8 µSOP DS4302U-019* 0V to 1.9V 4302A 8 µSOP PART PINPACKAGE Add “/T&R” for tape-and-reel orders. *Contact factory for availability. Pin Description Pin Configuration PIN NAME 1 SCL Serial Clock Input. 2-wire clock input. 2 SDA Serial Data Input/Output. Bidirectional, 2-wire data pin. SCL 1 3 VOUT DAC Output Voltage SDA 2 4 GND 5 P2 6 7 8 P1 P0 VCC FUNCTION TOP VIEW 8 VCC 7 P0 3 6 P1 GND 4 5 P2 DS4302 Ground VOUT Programmable Digital Output Power-Supply Input SO/µSOP SMBus is a trademark of Intel Corp. ______________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS4302 2-Wire, 5-Bit DAC with Three Digital Outputs ABSOLUTE MAXIMUM RATINGS Voltage Range on VCC, SDA, and SCL Pins Relative to Ground.............................................-0.5V to +6.0V Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature.....See IPC/JEDEC J-STD-020A Specification Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA = -40°C to +85°C) PARAMETER SYMBOL Supply Voltage VCC Input Logic 1 (SDA, SCL) VIH Input Logic 0 (SDA, SCL) VIL CONDITIONS (Note 1) MIN TYP 4.5 MAX 5.5 2.0 VCC + 0.3 GND - 0.3 UNITS V V 0.8 V TYP MAX UNITS 200 300 µA µA DC ELECTRICAL CHARACTERISTICS (VCC = +4.5V to 5.5V, TA = -40°C to +85°C.) PARAMETER Standby Current Input Leakage SYMBOL ISTBY IL CONDITIONS MIN (Notes 2, 3) (Note 4) -1.0 +1.0 3mA sink current 0.0 0.4 6mA sink current 0.0 0.6 SDA Low-Level Output Voltage VOL1 P0, P1, P2 Low-Level Output Voltage VOL2 (Note 1) 4mA sink P0, P1, P2 High-Level Output Voltage VOH (Note 1) 4mA source VOUT Maximum Level (-020) VCC = 5.0V, Data = 00000XXX (Note 3) VOUT Minimum Level (-020) VCC = 5.0V, Data = 11111XXX VOUT Maximum Level (-019) VCC = 5.0V, Data = 00000XXX (Note 3) VOUT Minimum Level (-019) VCC = 5.0V, Data = 11111XXX +0.4V VCC - 0.4V V V V 1.925 2.0 2.075 V 0.0 0.05 0.1 V 1.825 1.9 1.975 V 0.0 0.05 0.1 V Power-On Reset 1.7 V Settling Time 10 µs D/A Output Levels 32 steps X = Don’t care. 2 _____________________________________________________________________ 2-Wire, 5-Bit DAC with Three Digital Outputs (VCC = +4.5V to 5.5V, TA = -40°C to +85°C, timing referenced to VIL(MAX) and VIH(MIN).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 400 kHz SCL Clock Frequency fSCL 0 Bus Free Time Between STOP and START Conditions tBUF 1.3 µs Low Period of SCL tLOW 1.3 µs High Period of SCL tHIGH 0.6 Data Hold Time tHD:DAT 0 Data Setup Time tSU:DAT 100 ns Start Setup Time tSU:STA 0.6 µs SDA and SCL Rise Time SDA and SCL Fall Time Stop Setup Time SDA and SCL Capacitive Loading µs 0.9 tR (Note 5) 20 + 0.1CB 300 tF (Note 5) 20 + 0.1CB 300 tSU:STO CB 0.6 (Note 5) µs ns ns µs 400 pF Note 1: Note 2: Note 3: Note 4: All voltages referenced to ground. ISTBY specified for the inactive state measured with SDA = SCL = VCC and with VOUT, P0, P1, and P2 floating. No load on VOUT. The DS4302 will not obstruct the SDA and SCL lines if VCC is switched off as long as the voltages applied to these inputs does not violate their min and max input-voltage levels. Note 5: CB—total capacitance of one bus line in picofarads. _____________________________________________________________________ 3 DS4302 AC ELECTRICAL CHARACTERISTICS (Figure 3) Typical Operating Characteristics (VCC = +5.0V, TA = +25°C.) STANDBY SUPPLY CURRENT vs. TEMPERATURE 200 150 100 50 0 OUTPUTS UNLOADED SDA = SCL = VCC = 5.0V 250 200 150 100 4.75 5.00 5.25 50 5.50 150 100 50 0 -40 -20 0 20 40 60 80 0 100 200 400 300 TEMPERATURE (°C) SCL FREQUENCY (kHz) VOUT vs. DAC SETTING VOUT vs. SUPPLY VOLTAGE VOUT PERCENT CHANGE FROM +25°C vs. TEMPERATURE 2.05 VOUT (V) 2.00 1.95 0.5 10 15 20 DAC SETTING (dec) 25 30 DS4302 toc06 0.5 0 -0.5 -1.0 1.90 0 VCC = SDA = SCL VOUT PERCENT CHANGE (%) VCC = SDA = SCL 1.5 1.0 1.0 DS4302 toc05 2.10 DS4302 toc04 DS4302-020 VERSION 5 200 SUPPLY VOLTAGE (V) 2.0 0 OUTPUTS UNLOADED SDA = VCC 250 0 4.50 4 300 SUPPLY CURRENT (µA) 250 300 DS4302 toc02 OUTPUTS UNLOADED SDA = SCL = VCC STANDBY SUPPLY CURRENT (µA) DS4302 toc01 STANDBY SUPPLY CURRENT (µA) 300 SUPPLY CURRENT vs. SCL FREQUENCY DS4302 toc03 STANDBY SUPPLY CURRENT vs. SUPPLY VOLTGE VOUT (V) DS4302 2-Wire, 5-Bit DAC with Three Digital Outputs 4.50 4.75 5.00 5.25 5.50 SUPPLY VOLTAGE (V) _____________________________________________________________________ -40 -20 0 20 40 TEMPERATURE (°C) 60 80 2-Wire, 5-Bit DAC with Three Digital Outputs DATA BYTE REGISTER SDA 2-WIRE INTERFACE SCL MSB DAC VALUE P2 P1 P0 LSB OUTPUT CELL VCC P0 VOUT 5-BIT DAC VCC VCC OUTPUT CELL BUFFER P1 GND OUTPUT CELL BANDGAP REFERENCE P2 DS4302 _____________________________________________________________________ 5 DS4302 Functional Diagram DS4302 2-Wire, 5-Bit DAC with Three Digital Outputs 5-bit DAC to adjust the voltage on VOUT and set the level of the three output pins: P0, P1, and P2. The read operation is used to recall the programmed settings. DATA BYTE DAC VALUE P2 2-Wire Definitions P1 P0 The following terminology is commonly used to describe 2-wire data transfers. MSB Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses, START, and STOP conditions. Figure 1. Data Byte Configuration Detailed Description The DS4302 contains a 5-bit DAC and three programmable digital outputs. The DAC setting and the programmed output levels are contained in a 1-byte data word that defaults to 00h on power-up (see Figure 1 for data byte configuration). The upper 5 MSbits of the byte set the DAC and control the voltage produced on VOUT. A setting of 1111 1XXX sets the minimum output voltage from the DAC while a setting of 0000 0XXX sets the maximum output voltage from the DAC. The three LSbits of the data byte control the three output pins, P0, P1, and P2. Setting any of these control bits to a 0 pulls the corresponding outputs low and setting the bits to a 1 pulls the outputs high. The DS4302 communicates through a 2-wire (SMBuscompatible) digital interface and has a 2-wire address of 58h. Write and read operations are used to access the DAC and output settings. Each operation begins with a 2-wire START condition, consists of three bytes, and ends with a 2-wire STOP condition (see Figure 2). Using the write operation, the 2-wire master can program the Slave Devices: Slave devices send and receive data at the master’s request. Bus Idle or Not Busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. When the bus is idle, it initiates a low-power mode for slave devices. START Condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a START condition. See Figure 3 for applicable timing. STOP Condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. See Figure 3 for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements (see Figure 3). Data is shifted into the device during the rising edge of the SCL. COMMUNICATIONS KEY S P A START ACK X 0 1 0 1 1 READ A SINGLE BYTE S 0 1 X 8-BITS ADDRESS OR DATA 58h AAh X X X WRITE A SINGLE BYTE S 2) THE FIRST BYTE SENT AFTER A START CONDITION IS ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE READ/WRITE BIT. SHADED BOXES INDICATE THE SLAVE IS CONTROLLING SDA STOP X X X NOTES: 1) ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST. WHITE BOXES INDICATE THE MASTER IS CONTROLLING SDA 0 1 0 0 0 A 1 0 1 59h 1 0 0 1 0 1 0 A DATA BYTE A P A DATA BYTE A P 00h 0 1 A 0 0 0 0 0 0 0 0 Figure 2. 2-Wire Communication Examples 6 _____________________________________________________________________ 2-Wire, 5-Bit DAC with Three Digital Outputs DS4302 SDA tBUF tHD:STA tLOW tSP tF tR SCL tSU:STA tHIGH tHD:STA tSU:DAT STOP START tHD:DAT tSU:STO REPEATED START NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN). Figure 3. 2-Wire Timing Diagram Bit Read: At the end a write operation, the master must release the SDA bus line for the proper amount of setup time (see Figure 3) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses including when it is reading bits from the slave. Acknowledgement (ACK): An Acknowledgement (ACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. For timing, see Figure 3. An ACK is the acknowledgement that the device is properly receiving data. Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must ACK the last byte read to terminated communication so the slave returns control of SDA to the master. 7-BIT SLAVE ADDRESS 0 1 0 1 1 0 0 R/W MOST SIGNIFICANT BIT DETERMINES READ OR WRITE Figure 4. Slave Address and the R/W Bit Slave Address and the R/W Bit: Each slave on the 2-wire bus responds to a slave addressing byte sent immediately following a START condition. The slave address byte contains the slave address and the R/W bit. The slave address (see Figure 4) is the most significant 7 bits and the R/W bit is the least significant bit. The DS4302’s slave address is 0101100X (binary), where X is the R/W bit. If the R/W bit is zero (01011000), the master will write data to the slave. If the R/W is a one (01011001), the master will read data from the slave. Memory Address: During a 2-wire write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is the second byte transmitted during a write or read operation following the slave address byte (R/W=0). For a write operation, the memory address is 10101010 (AAh) and for a read operation, the memory address is 00000000 (00h). _____________________________________________________________________ 7 DS4302 2-Wire, 5-Bit DAC with Three Digital Outputs 2-Wire Communication Writing to a Slave: The master must generate a START condition, write the slave address (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember the master must read the slave’s acknowledgement during all byte-write operations. See Figure 2 for the write command example. Reading from a Slave: To read from the slave, the master generates a START condition, writes the slave address with R/W = 1, receives an ACK from the slave, reads a memory address of 00h from the slave, sends an ACK to the slave, reads the data byte, then sends an ACK to indicate the end of the transfer, and generates a STOP condition. See Figure 2 for the read command example. Chip Information TRANSISTOR COUNT: 2428 SUBSTRATE CONNECTED TO GROUND Package Information For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. Application Information Power-Supply Decoupling To achieve the best results when using the DS4302, decouple the power supply with a 0.01µF or a 0.1µF capacitor. Use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the VCC and GND pins of the DS4302 to minimize lead inductance. SDA and SCL Pullup Resistors Pullup resistor values for SDA and SCL should be chosen to ensure that the rise and fall times listed in the AC electrical characteristics are within specification. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. DALLAS is a registered trademark of Dallas Semiconductor Corporation.