P itle G20 bt MO uad ST aitch utho ) eyrds terrpoion, inctor, itch OS PST, DT, ST, DT, eo, ET, alog itch, anl) rer () OCI DG201 T CT DUC P R O P R OD U E T OL E UT E OBS UBSTIT 444 S G Data Sheet IBLE G441, D D OS S May 2001 File Number 3115.5 CMOS Quad SPST Analog Switch Features The DG201 solid state analog switch is designed using an improved, high voltage CMOS monolithic technology. It provides ease-of-use and performance advantages not previously available from solid state switches. Destructive latch-up of solid state analog gates have been eliminated by Intersil’s CMOS technology. • Switches Greater than 28VP-P Signals with ±15V Supplies The DG201 is completely specification and pinout compatible with the industry standard devices. • Non-Latching with Supply Turn-Off Part Number Information • Industry Standard (DG201) PART NUMBER TEMP. RANGE ( oC) DG201CJ 0 to 70 PACKAGE 16 Ld PDIP • Break-Before-Make Switching - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700ns • TTL, DTL, CMOS, PMOS Compatible • Complete Monolithic Construction PKG. NO. E16.3 Applications • Data Acquisition • Sample and Hold Circuits Functional Diagram • Operational Amplifier Gain Switching Networks S IN Pinout DG201 (PDIP) TOP VIEW P N D DG201 SWITCH CELL TRUTH TABLE LOGIC DG201 0 ON 1 OFF 1 IN1 1 16 IN2 D1 2 15 D2 S1 3 14 S2 V- 4 13 V+(SUBSTRATE) GND 5 12 VREF S4 6 11 S3 D4 7 10 D3 IN4 8 9 IN3 SWITCHES SHOWN FOR LOGIC “1” INPUT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. | Copyright © Intersil Americas Inc. 2001 DG201 Functional Diagram (1/4 DG201) V+ V- Q3 Q7 Q5 Q14 Q15 Q8 V+ VREF Q1 Q10 Q12 Q2 Q9 GATE PROTECTION RESISTOR S1 Q4 Q6 V- INPUT Pin Descriptions PIN SYMBOL DESCRIPTION 1 IN1 Logic Control for Switch 1 2 D1 Drain (Output) Terminal for Switch 1 3 S1 Source (Input) Terminal for Switch 1 4 V- Negative Power Supply Terminal 5 GND 6 S4 Source (Input) Terminal for Switch 4 7 D4 Drain (Output) Terminal for Switch 4 8 IN4 Logic Control for Switch 4 9 IN3 Logic Control for Switch 3 10 D3 Drain (Output) Terminal for Switch 3 11 S3 Source (Input) Terminal for Switch 3 12 VREF 13 V+ Positive Power Supply Terminal (Substrate) 14 S2 Source (Input) Terminal for Switch 2 15 D2 Drain (Output) Terminal for Switch 2 16 IN2 Logic Control for Switch 2 Ground Terminal (Logic Common) Logic Reference Voltage 2 Q13 Q11 D1 DG201 Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V V+ to VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V VD to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V VD to VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28V VREF to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33V VREF to VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V Current (Any Terminal). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Thermal Resistance (Typical, Note 1) θJA ( oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A Maximum Junction Temperature Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Range “C” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. TA = 25oC, V+ = +15V, V- = -15V Electrical Specifications “C” SUFFIX TEST CONDITIONS 0oC (NOTE 2) 25oC 70oC UNITS Turn-ON Time (Note 3), tON RL = 1kΩ, VANALOG = -10V to +10V (Figure 1) - 1.0 - µs Turn-OFF Time (Note 3), tOFF RL = 1kΩ, VANALOG = -10V to +10V (Figure 1) - 0.5 - µs Charge Injection, Q Figure 2 - 20 (Typ) - mV Off Isolation Rejection Ratio, OIRR f = 1MHz, R L = 100Ω, CL ≤ 5pF, (Figure 3) - 50 (Typ) - dB Crosstalk (Channel-to-Channel), CCRR One Channel Off - -50 (Typ) - dB PARAMETER DYNAMIC CHARACTERISTICS DIGITAL INPUT CHARACTERISTICS Input Logic Current, IIN(ON) VIN = 0.8V (Note 3) ±1 ±1 ±10 µA Input Logic Current, IN(OFF) VIN = 2.4V (Note 3) ±1 ±1 ±10 µA - ±15 (Typ) - V 100 100 125 Ω - 30 (Typ) - Ω ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, r DS(ON) IS = 10mA, VANALOG = ±10V Channel-to-Channel r DS(ON) Match, r DS(ON) Drain OFF Leakage Current, ID(OFF) VANALOG = -14V to +14V - ±5 100 nA Source OFF Leakage Current, IS(OFF) VANALOG = -14V to +14V - ±5 100 nA Channel ON Leakage Current, ID(ON) + IS(ON) VD = VS = -14V to +14V - ±5 200 nA 2000 1000 2000 µA 2000 1000 2000 µA POWER SUPPLY CHARACTERISTICS Supply Current, I+ Positive VIN = 0V or VIN = 5V Supply Current, I- Negative NOTES: 2. Typical values are for design aid only, not guaranteed and not subject to production testing. 3. All channels are turned off by high “1” logic inputs and all channels are turned on by low “0” inputs; however 0.8V to 2.4V describes the minimum range for switching properly. Peak input current required for transition is typically -120µA. 3 DG201 Test Circuits ANALOG INPUT 10V ANALOG INPUT 10V 3V 3V 0V 0V VOUT LOGIC INPUT 1kΩ 10pF VOUT LOGIC INPUT FIGURE 1. t ON AND tOFF TEST CIRCUIT 10nF FIGURE 2. CHARGE INJECTION TEST CIRCUIT ANALOG INPUT LOGIC INPUT 2VP-P AT 1MHz 51Ω 3V VOUT 100Ω FIGURE 3. OFF ISOLATION TEST CIRCUIT V+ Typical Applications Using the VREF Terminal The DG201 has an internal voltage divider setting the TTL threshold on the input control lines for V+ equal to +15V. The schematic shown in Figure 4 with nominal resistor values, gives approximately 2.4V on the VREF pin. As the TTL input signal goes from +0.8V to +2.4V, Q 1 and Q 2 switch states to turn the switch ON and OFF. If the power supply voltage is less than +15V, then a resistor (REXT) must be added between V+ and the V REF pin, to restore +2.4V at V REF. The table shows the value of this resistor for various supply voltages, to maintain TTL compatibility. If CMOS logic levels with a +5V supply are being used, the threshold shifts are less critical, but a separate column of suitable values is given in the table. For logic swings of -5V to + 5V, no resistor is needed. In general, the “low” logic level should be <0.8V to prevent Q1 and Q2 from both being ON together (this will cause incorrect switch function). TABLE 1. V+ SUPPLY (V) REXT FOR TTL LEVELS (kΩ) REXT FOR CMOS LEVELS (kΩ) +15 - - +12 420 - +10 190 - +9 136 136 +8 98 98 +7 70 70 4 118kΩ REXT VREF Q1 23kΩ Q2 GATE PROTECTION RESISTOR INPUT FIGURE 4. DG201 Typical Performance Curves V+ = +15V V- = -15V 100 125 oC 25 oC 50 -55oC 0 -15 -10 -5 0 5 DRAIN VOLTAGE (V) 10 C B 50 A A: B: C: D: 0 -15 15 FIGURE 5. rDS(ON) vs VD AND TEMPERATURE -10 V+ = +15V, V- = -15V V+ = +12V, V- = -12V V+ = +10V, V- = -10V V+ = +8V, V- = -8V -5 0 5 DRAIN VOLTAGE (V) 10 15 FIGURE 6. r DS(ON) vs VD AND POWER SUPPLY VOLTAGE 10 10 SOURCE OR DRAIN OFF LEAKAGE CURRENT (nA) CHANNEL ON LEAKAGE CURRENT (nA) D DRAIN-SOURCE ON RESISTANCE (Ω) DRAIN-SOURCE ON RESISTANCE (Ω) 100 1 0.1 0.01 1 0.1 0.01 25 45 65 85 TEMPERATURE (oC) 105 FIGURE 7. ID(ON) vs TEMPERATURE 5 125 25 45 65 85 TEMPERATURE (oC) 105 FIGURE 8. IS(OFF) OR ID(OFF) vs TEMPERATURE 125 DG201 Die Characteristics DIE DIMENSIONS: PASSIVATION: 94 mils x 101 mils x 14 mils Type: SiO2/Si3N4 SiO2 Thickness: 7kÅ Si3N4 Thickness: 8kÅ METALLIZATION: Type: Al Thickness: 10kÅ WORST CASE CURRENT DENSITY: 1 x 105 A/cm2 Metallization Mask Layout DG201 D1 IN1 IN2 D2 (2) (1) (16) (15) S1 (3) (14) S2 V- (4) (13) V+ (SUBSTRATE)† GND (5) (12) VREF S4 (6) (11) S3 (7) D4 † BACKSIDE OF CHIP IS V+ 6 (8) IN4 (9) IN3 (10) D3 DG201 Dual-In-Line Plastic Packages (PDIP) N E16.3 (JEDEC MS-001-BB ISSUE D) 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 N/2 INCHES -B- SYMBOL -AD E BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 C L eA A1 eC B MAX MIN MAX NOTES A - A1 0.015 0.210 - 5.33 4 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - C eB 0.010 (0.25) M C A B S MILLIMETERS MIN NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . D 0.735 0.775 18.66 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC 6 eB - 0.430 - L 0.115 0.150 2.93 N 16 10.92 7 3.81 4 16 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality/iso.asp Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 NORTH AMERICA Intersil Corporation 2401 Palm Bay Rd. Palm Bay, FL 32905 TEL: (321) 724-7000 FAX: (321) 724-7240 7 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369