CAT34C02 2-Kb I2C EEPROM for DDR2 DIMM Serial Presence Detect FEATURES DEVICE DESCRIPTION ■ Supports Standard and Fast I2C Protocol The CAT34C02 is a 2-Kb Serial CMOS EEPROM, internally organized as 16 pages of 16 bytes each, for a total of 256 bytes of 8 bits each. ■ 1.7 V to 5.5 V Supply Voltage Range ■ 16-Byte Page Write Buffer It features a 16-byte page write buffer and supports both the Standard (100 kHz) as well as Fast (400 kHz) I2C protocol. ■ Hardware Write Protection for entire memory ■ Software Write Protection for lower 128 Bytes ■ Schmitt Triggers and Noise Suppression Filters Write operations can be inhibited by taking the WP pin High (this protects the entire memory) or by setting an internal Write Protect flag via Software command (this protects the lower half of the memory). on I2C Bus Inputs (SCL and SDA). ■ Low power CMOS technology ■ 1,000,000 program/erase cycles In addition to Permanent Software Write Protection, the CAT34C02 also features JEDEC compatible Reversible Software Write Protection for DDR2 Serial Presence Detect (SPD) applications operating over the 1.7 V to 3.6 V supply voltage range. ■ 100 year data retention “ ”&“ 8-pin TSSOP and TDFN packages ■ RoHS compliant ” ■ Industrial temperature range The CAT34C02 is fully backwards compatible with earlier DDR1 SPD applications operating over the 1.7 V to 5.5 V supply voltage range. PIN CONFIGURATION TSSOP (Y) TDFN (VP2) FUNCTIONAL SYMBOL A0 1 8 VCC A1 A2 2 7 WP 3 6 SCL VSS 4 5 SDA VCC SCL For the location of Pin 1, please consult the corresponding package drawing. A2, A1, A0 Device Address SDA Serial Data SCL Serial Clock WP Write Protect VCC Power Supply VSS Ground © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice SDA WP PIN FUNCTIONS A0, A1, A2 CAT34C02 VSS * Catalyst carries the I2C protocol under a license from the Philips Corporation. 1 Doc. No. 1095, Rev. C CAT34C02 ABSOLUTE MAXIMUM RATINGS* Storage Temperature -65°C to +150°C Voltage on Any Pin with Respect to Ground(1) -0.5 V to +6.5 V * Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. RELIABILITY CHARACTERISTICS(2) Symbol Parameter Min Units NEND(*) Endurance 1,000,000 Program/ Erase Cycles 100 Years TDR Data Retention (*) Page Mode, VCC = 5 V, 25°C D.C. OPERATING CHARACTERISTICS VCC = 1.7 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. Symbol Parameter Test Conditions ICC Supply Current ISB Min Max Units Read or Write at 400 kHz 1 mA Standby Current All I/O Pins at GND or VCC 1 μA IL I/O Pin Leakage Pin at GND or VCC 1 μA VIL Input Low Voltage VCC x 0.3 V VIH Input High Voltage VCC x 0.7 VCC + 0.5 V VOL1 Output Low Voltage VCC > 2.5 V, IOL = 3.0 mA 0.4 V VOL2 Output Low Voltage VCC > 1.7 V, IOL = 1.0 mA 0.2 V VHV(1) RSWP Set/Clear A0 High Voltage 1.7 V < VCC < 3.6 V VCC + 4.8 10 V Min Max Units -0.5 PIN IMPEDANCE CHARACTERISTICS TA = 25°C, f = 400 kHz, VCC = 5 V Symbol Parameter Conditions CIN(2) SDA I/O Pin Capacitance VIN = 0 V 8 pF CIN(2) Input Capacitance (other pins) VIN = 0 V 6 pF ZWPL WP Input Low Impedance VIN < 0.5 V 70 kΩ ILWPH WP Input High Leakage VIN > VCC x 0.7 1 μA 5 Note: (1) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. The maximum DC voltage on address pin A0 is +10.0 V at 25°C. A series resistor of ~ 1.5 kΩ should be used when driving pin A0 to VHV, or else, the current compliance of the VHV driver should be limited to ~ 1 mA. (2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. Doc. No. 1095, Rev. C 2 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT34C02 A.C. CHARACTERISTICS VCC = 1.7 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. 1.7 V - 5.5 V Symbol Parameter Min Max 2.5 V - 5.5 V Min Max Units FSCL Clock Frequency 100 400 kHz TI(1) Noise Suppression Time Constant at SCL, SDA Inputs 100 100 ns tAA(2) SCL Low to SDA Data Out 3.5 0.9 μs tBUF(1) Time the Bus Must be Free Before a New Transmission Can Start tHD:STA Start Condition Hold Time 4.7 1.3 μs 4 0.6 μs tLOW Clock Low Period 4.7 1.3 μs tHIGH Clock High Period 4 0.6 μs 4.7 0.6 μs tSU:STA Start Condition Setup Time tHD:DAT Data In Hold Time 0 0 ns tSU:DAT Data In Setup Time 250 100 ns tR(1) SDA and SCL Rise Time 1 0.3 μs tF(1) SDA and SCL Fall Time 300 300 ns tSU:STO Stop Condition Setup Time 4 0.6 μs 100 100 ns tDH Data Out Hold Time tWR Write Cycle Time 5 5 ms Power-up to Ready Mode 1 1 ms tPU(1), (3) Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) For timing measurements the SDA line capacitance is ~ 100 pF; the SCL input is driven with rise and fall times of < 50 ns; the SDA I/O is pulled-up by a 3 mA current source; input driving signals swing from 20% to 80% of VCC. Output level reference levels are 30% and respectively 70% of VCC. (3) tPU is the delay required from the time VCC is stable until the device is ready to accept commands. Power-On Reset (POR) The CAT34C02 incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The CAT34C02 will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi-directional POR feature protects the device against ‘brown-out’ failure following a temporary loss of power. The POR circuitry triggers at the minimum VCC level required for proper initialization of the internal state machines. The POR trigger level automatically tracks the internal CMOS device thresholds, and is naturally well below the minimum recommended VCC supply voltage. © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc No. 1095, Rev. C CAT34C02 PIN DESCRIPTION START SCL: The Serial Clock input pin accepts the Serial Clock generated by the Master. The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a ‘wake-up’ call to all receivers. Absent a START, a Slave will not respond to commands. SDA: The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. STOP The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. The STOP starts the internal Write cycle (when following a Write command) or sends the Slave into standby mode (when following a Read command). A0, A1 and A2: The Address pins accept the device address. These pins have on-chip pull-down resistors. WP: The Write Protect input pin inhibits all write operations, when pulled HIGH. This pin has an on-chip pull-down resistor. Device Addressing The Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8-bit serial Slave address. The first 4 bits of the Slave address are set to 1010, for normal Read/Write operations (Figure 2). The next 3 bits, A2, A1 and A0, select one of 8 possible Slave devices. The last bit, R/W, specifies whether a Read (1) or Write (0) operation is to be performed. FUNCTIONAL DESCRIPTION The CAT34C02 supports the Inter-Integrated Circuit (I2C) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all START and STOP conditions. The CAT34C02 acts as a Slave device. Master and Slave alternate as either transmitter or receiver. Up to 8 devices may be connected to the bus as determined by the device address inputs A0, A1, and A2. Acknowledge After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle (Figure 3). The Slave will also acknowledge the byte address and every data byte presented in Write mode. In Read mode the Slave shifts out a data byte, and then releases the SDA line during the 9th clock cycle. If the Master acknowledges the data, then the Slave continues transmitting. The Master terminates the session by not acknowledging the last data byte (NoACK) and by sending a STOP to the Slave. Bus timing is illustrated in Figure 4. I2C BUS PROTOCOL The I2C bus consists of two ‘wires’, SCL and SDA. The two wires are connected to the VCC supply via pull-up resistors. Master and Slave devices connect to the 2wire bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to ‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, the SDA line must remain stable while the SCL line is HIGH. An SDA transition while SCL is HIGH will be interpreted as a START or STOP condition (Figure 1). Doc. No. 1095, Rev. C 4 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT34C02 Figure 1. Start/Stop Timing SDA SCL START BIT STOP BIT Figure 2. Slave Address Bits 1 0 1 A2 0 A1 A0 R/W DEVICE ADDRESS Figure 3. Acknowledge Timing SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACKNOWLEDGE START Figure 4. Bus Timing tHIGH tF tLOW tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tDH tBUF SDA OUT © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc No. 1095, Rev. C CAT34C02 WRITE OPERATIONS Byte Write In Byte Write mode the Master sends a START, followed by Slave address, byte address and data to be written (Figure 5). The Slave acknowledges all 3 bytes, and the Master then follows up with a STOP, which in turn starts the internal Write operation (Figure 6). During internal Write, the Slave will not acknowledge any Read or Write request from the Master. Page Write The CAT34C02 contains 256 bytes of data, arranged in 16 pages of 16 bytes each. A page is selected by the 4 most significant bits of the address byte following the Slave address, while the 4 least significant bits point to the byte within the page. Up to 16 bytes can be written in one Write cycle (Figure 7). The internal byte address counter is automatically incremented after each data byte is loaded. If the Master transmits more than 16 data bytes, then earlier bytes will be overwritten by later bytes in a ‘wrap-around’ fashion (within the selected page). The internal Write cycle starts immediately following the STOP. Acknowledge Polling Acknowledge polling can be used to determine if the CAT34C02 is busy writing or is ready to accept commands. Polling is implemented by interrogating the device with a ‘Selective Read’ command (see READ OPERATIONS). The CAT34C02 will not acknowledge the Slave address, as long as internal Write is in progress. Hardware Write Protection With the WP pin held HIGH, the entire memory, as well as the SWP flags are protected against Write operations (Figure 8). If the WP pin is left floating or is grounded, it has no impact on the operation of the CAT34C02. Doc. No. 1095, Rev. C 6 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT34C02 Figure 5. Byte Write Timing S T A R T BUS ACTIVITY: MASTER SDA LINE BYTE ADDRESS SLAVE ADDRESS S T O P DATA S P A C K A C K A C K Figure 6. Write Cycle Timing SCL 8th Bit Byte n SDA ACK tWR STOP CONDITION START CONDITION ADDRESS Figure 7. Page Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS (n) DATA n+1 DATA n S T O P DATA n+P S P A C K A C K A C K A C K A C K NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0 Figure 8. Memory Array FFH Hardware Write Protectable (by connecting WP pin to Vcc) 7FH Software Write Protectable (by setting the write protect flags) 00H © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc No. 1095, Rev. C CAT34C02 READ OPERATIONS Immediate Address Read In standby mode, the CAT34C02 internal address counter points to the data byte immediately following the last byte accessed by a previous operation. If that ‘previous’ byte was the last byte in memory, then the address counter will point to the 1st memory byte, etc. When, following a START, the CAT34C02 is presented with a Slave address containing a ‘1’ in the R/W bit position (Figure 9), it will acknowledge (ACK) in the 9th clock cycle, and will then transmit data being pointed at by the internal address counter. The Master can stop further transmission by issuing a NoACK, followed by a STOP condition. Selective Read The Read operation can also be started at an address different from the one stored in the internal address counter. The address counter can be initialized by performing a ‘dummy’ Write operation (Figure 10). Here the START is followed by the Slave address (with the R/W bit set to ‘0’) and the desired byte address. Instead of following up with data, the Master then issues a 2nd START, followed by the ‘Immediate Address Read’ sequence, as described earlier. Sequential Read If the Master acknowledges the 1st data byte transmitted by the CAT34C02, then the device will continue transmitting as long as each data byte is acknowledged by the Master (Figure 11). If the end of memory is reached during sequential Read, then the address counter will ‘wrap-around’ to the beginning of memory, etc. Sequential Read works with either ‘Immediate Address Read’ or ‘Selective Read’, the only difference being the starting byte address. Doc. No. 1095, Rev. C 8 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT34C02 Figure 9. Immediate Address Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T S T O P SLAVE ADDRESS S P A C K DATA N O A C K 8 SCL 9 8th Bit SDA DATA OUT NO ACK STOP Figure 10. Selective Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T S T A R T BYTE ADDRESS (n) SLAVE ADDRESS S T O P SLAVE ADDRESS S S P A C K A C K A C K DATA n N O A C K Figure 11. Sequential Read Timing BUS ACTIVITY: MASTER SLAVE ADDRESS DATA n DATA n+1 S T O P DATA n+x DATA n+2 SDA LINE P A C K A C K A C K A C K N O A C K © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 Doc No. 1095, Rev. C CAT34C02 SOFTWARE WRITE PROTECTION The lower half of memory (first 128 bytes) can be protected against Write operations by setting one of two Software Write Protection (SWP) flags. The Permanent Software Write Protection (PSWP) flag can be set, but not cleared, by the user. This flag can be set or queried ‘in-system’. The Reversible Software Write Protection (RSWP) flag can be set or queried and cleared by the user during DDR2 DIMM testing. All RSWP related commands require the presence of a very high voltage - VHV - on address pin A0 and fixed CMOS logic levels on the other two address pins. Thus, for RSWP related commands, the address pins are used to decode the mode, rather than to ‘identify’ the device. A detailed description of all SWP commands can be found in Table 1. All these commands are preceded by a START and terminated with a STOP, following the ACK or NoACK from the CAT34C02. The first four bits of the Slave address byte must be 0110, in contrast to the regular 1010 ‘preamble’ used for memory Read or Write commands. The next three bits must match the logic state of the three physical address pins. For PSWP commands, the address pins are all at CMOS levels, and any one of the eight possible combinations is valid. For RSWP commands, the A0 pin must be at VHV and will be interpreted as a logic ‘1’. The other two address pins must be at fixed CMOS levels, A2 at GND and A1 at GND for Set RSWP commands and at VCC for Clear RSWP commands. The VHV level must be established on pin A0 before the START and maintained just beyond the STOP. Commands where the last bit of the Slave address is ‘0’, are similar to a ‘Byte Write’, except that both byte address and data following the Slave address, are ‘don’t care’ (i.e. just place holders) (Figure 12). Query type commands, where the last bit in the Slave address is ‘1’, are somewhat similar to an’‘Immediate Address Read’, except that no data byte is expected from the device; the ACK or NoACK itself is the response to the query. Therefore, the Master will immediately follow up this response with a STOP (Figure 13). DELIVERY STATE The CAT34C02 is shipped ‘unprotected’, i.e. neither SWP flag is set. The entire 2-Kb memory is erased, i.e. all bytes are FF. Doc. No. 1095, Rev. C 10 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT34C02 Table 1. SWP Commands Action Control Pin Levels (1) WP Set PSWP Set RSWP Clear RSWP A2 A1 A0 Flag State (2) Slave Address PSWP RSWP b7 to b4 b3 b2 b1 b0 ACK Address ACK Data ACK Write ? Byte ? Byte ? Cycle X A2 A1 A0 1 X A2 A1 A0 X No GND A2 A1 A0 0 X A2 A1 A0 0 Yes X Yes X Yes Yes VCC A2 A1 A0 0 X A2 A1 A0 0 Yes X Yes X No No X A2 A1 A0 0 X A2 A1 A0 1 Yes X GND GND VHV 1 X 0 0 1 X No X GND GND VHV 0 1 0 0 1 X No GND GND GND VHV 0 0 0 0 1 0 Yes X Yes X Yes Yes VCC GND GND VHV 0 0 0 0 1 0 Yes X Yes X No No 0110 X GND GND VHV 0 0 0 0 1 1 Yes X GND VCC VHV 1 X 0 1 1 X No GND GND VCC VHV 0 X 0 1 1 0 Yes X Yes X Yes Yes VCC GND VCC VHV 0 X 0 1 1 0 Yes X Yes X No No X GND VCC VHV 0 X 0 1 1 1 Yes Note: (1) Here A2, A1 and A0 are either at VCC or GND. (2) 1 stands for ‘Set’, 0 stands for ‘Not Set’, X stands for ‘don’t care’. Figure 12. Software Write Protect (Write) BUS ACTIVITY: MASTER SDA LINE S T A R T S S T O P BYTE ADDRESS DATA XXXXXXXX XXXXXXXX SLAVE ADDRESS A C K A C K P N A C or O K A C K X = Don't Care Figure 13. Software Write Protect (Read) BUS ACTIVITY: MASTER SDA LINE S T A R T S SLAVE ADDRESS S T O P P N A C or O K A C K © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 11 Doc No. 1095, Rev. C CAT34C02 8-LEAD TSSOP (Y) D 5 8 SEE DETAIL A C E E1 E/2 GAGE PLANE 4 1 PIN #1 IDENT. 0.25 θ1 L A2 SEATING PLANE SEE DETAIL A A e A1 b SYMBOL A A1 A2 b c D E E1 e L θ1 MIN 0.05 0.18 0.19 0.09 2.90 4.30 0.50 0.00 NOM 0.19 3.00 6.4 BSC 4.40 0.65 BSC 0.60 MAX 1.10 0.15 1.05 0.30 0.02 3.10 4.50 0.70 8.00 Notes: 1. Lead coplanarity is 0.004” (0.102mm) maximum. Doc. No. 1095, Rev. C 12 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT34C02 8-PAD TDFN 2X3 PACKAGE (VP2) A E PIN 1 INDEX AREA A1 D D2 A2 A3 K SYMBOL MIN NOM MAX A A1 A2 A3 b D D2 E E2 e K L 0.70 0.00 0.45 0.75 0.02 0.55 0.20 REF 0.25 2.00 1.40 3.00 1.30 0.50 TYP 0.80 0.05 0.65 0.30 0.40 0.20 1.90 1.30 2.90 1.20 0.20 0.20 E2 0.30 2.10 1.50 3.10 1.40 PIN 1 ID L b e 3xe NOTE: 1. ALL DIMENSIONS IN MM. ANGLES IN DEGREES. 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMNALS. COPLANARITY SHALL NOT EXCEED 0.08 MM. 3. WARPAGE SHALL NOT EXCEED 0.10 MM. 4. PACKAGE LENGTH / PACKAGE WIDTH ARE NOT CONSIDERED AS SPECIAL CHARACTERISTIC. 5. REFER JEDEC MO-229. 6. FRAME STOCK# FLXXX (Selective PPF), NSE PKG CODE TD23B008P. TDFN2X3 (03).eps © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 13 Doc No. 1095, Rev. C CAT34C02 ORDERING INFORMATION Prefix Device # CAT 34C02 Company ID Suffix Y Product Number TE13 I Temperature Range I = Industrial (-40°C to +85°C) Package Y: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating) VP2: TDFN (Lead-free, Halogen-free, NiPdAu lead plating) Tape & Reel TE13: 3000/Reel Notes: (1) The device used in the above example is a CAT34C02YI-TE13 (TSSOP, Industrial Temperature, 1.7 Volt to 5.5 Volt Operating Voltage, Tape & Reel) PACKAGE MARKING 8-Lead TSSOP 8-Lead TDFN YMG EAN 34C02I NNN YM Y M G 34C02 I = Production Year = Production Month = Die Revision = Device Code = Industrial Temperature Range E A = Device Code N = Traceability Code Y = Production Year M = Production Month Notes: (1) The circle on the package marking indicates the location of Pin 1. Doc. No. 1095, Rev. C 14 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT34C02 REVISION HISTORY Date Revision Comments 09/27/05 A Initial Issue 09/28/05 B Update Features Update Absolute Maximum Ratings Update D.C. Operating Characteristics Update Pin Impedance Characteristics Update A.C. Characteristics Update I2C Bus Protocol - Power-On Reset (POR) 10/03/05 C Update Power-On Reset (POR) © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 15 Doc No. 1095, Rev. C CAT34C02 Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ MiniPot™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled “Advance Information” or “Preliminary” and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Doc. No. 1095, Rev. C 16 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.caalyst-semiconductor.com Publication #: Revison: Issue date: 1095 C 10/03/05