Cypress CY7C4285V 32k/64kx18 low voltage deep sync fifo Datasheet

285V
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
32K/64Kx18 Low Voltage Deep Sync FIFOs
Features
Functional Description
• 3.3V operation for low power consumption and easy
integration into low-voltage systems
• High-speed, low-power, first-in first-out (FIFO)
memories
• 8K x 18 (CY7C4255V)
• 16K x 18 (CY7C4265V)
• 32K x 18 (CY7C4275V)
• 64K x 18 (CY7C4285V)
• 0.35 micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
times)
• Low power
— ICC = 30 mA
— ISB = 4 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
• Retransmit function
• Output Enable (OE) pin
• Independent read and write enable pins
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• 64-pin 10x10 STQFP
• Pin-compatible density upgrade to CY7C42X5V-ASC
families
• Pin-compatible 3.3V solutions for CY7C4255/65/75/85
The CY7C4255/65/75/85V are high-speed, low-power, first-in
first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to
the CY7C42X5V Synchronous FIFO family. The
CY7C4255/65/75/85V can be cascaded to increase FIFO
depth. Programmable features include Almost Full/Almost
Empty flags. These FIFOs provide solutions for a wide variety of
data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and a write enable
pin (WEN).
When WEN is asserted, data is written into the FIFO on the rising
edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled
in a similar manner by a free-running read clock (RCLK) and a read
enable pin (REN). In addition, the CY7C4255/65/75/85V have an
output enable pin (OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies
up to 67 MHz are achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (WXI,
RXI), cascade output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of the
next device, and the WXO and RXO pins of the last device should be
connected to the WXI and RXI pins of the first device. The FL pin of
the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC.
D0 – 17
Logic Block Diagram
INPUT
REGISTER
WCLK
WEN
FLAG
PROGRAM
REGISTER
WRITE
CONTROL
High
Density
Dual-Port
RAM Array
8Kx9
16Kx9
32Kx9
64Kx9
WRITE
POINTER
RS
FL/RT
WXI
WXO/HF
RXI
RXO
FF
EF
PAE
PAF
SMODE
FLAG
LOGIC
READ
POINTER
RESET
LOGIC
THREE-ST ATE
OUTPUT REGISTER
EXPANSION
LOGIC
Cypress Semiconductor Corporation
Document #: 38-06012 Rev. **
Q0 – 17
•
READ
CONTROL
OE
3901 North First Street
RCLK
•
REN
San Jose
4275V–1
•
CA 95134 • 408-943-2600
Revised September 7, 2001
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REN
LD
OE
RS
VCC
GND
EF
Q17
Q16
GND
Q15
VCC/SMODE
CY7C4255V
CY7C4265V
CY7C4275V
CY7C4285V
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
D16
D17
GND
RCLK
STQFP
Top View
Q14
Q13
GND
Q12
Q11
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCC
Q10
Q9
GND
Q8
Q7
Q6
Q5
GND
Q4
VCC
Functional Description (continued)
The CY7C4255/65/75/85V provides five status pins. These
pins are decoded to determine one of five states: Empty, Almost Empty, Half Full, Almost Full, and Full (see Table 2). The
Half Full flag shares the WXO pin. This flag is valid in the
stand-alone and width-expansion configurations. In the depth
expansion, this pin provides the expansion out (WXO) information that is used to signal the next FIFO when it will be activated.
Q3
Q0
Q1
GND
Q2
PAE
FL/RT
WCLK
WEN
WXI
VCC
PAF
RXI
FF
XO/HF
RXO
4275V–3
The Empty and Full flags are synchronous, i.e., they change
state relative to either the read clock (RCLK) or the write clock
(WCLK). When entering or exiting the Empty states, the flag is
updated exclusively by the RCLK. The flag denoting Full states
is updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags will remain valid from one
clock cycle to the next. The Almost Empty/Almost Full flags
become synchronous if the VCC/SMODE is tied to VSS. All
configurations are fabricated using an advanced 0.35µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Selection Guide
7C4255/65/75/85V-10
7C4255/65/75/85V-15
7C4255/65/75/85V-25
Maximum Frequency (MHz)
100
66.7
40
Maximum Access Time (ns)
8
10
15
Minimum Cycle Time (ns)
10
15
25
Minimum Data or Enable Set-Up (ns)
3.5
4
6
Minimum Data or Enable Hold (ns)
0
0
1
Maximum Flag Delay (ns)
8
10
15
30
30
30
Active Power Supply
Current (ICC1) (mA)
Commercial
Industrial
CY7C4255V
35
CY7C4265V
CY7C4275V
CY7C4285V
Density
8K x 18
16K x 18
32K x 18
64K x 18
Package
64-pin 10x10 TQFP
64-pin 10x10 TQFP
64-pin 10x10 TQFP
64-pin 10x10 TQFP
Document #: 38-06012 Rev. **
Page 2 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Pin Definitions
Signal Name
Description
I/O
Function
D0–17
Data Inputs
I
Data inputs for an 18-bit bus.
Q0–17
Data Outputs
O
Data outputs for an 18-bit bus.
WEN
Write Enable
I
Enables the WCLK input.
REN
Read Enable
I
Enables the RCLK input.
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not
Full. When LD is asserted, WCLK writes data into the programmable flag-offset
register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flagoffset register.
WXO/HF
Write Expansion
Out/Half Full Flag
O
Dual-Mode Pin:
Single device or width expansion – Half Full status flag.
Cascaded – Write Expansion Out signal, connected to WXI of next device.
EF
Empty Flag
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
O
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
O
When PAE is LOW, the FIFO is almost empty based on the almost-empty offset
value programmed into the FIFO. PAE is asynchronous when VCC/SMODE is tied
to VCC; it is synchronized to RCLK when V CC/SMODE is tied to VSS.
PAF
Programmable
Almost Full
O
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when VCC/SMODE is tied to
VCC; it is synchronized to WCLK when V CC/SMODE is tied to VSS.
LD
Load
I
When LD is LOW, D0–17 (Q0–17) are written (read) into (from) the programmableflag-offset register.
FL/RT
First Load/
Retransmit
I
Dual-Mode Pin:
Cascaded – The first device in the daisy chain will have FL tied to VSS; all other
devices will have FL tied to VCC. In standard mode or width expansion, FL is tied
to VSS on all devices.
Not Cascaded – Tied to VSS. Retransmit function is also available in stand-alone
mode by strobing RT.
WXI
Write Expansion
Input
I
Cascaded – Connected to WXO of previous device.
Not Cascaded – Tied to VSS.
RXI
Read Expansion
Input
I
Cascaded – Connected to RXO of previous device.
Not Cascaded – Tied to VSS.
RXO
Read Expansion
Output
O
Cascaded – Connected to RXI of next device.
RS
Reset
I
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
VCC/SMODE
Synchronous
Almost Empty/
Almost Full Flags
I
Dual-Mode Pin:
Asynchronous Almost Empty/Almost Full flags – tied to VCC.
Synchronous Almost Empty/Almost Full flags – tied to VSS.
(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)
Document #: 38-06012 Rev. **
Page 3 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL–STD–883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature ................................ –65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied............................................ –55°C to +125°C
Supply Voltage to Ground Potential .........–0.5V to VCC+0.5V
Range
Ambient
Temperature
VCC[2]
DC Voltage Applied to Outputs
in High Z State .........................................–0.5V to VCC+0.5V
Commercial
0°C to +70°C
3.3V ±300 mV
–40°C to +85°C
3.3V ±300 mV
Industrial
DC Input Voltage ..........................................−0.5V to VCC+0.5V
[1]
Electrical Characteristics Over the Operating Range[3]
Parameter
Description
7C4255/65/75/
85V-10
7C4255/65/75/
85V-15
7C4255/65/75/
85V-25
Test Conditions
Min.
Min.
Min.
VCC = Min., IOH = –1.0 mA
VCC = 3.0V. IOH = –2.0 mA
2.4
Max.
Max.
VOH
Output HIGH
Voltage
VOL
Output LOW Volt- VCC = Min.,IOL = 4.0 mA
age
VCC = 3.0V.,IOL = 8.0 mA
VIH[4]
Input HIGH
Voltage
2.0
VCC
2.0
VCC
VIL[4]
Input LOW
Voltage
–0.5
0.8
–0.5
IIX
Input Leakage
Current
VCC = Max.
–10
+10
IOZL
IOZH
Output OFF,
High Z Current
OE > VIH,
VSS < VO < VCC
–10
+10
ICC1[5]
Active Power
Supply Current
Com’l
Average Standby
Current
Com’l
ISB
[6]
2.4
0.4
30
Ind
Max.
2.4
0.4
V
0.4
V
2.0
VCC
V
0.8
–0.5
0.8
V
–10
+10
–10
+10
µA
–10
+10
–10
+10
µA
30
mA
30
35
4
Ind
Unit
mA
4
4
mA
4
mA
Capacitance[7]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Max.
Unit
5
pF
7
pF
Notes:
1. TA is the “instant on” case temperature.
2. VCC range for commercial -10 ns is 3.3V ±150mV.
3. See the last page of this specification for Group A subgroup testing information.
4. The VIH and VIL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the
previous device or VSS .
5. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs
are unloaded.
6. All inputs = VCC – 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz), and FL/RT which is at VSS. All outputs are unloaded.
7. Tested initially and after any design changes that may affect these parameters.
Document #: 38-06012 Rev. **
Page 4 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
AC Test Loads and Waveforms (-15 -25)[8, 9]
R1=330Ω
ALL INPUT PULSES
3.3V
OUTPUT
3.0V
R2=510Ω
CL
90%
10%
90%
10%
GND
≤ 3 ns
INCLUDING
JIG AND
SCOPE
4275V–4
Equivalent to:
≤ 3 ns
THÉVENIN EQUIVALENT
200 Ω
OUTPUT
4287V–5
2.0V
AC Test Loads and Waveforms (-10)
ALL INPUT PULSES
VCC/2
3.0V
50Ω
I/O
90%
10%
90%
10%
GND
≤ 3 ns
Z0=50Ω
≤ 3 ns
4275V–6
4275V–7
Switching Characteristics Over the Operating Range
7C4255/65/75/85V
-10
Parameter
Description
Min.
Max.
7C4255/65/75/85V 7C4255/65/75/85V
-15
-25
Min.
100
Max.
Min.
Unit
40
MHz
15
ns
tS
Clock Cycle Frequency
tA
Data Access Time
2
tCLK
Clock Cycle Time
10
15
25
ns
tCLKH
Clock HIGH Time
4.5
6
10
ns
tCLKL
Clock LOW Time
4.5
6
10
ns
tDS
Data Set-Up Time
3.5
4
6
ns
tDH
Data Hold Time
0
0
1
ns
tENS
Enable Set-Up Time
3.5
4
6
ns
tENH
Enable Hold Time
0
0
1
ns
10
15
25
ns
8
10
15
ns
[10]
tRS
Reset Pulse Width
tRSR
Reset Recovery Time
tRSF
Reset to Flag and Output Time
tPRT
Retransmit Pulse Width
tRTR
Retransmit Recovery Time
tOLZ
Output Enable to Output in Low Z
tOE
Output Enable to Output Valid
8
66.7
Max.
2
10
[11]
10
2
15
25
ns
60
60
60
ns
90
90
90
ns
0
0
0
ns
3
7
3
10
3
12
ns
Notes:
8. CL = 30 pF for all AC parameters except for tOHZ.
9. CL = 5 pF for tOHZ .
10. Pulse widths less than minimum values are not allowed.
11. Values guaranteed by design, not currently tested.
Document #: 38-06012 Rev. **
Page 5 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Switching Characteristics Over the Operating Range (continued)
7C4255/65/75/85V
-10
Parameter
Description
[11]
7C4255/65/75/85V 7C4255/65/75/85V
-15
-25
Min.
Max.
Min.
Max.
Min.
Max.
Unit
3
7
3
8
3
12
ns
tOHZ
Output Enable to Output in High Z
tWFF
Write Clock to Full Flag
8
10
15
ns
tREF
Read Clock to Empty Flag
8
10
15
ns
tPAFasynch
Clock to Programmable Almost-Full
Flag[12] (Asynchronous mode,
VCC/SMODE tied to VCC)
15
16
20
ns
tPAFsynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to
VSS)
8
10
15
ns
tPAEasynch
Clock to Programmable Almost-Empty
Flag[12] (Asynchronous mode, VCC/SMODE
tied to VCC)
15
16
20
ns
tPAEsynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to
VSS)
8
10
15
ns
tHF
Clock to Half-Full Flag
12
16
20
ns
tXO
Clock to Expansion Out
6
10
15
ns
tXI
Expansion in Pulse Width
4.5
6.5
10
ns
tXIS
Expansion in Set-Up Time
4
5
10
ns
tSKEW1
Skew Time between Read Clock and
Write Clock for Full Flag
5
6
10
ns
tSKEW2
Skew Time between Read Clock and
Write Clock for Empty Flag
5
6
10
ns
tSKEW3
Skew Time between Read Clock and
Write Clock for Programmable Almost
Empty and Programmable Almost Full
Flags (Synchronous Mode only)
10
15
18
ns
Note:
12. tPAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tPAF(E).
Document #: 38-06012 Rev. **
Page 6 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Switching Waveforms
Write Cycle Timing
tCLK
tCLKH
tCLKL
WCLK
tDS
tDH
D0 –D17
tENS
tENH
WEN
NO OPERATION
tWFF
tWFF
FF
tSKEW1 [13]
RCLK
REN
4275V–8
Read Cycle Timing
tCLK
tCLKH
tCLKL
RCLK
tENS
tENH
REN
NO OPERATION
tREF
tREF
EF
tA
VALID DATA
Q0 –Q17
tOLZ
tOHZ
tOE
OE
tSKEW2[14]
WCLK
WEN
4275V–9
Notes:
13. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
14. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge.
Document #: 38-06012 Rev. **
Page 7 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Switching Waveforms (continued)
Reset Timing [15]
tRS
RS
tRSR
REN, WEN,
LD
tRSF
EF,PAE
tRSF
FF,PAF,
HF
tRSF
[16]
OE=1
Q0 – Q17
OE=0
4275V–10
First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
tDS
D0 –D17
D0 (FIRSTVALID WRITE)
D1
D2
D3
D4
tENS
[17]
tFRL
WEN
tSKEW2
RCLK
tREF
EF
REN
tA
Q0 –Q17
tA
D0
[18]
D1
tOLZ
tOE
OE
4275V–11
Notes:
15. The clocks (RCLK, WCLK) can be free-running during reset.
16. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
17. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2
or tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW).
18. The first word is always available the cycle after EF goes HIGH.
Document #: 38-06012 Rev. **
Page 8 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Switching Waveforms (continued)
Empty Flag Timing
WCLK
tDS
tDS
D0
D0 –D17
D1
tENH
tENS
tENH
tENS
WEN
tFRL[17]
tFRL[17]
RCLK
tREF
tSKEW2
tREF
tREF
tSKEW2
EF
REN
OE
tA
D0
Q0 –Q17
4275V–12
Full FlagTiming
NO WRITE
NO WRITE
WCLK
tSKEW1
[13]
tDS
tSKEW1 [13]
DATA WRITE
DATA WRITE
D0 –D17
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENH
tENH
tENS
tENS
REN
OE
LOW
tA
Q0 –Q17
DATA IN OUTPUT REGISTER
tA
DATA READ
NEXT DATA READ
4275V–13
Document #: 38-06012 Rev. **
Page 9 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Switching Waveforms (continued)
Half-Full Flag Timing
tCLKH
tCLKL
WCLK
tENS tENH
WEN
tHF
HF
HALF FULL + 1
OR MORE
HALF FULL OR LESS
HALF FULL OR LESS
tHF
RCLK
tENS
REN
4275V–14
Programmable Almost Empty Flag Timing
tCLKH
tCLKL
WCLK
tENS tENH
WEN
tPAE
PAE
[19]
N + 1 WORDS
IN FIFO
tPAE
n WORDS IN FIFO
RCLK
tENS
REN
4275V–15
Note:
19. PAE is offset = n. Number of data words into FIFO already = n.
Document #: 38-06012 Rev. **
Page 10 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Switching Waveforms (continued)
Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW))
tCLKL
tCLKH
WCLK
tENS tENH
WEN
Note 20
PAE
N + 1 WORDS
IN FIFO
tSKEW3 [21]
tPAE synch
Note 22
tPAE synch
RCLK
tENS
tENS tENH
REN
4275V–16
Programmable Almost Full Flag Timing
tCLKL
tCLKH
Note 23
WCLK
tENS tENH
WEN
PAF
[24]
tPAF
FULL– M WORDS
IN FIFO [25]
FULL– (M+1) WORDS
IN FIFO [26]
tPAF
RCLK
tENS
REN
4275V–17
Notes:
20. PAE offset − n.
21. tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the
rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK.
22. If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW.
23. PAF offset = m. Number of data words written into FIFO already = 8192 − (m + 1) for the CY7C4255V, 16384 − (m + 1) for the CY7C4265V, 32768 − (m + 1)
for the CY7C4275V, and 65536 − (m + 1) for the CY7C4285V.
24. PAF is offset = m.
25. 8192 − m words in CY7C4255V, 16384 − m words in CY7C4265V, 32768 − m words in CY7C4275V, and 65536 − m words in CY7C4285V.
26. 8192 − (m + 1) words in CY7C4255V, 16384 − (m + 1) words in CY7C4265V, 32768 − (m + 1) words in CY7C4275V, and 65536 − (m + 1) words in CY7C4285V.
Document #: 38-06012 Rev. **
Page 11 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Switching Waveforms (continued)
Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW))
Note 27
tCLKL
tCLKH
WCLK
tENS tENH
WEN
tPAF
PAF
FULL– M WORDS
IN FIFO [25]
FULL – M + 1 WORDS
IN FIFO
tSKEW3[28]
tPAF synch
RCLK
tENS
tENS tENH
REN
4275V–18
Write Programmable Registers
tCLK
tCLKL
tCLKH
WCLK
tENS
tENH
LD
tENS
WEN
tDS
tDH
PAE OFFSET
D0 –D17
PAE OFFSET
PAF OFFSET
D0 – D11
4275V–19
Notes:
27. If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LOW.
28. tSKEW3 is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge
of RCLK and the rising edge of WCLK is less than tSKEW3, then PAF may not change state until the next WCLK rising edge.
Document #: 38-06012 Rev. **
Page 12 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Switching Waveforms (continued)
Read Programmable Registers
tCLK
tCLKL
tCLKH
RCLK
tENS
tENH
LD
tENS
WEN
tA
UNKNOWN
Q0 –Q17
PAE OFFSET
PAF OFFSET
PAE OFFSET
4275V–20
Write Expansion Out Timing
tCLKH
WCLK
Note 30
tXO
Note 29
WXO
tXO
tENS
WEN
4275V–21
Read Expansion Out Timing
tCLKH
WCLK
Note 30
tXO
RXO
tXO
tENS
REN
4275V–22
Write Expansion In Timing
tXI
WXI
WCLK
tXIS
4275V–23
Notes:
29. Write to Last Physical Location.
30. Read from Last Physical Location.
Document #: 38-06012 Rev. **
Page 13 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Switching Waveforms (continued)
Read Expansion In Timing
tXI
RXI
tXIS
RCLK
4275V–24
Retransmit Timing
[31, 32, 33]
FL/RT
tPRT
tRTR
REN/WEN
EF/FF
and all
async flags
HF/PAE/PAF
4275V–25
Notes:
31. Clocks are free-running in this case.
32. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR.
33. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after tRTR to update these flags.
Document #: 38-06012 Rev. **
Page 14 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Architecture
normal read/write operation. When the LD pin is set LOW, and
WEN is LOW, the next offset register in sequence is written.
The CY7C4255/65/75/85V consists of an array of
8K/16K/32K/64K words of 18 bits each (implemented by a
dual-port array of SRAM cells), a read pointer, a write pointer,
control signals (RCLK, WCLK, REN, WEN, RS), and flags (EF,
PAE, HF, PAF, FF). The CY7C4255/65/75/85V also includes
the control signals WXI, RXI, WXO, RXO for depth expansion.
The contents of the offset registers can be read on the output
lines when the LD pin is set LOW and REN is set LOW; then,
data can be read on the LOW-to-HIGH transition of the read
clock (RCLK).
Resetting the FIFO
Table 1. Write Offset Register
WCLK[34]
LD
WEN
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition signified by EF being LOW. All data outputs go LOW after the
falling edge of RS only if OE is asserted. In order for the FIFO
to reset to its default state, the user must not read or write while
RS is LOW.
0
0
Writing to offset registers:
Empty Offset
Full Offset
0
1
No Operation
FIFO Operation
1
0
Write Into FIFO
1
1
No Operation
When the WEN signal is active (LOW), data present on the
D0–17 pins is written into the FIFO on each rising edge of the
WCLK signal. Similarly, when the REN signal is active LOW,
data in the FIFO memory will be presented on the Q0–17 outputs. New data will be presented on each rising edge of RCLK
while REN is active LOW and OE is LOW. REN must set up
tENS before RCLK for it to be a valid read function. WEN must
occur tENS before WCLK for it to be a valid write function.
An output enable (OE) pin is provided to three-state the Q0–17
outputs when OE is deasserted. When OE is enabled (LOW),
data in the output register will be available to the Q0–17 outputs
after tOE. If devices are cascaded, the OE function will only
output data on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and under flow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0–17 outputs
even after additional reads occur.
Programming
The CY7C4255/65/75/85V devices contain two 16-bit offset
registers. Data present on D0–15 during a program write will
determine the distance from Empty (Full) that the Almost Empty (Almost Full) flags become active. If the user elects not to
program the FIFO’s flags, the default offset values are used
(see Table 2). When the Load LD pin is set LOW and WEN is
set LOW, data on the inputs D0–15 is written into the Empty
offset register on the first LOW-to-HIGH transition of the write
clock (WCLK). When the LD pin and WEN are held LOW then
data is written into the Full offset register on the second LOWto-HIGH transition of the write clock (WCLK). The third transition of the write clock (WCLK) again writes to the Empty offset
register (see Table 1). Writing all offset registers does not have
to occur at one time. One or two offset registers can be written
and then, by bringing the LD pin HIGH, the FIFO is returned to
Selection
Flag Operation
The CY7C4255/65/75/85V devices provide five flag pins to indicate the condition of the FIFO contents. Empty and Full are
synchronous. PAE and PAF are synchronous if VCC/SMODE
is tied to VSS.
Full Flag
The Full Flag (FF) will go LOW when device is Full. Write operations are inhibited whenever FF is LOW regardless of the
state of WEN. FF is synchronized to WCLK, i.e., it is exclusively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW, regardless of the state of REN. EF is synchronized to RCLK, i.e., it is
exclusively updated by each rising edge of RCLK.
Programmable Almost Empty/Almost Full Flag
The CY7C4255/65/75/85V features programmable Almost
Empty and Almost Full Flags. Each flag can be programmed
(described in the Programming section) a specific distance
from the corresponding boundary flags (Empty or Full). When
the FIFO contains the number of words or fewer for which the
flags have been programmed, the PAF or PAE will be asserted,
signifying that the FIFO is either Almost Full or Almost Empty.
See Table 2 for a description of programmable flags.
When the SMODE pin is tied LOW, the PAF flag signal transition is caused by the rising edge of the write clock and the PAE
flag transition is caused by the rising edge of the read clock.
Note:
34. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Document #: 38-06012 Rev. **
Page 15 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Table 2. Flag Truth Table
Number of Words in FIFO
7C4255V – 8K x 18
0
1 to n
[35]
7C4265V – 16K x 18 7C4275V – 32K x 18
7C4285V – 64K x 18
FF
PAF
HF
PAE
EF
0
0
H
H
H
L
L
[35]
1 to n
H
H
H
L
H
1 to n
(n+1) to 4096
0
[35]
1 to n
(n+1) to 8192
[35]
(n+1) to 16384
(n+1) to 32768
H
H
H
H
H
4097 to (8192–(m+1)) 8193 to (16384
–(m+1))
16385 to
(32768–(m+1))
32769 to (65536
–(m+1))
H
H
L
H
H
(8192–m)[36] to 8192
(16384–m)[36] to
16384
(32768–m)[36] to
32767
(65536–m)[36] to
65535
H
L
L
H
H
8192
16384
32768
65536
L
L
L
H
H
Retransmit
Data written to the FIFO after activation of RT are transmitted
also.
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The full depth of the FIFO can be repeatedly retransmitted.
Width Expansion Configuration
The Retransmit (RT) input is active in the stand-alone and
width expansion modes. The retransmit feature is intended for
use when a number of writes equal to or less than the depth
of the FIFO have occurred and at least one word has been
read since the last RS cycle. A HIGH pulse on RT resets the
internal read pointer to the first physical location of the FIFO.
WCLK and RCLK may be free running but must be disabled
during and tRTR after the retransmit pulse. With every valid
read cycle after retransmit, previously accessed data is read
and the read pointer is incremented until it is equal to the write
pointer. Flags are governed by the relative locations of the read
and write pointers and are updated during a retransmit cycle.
The CY7C4255/65/75/85V can be expanded in width to provide word widths greater than 18 in increments of 18. During
width expansion mode all control line inputs are common and
all flags are available. Empty (Full) flags should be created by
ANDing the Empty (Full) flags of every FIFO; the PAE and PAF
flags can be detected from any one device. This technique will
avoid reading data from, or writing data to the FIFO that is
“staggered” by one clock cycle due to the variations in skew
between RCLK and WCLK. Figure 1 demonstrates a 36-word
width by using two CY7C4255/65/75/85Vs.
RESET (RS)
DATA IN (D) 36
RESET (RS)
18
18
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
READ ENABLE (REN)
WRITE ENABLE (WEN)
OUTPUT ENABLE (OE)
LOAD (LD)
PROGRAMMABLE (PAF)
PROGRAMMABLE(PAE)
7C4255V
7C4265V
7C4275V
7C4285V
7C4255V
7C4265V
7C4275V
7C4285V
HALF FULL FLAG (HF)
FF
FF
EF
EMPTY FLAG (EF)
EF
18
FULL FLAG (FF)
DATA OUT (Q)
36
18
FIRST LOAD (FL)
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (RXI)
4275V–24
Figure 1. Block Diagram of 8K/16K/32K/64K x 18 Low-Voltage Synchronous FIFO Memory Used in a Width Expansion
Configuration
Notes:
35. n = Empty Offset (Default Values: CY7C4255/65/75/85V n = 127).
36. m = Full Offset (Default Values: CY7C4255/65/75/85V n = 127).
Document #: 38-06012 Rev. **
Page 16 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Depth Expansion Configuration
(with Programmable Flags)
3. The Write Expansion Out (WXO) pin of each device must
be tied to the Write Expansion In (WXI) pin of the next
device.
The CY7C4255/65/75/85V can easily be adapted to applications requiring more than 8K/16K/32K/64K words of buffering.
Figure 2 shows Depth Expansion using three CY7C4255/65/
75/85Vs. Maximum depth is limited only by signal loading. Follow these steps:
4. The Read Expansion Out (RXO) pin of each device must be
tied to the Read Expansion In (RXI) pin of the next device.
1. The first device must be designated by grounding the First
Load (FL) control input.
2. All other devices must have FL in the HIGH state.
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in the Depth Expansion Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by
ORing together these respective flags for monitoring. The
composite PAE and PAF flags are not precise.
WXO RXO
7C4255V
7C4265V
7C4275V
7C4285V
VCC
FL
FF
EF
PAE
PAF
WXI RXI
WXO RXO
7C4255V
7C4265V
7C4275V
7C4285V
DATAIN (D)
VCC
DATA OUT (Q)
FL
FF
EF
PAF
PAE
WXI RXI
WRITE CLOCK (WCLK)
WXO RXO
WRITE ENABLE (WEN)
READ ENABLE (REN)
7C4255V
7C4265V
7C4275V
7C4285V
RESET (RS)
READ CLOCK (RCLK)
OUTPUT ENABLE (OE)
LOAD (LD)
FF
FF
PAF
EF
EF
PAFWXI RXI PAE
PAE
FIRST LOAD (FL)
4275V–25
Figure 2. Block Diagram of 8K/16K/32K/64K x 18 Low-Voltage Synchronous FIFO Memory
with Programmable Flags used in Depth Expansion Configuration
Document #: 38-06012 Rev. **
Page 17 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Ordering Information
8Kx18 Low-Voltage Deep Sync FIFO
Speed
(ns)
Ordering Code
Package
Name
Package
Type
Operating
Range
10
CY7C4255V–10ASC
A64
64-Lead 10x10 Thin Quad Flatpack
Commercial
15
CY7C4255V–15ASC
A64
64-Lead 10x10 Thin Quad Flatpack
Commercial
25
CY7C4255V–25ASC
A64
64-Lead 10x10 Thin Quad Flatpack
Commercial
16Kx18 Low-Voltage Deep Sync FIFO
Speed
(ns)
Ordering Code
Package
Name
Package
Type
Operating
Range
10
CY7C4265V–10ASC
A64
64-Lead 10x10 Thin Quad Flatpack
Commercial
15
CY7C4265V–15ASC
A64
64-Lead 10x10 Thin Quad Flatpack
Commercial
25
CY7C4265V–25ASC
A64
64-Lead 10x10 Thin Quad Flatpack
Commercial
32Kx18 Low-Voltage Deep Sync FIFO
Speed
(ns)
Ordering Code
Package
Name
Package
Type
Operating
Range
10
CY7C4275V–10ASC
A64
64-Lead 10x10 Thin Quad Flatpack
Commercial
15
CY7C4275V–15ASC
A64
64-Lead 10x10 Thin Quad Flatpack
Commercial
64Kx18 Low-Voltage Deep Sync FIFO
Speed
(ns)
Ordering Code
Package
Name
Package
Type
Operating
Range
10
CY7C4285V–10ASC
A64
64-Lead 10x10 Thin Quad Flatpack
Commercial
15
CY7C4285V–15ASI
A64
64-Lead 10x10 Thin Quad Flatpack
Industrial
25
CY7C4285V–25ASC
A64
64-Lead 10x10 Thin Quad Flatpack
Commercial
Document #: 38-06012 Rev. **
Page 18 of 20
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Package Diagrams
64-Pin Thin Plastic Quad Flat Pack (10 x 10 x 1.4 mm) A64
51-85051-A
Document #: 38-06012 Rev. **
Page 19 of 20
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Document Title: CY7C4255V, CY7C4265V, CY7C4275V, CY7C4285V 32K/64K x 18 Low Voltage Deep Sync FIFOs
Document Number: 38-06012
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
106473
09/10/01
SZV
Change from Spec number: 38-00654 to 38-06012
Document #: 38-06012 Rev. **
Page 20 of 20