CALMIRCO CM3112 150ma/1.2v cmos ldo regulator Datasheet

PRELIMINARY
CM3112
150mA/1.2V CMOS LDO Regulator
with Power Good
Features
Product Description
•
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•
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•
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The CM3112-12 is a low quiescent current (90uA) regulator that delivers up to 150mA of load current at a
fixed 1.2V output. All the necessary circuitry has been
included to deliver a 50Ω power good signal (open
drain) which remains for 5ms after the output has
exceeded 90% (typ) of its nominal level.
LDO regulator with Power Good
No capacitor required on the LDO output
Power Good (PG) control signal
Regulated 1.2V output
150mA output current
Low quiescent operating current (90µA typical)
"Zero" disable mode current
Foldback current limiting protection
Thermal shutdown protection
SOT23-5 package
Micrel MIC5258, MIC5268 compatible pinout
Lead-free version available
A dedicated control input (EN, Active High) has been
included for power-up sequencing flexibility. When this
input is taken low, the regulator is disabled. In this
state, the supply current will drop to near zero. An internal discharge MOSFET (500Ω) resistance will force the
output to ground whenever the device has been shutdown.
Applications
•
•
•
The CM3112-12 is fully protected, offering both overload current limiting and high temperature thermal
shutdown.
Pentium 4 Motherboards
PC Cards
Peripheral Adapter Cards
Housed in a tiny SOT23 package, the device is ideal for
space critical applications and is also available with
optional lead-free finishing.
Typical Application Circuit
Simplified Electrical Schematic
1.2V/150mA
IN
1kΩ
EN
+
CM3112-12
VIN
IN
EN
EN
OUT
OUT
VOUT
PG
PG
VREF
1.2V
-
+
GND
0.1µF*
2.5ms
-
0.1µF*
PG
VREF X 0.93
GND
1X
* Optional
GND
© 2004 California Micro Devices Corp. All rights reserved.
01/20/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com
1
PRELIMINARY
CM3112
PACKAGE / PINOUT DIAGRAM
Top View
1
GND
2
EN
3
FA12/FB12
IN
5
OUT
4
PG
5-pin SOT23
Note: This drawing is not to scale.
PIN DESCRIPTIONS
PIN
NAME
1
IN
2
GND
3
EN
DESCRIPTION
Positive input voltage for the regulator. The internal loading on this input is typically 300µA whenever the regulator is enabled, and less than 10µA when the regulator is disabled. If the IN pin is
within a few inches of the main input filter, a capacitor may not be necessary. Otherwise an input filter capacitor (CIN) of 0.1uF to 1uF will ensure adequate filtering.
The negative reference for all voltages.
Enable/shutdown input. When EN is asserted high (VEN ≥ 1.6V), the regulator is enabled. When EN
is asserted low (VEN ≤0.4V), the regulator’s series pass transistor is forced into a high impedance
mode and an internal discharge resistance (500Ω) is applied to the output to quickly reduce the output voltage to 0 volts.
4
PG
Power Good output. This is an open drain output and functions as a supply voltage supervisor for
the output voltage. It is asserted low when the output falls below 84% of its nominal value. This output becomes inactive when (EN > 1.5V), (2.5V < VIN < 5.5V) and (VOUT > 97% of VOUTNOM), all of
which are valid for more than 1-10ms.
5
OUT
The regulated voltage output. Although an output capacitor is not necessary for stable regulator
operation, a optional 0.1uF capacitor can be used to provide an added measure of output stability.
Ordering Information
PART NUMBERING INFORMATION
Standard Finish
Ordering Part
Lead-free Finish
Ordering Part
Regulator
Pins
Package
Number1
Part Marking
Number1
Part Marking
CM3112-12
5
SOT23-5
CM3112-12ST
FA12
CM3112-12SO
FB12
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
© 2004 California Micro Devices Corp. All rights reserved.
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01/20/04
PRELIMINARY
CM3112
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNITS
+2000
V
[GND - 0.6] to +6.0
[GND - 0.6] to [VIN+0.6]
[GND - 0.6] to [VIN+0.6]
V
V
V
-40 to +150
°C
Operating Temperature Range
Ambient
Junction
0 to +70
0 to +150
°C
°C
Power Dissipation (See note 1)
Internally Limited
W
ESD Protection (HBM)
Pin Voltages
VIN
VOUT
VEN
Storage Temperature Range
Note 1: The power rating is based on a printed circuit board heat spreading capability equivalent to 2 square inches of copper connected to the GND pins. Typical multi-layer boards using power plane construction will provide this heat spreading ability
without the need for additional dedicated copper area. Please consult with factory for thermal evaluation assistance.
STANDARD OPERATING CONDITIONS
PARAMETER
VALUE
UNITS
VIN
2.5 to 5.5
V
Ambient Operating Temperature Range
0 to +70
°C
Load Current
0 to 150
mA
COUT
0 to 10
µF
© 2004 California Micro Devices Corp. All rights reserved.
01/20/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com
3
PRELIMINARY
CM3112
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1)
SYMBOL
PARAMETER
CONDITIONS
VOUT
Output Voltage Accuracy
ILOAD = 5mA, VIN = 3.3V
VOUT
Output Voltage
5mA < ILOAD < 150mA, 3.135V < VIN < 5.5V
VR LOAD
Load Regulation
VR LINE
RDROP
MAX
UNITS
-2
-3
2
3
%
%
-4
-5
4
5
%
%
5mA < ILOAD < 100mA
0.5
0.7
%
%
Line Regulation xx
ILOAD = 5mA; 2.5V < VIN < 5.5V
0.1
0.15
%/V
%/V
Dropout Resistance
VIN = 2.7V
10
Ω
ILIM
Overload Current Limit
ISC
Short Circuit Current Limit
MIN
400
mA
VOUT < 0.5V
150
mA
Discharge Resistance
EN tied to GND
500
Ω
IGND
Ground Current
Regulator Enabled (EN=VIN); ILOAD= 0mA
Regulator Enabled (EN=VIN); ILOAD= 150mA
Regulator Disabled (EN=GND); (Disable
Mode)
90
100
0.01
VEN
EN Input Logic High Threshold Regulator Enabled, VIN = 5.5V
VDIS
EN Input Logic Low Threshold
RDISCH
160
TYP
1.6
0.01
VPGL
Power Good Low Threshold
% of VOUT (PG ON)
VPGH
Power Good High Threshold
% of VOUT (PG OFF)
VOL
Power Good Logic "0" Voltage
IL= 2mA; Fault Condition
IPG
Power Good Leakage Current
Power Good Off; VPG = 5.5V
Power Good Delay Time
To de-assert PG
To assert PG
2.5V < VIN < 5.5V (applies to DPGD only)
DPGD
DPGA
0.4
V
10
µA
84
1
µA
µA
µA
V
Regulator Disabled, VIN = 5.5V
Enable Input Current
IEN
150
200
10
%
97
%
0.05
0.1
V
0.01
50
µA
10
1
mS
mS
Note 1: Bold values indicate 0 °C < TJ <125 °C.
© 2004 California Micro Devices Corp. All rights reserved.
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01/20/04
PRELIMINARY
CM3112
Timing Diagram
VOUT
VPG
100%
90%
EN
PG
Inactive
DPGA
DPGD
DPGD
Active
Figure 1. Power Good Delay Timing
© 2004 California Micro Devices Corp. All rights reserved.
01/20/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com
5
PRELIMINARY
CM3112
Performance Information
CM3112 Typical DC Characteristics (nominal conditions unless specified otherwise)
Nominal Conditions: VIN = 3.3V, ILOAD=1mA, no COUT
Line Regulation (1% and 100% rated load)
1.248
1.248
1.236
1.236
OUTPUT VOLTAGE [V]
OUTPUT VOLTAGE [V]
Load Regulation
1.224
1.212
1.200
1.188
1.176
1.164
1.224
1mA Load
1.212
1.200
150mA Load
1.188
1.176
1.164
1.152
1.152
0
100
200
300
1.0
400
2.0
3.0
5.0
6.0
Line Regulation (Close-up)
0
2.5
-1
2.0
DELTA VOUT [mV]
DELTA VOUT [mV]
Load Regulation (Close-up)
-2
-3
1mA Load
1.5
1.0
0.5
-4
-5
0.0
0
50
100
150
2.0
3.0
4.0
5.0
6.0
INPUT VOLTAGE [V]
LOAD CURRENT [mA]
Foldback Current Limiting
Line Regulation
1.4
1.40
1.2
1.20
OUTPUT VOLTAGE [V]
OUTPUT VOLTAGE [V]
4.0
INPUT VOLTAGE [V]
LOAD CURRENT [mA]
1.0
0.8
0.6
0.4
0.2
1.00
1mA Load
0.80
0.60
0.40
0.20
0.00
0.0
0
100
200
300
LOAD CURRENT [mA]
400
0
1
2
3
4
INPUT VOLTAGE [V]
5
6
© 2004 California Micro Devices Corp. All rights reserved.
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01/20/04
PRELIMINARY
CM3112
Performance Information (cont’d)
CM3112 Typical DC Characteristics (cont’d, nominal conditions unless specified otherwise)
Ground Current Vs. Supply Voltage
150
En = Vin
100
GROUND CURRENT [uA]
GROUND CURRENT [uA]
120
Ground Current Vs. Load Current
80
1mA Load
60
40
20
100
75
50
25
0
0
0
1
2
3
4
INPUT VOLTAGE [V]
5
0
6
Enable Threshold Vs. Supply Voltage
50
100
150
LOAD CURRENT [mA]
Power Good Voltage Vs. Pull-Up Resistor
0.8
3.5
0.7
3.0
0.6
POWER GOOD [V]
THRESHOLD [V]
125
0.5
0.4
0.3
0.2
2.5
Power Fail
2.0
1.5
1.0
0.5
0.1
0.0
0.0
PULL-UP RESISTOR [Ω ]
10000
1000
100
6
10
3
4
5
SUPPLY VOLTAGE [V]
1
2
© 2004 California Micro Devices Corp. All rights reserved.
01/20/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com
7
PRELIMINARY
CM3112
Performance Information (cont’d)
CM3112 Transient Characteristics (nominal conditions unless specified otherwise)
Load transient Step Response
Load transient Step Response
Load transient Step Response
Load transient Step Response
Load transient Step Response
Load transient Step Response
© 2004 California Micro Devices Corp. All rights reserved.
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430 N. McCarthy Blvd., Milpitas, CA 95035-5112
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01/20/04
PRELIMINARY
CM3112
Performance Information (cont’d)
CM3112 Transient Characteristics (nominal conditions unless specified otherwise)
Line Transient Step Response
Line Transient Step Response
Line Transient Step Response
Cold Start & Power Down
Enable Response
Vout Enable Response
© 2004 California Micro Devices Corp. All rights reserved.
01/20/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com
9
PRELIMINARY
CM3112
Performance Information (cont’d)
CM3112 Typical AC Characteristics (nominal conditions unless specified otherwise)
Power Supply Ripple Rejection
Power Supply Ripple Rejection
(No Cout, Vin=5V)
90
(Cout=1uF, Vin=5V)
90
50mA
50mA
20mA
20mA
80
80
150mA
150mA
70
70
1mA
PSRR [dB]
PSRR [dB]
1mA
60
60
50
40
50
40
30
30
20
20
10
10
No Cout, Vin = 5V
Cout=1uF, Vin=5V
0
0
10
100
1000
10000
10
100000
100
1000
10000
100000
Frequency [Hz]
Frequency [Hz]
Power Supply Ripple Rejection
Power Supply Ripple Rejection
(No Cout, Vin=3.3V)
(Cout=1uF, Vin=3.3V)
80
80
1mA
1mA
20mA
70
20mA
70
50mA
50mA
150mA
60
60
50
50
PSRR [dB]
PSRR [dB]
150mA
40
40
30
30
20
20
10
10
Cout=1uF, Vin=3.3V
No Cout, Vin = 3.3V
0
0
10
100
1000
10000
10
100000
100
1000
10000
100000
Frequency [Hz]
Frequency [Hz]
Output Noise (No Cout)
Output Noise (1uF Cout)
1.E-05
1.E-05
1 mA
En[uV/rootHz]
En[uV/rootHz]
1 mA
150 mA
150 mA
N o C out
Cout=1uf
1.E-06
1.E-06
10
100
1000
10000
Frequency [Hz]
100000
10
100
1000
10000
100000
Frequency [Hz]
© 2004 California Micro Devices Corp. All rights reserved.
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01/20/04
PRELIMINARY
CM3112
Performance Information (cont’d)
CM3112 Typical Thermal Characteristics
VOUT Over Temperature
50
50
40
40
30
30
OUTPUT CHANGE [mV]
OUTPUT CHANGE [mV]
VOUT Over Temperature
20
10
0
-10
-20
-30
-40
20
10
0
-10
-20
-30
-40
-50
-50
0
25
50
75
100
-50 -25
125
Ground Current Over Temperature
25
50
75 100 125 150
Time Delay Over Temperature
200
10
8
150
Time Delay [ms]
GROUND CURRENT [uA]
0
TEMPERATURE [oC]
TEMPERATURE [oC]
100
50
0
6
4
2
0
-50 -25
0
25
50
75 100 125 150
TEMPERATURE [oC]
25
50
75
100
125
TEMPERATURE [oC]
© 2004 California Micro Devices Corp. All rights reserved.
01/20/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com
11
PRELIMINARY
CM3112
Application Information
Output Capacitor
Unlike other LDO regulators the CM3112 does not
require an output capacitor for stability. It is stable with
any capacitor from 0 to 10uF.
In first 3 figures the load step is applied with a rise time
of approximately 1us. Adding capacitance does not
improve the response.
Adding output capacitance will improve the very high
frequency transient response of the part. Figures 1-7
demonstrate the effect of output capacitance on a
10mA to 140mA transient load step.
The last three figures show the load step with a rise
time of about 200ns. While the 0.1uF capacitor does
not improve the response the 1uF capacitor decreases
the overall magnitude of the transient spike.
Figure: 2
Figure: 5
Figure: 3
Figure: 6
Figure: 4
Figure: 7
© 2004 California Micro Devices Corp. All rights reserved.
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01/20/04
PRELIMINARY
CM3112
Application Information (cont’d)
Power Dissipation/Handling
Input Capacitor
The overall junction to ambient thermal resistance
(θJA) for device power dissipation (PD) consists primarily of two paths in series. The first path is the junction
to the case (θ JC) which is defined by the package style,
If the VIN pin is within a few inches of the main input filter, a capacitor may not be necessary. Otherwise an
input filter capacitor (CIN) of 0.1uF to 1uF will ensure
adequate filtering.
and the second path is case to ambient (θ CA) thermal
resistance which is dependent on board layout. The
final operating junction temperature for any set of conditions can be estimated by the following thermal equation:
TJUNC = TAMB + PD (θ JC ) + PD (θ CA )
= TAMB + PD (θ JA)
Enable/Disable
Whenever this input is taken low, the regulator pass
transistor is forced into a high impedance mode and an
internal discharge resistance (500Ω) will be applied
from the output to ground.
Power Good
The CM3112-12 uses a SOT23-5 package. When this
package is mounted on a double sided printed circuit
board with two square inches of copper allocated for
"heat spreading", the resulting θJA is 175°C/W.
Based on a maximum power dissipation of 315mW
(2.1Vx150mA), with an ambient of 70°C the resulting
junction temperature will be:
TJUNC = TAMB + PD (θ JA )
= 70°C + 315mW (175°C/W)
= 70°C + 55°C = 125°C
This is an open drain output signal. It works as a supply voltage supervisor for the output voltage.
It is asserted when the output falls below 84% (when
2.5V<Vin<5.5V) of its nominal value. The signal
becomes inactive when the three following conditions
are met (valid) for more than 1-10ms:
a) EN > 1.5V
b) 2.5V < VIN < 5.5V
c) VOUT > 97% of VOUTNOM
Thermal characteristics were measured using a double
sided board with two square inches of copper area
connected to the GND pins for "heat spreading".
Measurements showing performance up to junction
temperature of 125°C were performed under light load
conditions (1mA). This allows the ambient temperature
to be representative of the internal junction temperature.
Note: The use of multi-layer board construction with
separate ground and power planes will further enhance
the overall thermal performance. In the event of no
copper area being dedicated for heat spreading, a
multi-layer board construction, using only the minimum
size pad layout, will provide the CM3112-12 with an
overall θ JA of 175°C/W which allows up to 450mW to
be safely dissipated.
© 2004 California Micro Devices Corp. All rights reserved.
01/20/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com
13
PRELIMINARY
CM3112
Mechanical Details
SOT23-5 Mechanical Specifications
Mechanical Package Diagrams
Dimensions for CM3112-12 device packaged in 5-pin
SOT23 package are presented below.
TOP VIEW
For complete information on the SOT23-5 package,
see the California Micro Devices SOT23 Package Information document.
e1
e
5
4
E1 E
1
2
3
PACKAGE DIMENSIONS
Package
SOT23-5 (JEDEC name is MO-178)
Pins
5
Dimensions
Millimeters
SIDE VIEW
Inches
Min
Max
Min
Max
A
--
1.45
--
0.0571
A1
0.00
0.15
0.0000
0.0059
b
0.30
0.50
0.0118
0.0197
c
0.08
0.22
0.0031
0.0087
D
2.75
3.05
0.1083
0.1201
E
2.60
3.00
0.1024
0.1181
E1
1.45
1.75
0.0571
0.0689
e
0.95 BSC
0.0374 BSC
e1
1.90 BSC
0.0748 BSC
L
L1
# per tape
and reel
0.30
0.60
0.60 REF
b
0.0118
D
A
A1
END VIEW
c
0.0236
0.0236 REF
L1
L
3000 pieces
Package Dimensions for SOT23-5.
© 2004 California Micro Devices Corp. All rights reserved.
14
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com
01/20/04
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