CMP0417AA8-I CMOS LPRAM Document Title 256K x 16 bit Super Low Power and Low Voltage Full CMOS RAM Revision History Revision No. History Draft date Remark 0.0 Initial Draft May. 2nd, 2004 Final 0.1 Added G(Pb-Free) and H(Pb-Free & Halogen Free) descriptions Oct. 26th, 2005 Final 0.2 Removed 60ns descriptions Aug. 22nd, 2006 Final 0.3 Added Power Up Sequence Sep. 6th, 2006 Final 1 Revision 0.3 Sep. 2006 CMP0417AA8-I CMOS LPRAM 256K x 16 bit Super Low Power and Low Voltage Full CMOS RAM FEATURES • Process Technology : Full CMOS • Organization : 256K x 16 • Power Supply Voltage : 2.7~3.3V • Three state output and TTL Compatible • Package Type : 48-FBGA-6.00x8.00 mm2 • Separated I/O power(VCCQ) & Core Power(VCC) • Automatic power-down when deselected PRODUCT FAMILY Operating Temperature Product Family Power Dissipation Operating Voltage (V) ICC2 f = 1MHz f = fmax Speed Min. Typ. Max. Industrial (-40~85’C) CMP0417AA8-F70I ICC1 2.7 3.0 3.3 70ns ISB1 (CMOS Standby Current) Typ. Max. Typ. Max. Typ. Max. 1.5mA 3mA 12mA 20mA 30uA 70uA 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc = Vcc (typ) and TA = 25C. 2. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER PIN DESCRIPTION 1 2 3 4 5 6 A /LB /OE A0 A1 A2 NC B I/O9 /UB A3 A4 /CS I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D VSS I/O12 A17 A7 I/O4 VCC E VCCQ I/O13 DNU A16 I/O5 VSS F I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 NC A12 A13 /WE I/O8 H NC A8 A9 A10 A11 NC FUNCTIONAL BLOCK DIAGRAM Clk gen. VCC VSS Row Addresses I/O1~I/O8 Function Name Function /CS Chip Select Input VCC Core Power I/O Power Output Enable Input VCCQ Write Enable Input VSS Ground A0~A17 Address Inputs /UB Upper Byte(I/O9~16) I/O1~I/O16 Data Inputs/Outputs /LB Lower Byte(I/O 1~8) /WE Do Not Use /UB DNU I/O Circuit Column select Column Addresses /OE No Connection Data cont Memory array Data cont /WE NC Row select Data cont I/O9~I/O16 48-FBGA : Top View(Ball Down) Name Precharge circuit. /CS1 /OE Control Logic /LB 2 Revision 0.3 Sep. 2006 CMP0417AA8-I CMOS LPRAM PRODUCT LIST Industrial Temperature Products(-40~85’C) Part Name Function CMP0417AA8-F70I 48-FBGA, 70ns, VCC=3.0V, VCCQ=3.0V(2.5V,1.8V) 1. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER FUNCTIONAL DESCRIPTION /CS1 /OE /WE /LB /UB I/O1-8 I/O9-16 Mode Power H X1) X1) X1) X1) High-Z High-Z Deselect/Power-down Standby X1) X1) X1) H H High-Z High-Z Deselect/Power-down Standby H H L X1) High-Z High-Z Output Disabled Active H H X1) L High-Z High-Z Output Disabled Active L H Dout High-Z Lower Byte Read Active H L High-Z Dout Upper Byte Read Active L L H L X1) L L L Dout Dout Word Read Active L H Din High-Z Lower Byte Write Active H L High-Z Din Upper Byte Write Active L L Din Din Word Write Active Unit 1. X means don’t care.(Must be low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Symbol Ratings VIN, VOUT -0.2 to Vcc+0.3V V Vcc -0.2 to 3.6 V Voltage on Vcc supply relative to Vss PD 1.0 W TSTG -65 to 150 ’C TA -40 to 85 ’C Power Dissipation Storage temperature Operating Temperature 1. Str es s e s g r e ate r tha n th o s e l i st e d u n d er “ A bsolute Maxim um Ratings” may cause permanent dam age to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for Industrial periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS1) Item Symbol I/O operating voltage (VCCQ ≤ VCC) Ground CMP0417AA8 Max VCC 2.7 3.3 2.7 3.3 2.7 3.3 V VCCQ 2.7 3.3 2.25 2.75 1.65 1.95 V VSS 0 0 0 0 0 0 V Input high voltage VIH 0.8VCCQ VCC+0.22) 0.8VCCQ VCC+0.22) 0.8VCCQ VCC+0.22) V Input low voltage VIL -0.23) 0.2VCCQ -0.23) 0.2VCCQ -0.23) 0.2VCCQ V Supply voltage Min Max Min Max Unit Min Note : 1.TA=-40 to 85’C, otherwise specified. 2. Overshoot : Vcc+1.0V in case of pulse width≤20ns. 3. Undershoot : -1.0V in case of pulse width≤20ns. 4. Overshoot and undershoot are sampled, not 100% tested. 3 Revision 0.3 Sep. 2006 CMP0417AA8-I CMOS LPRAM CAPACITANCE1) (f=1MHz , TA=25’C) Symbol Test Condition Min Max Input capacitance Item CIN VIN=0V - 8 Unit pF Input/Output capacitance CIO VIO=0V - 8 pF 1. Capacitance is sampled, not 100% tested. DC AND OPERATING CHARACTERISTICS Min Typ Max Unit Input leakage current Item Symbol ILI VIN=VSS to VCC -1 - 1 uA Output leakage current ILO /CS=VIH, /OE=VIH or /WE=VIL, VIO=VSS to VCC -1 - 1 uA ICC1 Cycle time=1us, 100%duty, IIO=0mA, /CS≤0.2V, VIN≤0.2V or VIN≥VCC-0.2V - - 3 mA ICC2 Cycle time=Min, IIO=0mA, 100% duty, /CS=VIL, VIN=VIL or VIH - - 25 mA Output low voltage VOL IOL=0.5mA 0.2VCCQ V Output high voltage VOH IOH=-0.5mA Standby Current(TTL) ISB /CS=VIH, Other inputs=VIH or VIL - - 0.3 mA Standby Current(CMOS) ISB1 /CS≥VCC-0.2V, Other inputs=0~VCC - - 70 uA Average operating current Test Conditions 0.8VCCQ 4 V Revision 0.3 Sep. 2006 CMP0417AA8-I CMOS LPRAM AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Input/Output Reference) 1TTL 30pf Input pulse level : 0.2 to VCC-0.2V Input rising and falling time : 5ns Input and output reference voltage : 0.5*VCCQ Output load(see right) : CL=30pF+1TTL AC CHARACTERISTICS(VCC=2.7V~3.3V, Industrial product : TA=-40 to 85’C) Parameter List Read Cycle Time Read tRC Units Min Max 70 - ns ns Address Access Time tAA - 70 Chip Select to Output tCO - 70 ns Output Enable to Valid Output tOE - 25 ns /UB, /LB Access Time tBA - 70 ns ns tLZ 10 - /UB, /LB Enable to Low-Z Output Chip Select to Low-Z Output tBLZ 10 - ns Output Enable to Low-Z Output tOLZ 5 - ns Chip Disable to High- Z Output Write 70ns Symbol tHZ 0 5 ns /UB, /LB Disable to High- Z Output tBHZ 0 5 ns Output Disable to High- Z Output tOHZ 0 5 ns Output Hold from Address Change tOH 5 - ns Write Cycle Time tWC 70 - ns Chip Select to End of Write tCW 60 - ns Address Set-up Time tAS 0 - ns Address Valid to End of Write tAW 60 - ns /UB, /LB Valid to End of Write tBW 60 - ns Write Pulse Width tWP 50 - ns Write Recovery Time Write to Output High-Z Data to Write Time Overlap tWR 0 - ns tWHZ 0 5 ns tDW 20 - ns Data Hold from Write Time tDH 0 - ns End Write to Output Low-Z tOW 5 - ns /CS High Pulse Width1) tCP 10 - ns 1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High. 5 Revision 0.3 Sep. 2006 CMP0417AA8-I CMOS LPRAM Power Up Sequence 1. Apply Power 2. Maintain stable power for a minimum of 200us with /CS=VIH Standby Mode State machines Power On /CS=VIH Wait min.200us Initial State /CS=VIL, /UB or/and /LB=VIL Active Mode /CS=VIlL /CS=VIH (or/and /UB=/LB=VIH) Standby Mode Standby Mode Characteristics Mode Memory Cell Data Standby Current(uA) Wait Time(us) Standby Valid 70 (ISB1) 0 6 Revision 0.3 Sep. 2006 CMP0417AA8-I READ CYCLE (1) CMOS LPRAM (Address controlled,/CS=/OE=VIL, /WE=VIH, /UB or/and /LB=VIL) tRC Address tOH Data Out READ CYCLE (2) tAA Previous Data Valid Data Valid (/WE=VIH) tRC Address tOH tAA tCO /CS tHZ tBA /UB, /LB tBHZ tOE /OE tOLZ Data Out High-Z tOHZ tBLZ tLZ Data Valid 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 7 Revision 0.3 Sep. 2006 CMP0417AA8-I WRITE CYCLE (1) CMOS LPRAM (/WE controlled) tWC Address tCW(2) tWR(4) /CS tAW tBW /UB, /LB tWP(1) /WE tAS(3) tDW Data in tWHZ Data Out WRITE CYCLE (2) tDH Data Valid High-Z High-Z tOW Data Undefined (/CS controlled, /WE=VIH) tWC Address tAS(3) tWR(4) tCW(2) /CS tAW tBW /UB, /LB tWP(1) /WE tDW Data in Data Out WRITE CYCLE (3) tDH Data Valid High-Z High-Z (/UB, /LB controlled) tWC Address tWR(4) tCW(2) /CS tAW tBW /UB, /LB tAS(3) tWP(1) /WE tDW Data in Data Out tDH Data Valid High-Z High-Z 1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 8 Revision 0.3 Sep. 2006 CMP0417AA8-I CMOS LPRAM PACKAGE DIMENSION Unit : millimeters 48 BALL FINE PITCH BGA(0.75mm ball pitch) Top View Bottom View B A1 INDEX MARK B1 B 0.05 0.05 6 5 4 3 2 1 A B C #A1 C C C1 D C1/2 E F G H B/2 0.25/Typ. E2 D A Y 0.85/Typ. E Detail A E1 0.30 Side View C - Min Typ A - 0.75 Max - B 5.90 6.00 6.10 B1 - 3.75 - C 7.90 8.00 8.10 C1 - 5.25 - D 0.30 0.35 0.40 E - 1.00 - E1 - 0.75 - E2 0.20 0.25 0.30 Y - - 0.08 9 NOTES. 1. Bump counts : 48(8row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. All tolerance are +/-0.050 unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity : 0.08(Max) Revision 0.3 Sep. 2006